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| author | Lubomir Popov <lpopov@mm-sol.com> | 2014-12-19 17:34:31 +0200 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2015-01-29 12:00:49 -0500 |
| commit | b558af81281975d032c063ad228a400d8e619ad5 (patch) | |
| tree | 8cb863af9cd24cb23522341ac17172499b5f96f9 /arch/arm/include | |
| parent | 2af13d6b6265a6700c4f65597410b769895024bf (diff) | |
| download | u-boot-b558af81281975d032c063ad228a400d8e619ad5.tar.gz u-boot-b558af81281975d032c063ad228a400d8e619ad5.tar.xz u-boot-b558af81281975d032c063ad228a400d8e619ad5.zip | |
ARM: OMAP5: DRA7xx: Add support for power rail grouping
On the DRA72x (J6Eco) EVM one PMIC SMPS is powering three SoC
core rails. This concept of using one SMPS to supply multiple
core domains (in various, although limited combinations, per
primary device use case) has now become common and is used by
many customer J6/J6Eco designs; it is supported by a number of
corresponding PMIC OTP versions.
This patch implements correct operation of the core voltages
scaling routine by ensuring that each SMPS that is supplying
more than one domain shall be written only once, and with the
highest voltage of those fused in the SoC (or of those defined
in the corresponding header if fuse read is disabled or fails)
for the power rails belonging to the group.
The patch also replaces some PMIC-related magic numbers with
the appropriate definitions. The default OPP_NOM voltages for
the DRA7xx SoCs are updated as well, per the latest DMs.
Signed-off-by: Lubomir Popov <l-popov@ti.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/clock.h | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 0dc584b8ce..f8e5630bcb 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -236,13 +236,20 @@ #define VDD_MPU_ES2_LOW 880 #define VDD_MM_ES2_LOW 880 -/* TPS659038 Voltage settings in mv for OPP_NOMINAL */ -#define VDD_MPU_DRA752 1090 +/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */ +#define VDD_MPU_DRA752 1100 #define VDD_EVE_DRA752 1060 #define VDD_GPU_DRA752 1060 -#define VDD_CORE_DRA752 1030 +#define VDD_CORE_DRA752 1060 #define VDD_IVA_DRA752 1060 +/* DRA72x voltage settings in mv for OPP_NOM per DM */ +#define VDD_MPU_DRA72x 1100 +#define VDD_EVE_DRA72x 1060 +#define VDD_GPU_DRA72x 1060 +#define VDD_CORE_DRA72x 1060 +#define VDD_IVA_DRA72x 1060 + /* Efuse register offsets for DRA7xx platform */ #define DRA752_EFUSE_BASE 0x4A002000 #define DRA752_EFUSE_REGBITS 16 @@ -284,6 +291,13 @@ #define TPS659038_REG_ADDR_SMPS7 0x33 #define TPS659038_REG_ADDR_SMPS8 0x37 +/* TPS65917 */ +#define TPS65917_I2C_SLAVE_ADDR 0x58 +#define TPS65917_REG_ADDR_SMPS1 0x23 +#define TPS65917_REG_ADDR_SMPS2 0x27 +#define TPS65917_REG_ADDR_SMPS3 0x2F + + /* TPS */ #define TPS62361_I2C_SLAVE_ADDR 0x60 #define TPS62361_REG_ADDR_SET0 0x0 |