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| author | Jaehoon Chung <jh80.chung@samsung.com> | 2014-05-16 13:59:50 +0900 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2014-05-16 14:54:26 +0900 |
| commit | 39c49756221b53f2672452bef1f4b00a8dbad49c (patch) | |
| tree | 06f90ba206bfb34660ad30a15eb440f5ccc77c30 /arch/arm/include | |
| parent | 58209dfaced619a53581c4d66d9791ce8316e0d5 (diff) | |
| download | u-boot-39c49756221b53f2672452bef1f4b00a8dbad49c.tar.gz u-boot-39c49756221b53f2672452bef1f4b00a8dbad49c.tar.xz u-boot-39c49756221b53f2672452bef1f4b00a8dbad49c.zip | |
ARM: exynos: clock: modify the set_mmc_clk for exynos4
Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-exynos/clk.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index cdeef324cc..ffbc07e228 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -16,6 +16,11 @@ #define BPLL 5 #define RPLL 6 +#define MASK_PRE_RATIO(x) (0xff << ((x << 4) + 8)) +#define MASK_RATIO(x) (0xf << (x << 4)) +#define SET_PRE_RATIO(x, y) ((y & 0xff) << ((x << 4) + 8)) +#define SET_RATIO(x, y) ((y & 0xf) << (x << 4)) + enum pll_src_bit { EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL, |