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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-09-21 16:56:44 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-09-21 16:56:44 +0200 |
| commit | 2a8c9c86b92a9ccee3c27286de317e19bb0530b3 (patch) | |
| tree | 6ed0c2f3f2f089e16e6a4b1e7e34b3df3556e87d /arch/arm/include | |
| parent | 015b18c642d9b0f92d1b35f6d6ed73a6a0b29675 (diff) | |
| parent | 3aae66e2a74ac89724d16b6e8908dcd0d2825eeb (diff) | |
| download | u-boot-2a8c9c86b92a9ccee3c27286de317e19bb0530b3.tar.gz u-boot-2a8c9c86b92a9ccee3c27286de317e19bb0530b3.tar.xz u-boot-2a8c9c86b92a9ccee3c27286de317e19bb0530b3.zip | |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/ddr3.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h index 4d229a25fa..6bf35d3543 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -50,6 +50,7 @@ struct ddr3_emif_config { void ddr3_init(void); void ddr3_reset_ddrphy(void); +void ddr3_err_reset_workaround(void); void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index d6726a1eca..76e6441e57 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -121,9 +121,11 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_CLOCK_BASE KS2_PLL_CNTRL_BASE #define KS2_RSTCTRL_RSTYPE (KS2_PLL_CNTRL_BASE + 0xe4) #define KS2_RSTCTRL (KS2_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_RSCFG (KS2_PLL_CNTRL_BASE + 0xec) #define KS2_RSTCTRL_KEY 0x5a69 #define KS2_RSTCTRL_MASK 0xffff0000 #define KS2_RSTCTRL_SWRST 0xfffe0000 +#define KS2_RSTYPE_PLL_SOFT BIT(13) /* SPI */ #define KS2_SPI0_BASE 0x21000400 |