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| author | Alexander Graf <agraf@suse.de> | 2016-03-04 01:09:45 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-03-15 15:12:59 -0400 |
| commit | 0691484ac1efb1981dfd1b38df9646128bafff32 (patch) | |
| tree | 34841bd6307df363f2f3783d1a0a219a16b553bf /arch/arm/include/asm/armv8 | |
| parent | dcac8843a8904c939f70489b8dd410cde32b7df5 (diff) | |
| download | u-boot-0691484ac1efb1981dfd1b38df9646128bafff32.tar.gz u-boot-0691484ac1efb1981dfd1b38df9646128bafff32.tar.xz u-boot-0691484ac1efb1981dfd1b38df9646128bafff32.zip | |
thunderx: Calculate TCR dynamically
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/arm/include/asm/armv8')
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 897f010207..39ff74566e 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -159,11 +159,6 @@ #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */ #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */ #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */ -#else -#define TCR_EL1_IPS_BITS CONFIG_SYS_TCR_EL1_IPS_BITS -#define TCR_EL2_IPS_BITS CONFIG_SYS_TCR_EL2_IPS_BITS -#define TCR_EL3_IPS_BITS CONFIG_SYS_TCR_EL3_IPS_BITS -#endif /* PTWs cacheable, inner/outer WBWA and inner shareable */ #define TCR_FLAGS (TCR_TG0_64K | \ @@ -171,6 +166,7 @@ TCR_ORGN_WBWA | \ TCR_IRGN_WBWA | \ TCR_T0SZ(VA_BITS)) +#endif #define TCR_EL1_RSVD (1 << 31) #define TCR_EL2_RSVD (1 << 31 | 1 << 23) |