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author | Lucas Stach <dev@lynxeye.de> | 2012-09-25 20:21:13 +0000 |
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committer | Tom Rini <trini@ti.com> | 2012-10-15 11:54:07 -0700 |
commit | 65530a842eeaf7ad07e0613ac6f883f2f1f1e33f (patch) | |
tree | 01e704c3bbf59d1c5f7be1ba55ae8dcf656a5128 /arch/arm/include/asm/arch-tegra/clock.h | |
parent | 3f44e44f33899821c4703c3bd5f9c117bb328e8b (diff) | |
download | u-boot-65530a842eeaf7ad07e0613ac6f883f2f1f1e33f.tar.gz u-boot-65530a842eeaf7ad07e0613ac6f883f2f1f1e33f.tar.xz u-boot-65530a842eeaf7ad07e0613ac6f883f2f1f1e33f.zip |
tegra20: add clock_set_pllout function
Common practice on Tegra 2 boards is to use the pllp_out4 FO
to generate the ULPI reference clock. For this to work we have
to override the default hardware generated output divider.
This function adds a clean way to do so.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch/arm/include/asm/arch-tegra/clock.h')
-rw-r--r-- | arch/arm/include/asm/arch-tegra/clock.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 3eff163e85..eac1dc2662 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -58,6 +58,18 @@ unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon); /** + * Set PLL output frequency + * + * @param clkid clock id + * @param pllout pll output id + * @param rate desired output rate + * + * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) + */ +int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, + unsigned rate); + +/** * Read low-level parameters of a PLL. * * @param id clock id to read (note: USB is not supported) |