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| author | Marek Vasut <marex@denx.de> | 2021-01-19 00:58:32 +0100 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-01-23 13:40:29 +0100 |
| commit | 6cd4f48b64d4b9a4f737c2aa4e6550d2eb8c80a5 (patch) | |
| tree | 311f342403c287346df621777491de8e5923ee2c /arch/arm/include/asm/arch-mx7 | |
| parent | 85b1c11989ca7a7321889efefa58c125aa30ab34 (diff) | |
| download | u-boot-6cd4f48b64d4b9a4f737c2aa4e6550d2eb8c80a5.tar.gz u-boot-6cd4f48b64d4b9a4f737c2aa4e6550d2eb8c80a5.tar.xz u-boot-6cd4f48b64d4b9a4f737c2aa4e6550d2eb8c80a5.zip | |
spi: imx: Define register bits in the driver
The CSPI/ECSPI register bits do not differ between newer SoCs, instead
of having multiple copies of the same thing for each iMX SoC, define
the bits in the driver.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Diffstat (limited to 'arch/arm/include/asm/arch-mx7')
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index f37419c07f..5cab12f30d 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -842,46 +842,9 @@ struct iomuxc_gpr_base_regs { u32 gpr[23]; /* 0x000 */ }; -/* ECSPI registers */ -struct cspi_regs { - u32 rxdata; - u32 txdata; - u32 ctrl; - u32 cfg; - u32 intr; - u32 dma; - u32 stat; - u32 period; -}; - /* * CSPI register definitions */ -#define MXC_ECSPI -#define MXC_CSPICTRL_EN (1 << 0) -#define MXC_CSPICTRL_MODE (1 << 1) -#define MXC_CSPICTRL_XCH (1 << 2) -#define MXC_CSPICTRL_MODE_MASK (0xf << 4) -#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS 0xfff -#define MXC_CSPICTRL_TC (1 << 7) -#define MXC_CSPICTRL_RXOVF (1 << 6) -#define MXC_CSPIPERIOD_32KHZ (1 << 15) -#define MAX_SPI_BYTES 32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN 18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_PHA 0 /* SCLK phase control */ -#define MXC_CSPICON_POL 4 /* SCLK polarity */ -#define MXC_CSPICON_SSPOL 12 /* SS polarity */ -#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ - #define MXC_SPI_BASE_ADDRESSES \ ECSPI1_BASE_ADDR, \ ECSPI2_BASE_ADDR, \ |