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| author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-04-09 13:06:25 +0000 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2013-04-13 17:46:42 +0200 |
| commit | 0f1411bc8dade4472ca802f46f75714e67301bb0 (patch) | |
| tree | 38bb65f86352d2da7a20452e92076908b96f9faf /arch/arm/include/asm/arch-mx5 | |
| parent | 66300ac25b70018c81c931c981317f6ba390182d (diff) | |
| download | u-boot-0f1411bc8dade4472ca802f46f75714e67301bb0.tar.gz u-boot-0f1411bc8dade4472ca802f46f75714e67301bb0.tar.xz u-boot-0f1411bc8dade4472ca802f46f75714e67301bb0.zip | |
spi: mxc_spi: Set master mode for all channels
The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi
clock glitch durant reset) solved, is back now and itwas re-introduced by
commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling).
Actually the glitch is happening due to always toggling between slave mode
and master mode by configuring the CHANNEL_MODE bits in this reset function.
Since the spi driver only supports master mode, set the mode for all channels
always to master mode in order to have a stable, "glitch-free" SPI clock line.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-mx5')
| -rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 249d15a505..a71cc13e2a 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -230,6 +230,7 @@ #define MXC_CSPICTRL_EN (1 << 0) #define MXC_CSPICTRL_MODE (1 << 1) #define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_MODE_MASK (0xf << 4) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) |