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author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-28 12:26:21 +0200 |
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committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-28 12:26:21 +0200 |
commit | b1cdd8baa14f518288ceddb391d6587c1ecb3174 (patch) | |
tree | c3d00b3193b2ee86b9679baf1933b10a7d07a13d /arch/arm/include/asm/arch-keystone/hardware-k2e.h | |
parent | 48b3ed217f58487c583d59575d7dfe2aafbb738d (diff) | |
parent | 434f2cfcad9f70231ad5a096325ba72ef0d2a2cc (diff) | |
download | u-boot-b1cdd8baa14f518288ceddb391d6587c1ecb3174.tar.gz u-boot-b1cdd8baa14f518288ceddb391d6587c1ecb3174.tar.xz u-boot-b1cdd8baa14f518288ceddb391d6587c1ecb3174.zip |
Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/include/asm/arch-keystone/hardware-k2e.h')
-rw-r--r-- | arch/arm/include/asm/arch-keystone/hardware-k2e.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h new file mode 100644 index 0000000000..62172a4b84 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -0,0 +1,44 @@ +/* + * K2E: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2E_H +#define __ASM_ARCH_HARDWARE_K2E_H + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x24000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD_RST 0 +#define KS2_LPSC_USB_1 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE 10 +#define KS2_LPSC_VUSR0 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_PCIE_1 27 +#define KS2_LPSC_XGE 50 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 1 + +#endif |