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| author | Mingkai Hu <Mingkai.Hu@freescale.com> | 2015-10-26 19:47:50 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2015-10-29 10:34:00 -0700 |
| commit | 9f3183d2d69f6d392fb943d249934f8648531e7e (patch) | |
| tree | a122bb60c3b3df518d476a1fa971e3ba17365c7f /arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h | |
| parent | 23e1acaf4b2863917247a925c81f6ce5a4eadcc2 (diff) | |
| download | u-boot-9f3183d2d69f6d392fb943d249934f8648531e7e.tar.gz u-boot-9f3183d2d69f6d392fb943d249934f8648531e7e.tar.xz u-boot-9f3183d2d69f6d392fb943d249934f8648531e7e.zip | |
armv8/fsl_lsch3: Change arch to fsl-layerscape
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h')
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h new file mode 100644 index 0000000000..57e417b9e0 --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h @@ -0,0 +1,55 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ +#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ + +#define I2C_QUIRK_REG /* enable 8-bit driver */ + +#ifdef CONFIG_FSL_LPUART +#ifdef CONFIG_LPUART_32B_REG +struct lpuart_fsl { + u32 baud; + u32 stat; + u32 ctrl; + u32 data; + u32 match; + u32 modir; + u32 fifo; + u32 water; +}; +#else +struct lpuart_fsl { + u8 ubdh; + u8 ubdl; + u8 uc1; + u8 uc2; + u8 us1; + u8 us2; + u8 uc3; + u8 ud; + u8 uma1; + u8 uma2; + u8 uc4; + u8 uc5; + u8 ued; + u8 umodem; + u8 uir; + u8 reserved; + u8 upfifo; + u8 ucfifo; + u8 usfifo; + u8 utwfifo; + u8 utcfifo; + u8 urwfifo; + u8 urcfifo; + u8 rsvd[28]; +}; +#endif +#endif /* CONFIG_FSL_LPUART */ + +#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */ |