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| author | Patrick Delaunay <patrick.delaunay@st.com> | 2018-07-09 15:17:24 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-07-20 15:55:06 -0400 |
| commit | 8a07d5bfe1f7e3d21aebdc849219caddf9297244 (patch) | |
| tree | 360bcab70c4d8acf8d415b10e20d7aa8a789e3ae /arch/arm/dts | |
| parent | aeac16af7cea9d9f9108644d1934fa1aa4b0bc2d (diff) | |
| download | u-boot-8a07d5bfe1f7e3d21aebdc849219caddf9297244.tar.gz u-boot-8a07d5bfe1f7e3d21aebdc849219caddf9297244.tar.xz u-boot-8a07d5bfe1f7e3d21aebdc849219caddf9297244.zip | |
stm32mp1: clock tree update
Configure clock tree for all the devices.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Diffstat (limited to 'arch/arm/dts')
| -rw-r--r-- | arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 46 |
1 files changed, 35 insertions, 11 deletions
diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index f6d1528aeb..39a0ebce90 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -73,18 +73,41 @@ >; st,pkcs = < - CLK_CKPER_DISABLED + CLK_CKPER_HSE + CLK_FMC_ACLK + CLK_QSPI_ACLK + CLK_ETH_DISABLED CLK_SDMMC12_PLL3R + CLK_DSI_DSIPLL CLK_STGEN_HSE - CLK_I2C46_PCLK5 - CLK_I2C12_PCLK1 + CLK_USBPHY_HSE + CLK_SPI2S1_PLL3Q + CLK_SPI2S23_PLL3Q + CLK_SPI45_HSI + CLK_SPI6_HSI + CLK_I2C46_HSI CLK_SDMMC3_PLL3R - CLK_I2C35_PCLK1 - CLK_UART1_PCLK5 - CLK_UART24_PCLK1 - CLK_UART35_PCLK1 - CLK_UART6_PCLK2 - CLK_UART78_PCLK1 + CLK_USBO_USBPHY + CLK_ADC_CKPER + CLK_CEC_LSE + CLK_I2C12_HSI + CLK_I2C35_HSI + CLK_UART1_HSI + CLK_UART24_HSI + CLK_UART35_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SPDIF_PLL3Q + CLK_FDCAN_PLL4Q + CLK_SAI1_PLL3Q + CLK_SAI2_PLL3Q + CLK_SAI3_PLL3Q + CLK_SAI4_PLL3Q + CLK_RNG1_CSI + CLK_RNG2_CSI + CLK_LPTIM1_PCLK1 + CLK_LPTIM23_PCLK3 + CLK_LPTIM45_PCLK3 >; /* VCO = 1300.0 MHz => P = 650 (CPU) */ @@ -101,9 +124,10 @@ u-boot,dm-pre-reloc; }; - /* VCO = 774.0 MHz => P = 194, Q = 37, R = 97 */ + /* VCO = 786.4 MHz => P = 197, Q = 49, R = 98 */ pll3: st,pll@2 { - cfg = < 3 128 3 20 7 PQR(1,1,1) >; + cfg = < 2 97 3 15 7 PQR(1,1,1) >; + frac = < 0x9ba >; u-boot,dm-pre-reloc; }; |