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authorMichal Simek <michal.simek@xilinx.com>2016-04-07 16:00:11 +0200
committerMichal Simek <michal.simek@xilinx.com>2016-04-13 18:29:06 +0200
commit6c0c958de8259d1163afd5f3b20206a0b6f61c54 (patch)
tree716fadc5ba2bcb0aa3b360ed99f00326ef7d14ec /arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
parentda81db61d562e473765bbe902f5ba21f1fd4806b (diff)
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ARM64: zynqmp: Add support for zc1751 with DC cards
Support ZynqMP zc1751 with DC cards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts')
-rw-r--r--arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts211
1 files changed, 211 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
new file mode 100644
index 0000000000..c68a41bea7
--- /dev/null
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -0,0 +1,211 @@
+/*
+ * dts file for Xilinx ZynqMP zc1751-xm015-dc1
+ *
+ * (C) Copyright 2015, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk.dtsi"
+
+/ {
+ model = "ZynqMP zc1751-xm015-dc1 RevA";
+ compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ gpio0 = &gpio;
+ i2c0 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+};
+
+/* fpd_dma clk 667MHz, lpd_dma 500MHz */
+&fpd_dma_chan1 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+ xlnx,overfetch; /* for testing purpose */
+ xlnx,ratectrl = <0>; /* for testing purpose */
+ xlnx,src-issue = <31>;
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+ xlnx,ratectrl = <100>; /* for testing purpose */
+ xlnx,src-issue = <4>; /* for testing purpose */
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+ xlnx,include-sg; /* for testing purpose */
+};
+
+&gem3 {
+ status = "okay";
+ local-mac-address = [00 0a 35 00 02 90];
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ phy0: phy@0 {
+ reg = <0>;
+ };
+};
+
+&gpio {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ eeprom@55 {
+ compatible = "at,24c64"; /* 24AA64 */
+ reg = <0x55>;
+ };
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ partition@qspi-fsbl-uboot { /* for testing purpose */
+ label = "qspi-fsbl-uboot";
+ reg = <0x0 0x100000>;
+ };
+ partition@qspi-linux { /* for testing purpose */
+ label = "qspi-linux";
+ reg = <0x100000 0x500000>;
+ };
+ partition@qspi-device-tree { /* for testing purpose */
+ label = "qspi-device-tree";
+ reg = <0x600000 0x20000>;
+ };
+ partition@qspi-rootfs { /* for testing purpose */
+ label = "qspi-rootfs";
+ reg = <0x620000 0x5E0000>;
+ };
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA phy OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+};
+
+/* eMMC */
+&sdhci0 {
+ status = "okay";
+ bus-width = <8>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ no-1-8-v; /* for 1.0 silicon */
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&xilinx_drm {
+ status = "okay";
+};
+
+&xlnx_dp {
+ status = "okay";
+};
+
+&xlnx_dp_sub {
+ status = "okay";
+ xlnx,vid-clk-pl;
+};
+
+&xlnx_dp_snd_pcm0 {
+ status = "okay";
+};
+
+&xlnx_dp_snd_pcm1 {
+ status = "okay";
+};
+
+&xlnx_dp_snd_card {
+ status = "okay";
+};
+
+&xlnx_dp_snd_codec0 {
+ status = "okay";
+};
+
+&xlnx_dpdma {
+ status = "okay";
+};