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| author | Michal Simek <michal.simek@xilinx.com> | 2018-07-20 10:16:21 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2018-08-06 08:44:35 +0200 |
| commit | 7996fcca9d401437527d9e9a464cb79965c90c98 (patch) | |
| tree | 0be9bfe26a63ffa1f952071407c587b7a1838e39 /arch/arm/dts/zynq-cse-nor.dts | |
| parent | 92226b5a6d00689dce5c1406913ca97b0b89bda9 (diff) | |
| download | u-boot-7996fcca9d401437527d9e9a464cb79965c90c98.tar.gz u-boot-7996fcca9d401437527d9e9a464cb79965c90c98.tar.xz u-boot-7996fcca9d401437527d9e9a464cb79965c90c98.zip | |
arm: zynq: Remove fclk-enable property for cse-nor target
Mini cse NOR configuration is running without PL that's why there is no
reason to enable clock to PL.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm/dts/zynq-cse-nor.dts')
| -rw-r--r-- | arch/arm/dts/zynq-cse-nor.dts | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index ba6f9a1a79..edc8f59f6c 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -56,7 +56,6 @@ clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - fclk-enable = <0xf>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", |