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author | Andre Przywara <andre.przywara@arm.com> | 2018-07-04 14:16:36 +0100 |
---|---|---|
committer | Jagan Teki <jagan@amarulasolutions.com> | 2018-07-16 12:02:54 +0530 |
commit | 7514ed33d21318edb5d28ab0f4afc23625fd3530 (patch) | |
tree | 35d88fd551d6af731564a3a9363a18d31206557c /arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | |
parent | 68dd17c302a983f78fb95a51e553248ee141d06d (diff) | |
download | u-boot-7514ed33d21318edb5d28ab0f4afc23625fd3530.tar.gz u-boot-7514ed33d21318edb5d28ab0f4afc23625fd3530.tar.xz u-boot-7514ed33d21318edb5d28ab0f4afc23625fd3530.zip |
sunxi: DT: update device tree files for Allwinner H3 and H5 SoCs
Update the device tree files from the Linux tree as of v4.18-rc3,
exactly Linux commit:
commit 55c5ba5e49a0a124ed416880e8227b493474495e
Author: Chen-Yu Tsai <wens@csie.org>
Date: Tue Apr 24 19:34:22 2018 +0800
arm64: dts: allwinner: h5: Add cpu0 label for first cpu
Since the H3 and H5 are very similar (aside from the actual ARM cores),
they share most the SoC .dtsi and thus have to be updated together.
One tiny change is the removal of the "arm/" prefix from the include
path in the sun50i-h5.dtsi, which is needed because we don't share the
same sophisticated DT directory layout of Linux.
Also we need to fix up the board .dts files already, since the .dtsi
removes some pins, so the .dts can't reference them anymore. This is to
maintain bisectability.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Diffstat (limited to 'arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts')
-rw-r--r-- | arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts index e0efcb3ba3..7c38264246 100644 --- a/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts +++ b/arch/arm/dts/sun8i-h2-plus-orangepi-zero.dts @@ -107,8 +107,6 @@ }; &mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ @@ -117,8 +115,6 @@ }; &mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_a>; vmmc-supply = <®_vcc_wifi>; mmc-pwrseq = <&wifi_pwrseq>; bus-width = <4>; |