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| author | Marek Vasut <marex@denx.de> | 2020-12-01 11:29:18 +0100 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2020-12-09 10:57:50 +0100 |
| commit | 75df748b87f86e87a4393d8ebc274e5806f2079a (patch) | |
| tree | 063eb581720ddb3b2462c314dc28367b86399bf9 /arch/arm/dts/stm32mp15xx-dhcom-drc02.dts | |
| parent | 845c6720eca92be09127f7d306349ab31dbf372d (diff) | |
| download | u-boot-75df748b87f86e87a4393d8ebc274e5806f2079a.tar.gz u-boot-75df748b87f86e87a4393d8ebc274e5806f2079a.tar.xz u-boot-75df748b87f86e87a4393d8ebc274e5806f2079a.zip | |
ARM: dts: stm32: Disable SDMMC1 CKIN feedback clock
The STM32MP1 DHCOM SoM can be built with either bus voltage level shifter
or without one on the SDMMC1 interface. Because the SDMMC1 interface is
limited to 50 MHz and hence SD high-speed anyway, disable the SD feedback
clock to permit operation of the same U-Boot image on both SoM with and
without voltage level shifter.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Diffstat (limited to 'arch/arm/dts/stm32mp15xx-dhcom-drc02.dts')
0 files changed, 0 insertions, 0 deletions