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author | Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> | 2018-11-02 11:54:52 +0100 |
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committer | Marek Vasut <marex@denx.de> | 2018-11-29 12:45:15 +0100 |
commit | c402e8170245a0ca2b9398185638b349eeff10a3 (patch) | |
tree | 27e414029b8c7541c113998e32fc83c0bcefb563 /arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi | |
parent | 2a3a99932b8ce12fefd65bde03dc4a33b5317b45 (diff) | |
download | u-boot-c402e8170245a0ca2b9398185638b349eeff10a3.tar.gz u-boot-c402e8170245a0ca2b9398185638b349eeff10a3.tar.xz u-boot-c402e8170245a0ca2b9398185638b349eeff10a3.zip |
dts: arm: socfpga: merge gen5 devicetrees from linux
Add -u-boot.dtsi files to keep the current U-Boot behaviour:
- add u-boot,dm-pre-reloc where required
- disable watchdog
- set uart clock frequency
- add gpio bank-name properties
where appropriate:
- make qspi work (add alias for spi0, fix compatible for flash)
- enable usb (status okay, add alias for udc0)
Adapt board dts files that are not in Linux to keep their old
behaviour.
Change licenses to SPDX.
(Patman warnings/errors are in 1:1 copied files from Linux)
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi')
-rw-r--r-- | arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi new file mode 100644 index 0000000000..648f1bd01d --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_sockit-u-boot.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de> + * Copyright (c) 2018 Simon Goldschmidt + */ + +/{ + aliases { + spi0 = "/soc/spi@ff705000"; + udc0 = &usb1; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + u-boot,dm-pre-reloc; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&flash { + compatible = "n25q00", "spi-flash"; + u-boot,dm-pre-reloc; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; |