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| author | Faiz Abbas <faiz_abbas@ti.com> | 2020-02-26 13:44:33 +0530 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2020-03-09 08:33:16 +0800 |
| commit | c7d106b4eb3fef78cd05a51b3b6950f152d93c06 (patch) | |
| tree | c477dcc6134d91126376870d75a0c05badd0cd21 /arch/arm/dts/k3-j721e-main.dtsi | |
| parent | e8d5dde4473514327b5ea67fb69d8fdd8410240c (diff) | |
| download | u-boot-c7d106b4eb3fef78cd05a51b3b6950f152d93c06.tar.gz u-boot-c7d106b4eb3fef78cd05a51b3b6950f152d93c06.tar.xz u-boot-c7d106b4eb3fef78cd05a51b3b6950f152d93c06.zip | |
mmc: am654_sdhci: Update output tap delay writes
With the latest RIOT, there is a different otap delay value for each
speed mode. Add a new binding with every supported speed mode. Also
disable a given speed mode in the host caps if its corresponding
otap-del-sel is not present.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Diffstat (limited to 'arch/arm/dts/k3-j721e-main.dtsi')
| -rw-r--r-- | arch/arm/dts/k3-j721e-main.dtsi | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi index 45ac98c47e..1433932e7f 100644 --- a/arch/arm/dts/k3-j721e-main.dtsi +++ b/arch/arm/dts/k3-j721e-main.dtsi @@ -232,9 +232,14 @@ assigned-clocks = <&k3_clks 91 1>; assigned-clock-parents = <&k3_clks 91 2>; bus-width = <8>; - ti,otap-del-sel = <0x2>; ti,trm-icp = <0x8>; dma-coherent; + mmc-ddr-1_8v; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-hs400 = <0x0>; }; main_sdhci1: sdhci@4fb0000 { @@ -246,7 +251,13 @@ clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; dma-coherent; }; |