summaryrefslogtreecommitdiffstats
path: root/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
diff options
context:
space:
mode:
authorTom Rini <trini@konsulko.com>2021-03-15 12:15:38 -0400
committerTom Rini <trini@konsulko.com>2021-03-15 12:15:38 -0400
commit22fc991dafee0142fc6bf621e7bd558bd58020b4 (patch)
treee5da8826fd735de968519f432864dc1545d96017 /arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
parent1876b390f31afca15de334e499aa071b0bf64a44 (diff)
parent4103e13534141c31e4e9bf40848ab3a61dabce81 (diff)
downloadu-boot-22fc991dafee0142fc6bf621e7bd558bd58020b4.tar.gz
u-boot-22fc991dafee0142fc6bf621e7bd558bd58020b4.tar.xz
u-boot-22fc991dafee0142fc6bf621e7bd558bd58020b4.zip
Merge tag 'v2021.04-rc4' into next
Prepare v2021.04-rc4
Diffstat (limited to 'arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi')
-rw-r--r--arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi105
1 files changed, 105 insertions, 0 deletions
diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
new file mode 100644
index 0000000000..a4487e20c3
--- /dev/null
+++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
+ u-boot,dm-spl;
+};