Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

New for 2020.04
---------------

- New boards
	Embedded Artists COM board
	Xea Board
- Switch to DM:
	Aristainetos boards
	Toradex colibri (DM_ETH)
	iCubox
	GE bx50v3
	mx7dsabre (DM_ETH)
	cx9020
- New features:
	Bootaux with elf files
	Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
	DHCOM i.MX6 PDK
	Engicam
	i.MX8M tools (imx8m_image)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664

2 files changed, 8 insertions, 8 deletions

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 85c65dcb44..183aa40b6d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -98,13 +98,16 @@ int arch_cpu_init(void)
 	/*
 	 * Enable NAND clock
 	 */
-	/* Clear bypass bit */
+	/* Set bypass bit */
 	writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
 		&clkctrl_regs->hw_clkctrl_clkseq_set);
 
-	/* Set GPMI clock to ref_gpmi / 12 */
+	/* Set GPMI clock to ref_xtal / 1 */
+	clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
+	while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
+		;
 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
-		CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
+		CLKCTRL_GPMI_DIV_MASK, 1);
 
 	udelay(1000);
 
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 5b3b51ce15..9168b91f27 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -25,9 +25,7 @@ static bd_t bdata __section(".data");
 
 /*
  * This delay function is intended to be used only in early stage of boot, where
- * clock are not set up yet. The timer used here is reset on every boot and
- * takes a few seconds to roll. The boot doesn't take that long, so to keep the
- * code simple, it doesn't take rolling into consideration.
+ * clock are not set up yet.
  */
 void early_delay(int delay)
 {
@@ -35,8 +33,7 @@ void early_delay(int delay)
 		(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
 
 	uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
-	st += delay;
-	while (st > readl(&digctl_regs->hw_digctl_microseconds))
+	while (readl(&digctl_regs->hw_digctl_microseconds) - st <= delay)
 		;
 }