ARM: UniPhier: move SoC sources to mach-uniphier

Move
arch/arm/cpu/armv7/uniphier/* -> arch/arm/mach-uniphier/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

59 files changed, 0 insertions, 3588 deletions

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index b228ed6a2e..ad22489e1a 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -56,6 +56,5 @@ obj-$(CONFIG_SOCFPGA) += socfpga/
 obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_U8500) += u8500/
-obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
 obj-$(CONFIG_VF610) += vf610/
 obj-$(CONFIG_ZYNQ) += zynq/
diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig
deleted file mode 100644
index 8335685e32..0000000000
--- a/arch/arm/cpu/armv7/uniphier/Kconfig
+++ /dev/null
@@ -1,89 +0,0 @@
-menu "Panasonic UniPhier platform"
-	depends on ARCH_UNIPHIER
-
-config SYS_SOC
-	default "uniphier"
-
-config SYS_CONFIG_NAME
-	default "uniphier"
-
-config UNIPHIER_SMP
-	bool
-
-choice
-	prompt "UniPhier SoC select"
-
-config MACH_PH1_PRO4
-	bool "PH1-Pro4"
-	select UNIPHIER_SMP
-
-config MACH_PH1_LD4
-	bool "PH1-LD4"
-
-config MACH_PH1_SLD8
-	bool "PH1-sLD8"
-
-endchoice
-
-choice
-	prompt "UniPhier Support Card select"
-	optional
-
-config PFC_MICRO_SUPPORT_CARD
-	bool "Support card with PFC CPLD"
-	help
-	  This option provides support for the expansion board with PFC
-	  original address mapping.
-
-	  Say Y to use the on-board UART, Ether, LED devices.
-
-config DCC_MICRO_SUPPORT_CARD
-	bool "Support card with DCC CPLD"
-	help
-	  This option provides support for the expansion board with DCC-
-	  arranged address mapping that is compatible with legacy UniPhier
-	  reference boards.
-
-	  Say Y to use the on-board UART, Ether, LED devices.
-
-endchoice
-
-config SYS_MALLOC_F
-	default y
-
-config SYS_MALLOC_F_LEN
-	default 0x400
-
-config CMD_PINMON
-	bool "Enable boot mode pins monitor command"
-	default y
-	help
-	  The command "pinmon" shows the state of the boot mode pins.
-	  The boot mode pins are latched when the system reset is deasserted
-	  and determine which device the system should load a boot image from.
-
-config CMD_DDRPHY_DUMP
-	bool "Enable dump command of DDR PHY parameters"
-	help
-	  The command "ddrphy" shows the resulting parameters of DDR PHY
-	  training; it is useful for the evaluation of DDR PHY training.
-
-choice
-	prompt "DDR3 Frequency select"
-
-config DDR_FREQ_1600
-	bool "DDR3 1600"
-	depends on MACH_PH1_PRO4 || MACH_PH1_LD4
-
-config DDR_FREQ_1333
-	bool "DDR3 1333"
-	depends on MACH_PH1_LD4 || MACH_PH1_SLD8
-
-endchoice
-
-config DDR_FREQ
-	int
-	default 1333 if DDR_FREQ_1333
-	default 1600 if DDR_FREQ_1600
-
-endmenu
diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile
deleted file mode 100644
index df418dd3c4..0000000000
--- a/arch/arm/cpu/armv7/uniphier/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-
-obj-y += lowlevel_init.o
-obj-y += init_page_table.o
-obj-y += spl.o
-obj-y += ddrphy_training.o
-
-else
-
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += board_early_init_f.o
-obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
-obj-$(CONFIG_MISC_INIT_F) += print_misc_info.o
-obj-y += dram_init.o
-obj-y += board_common.o
-obj-$(CONFIG_BOARD_EARLY_INIT_R) += board_early_init_r.o
-obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o
-obj-y += reset.o
-obj-y += cache_uniphier.o
-obj-$(CONFIG_UNIPHIER_SMP) += smp.o
-obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
-obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
-
-endif
-
-obj-y += timer.o
-
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
-
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
diff --git a/arch/arm/cpu/armv7/uniphier/board_common.c b/arch/arm/cpu/armv7/uniphier/board_common.c
deleted file mode 100644
index 3fb26c6d84..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_common.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/led.h>
-
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
-	led_write(U, B, O, O);
-
-	return 0;
-}
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-
-	gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
-	gd->bd->bi_dram[0].size  = CONFIG_SDRAM0_SIZE;
-	gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
-	gd->bd->bi_dram[1].size  = CONFIG_SDRAM1_SIZE;
-}
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c b/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
deleted file mode 100644
index d25bbaec08..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_early_init_f.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void pin_init(void);
-
-int board_early_init_f(void)
-{
-	led_write(U, 0, , );
-
-	pin_init();
-
-	led_write(U, 1, , );
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c b/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
deleted file mode 100644
index cb7e04fc36..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_early_init_r.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/board.h>
-
-int board_early_init_r(void)
-{
-	uniphier_board_late_init();
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/board_late_init.c b/arch/arm/cpu/armv7/uniphier/board_late_init.c
deleted file mode 100644
index 0622a1e16e..0000000000
--- a/arch/arm/cpu/armv7/uniphier/board_late_init.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <../drivers/mtd/nand/denali.h>
-
-static void nand_denali_wp_disable(void)
-{
-#ifdef CONFIG_NAND_DENALI
-	/*
-	 * Since the boot rom enables the write protection for NAND boot mode,
-	 * it must be disabled somewhere for "nand write", "nand erase", etc.
-	 * The workaround is here to not disturb the Denali NAND controller
-	 * driver just for a really SoC-specific thing.
-	 */
-	void __iomem *denali_reg = (void __iomem *)CONFIG_SYS_NAND_REGS_BASE;
-
-	writel(WRITE_PROTECT__FLAG, denali_reg + WRITE_PROTECT);
-#endif
-}
-
-int board_late_init(void)
-{
-	puts("MODE:  ");
-
-	switch (spl_boot_device()) {
-	case BOOT_DEVICE_MMC1:
-		printf("eMMC Boot\n");
-		setenv("bootmode", "emmcboot");
-		break;
-	case BOOT_DEVICE_NAND:
-		printf("NAND Boot\n");
-		setenv("bootmode", "nandboot");
-		nand_denali_wp_disable();
-		break;
-	case BOOT_DEVICE_NOR:
-		printf("NOR Boot\n");
-		setenv("bootmode", "norboot");
-		break;
-	default:
-		printf("Unsupported Boot Mode\n");
-		return -1;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c b/arch/arm/cpu/armv7/uniphier/cache_uniphier.c
deleted file mode 100644
index e47f977fe5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cache_uniphier.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/armv7.h>
-#include <asm/arch/ssc-regs.h>
-
-#ifdef CONFIG_UNIPHIER_L2CACHE_ON
-static void uniphier_cache_maint_all(u32 operation)
-{
-	/* try until the command is successfully set */
-	do {
-		writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM);
-	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
-	/* wait until the operation is completed */
-	while (readl(SSCOLPQS) != SSCOLPQS_EF)
-		;
-
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
-
-	writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
-	readl(SSCOPE); /* need a read back to confirm */
-}
-
-void v7_outer_cache_flush_all(void)
-{
-	uniphier_cache_maint_all(SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_all(void)
-{
-	uniphier_cache_maint_all(SSCOQM_CM_INV);
-}
-
-static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation)
-{
-	/* try until the command is successfully set */
-	do {
-		writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM);
-		writel(start, SSCOQAD);
-		writel(size, SSCOQSZ);
-
-	} while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE));
-
-	/* wait until the operation is completed */
-	while (readl(SSCOLPQS) != SSCOLPQS_EF)
-		;
-
-	/* clear the complete notification flag */
-	writel(SSCOLPQS_EF, SSCOLPQS);
-}
-
-static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
-{
-	u32 size;
-
-	/*
-	 * If start address is not aligned to cache-line,
-	 * do cache operation for the first cache-line
-	 */
-	start = start & ~(SSC_LINE_SIZE - 1);
-
-	if (start == 0 && end >= (u32)(-SSC_LINE_SIZE)) {
-		/* this means cache operation for all range */
-		uniphier_cache_maint_all(operation);
-		return;
-	}
-
-	/*
-	 * If end address is not aligned to cache-line,
-	 * do cache operation for the last cache-line
-	 */
-	size = (end - start + SSC_LINE_SIZE - 1) & ~(SSC_LINE_SIZE - 1);
-
-	while (size) {
-		u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ?
-						SSC_RANGE_OP_MAX_SIZE : size;
-		__uniphier_cache_maint_range(start, chunk_size, operation);
-
-		start += chunk_size;
-		size -= chunk_size;
-	}
-
-	writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */
-	readl(SSCOPE); /* need a read back to confirm */
-}
-
-void v7_outer_cache_flush_range(u32 start, u32 end)
-{
-	uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV);
-}
-
-void v7_outer_cache_inval_range(u32 start, u32 end)
-{
-	uniphier_cache_maint_range(start, end, SSCOQM_CM_INV);
-}
-
-void v7_outer_cache_enable(void)
-{
-	u32 tmp;
-	tmp = readl(SSCC);
-	tmp |= SSCC_ON;
-	writel(tmp, SSCC);
-}
-#endif
-
-void v7_outer_cache_disable(void)
-{
-	u32 tmp;
-	tmp = readl(SSCC);
-	tmp &= ~SSCC_ON;
-	writel(tmp, SSCC);
-}
-
-void wakeup_secondary(void);
-
-void enable_caches(void)
-{
-	uint32_t reg;
-
-#ifdef CONFIG_UNIPHIER_SMP
-	/*
-	 * The secondary CPU must move to DDR,
-	 * before L2 disable.
-	 * On SPL, the Page Table is located on the L2.
-	 */
-	wakeup_secondary();
-#endif
-	/*
-	 * UniPhier SoCs must use L2 cache for init stack pointer.
-	 * We disable L2 and L1 in this order.
-	 * If CONFIG_SYS_DCACHE_OFF is not defined,
-	 * caches are enabled again with a new page table.
-	 */
-
-	/* L2 disable */
-	v7_outer_cache_disable();
-
-	/* L1 disable */
-	reg = get_cr();
-	reg &= ~(CR_C | CR_M);
-	set_cr(reg);
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-	dcache_enable();
-#endif
-}
diff --git a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c b/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c
deleted file mode 100644
index 431d9010f1..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-/* Select either decimal or hexadecimal */
-#if 1
-#define PRINTF_FORMAT "%2d"
-#else
-#define PRINTF_FORMAT "%02x"
-#endif
-/* field separator */
-#define FS "   "
-
-static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
-{
-	return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
-}
-
-static void dump_loop(void (*callback)(struct ddrphy_datx8 __iomem *))
-{
-	int ch, p, dx;
-	struct ddrphy __iomem *phy;
-
-	for (ch = 0; ch < NR_DDRCH; ch++) {
-		for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
-			phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
-			for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
-				printf("CH%dP%dDX%d:", ch, p, dx);
-				(*callback)(&phy->dx[dx]);
-				printf("\n");
-			}
-		}
-	}
-}
-
-static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
-	int i;
-
-	for (i = 0; i < 10; i++)
-		printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
-	printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
-}
-
-void wbdl_dump(void)
-{
-	printf("\n--- Write Bit Delay Line ---\n");
-	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");
-
-	dump_loop(&__wbdl_dump);
-}
-
-static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
-	int i;
-
-	for (i = 15; i < 24; i++)
-		printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
-	printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
-}
-
-void rbdl_dump(void)
-{
-	printf("\n--- Read Bit Delay Line ---\n");
-	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD)\n");
-
-	dump_loop(&__rbdl_dump);
-}
-
-static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
-{
-	int rank;
-	u32 lcdlr0 = readl(&dx->lcdlr[0]);
-	u32 gtr = readl(&dx->gtr);
-
-	for (rank = 0; rank < 4; rank++) {
-		u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
-		u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
-
-		printf(FS PRINTF_FORMAT "%sT", wld,
-		       wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
-	}
-}
-
-void wld_dump(void)
-{
-	printf("\n--- Write Leveling Delay ---\n");
-	printf("            Rank0   Rank1   Rank2   Rank3\n");
-
-	dump_loop(&__wld_dump);
-}
-
-static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
-{
-	int rank;
-	u32 lcdlr2 = readl(&dx->lcdlr[2]);
-	u32 gtr = readl(&dx->gtr);
-
-	for (rank = 0; rank < 4; rank++) {
-		u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
-		u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
-
-		printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
-	}
-}
-
-void dqsgd_dump(void)
-{
-	printf("\n--- DQS Gating Delay ---\n");
-	printf("            Rank0   Rank1   Rank2   Rank3\n");
-
-	dump_loop(&__dqsgd_dump);
-}
-
-static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
-{
-	int i;
-	u32 mdl = readl(&dx->mdlr);
-	for (i = 0; i < 3; i++)
-		printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
-}
-
-void mdl_dump(void)
-{
-	printf("\n--- Master Delay Line ---\n");
-	printf("          IPRD TPRD MDLD\n");
-
-	dump_loop(&__mdl_dump);
-}
-
-#define REG_DUMP(x) \
-	{ u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
-					p - (u32 *)phy, #x, p, readl(p)); }
-
-void reg_dump(void)
-{
-	int ch, p;
-	struct ddrphy __iomem *phy;
-
-	printf("\n--- DDR PHY registers ---\n");
-
-	for (ch = 0; ch < NR_DDRCH; ch++) {
-		for (p = 0; p < NR_DDRPHY_PER_CH; p++) {
-			printf("== Ch%d, PHY%d ==\n", ch, p);
-			printf(" No: Name      : Address  : Data\n");
-
-			phy = (struct ddrphy __iomem *)DDRPHY_BASE(ch, p);
-
-			REG_DUMP(ridr);
-			REG_DUMP(pir);
-			REG_DUMP(pgcr[0]);
-			REG_DUMP(pgcr[1]);
-			REG_DUMP(pgsr[0]);
-			REG_DUMP(pgsr[1]);
-			REG_DUMP(pllcr);
-			REG_DUMP(ptr[0]);
-			REG_DUMP(ptr[1]);
-			REG_DUMP(ptr[2]);
-			REG_DUMP(ptr[3]);
-			REG_DUMP(ptr[4]);
-			REG_DUMP(acmdlr);
-			REG_DUMP(acbdlr);
-			REG_DUMP(dxccr);
-			REG_DUMP(dsgcr);
-			REG_DUMP(dcr);
-			REG_DUMP(dtpr[0]);
-			REG_DUMP(dtpr[1]);
-			REG_DUMP(dtpr[2]);
-			REG_DUMP(mr0);
-			REG_DUMP(mr1);
-			REG_DUMP(mr2);
-			REG_DUMP(mr3);
-			REG_DUMP(dx[0].gcr);
-			REG_DUMP(dx[0].gtr);
-			REG_DUMP(dx[1].gcr);
-			REG_DUMP(dx[1].gtr);
-		}
-	}
-}
-
-static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char *cmd = argv[1];
-
-	if (argc == 1)
-		cmd = "all";
-
-	if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
-		wbdl_dump();
-
-	if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
-		rbdl_dump();
-
-	if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
-		wld_dump();
-
-	if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
-		dqsgd_dump();
-
-	if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
-		mdl_dump();
-
-	if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
-		reg_dump();
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	ddr,	2,	1,	do_ddr,
-	"UniPhier DDR PHY parameters dumper",
-	"- dump all of the followings\n"
-	"ddr wbdl - dump Write Bit Delay\n"
-	"ddr rbdl - dump Read Bit Delay\n"
-	"ddr wld - dump Write Leveling\n"
-	"ddr dqsgd - dump DQS Gating Delay\n"
-	"ddr mdl - dump Master Delay Line\n"
-	"ddr reg - dump registers\n"
-);
diff --git a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c b/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
deleted file mode 100644
index 3c1b325976..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cmd_pinmon.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/arch/boot-device.h>
-#include <asm/arch/sbc-regs.h>
-
-static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int mode_sel, i;
-
-	printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
-
-	mode_sel = get_boot_mode_sel();
-
-	puts("Boot Mode Pin:\n");
-
-	for (i = 0; boot_device_table[i].info; i++)
-		printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
-		       boot_device_table[i].info);
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	pinmon,	1,	1,	do_pinmon,
-	"pin monitor",
-	""
-);
diff --git a/arch/arm/cpu/armv7/uniphier/cpu_info.c b/arch/arm/cpu/armv7/uniphier/cpu_info.c
deleted file mode 100644
index 86d079ad56..0000000000
--- a/arch/arm/cpu/armv7/uniphier/cpu_info.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2013-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-int print_cpuinfo(void)
-{
-	u32 revision, type, model, rev, required_model = 1, required_rev = 1;
-
-	revision = readl(SG_REVISION);
-	type = (revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT;
-	model = (revision & SG_REVISION_MODEL_MASK) >> SG_REVISION_MODEL_SHIFT;
-	rev = (revision & SG_REVISION_REV_MASK) >> SG_REVISION_REV_SHIFT;
-
-	puts("CPU:   ");
-
-	switch (type) {
-	case 0x25:
-		puts("PH1-sLD3 (MN2WS0220)");
-		required_model = 2;
-		break;
-	case 0x26:
-		puts("PH1-LD4 (MN2WS0250)");
-		required_rev = 2;
-		break;
-	case 0x28:
-		puts("PH1-Pro4 (MN2WS0230)");
-		break;
-	case 0x29:
-		puts("PH1-sLD8 (MN2WS0270)");
-		break;
-	default:
-		printf("Unknown Processor ID (0x%x)\n", revision);
-		return -1;
-	}
-
-	if (model > 1)
-		printf(" model %d", model);
-
-	printf(" (rev. %d)\n", rev);
-
-	if (model < required_model) {
-		printf("Sorry, this model is not supported.\n");
-		printf("Required model is %d.", required_model);
-		return -1;
-	} else if (rev < required_rev) {
-		printf("Sorry, this revision is not supported.\n");
-		printf("Required revision is %d.", required_rev);
-		return -1;
-	}
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c b/arch/arm/cpu/armv7/uniphier/ddrphy_training.c
deleted file mode 100644
index cc8b8ad648..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ddrphy_training.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
-{
-	int dx;
-	u32 __iomem tmp, *p;
-
-	for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
-		p = &phy->dx[dx].gcr;
-
-		tmp = readl(p);
-		/* Specify the rank that should be write leveled */
-		tmp &= ~DXGCR_WLRKEN_MASK;
-		tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
-		writel(tmp, p);
-	}
-
-	p = &phy->dtcr;
-
-	tmp = readl(p);
-	/* Specify the rank used during data bit deskew and eye centering */
-	tmp &= ~DTCR_DTRANK_MASK;
-	tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
-	/* Use Multi-Purpose Register for DQS gate training */
-	tmp |= DTCR_DTMPR;
-	/* Specify the rank enabled for data-training */
-	tmp &= ~DTCR_RNKEN_MASK;
-	tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK;
-	writel(tmp, p);
-}
-
-struct ddrphy_init_sequence {
-	char *description;
-	u32 init_flag;
-	u32 done_flag;
-	u32 err_flag;
-};
-
-static struct ddrphy_init_sequence init_sequence[] = {
-	{
-		"DRAM Initialization",
-		PIR_DRAMRST | PIR_DRAMINIT,
-		PGSR0_DIDONE,
-		PGSR0_DIERR
-	},
-	{
-		"Write Leveling",
-		PIR_WL,
-		PGSR0_WLDONE,
-		PGSR0_WLERR
-	},
-	{
-		"Read DQS Gate Training",
-		PIR_QSGATE,
-		PGSR0_QSGDONE,
-		PGSR0_QSGERR
-	},
-	{
-		"Write Leveling Adjustment",
-		PIR_WLADJ,
-		PGSR0_WLADONE,
-		PGSR0_WLAERR
-	},
-	{
-		"Read Bit Deskew",
-		PIR_RDDSKW,
-		PGSR0_RDDONE,
-		PGSR0_RDERR
-	},
-	{
-		"Write Bit Deskew",
-		PIR_WRDSKW,
-		PGSR0_WDDONE,
-		PGSR0_WDERR
-	},
-	{
-		"Read Eye Training",
-		PIR_RDEYE,
-		PGSR0_REDONE,
-		PGSR0_REERR
-	},
-	{
-		"Write Eye Training",
-		PIR_WREYE,
-		PGSR0_WEDONE,
-		PGSR0_WEERR
-	}
-};
-
-int ddrphy_training(struct ddrphy __iomem *phy)
-{
-	int i;
-	u32 pgsr0;
-	u32 init_flag = PIR_INIT;
-	u32 done_flag = PGSR0_IDONE;
-	int timeout = 50000; /* 50 msec is long enough */
-#ifdef DISPLAY_ELAPSED_TIME
-	ulong start = get_timer(0);
-#endif
-
-	for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
-		init_flag |= init_sequence[i].init_flag;
-		done_flag |= init_sequence[i].done_flag;
-	}
-
-	writel(init_flag, &phy->pir);
-
-	do {
-		if (--timeout < 0) {
-#ifndef CONFIG_SPL_BUILD
-			printf("%s: error: timeout during DDR training\n",
-								__func__);
-#endif
-			return -1;
-		}
-		udelay(1);
-		pgsr0 = readl(&phy->pgsr[0]);
-	} while ((pgsr0 & done_flag) != done_flag);
-
-	for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
-		if (pgsr0 & init_sequence[i].err_flag) {
-#ifndef CONFIG_SPL_BUILD
-			printf("%s: error: %s failed\n", __func__,
-						init_sequence[i].description);
-#endif
-			return -1;
-		}
-	}
-
-#ifdef DISPLAY_ELAPSED_TIME
-	printf("%s: info: elapsed time %ld msec\n", get_timer(start));
-#endif
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/dram_init.c b/arch/arm/cpu/armv7/uniphier/dram_init.c
deleted file mode 100644
index 4b8c938b5e..0000000000
--- a/arch/arm/cpu/armv7/uniphier/dram_init.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-
-int dram_init(void)
-{
-	DECLARE_GLOBAL_DATA_PTR;
-	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
-
-	return 0;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/init_page_table.S b/arch/arm/cpu/armv7/uniphier/init_page_table.S
deleted file mode 100644
index 2638bcd779..0000000000
--- a/arch/arm/cpu/armv7/uniphier/init_page_table.S
+++ /dev/null
@@ -1,26 +0,0 @@
-#include <config.h>
-#include <linux/linkage.h>
-
-/* page table */
-#define NR_SECTIONS	4096
-#define SECTION_SHIFT	20
-#define DEVICE	0x00002002 /* Non-shareable Device */
-#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
-
-#define TEXT_SECTION	((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
-#define STACK_SECTION	((CONFIG_SYS_INIT_SP_ADDR) >> (SECTION_SHIFT))
-
-	.section ".rodata"
-	.align 14
-ENTRY(init_page_table)
-	section = 0
-	.rept NR_SECTIONS
-	.if section == TEXT_SECTION || section == STACK_SECTION
-	attr = NORMAL
-	.else
-	attr = DEVICE
-	.endif
-	.word (section << SECTION_SHIFT) | attr
-	section = section + 1
-	.endr
-END(init_page_table)
diff --git a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S b/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
deleted file mode 100644
index c208ab67a1..0000000000
--- a/arch/arm/cpu/armv7/uniphier/lowlevel_init.S
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/arch/led.h>
-#include <asm/arch/arm-mpcore.h>
-#include <asm/arch/sbc-regs.h>
-
-ENTRY(lowlevel_init)
-	mov	r8, lr			@ persevere link reg across call
-
-	/*
-	 * The UniPhier Boot ROM loads SPL code to the L2 cache.
-	 * But CPUs can only do instruction fetch now because start.S has
-	 * cleared C and M bits.
-	 * First we need to turn on MMU and Dcache again to get back
-	 * data access to L2.
-	 */
-	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR (System Contrl Register)
-	orr	r0, r0, #(CR_C | CR_M)		@ enable MMU and Dcache
-	mcr	p15, 0, r0, c1, c0, 0
-
-#ifdef CONFIG_DEBUG_LL
-	bl	setup_lowlevel_debug
-#endif
-
-	/*
-	 * Now we are using the page table embedded in the Boot ROM.
-	 * It is not handy since it is not a straight mapped table for sLD3.
-	 * What we need to do next is to switch over to the page table in SPL.
-	 */
-	ldr	r3, =init_page_table	@ page table must be 16KB aligned
-
-	/* Disable MMU and Dcache before switching Page Table */
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
-	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
-	mcr	p15, 0, r0, c1, c0, 0
-
-	bl	enable_mmu
-
-#ifdef CONFIG_UNIPHIER_SMP
-	/*
-	 * ACTLR (Auxiliary Control Register) for Cortex-A9
-	 * bit[9]  Parity on
-	 * bit[8]  Alloc in one way
-	 * bit[7]  EXCL (Exclusive cache bit)
-	 * bit[6]  SMP
-	 * bit[3]  Write full line of zeros mode
-	 * bit[2]  L1 Prefetch enable
-	 * bit[1]  L2 prefetch enable
-	 * bit[0]  FW (Cache and TLB maintenance broadcast)
-	 */
-	mrc	p15, 0, r0, c1, c0, 1	@ ACTLR (Auxiliary Control Register)
-	orr	r0, r0, #0x41		@ enable SMP, FW bit
-	mcr	p15, 0, r0, c1, c0, 1
-
-	/* branch by CPU ID */
-	mrc	p15, 0, r0, c0, c0, 5	@ MPIDR (Multiprocessor Affinity Register)
-	and  	r0, r0, #0x3
-	cmp	r0, #0x0
-	beq	primary_cpu
-	ldr	r1, =ROM_BOOT_ROMRSV2
-	mov	r0, #0
-	str	r0, [r1]
-0:	wfe
-	ldr	r0, [r1]
-	cmp	r0, #0
-	beq	0b
-	bx	r0			@ r0: entry point of U-Boot main for the secondary CPU
-primary_cpu:
-	ldr	r1, =ROM_BOOT_ROMRSV2
-	ldr	r0, =_start		@ entry for the secondary CPU
-	str	r0, [r1]
-	ldr	r0, [r1]		@ make sure str is complete before sev
-	sev				@ kick the sedoncary CPU
-	mrc	p15, 4, r1, c15, c0, 0	@ Configuration Base Address Register
-	bfc	r1, #0, #13		@ clear bit 12-0
-	mov	r0, #-1
-	str	r0, [r1, #SCU_INV_ALL]	@ SCU Invalidate All Register
-	mov	r0, #1			@ SCU enable
-	str	r0, [r1, #SCU_CTRL]	@ SCU Control Register
-#endif
-
-	bl	setup_init_ram		@ RAM area for temporary stack pointer
-
-	mov	lr, r8			@ restore link
-	mov	pc, lr			@ back to my caller
-ENDPROC(lowlevel_init)
-
-ENTRY(enable_mmu)
-	mrc	p15, 0, r0, c2, c0, 2	@ TTBCR (Translation Table Base Control Register)
-	bic	r0, r0, #0x37
-	orr	r0, r0, #0x20		@ disable TTBR1
-	mcr	p15, 0, r0, c2, c0, 2
-
-	orr	r0, r3, #0x8		@ Outer Cacheability for table walks: WBWA
-	mcr	p15, 0, r0, c2, c0, 0   @ TTBR0
-
-	mov	r0, #0
-	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
-
-	mov	r0, #-1			@ manager for all domains (No permission check)
-	mcr	p15, 0, r0, c3, c0, 0   @ DACR (Domain Access Control Register)
-
-	dsb
-	isb
-	/*
-	 * MMU on:
-	 * TLBs was already invalidated in "../start.S"
-	 * So, we don't need to invalidate it here.
-	 */
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
-	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
-	mcr	p15, 0, r0, c1, c0, 0
-
-	mov	pc, lr
-ENDPROC(enable_mmu)
-
-#include <asm/arch/ssc-regs.h>
-
-#define BOOT_RAM_SIZE    (SSC_WAY_SIZE)
-#define BOOT_WAY_BITS    (0x00000100)   /* way 8 */
-
-ENTRY(setup_init_ram)
-	/*
-	 * Touch to zero for the boot way
-	 */
-0:
-	/*
-	 * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order
-	 */
-	ldr	r0, = 0x00408006	@ touch to zero with address range
-	ldr	r1, = SSCOQM
-	str	r0, [r1]
-	ldr	r0, = (CONFIG_SYS_INIT_SP_ADDR - BOOT_RAM_SIZE)	@ base address
-	ldr	r1, = SSCOQAD
-	str	r0, [r1]
-	ldr	r0, = BOOT_RAM_SIZE
-	ldr	r1, = SSCOQSZ
-	str	r0, [r1]
-	ldr	r0, = BOOT_WAY_BITS
-	ldr	r1, = SSCOQWN
-	str	r0, [r1]
-	ldr	r1, = SSCOPPQSEF
-	ldr	r0, [r1]
-	cmp	r0, #0			@ check if the command is successfully set
-	bne	0b			@ try again if an error occurres
-
-	ldr	r1, = SSCOLPQS
-1:
-	ldr	r0, [r1]
-	cmp	r0, #0x4
-	bne	1b			@ wait until the operation is completed
-	str	r0, [r1]		@ clear the complete notification flag
-
-	mov	pc, lr
-ENDPROC(setup_init_ram)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
deleted file mode 100644
index 72f46636fd..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
-	pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
deleted file mode 100644
index 85f37f299b..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/bcu-regs.h>
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-void bcu_init(void)
-{
-	int shift;
-
-	writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
-	writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
-	writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
-	writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
-	writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
-
-	/* Specify DDR channel */
-	shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
-	writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
-	shift -= 32;
-	writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
-	shift -= 32;
-	writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
deleted file mode 100644
index d359b56291..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
deleted file mode 100644
index 18965a94c5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
-	u32 tmp;
-
-	/* deassert reset */
-	tmp = readl(SC_RSTCTRL);
-	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
-	writel(tmp, SC_RSTCTRL);
-	readl(SC_RSTCTRL); /* dummy read */
-
-	/* privide clocks */
-	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
-	writel(tmp, SC_CLKCTRL);
-	readl(SC_CLKCTRL); /* dummy read */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c
deleted file mode 100644
index 60fc5ad6ea..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
-	u32 tmp;
-
-	writel(0x0300c473, &phy->pgcr[1]);
-	if (freq == 1333) {
-		writel(0x0a806844, &phy->ptr[0]);
-		writel(0x208e0124, &phy->ptr[1]);
-	} else {
-		writel(0x0c807d04, &phy->ptr[0]);
-		writel(0x2710015E, &phy->ptr[1]);
-	}
-	writel(0x00083DEF, &phy->ptr[2]);
-	if (freq == 1333) {
-		writel(0x0f051616, &phy->ptr[3]);
-		writel(0x06ae08d6, &phy->ptr[4]);
-	} else {
-		writel(0x12061A80, &phy->ptr[3]);
-		writel(0x08027100, &phy->ptr[4]);
-	}
-	writel(0xF004001A, &phy->dsgcr);
-
-	/* change the value of the on-die pull-up/pull-down registors */
-	tmp = readl(&phy->dxccr);
-	tmp &= ~0x0ee0;
-	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
-	writel(tmp, &phy->dxccr);
-
-	writel(0x0000040B, &phy->dcr);
-	if (freq == 1333) {
-		writel(0x85589955, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a8253c0, &phy->dtpr[1]);
-		else
-			writel(0x1a8363c0, &phy->dtpr[1]);
-		writel(0x5002c200, &phy->dtpr[2]);
-		writel(0x00000b51, &phy->mr0);
-	} else {
-		writel(0x999cbb66, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a82dbc0, &phy->dtpr[1]);
-		else
-			writel(0x1a878400, &phy->dtpr[1]);
-		writel(0xa00214f8, &phy->dtpr[2]);
-		writel(0x00000d71, &phy->mr0);
-	}
-	writel(0x00000006, &phy->mr1);
-	if (freq == 1333)
-		writel(0x00000290, &phy->mr2);
-	else
-		writel(0x00000298, &phy->mr2);
-
-	writel(0x00000800, &phy->mr3);
-
-	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
-		;
-
-	writel(0x0300C473, &phy->pgcr[1]);
-	writel(0x0000005D, &phy->zq[0].cr[1]);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
deleted file mode 100644
index c0778a0abb..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK		36864000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
-		init_debug_uart	r0, r1, r2
-
-		/* UART Port 0 */
-		set_pinsel	85, 1, r0, r1
-		set_pinsel	88, 1, r0, r1
-
-		ldr		r0, =SG_IECTRL
-		ldr		r1, [r0]
-		orr		r1, r1, #1
-		str		r1, [r0]
-
-		mov		pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
deleted file mode 100644
index a7429402f3..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
-	u32 tmp;
-
-	/* Comment format:    PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
-	sg_set_pinsel(85, 1);	/* HSDOUT3 -> RXD0 */
-	sg_set_pinsel(88, 1);	/* HDDOUT6 -> TXD0 */
-
-	sg_set_pinsel(69, 23);	/* PCIOWR -> TXD1 */
-	sg_set_pinsel(70, 23);	/* PCIORD -> RXD1 */
-
-	sg_set_pinsel(128, 13);	/* XIRQ6 -> TXD2 */
-	sg_set_pinsel(129, 13);	/* XIRQ7 -> RXD2 */
-
-	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
-	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
-#endif
-
-#ifdef CONFIG_NAND_DENALI
-	sg_set_pinsel(158, 0);	/* XNFRE -> XNFRE_GB */
-	sg_set_pinsel(159, 0);	/* XNFWE -> XNFWE_GB */
-	sg_set_pinsel(160, 0);	/* XFALE -> NFALE_GB */
-	sg_set_pinsel(161, 0);	/* XFCLE -> NFCLE_GB */
-	sg_set_pinsel(162, 0);	/* XNFWP -> XFNWP_GB */
-	sg_set_pinsel(163, 0);	/* XNFCE0 -> XNFCE0_GB */
-	sg_set_pinsel(164, 0);	/* NANDRYBY0 -> NANDRYBY0_GB */
-	sg_set_pinsel(22, 0);	/* MMCCLK  -> XFNCE1_GB */
-	sg_set_pinsel(23, 0);	/* MMCCMD  -> NANDRYBY1_GB */
-	sg_set_pinsel(24, 0);	/* MMCDAT0 -> NFD0_GB */
-	sg_set_pinsel(25, 0);	/* MMCDAT1 -> NFD1_GB */
-	sg_set_pinsel(26, 0);	/* MMCDAT2 -> NFD2_GB */
-	sg_set_pinsel(27, 0);	/* MMCDAT3 -> NFD3_GB */
-	sg_set_pinsel(28, 0);	/* MMCDAT4 -> NFD4_GB */
-	sg_set_pinsel(29, 0);	/* MMCDAT5 -> NFD5_GB */
-	sg_set_pinsel(30, 0);	/* MMCDAT6 -> NFD6_GB */
-	sg_set_pinsel(31, 0);	/* MMCDAT7 -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
-	sg_set_pinsel(53, 0);	/* USB0VBUS -> USB0VBUS */
-	sg_set_pinsel(54, 0);	/* USB0OD   -> USB0OD */
-	sg_set_pinsel(55, 0);	/* USB1VBUS -> USB1VBUS */
-	sg_set_pinsel(56, 0);	/* USB1OD   -> USB1OD */
-	/* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
-	/* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
-#endif
-
-	tmp = readl(SG_IECTRL);
-	tmp |= 0x41;
-	writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
deleted file mode 100644
index 9d51299308..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK		36864000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
-	{
-		.base = 0x5a800100,
-	},
-	{
-		.base = 0x5a810100,
-	},
-	{
-		.base = 0x5a820100,
-	},
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
deleted file mode 100644
index b83582fee7..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
-	u32 tmp;
-
-	/*
-	 * Set Frequency
-	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
-	 * to FOUT (DPLLCTRL.bit[29:20])
-	 */
-	tmp = readl(SC_DPLLCTRL);
-	tmp &= ~0x000f0000;
-#if CONFIG_DDR_FREQ == 1600
-	tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
-	tmp |= 0x000d0000;
-#else
-# error "Unknown frequency"
-#endif
-
-#if defined(DPLL_SSC_RATE_1PER)
-	tmp &= ~SC_DPLLCTRL_SSC_RATE;
-#else
-	tmp |= SC_DPLLCTRL_SSC_RATE;
-#endif
-	writel(tmp, SC_DPLLCTRL);
-
-	tmp = readl(SC_DPLLCTRL2);
-	tmp |= SC_DPLLCTRL2_NRSTDS;
-	writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
-	u32 tmp, clk_mode_upll, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
-	tmp = readl(SC_UPLLCTRL);
-	tmp &= ~0x18000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
-		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-			/* AXO: 25MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x0228f5c0;
-		} else {
-			/* AXO: default 24.576MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x02328000;
-		}
-	}
-
-	writel(tmp, SC_UPLLCTRL);
-
-	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
-	tmp |= 0x08000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
-	tmp |= 0x10000000;
-	writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
-	u32 tmp, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* set 1 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-
-	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-		/* AXO: 25MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27BCTRL3);
-	} else {
-		/* AXO: default 24.576MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27BCTRL3);
-	}
-
-	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* set 0 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= ~0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
-	dpll_init();
-	upll_init();
-	vpll_init();
-
-	/*
-	 * Wait 500 usec until dpll get stable
-	 * We wait 10 usec in upll_init() and vpll_init()
-	 * so 20 usec can be saved here.
-	 */
-	udelay(480);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
deleted file mode 100644
index 837b2a891b..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/pll_spectrum.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
deleted file mode 100644
index 4839c943c7..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-	u32 tmp;
-
-	/* system bus output enable */
-	tmp = readl(PC0CTRL);
-	tmp &= 0xfffffcff;
-	writel(tmp, PC0CTRL);
-
-	/* XECS1: sub/boot memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-#if !defined(CONFIG_SPL_BUILD)
-	/* XECS0: boot/sub memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-	/* XECS3: peripherals */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
-	/* base address regsiters */
-	writel(0x0000bc01, SBBASE0);
-	writel(0x0400bc01, SBBASE1);
-	writel(0x0800bf01, SBBASE3);
-
-#if !defined(CONFIG_SPL_BUILD)
-	/* enable access to sub memory when boot swap is on */
-	sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-#endif
-	sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
deleted file mode 100644
index 2cc5df608f..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void sg_init(void)
-{
-	u32 tmp;
-
-	/* Set DDR size */
-	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
-	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
-	tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
-	writel(tmp, SG_MEMCONF);
-
-	/* Input ports must be enabled before deasserting reset of cores */
-	tmp = readl(SG_IECTRL);
-	tmp |= 0x1;
-	writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
deleted file mode 100644
index bbc3dcb3da..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
-	writel(0x00000000, ssif_base + 0x0000b004);
-	writel(0xffffffff, ssif_base + 0x0000c004);
-	writel(0x000fffcf, ssif_base + 0x0000c008);
-	writel(0x00000001, ssif_base + 0x0000b000);
-	writel(0x00000001, ssif_base + 0x0000c000);
-	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
-	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
-	writel(0x00000001, ssif_base + UMC_CPURST);
-	writel(0x00000001, ssif_base + UMC_IDSRST);
-	writel(0x00000001, ssif_base + UMC_IXMRST);
-	writel(0x00000001, ssif_base + UMC_MDMRST);
-	writel(0x00000001, ssif_base + UMC_MDDRST);
-	writel(0x00000001, ssif_base + UMC_SIORST);
-	writel(0x00000001, ssif_base + UMC_VIORST);
-	writel(0x00000001, ssif_base + UMC_FRCRST);
-	writel(0x00000001, ssif_base + UMC_RGLRST);
-	writel(0x00000001, ssif_base + UMC_AIORST);
-	writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			      int size, int freq)
-{
-	if (freq == 1333) {
-		writel(0x45990b11, dramcont + UMC_CMDCTLA);
-		writel(0x16958924, dramcont + UMC_CMDCTLB);
-		writel(0x5101046A, dramcont + UMC_INITCTLA);
-
-		if (size == 1)
-			writel(0x27028B0A, dramcont + UMC_INITCTLB);
-		else if (size == 2)
-			writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
-		writel(0x000FF0FF, dramcont + UMC_INITCTLC);
-		writel(0x00000b51, dramcont + UMC_DRMMR0);
-	} else if (freq == 1600) {
-		writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
-		writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
-		writel(0x5101387F, dramcont + UMC_INITCTLA);
-
-		if (size == 1)
-			writel(0x2F030D3F, dramcont + UMC_INITCTLB);
-		else if (size == 2)
-			writel(0x43030D3F, dramcont + UMC_INITCTLB);
-
-		writel(0x00FF00FF, dramcont + UMC_INITCTLC);
-		writel(0x00000d71, dramcont + UMC_DRMMR0);
-	}
-
-	writel(0x00000006, dramcont + UMC_DRMMR1);
-
-	if (freq == 1333)
-		writel(0x00000290, dramcont + UMC_DRMMR2);
-	else if (freq == 1600)
-		writel(0x00000298, dramcont + UMC_DRMMR2);
-
-	writel(0x00000800, dramcont + UMC_DRMMR3);
-
-	if (freq == 1333) {
-		if (size == 1)
-			writel(0x00240512, dramcont + UMC_SPCCTLA);
-		else if (size == 2)
-			writel(0x00350512, dramcont + UMC_SPCCTLA);
-
-		writel(0x00ff0006, dramcont + UMC_SPCCTLB);
-		writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
-	} else if (freq == 1600) {
-		if (size == 1)
-			writel(0x002B0617, dramcont + UMC_SPCCTLA);
-		else if (size == 2)
-			writel(0x003F0617, dramcont + UMC_SPCCTLA);
-
-		writel(0x00ff0008, dramcont + UMC_SPCCTLB);
-		writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
-	}
-
-	writel(0x04060806, dramcont + UMC_WDATACTL_D0);
-	writel(0x04a02000, dramcont + UMC_DATASET);
-	writel(0x00000000, ca_base + 0x2300);
-	writel(0x00400020, dramcont + UMC_DCCGCTL);
-	writel(0x00000003, dramcont + 0x7000);
-	writel(0x0000000f, dramcont + 0x8000);
-	writel(0x000000c3, dramcont + 0x8004);
-	writel(0x00000071, dramcont + 0x8008);
-	writel(0x0000003b, dramcont + UMC_DICGCTLA);
-	writel(0x020a0808, dramcont + UMC_DICGCTLB);
-	writel(0x00000004, dramcont + UMC_FLOWCTLG);
-	writel(0x80000201, ca_base + 0xc20);
-	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
-	writel(0x00200000, dramcont + UMC_FLOWCTLB);
-	writel(0x00004444, dramcont + UMC_FLOWCTLC);
-	writel(0x200a0a00, dramcont + UMC_SPCSETB);
-	writel(0x00000000, dramcont + UMC_SPCSETD);
-	writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
-	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
-	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
-	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
-	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
-	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
-	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
-	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
-	umc_dram_init_start(dramcont0);
-	umc_dram_init_start(dramcont1);
-	umc_dram_init_poll(dramcont0);
-	umc_dram_init_poll(dramcont1);
-
-	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
-	ddrphy_init(phy0_0, freq, size_ch0);
-
-	ddrphy_prepare_training(phy0_0, 0);
-	ddrphy_training(phy0_0);
-
-	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
-	ddrphy_init(phy1_0, freq, size_ch1);
-
-	ddrphy_prepare_training(phy1_0, 1);
-	ddrphy_training(phy1_0);
-
-	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
-	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
-	umc_start_ssif(ssif_base);
-
-	return 0;
-}
-
-int umc_init(void)
-{
-	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
-					CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
-    (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
-    CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
deleted file mode 100644
index e330fda1ed..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sbc_init.o sg_init.o pll_init.o clkrst_init.o \
-	pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
deleted file mode 100644
index c31b74badd..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <asm/io.h>
-#include <asm/arch/boot-device.h>
-#include <asm/arch/sg-regs.h>
-#include <asm/arch/sbc-regs.h>
-
-struct boot_device_info boot_device_table[] = {
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 4)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize   1MB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize   1MB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 4)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"},
-	{BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{ /* sentinel */ }
-};
-
-int get_boot_mode_sel(void)
-{
-	return (readl(SG_PINMON0) >> 1) & 0x1f;
-}
-
-u32 spl_boot_device(void)
-{
-	int boot_mode;
-
-	if (boot_is_swapped())
-		return BOOT_DEVICE_NOR;
-
-	boot_mode = get_boot_mode_sel();
-
-	return boot_device_table[boot_mode].type;
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
deleted file mode 100644
index 18965a94c5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
-	u32 tmp;
-
-	/* deassert reset */
-	tmp = readl(SC_RSTCTRL);
-	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
-	writel(tmp, SC_RSTCTRL);
-	readl(SC_RSTCTRL); /* dummy read */
-
-	/* privide clocks */
-	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
-	writel(tmp, SC_CLKCTRL);
-	readl(SC_CLKCTRL); /* dummy read */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c
deleted file mode 100644
index c5d1f606cf..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
-	u32 tmp;
-
-	writel(0x0300c473, &phy->pgcr[1]);
-	if (freq == 1333) {
-		writel(0x0a806844, &phy->ptr[0]);
-		writel(0x208e0124, &phy->ptr[1]);
-	} else {
-		writel(0x0c807d04, &phy->ptr[0]);
-		writel(0x2710015E, &phy->ptr[1]);
-	}
-	writel(0x00083DEF, &phy->ptr[2]);
-	if (freq == 1333) {
-		writel(0x0f051616, &phy->ptr[3]);
-		writel(0x06ae08d6, &phy->ptr[4]);
-	} else {
-		writel(0x12061A80, &phy->ptr[3]);
-		writel(0x08027100, &phy->ptr[4]);
-	}
-	writel(0xF004001A, &phy->dsgcr);
-
-	/* change the value of the on-die pull-up/pull-down registors */
-	tmp = readl(&phy->dxccr);
-	tmp &= ~0x0ee0;
-	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
-	writel(tmp, &phy->dxccr);
-
-	writel(0x0000040B, &phy->dcr);
-	if (freq == 1333) {
-		writel(0x85589955, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a8363c0, &phy->dtpr[1]);
-		else
-			writel(0x1a8363c0, &phy->dtpr[1]);
-		writel(0x5002c200, &phy->dtpr[2]);
-		writel(0x00000b51, &phy->mr0);
-	} else {
-		writel(0x999cbb66, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a878400, &phy->dtpr[1]);
-		else
-			writel(0x1a878400, &phy->dtpr[1]);
-		writel(0xa00214f8, &phy->dtpr[2]);
-		writel(0x00000d71, &phy->mr0);
-	}
-	writel(0x00000006, &phy->mr1);
-	if (freq == 1333)
-		writel(0x00000290, &phy->mr2);
-	else
-		writel(0x00000298, &phy->mr2);
-
-	writel(0x00000000, &phy->mr3);
-
-	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
-		;
-
-	writel(0x0300C473, &phy->pgcr[1]);
-	writel(0x0000005D, &phy->zq[0].cr[1]);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
deleted file mode 100644
index a793b7c118..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK		73728000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
-		ldr		r0, =SC_CLKCTRL
-		ldr		r1, [r0]
-		orr		r1, r1, #SC_CLKCTRL_CLK_PERI
-		str		r1, [r0]
-
-		init_debug_uart	r0, r1, r2
-
-		/* UART Port 0 */
-		set_pinsel	127, 0, r0, r1
-		set_pinsel	128, 0, r0, r1
-
-		ldr		r0, =SG_LOADPINCTRL
-		mov		r1, #1
-		str		r1, [r0]
-
-		ldr		r0, =SG_IECTRL
-		ldr		r1, [r0]
-		orr		r1, r1, #1
-		str		r1, [r0]
-
-		mov		pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
deleted file mode 100644
index 4e3d47615b..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
-	/* Comment format:    PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
-	sg_set_pinsel(127, 0);	/* RXD0 -> RXD0 */
-	sg_set_pinsel(128, 0);	/* TXD0 -> TXD0 */
-	sg_set_pinsel(129, 0);	/* RXD1 -> RXD1 */
-	sg_set_pinsel(130, 0);	/* TXD1 -> TXD1 */
-	sg_set_pinsel(131, 0);	/* RXD2 -> RXD2 */
-	sg_set_pinsel(132, 0);	/* TXD2 -> TXD2 */
-	sg_set_pinsel(88, 2);	/* CH6CLK -> RXD3 */
-	sg_set_pinsel(89, 2);	/* CH6VAL -> TXD3 */
-#endif
-
-#ifdef CONFIG_NAND_DENALI
-	sg_set_pinsel(40, 0);	/* NFD0   -> NFD0 */
-	sg_set_pinsel(41, 0);	/* NFD1   -> NFD1 */
-	sg_set_pinsel(42, 0);	/* NFD2   -> NFD2 */
-	sg_set_pinsel(43, 0);	/* NFD3   -> NFD3 */
-	sg_set_pinsel(44, 0);	/* NFD4   -> NFD4 */
-	sg_set_pinsel(45, 0);	/* NFD5   -> NFD5 */
-	sg_set_pinsel(46, 0);	/* NFD6   -> NFD6 */
-	sg_set_pinsel(47, 0);	/* NFD7   -> NFD7 */
-	sg_set_pinsel(48, 0);	/* NFALE  -> NFALE */
-	sg_set_pinsel(49, 0);	/* NFCLE  -> NFCLE */
-	sg_set_pinsel(50, 0);	/* XNFRE  -> XNFRE */
-	sg_set_pinsel(51, 0);	/* XNFWE  -> XNFWE */
-	sg_set_pinsel(52, 0);	/* XNFWP  -> XNFWP */
-	sg_set_pinsel(53, 0);	/* XNFCE0 -> XNFCE0 */
-	sg_set_pinsel(54, 0);	/* NRYBY0 -> NRYBY0 */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
-	sg_set_pinsel(184, 0);	/* USB2VBUS -> USB2VBUS */
-	sg_set_pinsel(185, 0);	/* USB2OD   -> USB2OD */
-	sg_set_pinsel(187, 0);	/* USB3VBUS -> USB3VBUS */
-	sg_set_pinsel(188, 0);	/* USB3OD   -> USB3OD */
-#endif
-
-	writel(1, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
deleted file mode 100644
index 31ee2a2100..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK		73728000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
-	{
-		.base = 0x5a800100,
-	},
-	{
-		.base = 0x5a810100,
-	},
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
deleted file mode 100644
index 1db90f88a0..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-#undef DPLL_SSC_RATE_1PER
-
-static void dpll_init(void)
-{
-	u32 tmp;
-
-	/*
-	 * Set Frequency
-	 * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
-	 * to FOUT ( DPLLCTRL.bit[29:20] )
-	 */
-	tmp = readl(SC_DPLLCTRL);
-	tmp &= ~(0x000f0000);
-#if CONFIG_DDR_FREQ == 1600
-	tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
-	tmp |= 0x000d0000;
-#else
-# error "Unsupported frequency"
-#endif
-
-	/*
-	 * Set Moduration rate
-	 * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
-	 */
-#if defined(DPLL_SSC_RATE_1PER)
-	tmp &= ~0x00008000;
-#else
-	tmp |= 0x00008000;
-#endif
-	writel(tmp, SC_DPLLCTRL);
-
-	tmp = readl(SC_DPLLCTRL2);
-	tmp |= SC_DPLLCTRL2_NRSTDS;
-	writel(tmp, SC_DPLLCTRL2);
-}
-
-static void stop_mpll(void)
-{
-	u32 tmp;
-
-	tmp = readl(SC_MPLLOSCCTL);
-
-	if (!(tmp & SC_MPLLOSCCTL_MPLLST))
-		return; /* already stopped */
-
-	tmp &= ~SC_MPLLOSCCTL_MPLLEN;
-	writel(tmp, SC_MPLLOSCCTL);
-
-	while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
-		;
-}
-
-static void vpll_init(void)
-{
-	u32 tmp, clk_mode_axosel;
-
-	/* Set VPLL27A &  VPLL27B */
-	tmp = readl(SG_PINMON0);
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-#if defined(CONFIG_MACH_PH1_PRO4)
-	/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
-		return;
-#endif
-
-	/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-
-	/* Unset VPLA_K_LD and VPLB_K_LD bit */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Set VPLA_M and VPLB_M to 0x20 */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
-		/* Set VPLA_K and VPLB_K for AXO: 25MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066666;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066666;
-		writel(tmp, SC_VPLL27BCTRL3);
-	} else {
-		/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27BCTRL3);
-	}
-
-	/* wait 1 usec */
-	udelay(1);
-
-	/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Unset VPLA_SNRST and VPLB_SNRST bit */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
-	dpll_init();
-	stop_mpll();
-	vpll_init();
-
-	/*
-	 * Wait 500 usec until dpll get stable
-	 * We wait 1 usec in vpll_init() so 1 usec can be saved here.
-	 */
-	udelay(499);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c
deleted file mode 100644
index 4538d1af44..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void enable_dpll_ssc(void)
-{
-	u32 tmp;
-
-	tmp = readl(SC_DPLLCTRL);
-	tmp |= SC_DPLLCTRL_SSC_EN;
-	writel(tmp, SC_DPLLCTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
deleted file mode 100644
index 3c82a1aca4..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-	/*
-	 * Only CS1 is connected to support card.
-	 * BKSZ[1:0] should be set to "01".
-	 */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
-
-	if (boot_is_swapped()) {
-		/*
-		 * Boot Swap On: boot from external NOR/SRAM
-		 * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
-		 *
-		 * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
-		 * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
-		 */
-		writel(0x0000bc01, SBBASE0);
-	} else {
-		/*
-		 * Boot Swap Off: boot from mask ROM
-		 * 0x00000000-0x01ffffff: mask ROM
-		 * 0x02000000-0x3effffff: memory bank (31MB)
-		 * 0x03f00000-0x3fffffff: peripherals (1MB)
-		 */
-		writel(0x0000be01, SBBASE0); /* dummy */
-		writel(0x0200be01, SBBASE1);
-	}
-#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-#if !defined(CONFIG_SPL_BUILD)
-	/* XECS0: boot/sub memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-	/* XECS1: sub/boot memory (boot swap = off/on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-	/* XECS3: peripherals */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
-	writel(0x0000bc01, SBBASE0); /* boot memory */
-	writel(0x0400bc01, SBBASE1); /* sub memory */
-	writel(0x0800bf01, SBBASE3); /* peripherals */
-
-#if !defined(CONFIG_SPL_BUILD)
-	sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-#endif
-	sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
-	writel(0x00000001, SG_LOADPINCTRL);
-
-#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
deleted file mode 100644
index b7c4b10969..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void sg_init(void)
-{
-	u32 tmp;
-
-	/* Set DDR size */
-	tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
-	tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
-	tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
-	writel(tmp, SG_MEMCONF);
-
-	/* Input ports must be enabled before deasserting reset of cores */
-	tmp = readl(SG_IECTRL);
-	tmp |= 1 << 6;
-	writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
deleted file mode 100644
index 2d1bde6f13..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/umc_init.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
-	writel(0x00000001, ssif_base + 0x0000b004);
-	writel(0xffffffff, ssif_base + 0x0000c004);
-	writel(0x07ffffff, ssif_base + 0x0000c008);
-	writel(0x00000001, ssif_base + 0x0000b000);
-	writel(0x00000001, ssif_base + 0x0000c000);
-
-	writel(0x03010100, ssif_base + UMC_HDMCHSEL);
-	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
-	writel(0x03010100, ssif_base + UMC_DVCCHSEL);
-	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-	writel(0x00000000, ssif_base + 0x0000c044);		/* DCGIV_SSIF_REG */
-
-	writel(0x00000001, ssif_base + UMC_CPURST);
-	writel(0x00000001, ssif_base + UMC_IDSRST);
-	writel(0x00000001, ssif_base + UMC_IXMRST);
-	writel(0x00000001, ssif_base + UMC_HDMRST);
-	writel(0x00000001, ssif_base + UMC_MDMRST);
-	writel(0x00000001, ssif_base + UMC_HDDRST);
-	writel(0x00000001, ssif_base + UMC_MDDRST);
-	writel(0x00000001, ssif_base + UMC_SIORST);
-	writel(0x00000001, ssif_base + UMC_GIORST);
-	writel(0x00000001, ssif_base + UMC_HD2RST);
-	writel(0x00000001, ssif_base + UMC_VIORST);
-	writel(0x00000001, ssif_base + UMC_DVCRST);
-	writel(0x00000001, ssif_base + UMC_RGLRST);
-	writel(0x00000001, ssif_base + UMC_VPERST);
-	writel(0x00000001, ssif_base + UMC_AIORST);
-	writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			      int size, int freq)
-{
-	writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
-	writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
-	writel(0x5101387f, dramcont + UMC_INITCTLA);
-	writel(0x43030d3f, dramcont + UMC_INITCTLB);
-	writel(0x00ff00ff, dramcont + UMC_INITCTLC);
-	writel(0x00000d71, dramcont + UMC_DRMMR0);
-	writel(0x00000006, dramcont + UMC_DRMMR1);
-	writel(0x00000298, dramcont + UMC_DRMMR2);
-	writel(0x00000000, dramcont + UMC_DRMMR3);
-	writel(0x003f0617, dramcont + UMC_SPCCTLA);
-	writel(0x00ff0008, dramcont + UMC_SPCCTLB);
-	writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
-	writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
-	writel(0x04060802, dramcont + UMC_WDATACTL_D0);
-	writel(0x04060802, dramcont + UMC_WDATACTL_D1);
-	writel(0x04a02000, dramcont + UMC_DATASET);
-	writel(0x00000000, ca_base + 0x2300);
-	writel(0x00400020, dramcont + UMC_DCCGCTL);
-	writel(0x0000000f, dramcont + 0x7000);
-	writel(0x0000000f, dramcont + 0x8000);
-	writel(0x000000c3, dramcont + 0x8004);
-	writel(0x00000071, dramcont + 0x8008);
-	writel(0x00000004, dramcont + UMC_FLOWCTLG);
-	writel(0x00000000, dramcont + 0x0060);
-	writel(0x80000201, ca_base + 0xc20);
-	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
-	writel(0x00200000, dramcont + UMC_FLOWCTLB);
-	writel(0x00004444, dramcont + UMC_FLOWCTLC);
-	writel(0x200a0a00, dramcont + UMC_SPCSETB);
-	writel(0x00010000, dramcont + UMC_SPCSETD);
-	writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
-	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
-	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
-	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
-	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
-	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
-	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
-	void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
-	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-	void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
-
-	umc_dram_init_start(dramcont0);
-	umc_dram_init_start(dramcont1);
-	umc_dram_init_poll(dramcont0);
-	umc_dram_init_poll(dramcont1);
-
-	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
-	ddrphy_init(phy0_0, freq, size_ch0);
-
-	ddrphy_prepare_training(phy0_0, 0);
-	ddrphy_training(phy0_0);
-
-	writel(0x00000103, dramcont0 + UMC_DIOCTLA);
-
-	ddrphy_init(phy0_1, freq, size_ch0);
-
-	ddrphy_prepare_training(phy0_1, 1);
-	ddrphy_training(phy0_1);
-
-	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
-	ddrphy_init(phy1_0, freq, size_ch1);
-
-	ddrphy_prepare_training(phy1_0, 0);
-	ddrphy_training(phy1_0);
-
-	writel(0x00000103, dramcont1 + UMC_DIOCTLA);
-
-	ddrphy_init(phy1_1, freq, size_ch1);
-
-	ddrphy_prepare_training(phy1_1, 1);
-	ddrphy_training(phy1_1);
-
-	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
-	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
-	umc_start_ssif(ssif_base);
-
-	return 0;
-}
-
-int umc_init(void)
-{
-	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
-					CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
-     (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
-    ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
-     (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
-/* OK */
-#else
- #error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile b/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
deleted file mode 100644
index 72f46636fd..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
-	pll_spectrum.o umc_init.o ddrphy_init.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
-obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c
deleted file mode 100644
index 69b172e4e7..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/bcu_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/bcu_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c
deleted file mode 100644
index d359b56291..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/boot-mode.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
deleted file mode 100644
index 18965a94c5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void clkrst_init(void)
-{
-	u32 tmp;
-
-	/* deassert reset */
-	tmp = readl(SC_RSTCTRL);
-	tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
-		| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
-	writel(tmp, SC_RSTCTRL);
-	readl(SC_RSTCTRL); /* dummy read */
-
-	/* privide clocks */
-	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
-	     | SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
-	writel(tmp, SC_CLKCTRL);
-	readl(SC_CLKCTRL); /* dummy read */
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c
deleted file mode 100644
index a5eafef9a8..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/ddrphy_init.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/types.h>
-#include <asm/io.h>
-#include <asm/arch/ddrphy-regs.h>
-
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
-{
-	u32 tmp;
-
-	writel(0x0300c473, &phy->pgcr[1]);
-	if (freq == 1333) {
-		writel(0x0a806844, &phy->ptr[0]);
-		writel(0x208e0124, &phy->ptr[1]);
-	} else {
-		writel(0x0c807d04, &phy->ptr[0]);
-		writel(0x2710015E, &phy->ptr[1]);
-	}
-	writel(0x00083DEF, &phy->ptr[2]);
-	if (freq == 1333) {
-		writel(0x0f051616, &phy->ptr[3]);
-		writel(0x06ae08d6, &phy->ptr[4]);
-	} else {
-		writel(0x12061A80, &phy->ptr[3]);
-		writel(0x08027100, &phy->ptr[4]);
-	}
-	writel(0xF004001A, &phy->dsgcr);
-
-	/* change the value of the on-die pull-up/pull-down registors */
-	tmp = readl(&phy->dxccr);
-	tmp &= ~0x0ee0;
-	tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
-	writel(tmp, &phy->dxccr);
-
-	writel(0x0000040B, &phy->dcr);
-	if (freq == 1333) {
-		writel(0x85589955, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a8363c0, &phy->dtpr[1]);
-		else
-			writel(0x1a8363c0, &phy->dtpr[1]);
-		writel(0x5002c200, &phy->dtpr[2]);
-		writel(0x00000b51, &phy->mr0);
-	} else {
-		writel(0x999cbb66, &phy->dtpr[0]);
-		if (size == 1)
-			writel(0x1a878400, &phy->dtpr[1]);
-		else
-			writel(0x1a878400, &phy->dtpr[1]);
-		writel(0xa00214f8, &phy->dtpr[2]);
-		writel(0x00000d71, &phy->mr0);
-	}
-	writel(0x00000006, &phy->mr1);
-	if (freq == 1333)
-		writel(0x00000290, &phy->mr2);
-	else
-		writel(0x00000298, &phy->mr2);
-
-#ifdef CONFIG_DDR_STANDARD
-	writel(0x00000000, &phy->mr3);
-#else
-	writel(0x00000800, &phy->mr3);
-#endif
-
-	while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
-		;
-
-	writel(0x0300C473, &phy->pgcr[1]);
-	writel(0x0000005D, &phy->zq[0].cr[1]);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S
deleted file mode 100644
index a413e5fd8a..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/lowlevel_debug.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <asm/arch/sg-regs.h>
-
-#define UART_CLK		80000000
-#include <asm/arch/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
-		init_debug_uart	r0, r1, r2
-
-		/* UART Port 0 */
-		set_pinsel	70, 3, r0, r1
-		set_pinsel	71, 3, r0, r1
-
-		ldr		r0, =SG_IECTRL
-		ldr		r1, [r0]
-		orr		r1, r1, #1
-		str		r1, [r0]
-
-		mov		pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
deleted file mode 100644
index 5e80335b58..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pinctrl.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sg-regs.h>
-
-void pin_init(void)
-{
-	/* Comment format:    PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
-	sg_set_pinsel(70, 3);	/* HDDOUT0 -> TXD0 */
-	sg_set_pinsel(71, 3);	/* HSDOUT1 -> RXD0 */
-
-	sg_set_pinsel(114, 0);	/* TXD1 -> TXD1 */
-	sg_set_pinsel(115, 0);	/* RXD1 -> RXD1 */
-
-	sg_set_pinsel(112, 1);	/* SBO1 -> TXD2 */
-	sg_set_pinsel(113, 1);	/* SBI1 -> RXD2 */
-
-	sg_set_pinsel(110, 1);	/* SBO0 -> TXD3 */
-	sg_set_pinsel(111, 1);	/* SBI0 -> RXD3 */
-#endif
-
-#ifdef CONFIG_SYS_I2C_UNIPHIER
-	{
-		u32 tmp;
-		tmp = readl(SG_IECTRL);
-		tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
-		writel(tmp, SG_IECTRL);
-	}
-#endif
-
-#ifdef CONFIG_NAND_DENALI
-	sg_set_pinsel(15, 0);	/* XNFRE_GB -> XNFRE_GB */
-	sg_set_pinsel(16, 0);	/* XNFWE_GB -> XNFWE_GB */
-	sg_set_pinsel(17, 0);	/* XFALE_GB -> NFALE_GB */
-	sg_set_pinsel(18, 0);	/* XFCLE_GB -> NFCLE_GB */
-	sg_set_pinsel(19, 0);	/* XNFWP_GB -> XFNWP_GB */
-	sg_set_pinsel(20, 0);	/* XNFCE0_GB -> XNFCE0_GB */
-	sg_set_pinsel(21, 0);	/* NANDRYBY0_GB -> NANDRYBY0_GB */
-	sg_set_pinsel(22, 0);	/* XFNCE1_GB  -> XFNCE1_GB */
-	sg_set_pinsel(23, 0);	/* NANDRYBY1_GB  -> NANDRYBY1_GB */
-	sg_set_pinsel(24, 0);	/* NFD0_GB -> NFD0_GB */
-	sg_set_pinsel(25, 0);	/* NFD1_GB -> NFD1_GB */
-	sg_set_pinsel(26, 0);	/* NFD2_GB -> NFD2_GB */
-	sg_set_pinsel(27, 0);	/* NFD3_GB -> NFD3_GB */
-	sg_set_pinsel(28, 0);	/* NFD4_GB -> NFD4_GB */
-	sg_set_pinsel(29, 0);	/* NFD5_GB -> NFD5_GB */
-	sg_set_pinsel(30, 0);	/* NFD6_GB -> NFD6_GB */
-	sg_set_pinsel(31, 0);	/* NFD7_GB -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
-	sg_set_pinsel(41, 0);	/* USB0VBUS -> USB0VBUS */
-	sg_set_pinsel(42, 0);	/* USB0OD   -> USB0OD */
-	sg_set_pinsel(43, 0);	/* USB1VBUS -> USB1VBUS */
-	sg_set_pinsel(44, 0);	/* USB1OD   -> USB1OD */
-	/* sg_set_pinsel(114, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
-	/* sg_set_pinsel(115, 4); */ /* RXD1 -> USB2OD */
-#endif
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
deleted file mode 100644
index ea0691dd67..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/platdevice.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/platdevice.h>
-
-#define UART_MASTER_CLK		80000000
-
-SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
-SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
-SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
-SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
-
-struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
-	{
-		.base = 0x5a800100,
-	},
-	{
-		.base = 0x5a810100,
-	},
-	{
-		.base = 0x5a820100,
-	},
-};
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
deleted file mode 100644
index 4b82700f44..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_init.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-static void dpll_init(void)
-{
-	u32 tmp;
-	/*
-	 * Set DPLL SSC parameters for DPLLCTRL3
-	 * [23]    DIVN_TEST    0x1
-	 * [22:16] DIVN         0x50
-	 * [10]    FREFSEL_TEST 0x1
-	 * [9:8]   FREFSEL      0x2
-	 * [4]     ICPD_TEST    0x1
-	 * [3:0]   ICPD         0xb
-	 */
-	tmp = readl(SC_DPLLCTRL3);
-	tmp &= ~0x00ff0717;
-	tmp |= 0x00d0061b;
-	writel(tmp, SC_DPLLCTRL3);
-
-	/*
-	 * Set DPLL SSC parameters for DPLLCTRL
-	 *                    <-1%>          <-2%>
-	 * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
-	 * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
-	 */
-	tmp = readl(SC_DPLLCTRL);
-	tmp &= ~0x3ff07fff;
-#ifdef CONFIG_DPLL_SSC_RATE_1PER
-	tmp |= 0x084018bf;
-#else
-	tmp |= 0x084031a6;
-#endif
-	writel(tmp, SC_DPLLCTRL);
-
-	/*
-	 * Set DPLL SSC parameters for DPLLCTRL2
-	 * [31:29]  SSC_STEP     0
-	 * [27]     SSC_REG_REF  1
-	 * [26:20]  SSC_M        79     (0x4f)
-	 * [19:0]   SSC_K        964689 (0xeb851)
-	 */
-	tmp = readl(SC_DPLLCTRL2);
-	tmp &= ~0xefffffff;
-	tmp |= 0x0cfeb851;
-	writel(tmp, SC_DPLLCTRL2);
-}
-
-static void upll_init(void)
-{
-	u32 tmp, clk_mode_upll, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
-	tmp = readl(SC_UPLLCTRL);
-	tmp &= ~0x18000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
-		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-			/* AXO: 25MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x0228f5c0;
-		} else {
-			/* AXO: default 24.576MHz */
-			tmp &= ~0x07ffffff;
-			tmp |= 0x02328000;
-		}
-	}
-
-	writel(tmp, SC_UPLLCTRL);
-
-	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
-	tmp |= 0x08000000;
-	writel(tmp, SC_UPLLCTRL);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
-	tmp |= 0x10000000;
-	writel(tmp, SC_UPLLCTRL);
-}
-
-static void vpll_init(void)
-{
-	u32 tmp, clk_mode_axosel;
-
-	tmp = readl(SG_PINMON0);
-	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-
-	/* set 1 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= 0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-
-	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp &= ~0x0000007f;
-	tmp |= 0x00000020;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
-	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
-		/* AXO: 25MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x00066664;
-		writel(tmp, SC_VPLL27BCTRL3);
-	} else {
-		/* AXO: default 24.576MHz */
-		tmp = readl(SC_VPLL27ACTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27ACTRL3);
-		tmp = readl(SC_VPLL27BCTRL3);
-		tmp &= ~0x000fffff;
-		tmp |= 0x000f5800;
-		writel(tmp, SC_VPLL27BCTRL3);
-	}
-
-	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
-	tmp = readl(SC_VPLL27ACTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL3);
-	tmp = readl(SC_VPLL27BCTRL3);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL3);
-
-	/* wait 10 usec */
-	udelay(10);
-
-	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
-	tmp = readl(SC_VPLL27ACTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27ACTRL2);
-	tmp = readl(SC_VPLL27BCTRL2);
-	tmp |= 0x10000000;
-	writel(tmp, SC_VPLL27BCTRL2);
-
-	/* set 0 to VPLA27WP and VPLA27WP */
-	tmp = readl(SC_VPLL27ACTRL);
-	tmp &= ~0x00000001;
-	writel(tmp, SC_VPLL27ACTRL);
-	tmp = readl(SC_VPLL27BCTRL);
-	tmp |= ~0x00000001;
-	writel(tmp, SC_VPLL27BCTRL);
-}
-
-void pll_init(void)
-{
-	dpll_init();
-	upll_init();
-	vpll_init();
-
-	/*
-	 * Wait 500 usec until dpll get stable
-	 * We wait 10 usec in upll_init() and vpll_init()
-	 * so 20 usec can be saved here.
-	 */
-	udelay(480);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c
deleted file mode 100644
index 9b8c4855e5..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/pll_spectrum.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/pll_spectrum.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
deleted file mode 100644
index 5efee9c505..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sbc_init.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sbc-regs.h>
-#include <asm/arch/sg-regs.h>
-
-void sbc_init(void)
-{
-	u32 tmp;
-
-	/* system bus output enable */
-	tmp = readl(PC0CTRL);
-	tmp &= 0xfffffcff;
-	writel(tmp, PC0CTRL);
-
-#if !defined(CONFIG_SPL_BUILD)
-	/* XECS0 : dummy */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-#endif
-	/* XECS1 : boot memory (always boot swap = on) */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
-	/* XECS4 : sub memory */
-	writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
-	writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
-	writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
-	writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
-
-	/* XECS5 : peripherals */
-	writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
-	writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
-	writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
-	writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
-
-	/* base address regsiters */
-	writel(0x0000bc01, SBBASE0); /* boot memory */
-	writel(0x0900bfff, SBBASE1); /* dummy */
-	writel(0x0400bc01, SBBASE4); /* sub memory */
-	writel(0x0800bf01, SBBASE5); /* peripherals */
-
-	sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
-	sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
-
-	/* dummy read to assure write process */
-	readl(SG_PINCTRL(33));
-}
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c
deleted file mode 100644
index a808289a56..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/sg_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/sg_init.c"
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c b/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
deleted file mode 100644
index 2fbc73ab03..0000000000
--- a/arch/arm/cpu/armv7/uniphier/ph1-sld8/umc_init.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/umc-regs.h>
-#include <asm/arch/ddrphy-regs.h>
-
-static void umc_start_ssif(void __iomem *ssif_base)
-{
-	writel(0x00000000, ssif_base + 0x0000b004);
-	writel(0xffffffff, ssif_base + 0x0000c004);
-	writel(0x000fffcf, ssif_base + 0x0000c008);
-	writel(0x00000001, ssif_base + 0x0000b000);
-	writel(0x00000001, ssif_base + 0x0000c000);
-	writel(0x03010101, ssif_base + UMC_MDMCHSEL);
-	writel(0x03010100, ssif_base + UMC_DMDCHSEL);
-
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
-	writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
-
-	writel(0x00000001, ssif_base + UMC_CPURST);
-	writel(0x00000001, ssif_base + UMC_IDSRST);
-	writel(0x00000001, ssif_base + UMC_IXMRST);
-	writel(0x00000001, ssif_base + UMC_MDMRST);
-	writel(0x00000001, ssif_base + UMC_MDDRST);
-	writel(0x00000001, ssif_base + UMC_SIORST);
-	writel(0x00000001, ssif_base + UMC_VIORST);
-	writel(0x00000001, ssif_base + UMC_FRCRST);
-	writel(0x00000001, ssif_base + UMC_RGLRST);
-	writel(0x00000001, ssif_base + UMC_AIORST);
-	writel(0x00000001, ssif_base + UMC_DMDRST);
-}
-
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			      int size, int freq)
-{
-#ifdef CONFIG_DDR_STANDARD
-	writel(0x55990b11, dramcont + UMC_CMDCTLA);
-	writel(0x16958944, dramcont + UMC_CMDCTLB);
-#else
-	writel(0x45990b11, dramcont + UMC_CMDCTLA);
-	writel(0x16958924, dramcont + UMC_CMDCTLB);
-#endif
-
-	writel(0x5101046A, dramcont + UMC_INITCTLA);
-
-	if (size == 1)
-		writel(0x27028B0A, dramcont + UMC_INITCTLB);
-	else if (size == 2)
-		writel(0x38028B0A, dramcont + UMC_INITCTLB);
-
-	writel(0x00FF00FF, dramcont + UMC_INITCTLC);
-	writel(0x00000b51, dramcont + UMC_DRMMR0);
-	writel(0x00000006, dramcont + UMC_DRMMR1);
-	writel(0x00000290, dramcont + UMC_DRMMR2);
-
-#ifdef CONFIG_DDR_STANDARD
-	writel(0x00000000, dramcont + UMC_DRMMR3);
-#else
-	writel(0x00000800, dramcont + UMC_DRMMR3);
-#endif
-
-	if (size == 1)
-		writel(0x00240512, dramcont + UMC_SPCCTLA);
-	else if (size == 2)
-		writel(0x00350512, dramcont + UMC_SPCCTLA);
-
-	writel(0x00ff0006, dramcont + UMC_SPCCTLB);
-	writel(0x000a00ac, dramcont + UMC_RDATACTL_D0);
-	writel(0x04060806, dramcont + UMC_WDATACTL_D0);
-	writel(0x04a02000, dramcont + UMC_DATASET);
-	writel(0x00000000, ca_base + 0x2300);
-	writel(0x00400020, dramcont + UMC_DCCGCTL);
-	writel(0x00000003, dramcont + 0x7000);
-	writel(0x0000004f, dramcont + 0x8000);
-	writel(0x000000c3, dramcont + 0x8004);
-	writel(0x00000077, dramcont + 0x8008);
-	writel(0x0000003b, dramcont + UMC_DICGCTLA);
-	writel(0x020a0808, dramcont + UMC_DICGCTLB);
-	writel(0x00000004, dramcont + UMC_FLOWCTLG);
-	writel(0x80000201, ca_base + 0xc20);
-	writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
-	writel(0x00200000, dramcont + UMC_FLOWCTLB);
-	writel(0x00004444, dramcont + UMC_FLOWCTLC);
-	writel(0x200a0a00, dramcont + UMC_SPCSETB);
-	writel(0x00000000, dramcont + UMC_SPCSETD);
-	writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
-}
-
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
-{
-	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
-	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
-	void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1);
-	void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0);
-	void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1);
-	void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0);
-	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
-
-	umc_dram_init_start(dramcont0);
-	umc_dram_init_start(dramcont1);
-	umc_dram_init_poll(dramcont0);
-	umc_dram_init_poll(dramcont1);
-
-	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
-
-	ddrphy_init(phy0_0, freq, size_ch0);
-
-	ddrphy_prepare_training(phy0_0, 0);
-	ddrphy_training(phy0_0);
-
-	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
-
-	ddrphy_init(phy1_0, freq, size_ch1);
-
-	ddrphy_prepare_training(phy1_0, 1);
-	ddrphy_training(phy1_0);
-
-	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
-	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
-
-	umc_start_ssif(ssif_base);
-
-	return 0;
-}
-
-int umc_init(void)
-{
-	return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
-					CONFIG_SDRAM1_SIZE / 0x08000000);
-}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
-    (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
-    CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/cpu/armv7/uniphier/print_misc_info.c b/arch/arm/cpu/armv7/uniphier/print_misc_info.c
deleted file mode 100644
index 69cfab519f..0000000000
--- a/arch/arm/cpu/armv7/uniphier/print_misc_info.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <asm/arch/board.h>
-
-int misc_init_f(void)
-{
-	return check_support_card();
-}
diff --git a/arch/arm/cpu/armv7/uniphier/reset.c b/arch/arm/cpu/armv7/uniphier/reset.c
deleted file mode 100644
index 50d1fed647..0000000000
--- a/arch/arm/cpu/armv7/uniphier/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/sc-regs.h>
-
-void reset_cpu(unsigned long ignored)
-{
-	u32 tmp;
-
-	writel(5, SC_IRQTIMSET); /* default value */
-
-	tmp  = readl(SC_SLFRSTSEL);
-	tmp &= ~0x3; /* mask [1:0] */
-	tmp |= 0x0;  /* XRST reboot */
-	writel(tmp, SC_SLFRSTSEL);
-
-	tmp = readl(SC_SLFRSTCTL);
-	tmp |= 0x1;
-	writel(tmp, SC_SLFRSTCTL);
-}
diff --git a/arch/arm/cpu/armv7/uniphier/smp.S b/arch/arm/cpu/armv7/uniphier/smp.S
deleted file mode 100644
index 25ba981cea..0000000000
--- a/arch/arm/cpu/armv7/uniphier/smp.S
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (C) 2013 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/system.h>
-#include <asm/arch/led.h>
-#include <asm/arch/sbc-regs.h>
-
-/* Entry point of U-Boot main program for the secondary CPU */
-LENTRY(secondary_entry)
-	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Contrl Register)
-	bic	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache disable
-	mcr	p15, 0, r0, c1, c0, 0
-	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs
-	mcr	p15, 0, r0, c7, c5, 0	@ invalidate icache
-	dsb
-	led_write(C,0,,)
-	ldr	r1, =ROM_BOOT_ROMRSV2
-	mov	r0, #0
-	str	r0, [r1]
-0:	wfe
-	ldr	r4, [r1]		@ r4: entry point for secondary CPUs
-	cmp	r4, #0
-	beq	0b
-	led_write(C, P, U, 1)
-	bx	r4			@ secondary CPUs jump to linux
-ENDPROC(secondary_entry)
-
-ENTRY(wakeup_secondary)
-	ldr	r1, =ROM_BOOT_ROMRSV2
-0:	ldr	r0, [r1]
-	cmp	r0, #0
-	bne	0b
-
-	/* set entry address and send event to the secondary CPU */
-	ldr	r0, =secondary_entry
-	str	r0, [r1]
-	ldr	r0, [r1]	@ make sure store is complete
-	mov	r0, #0x100
-0:	subs	r0, r0, #1	@ I don't know the reason, but without this wait
-	bne	0b		@ fails to wake up the secondary CPU
-	sev
-
-	/* wait until the secondary CPU reach to secondary_entry */
-0:	ldr	r0, [r1]
-	cmp	r0, #0
-	bne	0b
-	bx	lr
-ENDPROC(wakeup_secondary)
diff --git a/arch/arm/cpu/armv7/uniphier/spl.c b/arch/arm/cpu/armv7/uniphier/spl.c
deleted file mode 100644
index 8a4eafc266..0000000000
--- a/arch/arm/cpu/armv7/uniphier/spl.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/compiler.h>
-#include <asm/arch/led.h>
-#include <asm/arch/board.h>
-
-void __weak bcu_init(void)
-{
-};
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void clkrst_init(void);
-int umc_init(void);
-void enable_dpll_ssc(void);
-
-void spl_board_init(void)
-{
-	bcu_init();
-
-	sbc_init();
-
-	sg_init();
-
-	uniphier_board_reset();
-
-	pll_init();
-
-	uniphier_board_init();
-
-	led_write(L, 0, , );
-
-	clkrst_init();
-
-	led_write(L, 1, , );
-
-	{
-		int res;
-
-		res = umc_init();
-		if (res < 0) {
-			while (1)
-				;
-		}
-	}
-	led_write(L, 2, , );
-
-	enable_dpll_ssc();
-
-	led_write(L, 3, , );
-}
diff --git a/arch/arm/cpu/armv7/uniphier/support_card.c b/arch/arm/cpu/armv7/uniphier/support_card.c
deleted file mode 100644
index 443224c451..0000000000
--- a/arch/arm/cpu/armv7/uniphier/support_card.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/board.h>
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-
-#define PFC_MICRO_SUPPORT_CARD_RESET	\
-				((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
-#define PFC_MICRO_SUPPORT_CARD_REVISION	\
-				((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
-/*
- * 0: reset deassert, 1: reset
- *
- * bit[0]: LAN, I2C, LED
- * bit[1]: UART
- */
-void support_card_reset_deassert(void)
-{
-	writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-void support_card_reset(void)
-{
-	writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
-}
-
-static int support_card_show_revision(void)
-{
-	u32 revision;
-
-	revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
-	printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-
-#define DCC_MICRO_SUPPORT_CARD_RESET_LAN	\
-				((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
-#define DCC_MICRO_SUPPORT_CARD_RESET_UART	\
-				((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
-#define DCC_MICRO_SUPPORT_CARD_RESET_I2C	\
-				((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
-#define DCC_MICRO_SUPPORT_CARD_REVISION		\
-				((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
-
-void support_card_reset_deassert(void)
-{
-	writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
-	writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
-	writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-void support_card_reset(void)
-{
-	writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
-	writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
-	writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-static int support_card_show_revision(void)
-{
-	u32 revision;
-
-	revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
-
-	if (revision >= 0x67) {
-		printf("(DCC CPLD version 3.%d.%d)\n",
-		       revision >> 4, revision & 0xf);
-		return 0;
-	} else {
-		printf("(DCC CPLD unknown version)\n");
-		return -1;
-	}
-}
-#endif
-
-int check_support_card(void)
-{
-	printf("SC:    Micro Support Card ");
-	return support_card_show_revision();
-}
-
-void support_card_init(void)
-{
-	/*
-	 * After power on, we need to keep the LAN controller in reset state
-	 * for a while. (200 usec)
-	 * Fortunatelly, enough wait time is already inserted in pll_init()
-	 * function. So we do not have to wait here.
-	 */
-	support_card_reset_deassert();
-}
-
-#if defined(CONFIG_SMC911X)
-#include <netdev.h>
-
-int board_eth_init(bd_t *bis)
-{
-	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
-}
-#endif
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-
-#include <mtd/cfi_flash.h>
-#include <asm/arch/sbc-regs.h>
-
-struct memory_bank {
-	phys_addr_t base;
-	unsigned long size;
-};
-
-static int mem_is_flash(const struct memory_bank *mem)
-{
-	const int loop = 128;
-	u32 *scratch_addr;
-	u32 saved_value;
-	int ret = 1;
-	int i;
-
-	/* just in case, use the tail of the memory bank */
-	scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop,
-				   sizeof(u32) * loop, MAP_NOCACHE);
-
-	for (i = 0; i < loop; i++, scratch_addr++) {
-		saved_value = readl(scratch_addr);
-		writel(~saved_value, scratch_addr);
-		if (readl(scratch_addr) != saved_value) {
-			/* We assume no memory or SRAM here. */
-			writel(saved_value, scratch_addr);
-			ret = 0;
-			break;
-		}
-	}
-
-	unmap_physmem(scratch_addr, MAP_NOCACHE);
-
-	return ret;
-}
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
-	/* {address, size} */
-static const struct memory_bank memory_banks_boot_swap_off[] = {
-	{0x02000000, 0x01f00000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
-	{0x00000000, 0x01f00000},
-};
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-static const struct memory_bank memory_banks_boot_swap_off[] = {
-	{0x04000000, 0x02000000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
-	{0x00000000, 0x02000000},
-	{0x04000000, 0x02000000},
-};
-#endif
-
-static const struct memory_bank
-*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
-
-phys_addr_t cfi_flash_bank_addr(int i)
-{
-	return flash_banks_list[i]->base;
-}
-
-unsigned long cfi_flash_bank_size(int i)
-{
-	return flash_banks_list[i]->size;
-}
-
-static void detect_num_flash_banks(void)
-{
-	const struct memory_bank *memory_bank, *end;
-
-	cfi_flash_num_flash_banks = 0;
-
-	if (boot_is_swapped()) {
-		memory_bank = memory_banks_boot_swap_on;
-		end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
-	} else {
-		memory_bank = memory_banks_boot_swap_off;
-		end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
-	}
-
-	for (; memory_bank < end; memory_bank++) {
-		if (cfi_flash_num_flash_banks >=
-		    CONFIG_SYS_MAX_FLASH_BANKS_DETECT)
-			break;
-
-		if (mem_is_flash(memory_bank)) {
-			flash_banks_list[cfi_flash_num_flash_banks] =
-								memory_bank;
-
-			debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
-			      memory_bank->base, memory_bank->size);
-			cfi_flash_num_flash_banks++;
-		}
-	}
-
-	debug("number of flash banks: %d\n", cfi_flash_num_flash_banks);
-}
-#else /* ONFIG_SYS_NO_FLASH */
-void detect_num_flash_banks(void)
-{
-};
-#endif /* ONFIG_SYS_NO_FLASH */
-
-void support_card_late_init(void)
-{
-	detect_num_flash_banks();
-}
diff --git a/arch/arm/cpu/armv7/uniphier/timer.c b/arch/arm/cpu/armv7/uniphier/timer.c
deleted file mode 100644
index 6edc0842a9..0000000000
--- a/arch/arm/cpu/armv7/uniphier/timer.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- *   Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/arm-mpcore.h>
-
-#define PERIPHCLK (50 * 1000 * 1000) /* 50 MHz */
-#define PRESCALER ((PERIPHCLK) / (CONFIG_SYS_TIMER_RATE) - 1)
-
-static void *get_global_timer_base(void)
-{
-	void *val;
-
-	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (val) : : "memory");
-
-	return val + GLOBAL_TIMER_OFFSET;
-}
-
-unsigned long timer_read_counter(void)
-{
-	/*
-	 * ARM 64bit Global Timer is too much for our purpose.
-	 * We use only lower 32 bit of the timer counter.
-	 */
-	return readl(get_global_timer_base() + GTIMER_CNT_L);
-}
-
-int timer_init(void)
-{
-	/* enable timer */
-	writel(PRESCALER << 8 | 1, get_global_timer_base() + GTIMER_CTRL);
-
-	return 0;
-}