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| author | York Sun <york.sun@nxp.com> | 2016-10-04 14:45:54 -0700 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-10-06 09:59:11 -0700 |
| commit | 25af7dc19358f18ba826492f781fbdfab8fd8588 (patch) | |
| tree | ca427015c18eaa96b6551d9860411a3be75c8ed4 /arch/arm/cpu | |
| parent | b4b60d06c6f902cdd80236717375d03267dd949a (diff) | |
| download | u-boot-25af7dc19358f18ba826492f781fbdfab8fd8588.tar.gz u-boot-25af7dc19358f18ba826492f781fbdfab8fd8588.tar.xz u-boot-25af7dc19358f18ba826492f781fbdfab8fd8588.zip | |
arm: Move SYS_FSL_IFC_BANK_COUNT to Kconfig
Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.
Signed-off-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 5 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 |
2 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index e8264f54fb..88983f4c18 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -23,4 +23,9 @@ config MAX_CPUS config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1021A + default 8 + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 352d1d316a..c6cf7749ad 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -50,4 +50,11 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 8 if ARCH_LS2080A + endmenu |