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| author | Ashish kumar <Ashish.kumar@nxp.com> | 2017-02-23 16:03:57 +0530 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2017-03-28 09:17:07 -0700 |
| commit | dd48f0bfb5d44475481f2808338b90848d4a01e7 (patch) | |
| tree | 082e3e9728d8b24e3aa635220f7e1236f15b7b1f /arch/arm/cpu/armv8/fsl-layerscape/soc.c | |
| parent | 2652a28fee2f1e804afeb3373eca5c237f59218e (diff) | |
| download | u-boot-dd48f0bfb5d44475481f2808338b90848d4a01e7.tar.gz u-boot-dd48f0bfb5d44475481f2808338b90848d4a01e7.tar.xz u-boot-dd48f0bfb5d44475481f2808338b90848d4a01e7.zip | |
armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203
This i2c errata only applies to LS2080A and its variants, namely
LS2080A, LS2085A and LS2088A.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index b54a937971..9e3cdd78af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -152,6 +152,7 @@ static void erratum_rcw_src(void) * This erratum requires setting glitch_en bit to enable * digital glitch filter to improve clock stability. */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009203 static void erratum_a009203(void) { u8 __iomem *ptr; @@ -178,6 +179,7 @@ static void erratum_a009203(void) #endif #endif } +#endif void bypass_smmu(void) { @@ -191,7 +193,9 @@ void fsl_lsch3_early_init_f(void) { erratum_rcw_src(); init_early_memctl_regs(); /* tighten IFC timing */ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009203 erratum_a009203(); +#endif erratum_a008514(); erratum_a008336(); #ifdef CONFIG_CHAIN_OF_TRUST |