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| author | Nitin Garg <nitin.garg@freescale.com> | 2014-04-02 08:55:02 -0500 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2014-04-07 18:11:01 +0200 |
| commit | b7588e3bdcdb2ee073a6a66a4c882b23feaaa0e6 (patch) | |
| tree | 8955f4f4eeb50f404d798165bf0ff1391713ea23 /arch/arm/cpu/armv7/start.S | |
| parent | f71cbfe3ca5d2ad20159871700e8e248c8818ba8 (diff) | |
| download | u-boot-b7588e3bdcdb2ee073a6a66a4c882b23feaaa0e6.tar.gz u-boot-b7588e3bdcdb2ee073a6a66a4c882b23feaaa0e6.tar.xz u-boot-b7588e3bdcdb2ee073a6a66a4c882b23feaaa0e6.zip | |
ARM: Add workaround for Cortex-A9 errata 761320
Full cache line writes to the same memory region from at least two
processors might deadlock the processor. Exists on r1, r2, r3
revisions.
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch/arm/cpu/armv7/start.S')
| -rw-r--r-- | arch/arm/cpu/armv7/start.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index f3830c8471..27be451a89 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15) orr r0, r0, #1 << 11 @ set bit #11 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_761320 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register + orr r0, r0, #1 << 21 @ set bit #21 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register +#endif mov pc, lr @ back to my caller ENDPROC(cpu_init_cp15) |