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| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2019-03-21 16:37:23 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2019-04-18 09:12:38 +0300 |
| commit | cc2f7b6c7d7d5adeedecdb6c0599998b2e40b3f4 (patch) | |
| tree | 9493862e827a51c48da6e5be07e904b91167a810 /arch/arc | |
| parent | 54858311df4f4268b079dff9320f14c91e50dd8e (diff) | |
| download | u-boot-cc2f7b6c7d7d5adeedecdb6c0599998b2e40b3f4.tar.gz u-boot-cc2f7b6c7d7d5adeedecdb6c0599998b2e40b3f4.tar.xz u-boot-cc2f7b6c7d7d5adeedecdb6c0599998b2e40b3f4.zip | |
ARC: [plat-axs10x]: migrate to DM_MMC
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/dts/axs10x_mb.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi index b5aacd5170..6d97de9fd8 100644 --- a/arch/arc/dts/axs10x_mb.dtsi +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -31,6 +31,25 @@ #clock-cells = <0>; u-boot,dm-pre-reloc; }; + + mmcclk_ciu: mmcclk-ciu { + compatible = "fixed-clock"; + /* + * DW sdio controller has external ciu clock divider + * controlled via register in SDIO IP. It divides + * sdio_ref_clk (which comes from CGU) by 16 for + * default. So default mmcclk clock (which comes + * to sdk_in) is 25000000 Hz. + */ + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + + mmcclk_biu: mmcclk-biu { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; }; ethernet@18000 { @@ -53,6 +72,15 @@ reg = < 0x60000 0x100 >; }; + mmc: mmc@15000 { + compatible = "snps,dw-mshc"; + reg = <0x15000 0x400>; + bus-width = <4>; + clocks = <&mmcclk_biu>, <&mmcclk_ciu>; + clock-names = "biu", "ciu"; + max-frequency = <25000000>; + }; + uart0: serial0@22000 { compatible = "snps,dw-apb-uart"; reg = <0x22000 0x100>; |