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| author | Alexey Brodkin <Alexey.Brodkin@synopsys.com> | 2015-12-14 17:15:13 +0300 |
|---|---|---|
| committer | Alexey Brodkin <abrodkin@synopsys.com> | 2016-02-20 11:20:05 +0300 |
| commit | db6ce2312dcae87619136457d1f9df56789f630a (patch) | |
| tree | 1e894ccb3d9070f09d95a2930ea8dc3a67798ad3 /arch/arc/include/asm | |
| parent | 379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1 (diff) | |
| download | u-boot-db6ce2312dcae87619136457d1f9df56789f630a.tar.gz u-boot-db6ce2312dcae87619136457d1f9df56789f630a.tar.xz u-boot-db6ce2312dcae87619136457d1f9df56789f630a.zip | |
arc: cache - utilize IO coherency (AKA IOC) engine
With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.
With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h index 667f218bd8..cf999b0280 100644 --- a/arch/arc/include/asm/arcregs.h +++ b/arch/arc/include/asm/arcregs.h @@ -53,6 +53,13 @@ #define ARC_AUX_SLC_INVALIDATE 0x905 #define ARC_AUX_SLC_IVDL 0x910 #define ARC_AUX_SLC_FLDL 0x912 +#define ARC_BCR_CLUSTER 0xcf + +/* IO coherency related auxiliary registers */ +#define ARC_AUX_IO_COH_ENABLE 0x500 +#define ARC_AUX_IO_COH_PARTIAL 0x501 +#define ARC_AUX_IO_COH_AP0_BASE 0x508 +#define ARC_AUX_IO_COH_AP0_SIZE 0x509 #ifndef __ASSEMBLY__ /* Accessors for auxiliary registers */ |