diff options
| author | Alexey Brodkin <Alexey.Brodkin@synopsys.com> | 2014-02-04 12:56:13 +0400 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-07 08:14:32 -0500 |
| commit | 288aaacf2de5507f33c0bb26eb063f2f69033dd6 (patch) | |
| tree | 3bdacb2f9e28c14982d2a4957b6561f81e0e409c /arch/arc/include/asm/arcregs.h | |
| parent | 819ca38fa70da85a14b4328d1511146e6c59eb32 (diff) | |
| download | u-boot-288aaacf2de5507f33c0bb26eb063f2f69033dd6.tar.gz u-boot-288aaacf2de5507f33c0bb26eb063f2f69033dd6.tar.xz u-boot-288aaacf2de5507f33c0bb26eb063f2f69033dd6.zip | |
arc: add architecture header files
These are header files used by ARC700 architecture.
Also note that "arch-arc700/hardware.h" is only required for compilation of
"designware_i2c" driver which refers to "asm/arch/hardware.h".
It would be good to fix mentioned driver sometime soon but it will cause
changes in ARM board configs that use "designware_i2c".
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Vineet Gupta <vgupta@synopsys.com>
Cc: Francois Bedard <fbedard@synopsys.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Diffstat (limited to 'arch/arc/include/asm/arcregs.h')
| -rw-r--r-- | arch/arc/include/asm/arcregs.h | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h new file mode 100644 index 0000000000..5d48d11bab --- /dev/null +++ b/arch/arc/include/asm/arcregs.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARC_ARCREGS_H +#define _ASM_ARC_ARCREGS_H + +/* + * ARC architecture has additional address space - auxiliary registers. + * These registers are mostly used for configuration purposes. + * These registers are not memory mapped and special commands are used for + * access: "lr"/"sr". + */ + +#define ARC_AUX_IDENTITY 0x04 +#define ARC_AUX_STATUS32 0x0a + +/* Instruction cache related auxiliary registers */ +#define ARC_AUX_IC_IVIC 0x10 +#define ARC_AUX_IC_CTRL 0x11 +#define ARC_AUX_IC_IVIL 0x19 +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_IC_PTAG 0x1E +#endif + +/* Timer related auxiliary registers */ +#define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */ +#define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */ +#define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */ + +#define ARC_AUX_INTR_VEC_BASE 0x25 + +/* Data cache related auxiliary registers */ +#define ARC_AUX_DC_IVDC 0x47 +#define ARC_AUX_DC_CTRL 0x48 + +#define ARC_AUX_DC_IVDL 0x4A +#define ARC_AUX_DC_FLSH 0x4B +#define ARC_AUX_DC_FLDL 0x4C +#if (CONFIG_ARC_MMU_VER > 2) +#define ARC_AUX_DC_PTAG 0x5C +#endif + +#ifndef __ASSEMBLY__ +/* Accessors for auxiliary registers */ +#define read_aux_reg(reg) __builtin_arc_lr(reg) + +/* gcc builtin sr needs reg param to be long immediate */ +#define write_aux_reg(reg_immed, val) \ + __builtin_arc_sr((unsigned int)val, reg_immed) +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_ARC_ARCREGS_H */ |