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| author | Tom Rini <trini@ti.com> | 2014-12-08 16:35:07 -0500 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-12-08 16:35:07 -0500 |
| commit | 272a1acf1ef574356e5da51f7d6b3b07ab4e9b83 (patch) | |
| tree | b65e7b532ac7beb91cfbf3b16f1df76a3a65d59d /README | |
| parent | 98d2d5e8c473232dc718763dbec284b7349dcc05 (diff) | |
| parent | af7219de2c66b64ddae0348b3d3fa5072d800dd2 (diff) | |
| download | u-boot-272a1acf1ef574356e5da51f7d6b3b07ab4e9b83.tar.gz u-boot-272a1acf1ef574356e5da51f7d6b3b07ab4e9b83.tar.xz u-boot-272a1acf1ef574356e5da51f7d6b3b07ab4e9b83.zip | |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -409,6 +409,10 @@ The following options need to be configured: Enables a workaround for IFC erratum A003399. It is only requred during NOR boot. + CONFIG_A008044_WORKAROUND + Enables a workaround for T1040/T1042 erratum A008044. It is only + requred during NAND boot and valid for Rev 1.0 SoC revision + CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY This is the value to write into CCSR offset 0x18600 |