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authorTom Rini <trini@konsulko.com>2017-08-07 22:00:34 -0400
committerTom Rini <trini@konsulko.com>2017-08-08 17:02:31 -0400
commit1989374b21089c63019fc9648408c8d609023ffe (patch)
tree429c7284e4500562c315061ced6cd5f1e6b0f605 /README
parent6e7adf7037c76f081b149685fa5e978e2ddf2a22 (diff)
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configs: Finish migration of PHY_GIGE
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Tom Rini <trini@konsulko.com>
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diff --git a/README b/README
index 1edf3dbbd8..3735916314 100644
--- a/README
+++ b/README
@@ -1627,11 +1627,6 @@ The following options need to be configured:
The clock frequency of the MII bus
- CONFIG_PHY_GIGE
-
- If this option is set, support for speed/duplex
- detection of gigabit PHY is included.
-
CONFIG_PHY_RESET_DELAY
Some PHY like Intel LXT971A need extra delay after