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| author | Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> | 2021-03-05 11:27:48 +0100 |
|---|---|---|
| committer | Anatolij Gustschin <agust@denx.de> | 2021-04-10 11:52:43 +0200 |
| commit | ead61b8f7331ecbe95e0345365a1f1094465b6b4 (patch) | |
| tree | a1139581429a9e317de6a5731b3dc6d0421351fa | |
| parent | 04d67ceb1c62012822430135be31e18c9c176d85 (diff) | |
| download | u-boot-ead61b8f7331ecbe95e0345365a1f1094465b6b4.tar.gz u-boot-ead61b8f7331ecbe95e0345365a1f1094465b6b4.tar.xz u-boot-ead61b8f7331ecbe95e0345365a1f1094465b6b4.zip | |
Rockchip: video: edp: Change interrupt polarity configuration
The linux code is setting polarity configuration to 3 but
uboot code is setting it to 1. Change the configuration to match the
linux configuration
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
| -rw-r--r-- | arch/arm/include/asm/arch-rockchip/edp_rk3288.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h index 26ab9b7225..9559813e52 100644 --- a/arch/arm/include/asm/arch-rockchip/edp_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/edp_rk3288.h @@ -297,7 +297,9 @@ check_member(rk3288_edp, pll_reg_5, 0xa00); /* int_ctl */ #define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) +#define INT_POL1 (0x1 << 1) +#define INT_POL0 (0x1 << 0) +#define INT_POL (INT_POL0 | INT_POL1) /* sys_ctl_1 */ #define DET_STA (0x1 << 2) |