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| author | Fabio Estevam <festevam@gmail.com> | 2019-02-14 11:37:51 -0200 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2019-03-13 09:14:35 +0100 |
| commit | e077b3ba4dd74c67109bdf32048226d388abb24d (patch) | |
| tree | 59a5030dec165578b28938569444595fb94254a7 | |
| parent | 250cf75424f7e2b04bde90ef9d99aae4a9e34f1f (diff) | |
| download | u-boot-e077b3ba4dd74c67109bdf32048226d388abb24d.tar.gz u-boot-e077b3ba4dd74c67109bdf32048226d388abb24d.tar.xz u-boot-e077b3ba4dd74c67109bdf32048226d388abb24d.zip | |
warp7: Fix the write to the LDOGCTL PMIC register
The third parameter of the pmic_clrsetbits() function is the mask
to the register and the correct mask is 1 not 0.
Since the LDOGCTL only contains a single valid bit (bit 0),
we can use pmic_reg_write() and write 1 directly, which fixes
the problem in a simpler way and use the original pmic function
that was used prior to the DM PMIC conversion.
Fixes: 8ba377321c86 ("arm: imx7s-warp: Convert to DM PMIC")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
| -rw-r--r-- | board/warp7/warp7.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/warp7/warp7.c b/board/warp7/warp7.c index 49f290f978..2882dc9870 100644 --- a/board/warp7/warp7.c +++ b/board/warp7/warp7.c @@ -77,7 +77,7 @@ int power_init_board(void) printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); /* disable Low Power Mode during standby mode */ - pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1); + pmic_reg_write(dev, PFUZE3000_LDOGCTL, 1); return 0; } |