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authorTom Rini <trini@konsulko.com>2018-04-30 06:52:32 -0400
committerTom Rini <trini@konsulko.com>2018-04-30 06:52:32 -0400
commitabeb9d7897510533ce3a0a9515cac16db5bed834 (patch)
tree568d9fed2b2ed2edb5755b68f9cdabc5b4fb5c1c
parent8c84287a0f225e29b688bda848e49a555c68a442 (diff)
parent5ff8e54888e4d26a352453564f7f599d29696dc9 (diff)
downloadu-boot-abeb9d7897510533ce3a0a9515cac16db5bed834.tar.gz
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Merge git://git.denx.de/u-boot-sunxi
-rw-r--r--drivers/mmc/sunxi_mmc.c35
1 files changed, 20 insertions, 15 deletions
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index df6f32850e..5292f2d3cc 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -147,19 +147,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
oclk_dly = 0;
sclk_dly = 5;
#ifdef CONFIG_MACH_SUN9I
- } else if (hz <= 50000000) {
+ } else if (hz <= 52000000) {
oclk_dly = 5;
sclk_dly = 4;
} else {
- /* hz > 50000000 */
+ /* hz > 52000000 */
oclk_dly = 2;
sclk_dly = 4;
#else
- } else if (hz <= 50000000) {
+ } else if (hz <= 52000000) {
oclk_dly = 3;
sclk_dly = 4;
} else {
- /* hz > 50000000 */
+ /* hz > 52000000 */
oclk_dly = 1;
sclk_dly = 4;
#endif
@@ -188,15 +188,16 @@ static int mmc_update_clk(struct sunxi_mmc_priv *priv)
{
unsigned int cmd;
unsigned timeout_msecs = 2000;
+ unsigned long start = get_timer(0);
cmd = SUNXI_MMC_CMD_START |
SUNXI_MMC_CMD_UPCLK_ONLY |
SUNXI_MMC_CMD_WAIT_PRE_OVER;
+
writel(cmd, &priv->reg->cmd);
while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
- if (!timeout_msecs--)
+ if (get_timer(start) > timeout_msecs)
return -1;
- udelay(1000);
}
/* clock update sets various irq status bits, clear these */
@@ -277,18 +278,21 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
unsigned i;
unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
unsigned byte_cnt = data->blocksize * data->blocks;
- unsigned timeout_usecs = (byte_cnt >> 8) * 1000;
- if (timeout_usecs < 2000000)
- timeout_usecs = 2000000;
+ unsigned timeout_msecs = byte_cnt >> 8;
+ unsigned long start;
+
+ if (timeout_msecs < 2000)
+ timeout_msecs = 2000;
/* Always read / write data through the CPU */
setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
+ start = get_timer(0);
+
for (i = 0; i < (byte_cnt >> 2); i++) {
while (readl(&priv->reg->status) & status_bit) {
- if (!timeout_usecs--)
+ if (get_timer(start) > timeout_msecs)
return -1;
- udelay(1);
}
if (reading)
@@ -304,16 +308,16 @@ static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
uint timeout_msecs, uint done_bit, const char *what)
{
unsigned int status;
+ unsigned long start = get_timer(0);
do {
status = readl(&priv->reg->rint);
- if (!timeout_msecs-- ||
+ if ((get_timer(start) > timeout_msecs) ||
(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
debug("%s timeout %x\n", what,
status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
return -ETIMEDOUT;
}
- udelay(1000);
} while (!(status & done_bit));
return 0;
@@ -405,15 +409,16 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
}
if (cmd->resp_type & MMC_RSP_BUSY) {
+ unsigned long start = get_timer(0);
timeout_msecs = 2000;
+
do {
status = readl(&priv->reg->status);
- if (!timeout_msecs--) {
+ if (get_timer(start) > timeout_msecs) {
debug("busy timeout\n");
error = -ETIMEDOUT;
goto out;
}
- udelay(1000);
} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
}