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authorYe Li <ye.li@nxp.com>2019-07-22 01:24:47 +0000
committerStefano Babic <sbabic@denx.de>2019-10-08 16:35:16 +0200
commita0f4f7ee606296ac1090bd358696ee822b67d8cc (patch)
tree1ea890d8e728a31c6c08b27a4fa87c8b82abda40
parent3ed6734e698e4280361f1a509856c50b07861c99 (diff)
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i.MX7ULP: Fix PCC register bits mask and offset issue
The offset for FRAC and the mask for PCD are not correct. If we set FRAC, we can't get the right frequency. Fix them to correct value. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
-rw-r--r--arch/arm/include/asm/arch-mx7ulp/pcc.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-mx7ulp/pcc.h b/arch/arm/include/asm/arch-mx7ulp/pcc.h
index 67a0936150..dee3cfcdc0 100644
--- a/arch/arm/include/asm/arch-mx7ulp/pcc.h
+++ b/arch/arm/include/asm/arch-mx7ulp/pcc.h
@@ -289,10 +289,10 @@ enum pcc3_entry {
#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
#define PCC_PCS_OFFSET 24
#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
-#define PCC_FRAC_OFFSET 4
+#define PCC_FRAC_OFFSET 3
#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
#define PCC_PCD_OFFSET 0
-#define PCC_PCD_MASK (0xf << PCC_PCD_OFFSET)
+#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
enum pcc_clksrc_type {