summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMasahiro Yamada <yamada.masahiro@socionext.com>2016-06-08 18:02:32 +0900
committerMasahiro Yamada <yamada.masahiro@socionext.com>2016-06-09 08:19:13 +0900
commit9c2f9b2da650907b928995350cc4e29480fb0f80 (patch)
tree5c020419fa8e0c2977c1e45c117924a229bafc75
parentf7e9402b54db4bed916c9adb2565d9713ca5bbfa (diff)
downloadu-boot-9c2f9b2da650907b928995350cc4e29480fb0f80.tar.gz
u-boot-9c2f9b2da650907b928995350cc4e29480fb0f80.tar.xz
u-boot-9c2f9b2da650907b928995350cc4e29480fb0f80.zip
ARM: uniphier: insert dsb barrier to ensure visibility of store
I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
-rw-r--r--arch/arm/mach-uniphier/arm64/smp_kick_cpus.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 64412e0ecc..5971ad256b 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void)
rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
- readq(rom_boot_rsv0); /* relax */
unmap_sysmem(rom_boot_rsv0);
uniphier_smp_setup();
- asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+ asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */
+ "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
}