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authorStefan Roese <sr@denx.de>2017-03-10 15:40:31 +0100
committerStefan Roese <sr@denx.de>2017-03-29 07:38:10 +0200
commit9627ce2dab35acd7f64bbd492c599423f87c26bf (patch)
tree69ad1e132b1578a8ee955cb17d02628fde7d78c9
parent6bbe0924a799d33c1a8c9de38b60a5e0251f2aea (diff)
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arm: mvebu: theadorable: Add board-specific PEX detection pulse width
Define a board-specific detection pulse-width array for the SerDes PCIe interfaces. If not defined in the board code, the default of currently 2 is used. Values from 0...3 are possible (2 bits). In this case of the theadorable board, PEX interface 0 needs a value of 0 for the detection pulse width so that the PCIe device (Atheros WLAN PCIe device) is consistantly detected. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Adam Shobash <adams@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--board/theadorable/theadorable.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
index d621682d07..d4242170c7 100644
--- a/board/theadorable/theadorable.c
+++ b/board/theadorable/theadorable.c
@@ -115,6 +115,13 @@ MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
},
};
+/*
+ * Define a board-specific detection pulse-width array for the SerDes PCIe
+ * interfaces. If not defined in the board code, the default of currently 2
+ * is used. Values from 0...3 are possible (2 bits).
+ */
+u8 serdes_pex_pulse_width[4] = { 0, 2, 2, 2 };
+
MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
{
/* Only one mode supported for this board */