powerpc: ispan: remove orphan board

This board has been orphan for a while.
(Emails to its maintainer have been bouncing.)

Because MPC82xx family is old enough, nobody would pick up
the maintainership on it.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denx <wd@denx.de>

5 files changed, 1 insertions, 791 deletions

diff --git a/board/ispan/Makefile b/board/ispan/Makefile
deleted file mode 100644
index 39931fdfd6..0000000000
--- a/board/ispan/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= ispan.o
diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c
deleted file mode 100644
index c610c3bd7e..0000000000
--- a/board/ispan/ispan.c
+++ /dev/null
@@ -1,448 +0,0 @@
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Interphase iSPAN Communications Controllers
- * (453x and others). Tested on 4532.
- *
- * Derived from iSPAN 4539 port (iphase4539) by
- * Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/io.h>
-
-/*
- * I/O Ports configuration table
- *
- * If conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-    /* Port A */
-    {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
-	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
-	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
-	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
-	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
-	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
-	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
-	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
-	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
-	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
-	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
-	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
-	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
-	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
-	/* PA10 */ { 0,          0,   0,   0,   0,   0 }, /* PA10 */
-	/* PA9  */ { 0,          1,   0,   1,   0,   0 }, /* SMC2 SMTXD */
-	/* PA8  */ { 0,          1,   0,   0,   0,   0 }, /* SMC2 SMRXD */
-	/* PA7  */ { 0,          0,   0,   0,   0,   0 }, /* PA7 */
-	/* PA6  */ { 0,          0,   0,   0,   0,   0 }, /* PA6 */
-	/* PA5  */ { 0,          0,   0,   0,   0,   0 }, /* PA5 */
-	/* PA4  */ { 0,          0,   0,   0,   0,   0 }, /* PA4 */
-	/* PA3  */ { 0,          0,   0,   0,   0,   0 }, /* PA3 */
-	/* PA2  */ { 0,          0,   0,   0,   0,   0 }, /* PA2 */
-	/* PA1  */ { 0,          0,   0,   0,   0,   0 }, /* PA1 */
-	/* PA0  */ { 0,          0,   0,   0,   0,   0 }  /* PA0 */
-    },
-
-    /* Port B */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_DV  */
-	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_ER  */
-	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_ER  */
-	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_EN  */
-	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII COL    */
-	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII CRS    */
-	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[3] */
-	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[2] */
-	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[1] */
-	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[0] */
-	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[0] */
-	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[1] */
-	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[2] */
-	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[3] */
-	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PB0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
-    },
-
-    /* Port C */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PC31 */ { 0,          0,   0,   0,   0,   0 }, /* PC31 */
-	/* PC30 */ { 0,          0,   0,   0,   0,   0 }, /* PC30 */
-	/* PC29 */ { 0,          0,   0,   0,   0,   0 }, /* PC29 */
-	/* PC28 */ { 0,          0,   0,   0,   0,   0 }, /* PC28 */
-	/* PC27 */ { 0,          0,   0,   0,   0,   0 }, /* PC27 */
-	/* PC26 */ { 0,          0,   0,   0,   0,   0 }, /* PC26 */
-	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
-	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
-	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
-	/* PC22 */ { 0,          0,   0,   0,   0,   0 }, /* PC22 */
-	/* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21 */
-	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
-	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19 */
-	/* PC18 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Rx Clock (CLK14) */
-	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
-	/* PC16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Tx Clock (CLK16) */
-	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
-	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
-	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
-	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
-	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
-	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
-	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
-	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8  */
-	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7  */
-	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6  */
-	/* PC5  */ { 0,          0,   0,   0,   0,   0 }, /* PC5  */
-	/* PC4  */ { 0,          0,   0,   0,   0,   0 }, /* PC4  */
-	/* PC3  */ { 0,          0,   0,   0,   0,   0 }, /* PC3  */
-	/* PC2  */ { 0,          0,   0,   0,   0,   0 }, /* PC2  */
-	/* PC1  */ { 0,          0,   0,   0,   0,   0 }, /* PC1  */
-	/* PC0  */ { 0,          0,   0,   0,   0,   0 }  /* PC0  */
-    },
-
-    /* Port D */
-    {   /*	      conf      ppar psor pdir podr pdat */
-	/* PD31 */ { 0,          0,   0,   0,   0,   0 }, /* PD31 */
-	/* PD30 */ { 0,          0,   0,   0,   0,   0 }, /* PD30 */
-	/* PD29 */ { 0,          0,   0,   0,   0,   0 }, /* PD29 */
-	/* PD28 */ { 0,          0,   0,   0,   0,   0 }, /* PD28 */
-	/* PD27 */ { 0,          0,   0,   0,   0,   0 }, /* PD27 */
-	/* PD26 */ { 0,          0,   0,   0,   0,   0 }, /* PD26 */
-	/* PD25 */ { 0,          0,   0,   0,   0,   0 }, /* PD25 */
-	/* PD24 */ { 0,          0,   0,   0,   0,   0 }, /* PD24 */
-	/* PD23 */ { 0,          0,   0,   0,   0,   0 }, /* PD23 */
-	/* PD22 */ { 0,          0,   0,   0,   0,   0 }, /* PD22 */
-	/* PD21 */ { 0,          0,   0,   0,   0,   0 }, /* PD21 */
-	/* PD20 */ { 0,          0,   0,   0,   0,   0 }, /* PD20 */
-	/* PD19 */ { 0,          0,   0,   0,   0,   0 }, /* PD19 */
-	/* PD18 */ { 0,          1,   1,   0,   0,   0 }, /* SPICLK  */
-	/* PD17 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMOSI */
-	/* PD16 */ { 0,          1,   1,   0,   0,   0 }, /* SPIMISO */
-	/* PD15 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SDA */
-	/* PD14 */ { 0,          1,   1,   0,   1,   0 }, /* I2C SCL */
-	/* PD13 */ { 1,          0,   0,   0,   0,   0 }, /* MII MDIO */
-	/* PD12 */ { 1,          0,   0,   1,   0,   0 }, /* MII MDC  */
-	/* PD11 */ { 0,          0,   0,   0,   0,   0 }, /* PD11 */
-	/* PD10 */ { 0,          0,   0,   0,   0,   0 }, /* PD10 */
-	/* PD9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 SMTXD */
-	/* PD8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 SMRXD */
-	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7 */
-	/* PD6  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   1 }, /* MII PHY Reset  */
-	/* PD5  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   0 }, /* MII PHY Enable */
-	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4 */
-	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PD1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
-	/* PD0  */ { 0,          0,   0,   0,   0,   0 }  /* pin doesn't exist */
-    }
-};
-
-#define PSPAN_ADDR      0xF0020000
-#define EEPROM_REG      0x408
-#define EEPROM_READ_CMD 0xA000
-#define PSPAN_WRITE(a,v) \
-    *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
-#define PSPAN_READ(a) \
-    *((volatile unsigned long *)(PSPAN_ADDR+(a)))
-
-static int seeprom_read (int addr, uchar * data, int size)
-{
-	ulong val, cmd;
-	int i;
-
-	for (i = 0; i < size; i++) {
-
-		cmd = EEPROM_READ_CMD;
-		cmd |= ((addr + i) << 24) & 0xff000000;
-
-		/* Wait for ACT to authorize write */
-		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
-			eieio ();
-
-		/* Write command */
-		PSPAN_WRITE (EEPROM_REG, cmd);
-
-		/* Wait for data to be valid */
-		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
-			eieio ();
-		/* Do it twice, first read might be erratic */
-		while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
-			eieio ();
-
-		/* Read error */
-		if (val & 0x00000040) {
-			return -1;
-		} else {
-			data[i] = (val >> 16) & 0xff;
-		}
-	}
-	return 0;
-}
-
-/***************************************************************
- * We take some basic Hardware Configuration Parameter from the
- * Serial EEPROM conected to the PSpan bridge. We keep it as
- * simple as possible.
- */
-#ifdef DEBUG
-static int hwc_flash_size (void)
-{
-	uchar byte;
-
-	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
-		switch ((byte >> 2) & 0x3) {
-		case 0x1:
-			return 0x0400000;
-			break;
-		case 0x2:
-			return 0x0800000;
-			break;
-		case 0x3:
-			return 0x1000000;
-		default:
-			return 0x0100000;
-		}
-	}
-	return -1;
-}
-
-static int hwc_local_sdram_size (void)
-{
-	uchar byte;
-
-	if (!seeprom_read (0x40, &byte, sizeof (byte))) {
-		switch ((byte & 0x03)) {
-		case 0x1:
-			return 0x0800000;
-		case 0x2:
-			return 0x1000000;
-		default:
-			return 0;			/* not present */
-		}
-	}
-	return -1;
-}
-#endif	/* DEBUG */
-
-static int hwc_main_sdram_size (void)
-{
-	uchar byte;
-
-	if (!seeprom_read (0x41, &byte, sizeof (byte))) {
-		return 0x1000000 << ((byte >> 5) & 0x7);
-	}
-	return -1;
-}
-
-static int hwc_serial_number (void)
-{
-	int sn = -1;
-
-	if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
-		sn = cpu_to_le32 (sn);
-	}
-	return sn;
-}
-
-static int hwc_mac_address (char *str)
-{
-	char mac[6];
-
-	if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
-		sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
-				 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
-	} else {
-		strcpy (str, "ERROR");
-		return -1;
-	}
-	return 0;
-}
-
-static int hwc_manufact_date (char *str)
-{
-	uchar byte;
-	int value;
-
-	if (seeprom_read (0x92, &byte, sizeof (byte)))
-		goto out;
-	value = byte;
-	if (seeprom_read (0x93, &byte, sizeof (byte)))
-		goto out;
-	value += byte << 8;
-	sprintf (str, "%02d/%02d/%04d",
-			 value & 0x1F, (value >> 5) & 0xF,
-			 1980 + ((value >> 9) & 0x1FF));
-	return 0;
-
-out:
-	strcpy (str, "ERROR");
-	return -1;
-}
-
-static int hwc_board_type (char **str)
-{
-	ushort id = 0;
-
-	if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
-		switch (id) {
-		case 0x9080:
-			*str = "4532-002";
-			break;
-		case 0x9081:
-			*str = "4532-001";
-			break;
-		case 0x9082:
-			*str = "4532-000";
-			break;
-		default:
-			*str = "Unknown";
-		}
-	} else {
-		*str = "Unknown";
-	}
-
-	return id;
-}
-
-phys_size_t initdram (int board_type)
-{
-	long maxsize = hwc_main_sdram_size();
-
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE)
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar *base;
-	int i;
-
-	immap->im_siu_conf.sc_ppc_acr  = 0x00000026;
-	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
-	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
-	immap->im_siu_conf.sc_lcl_acr  = 0x00000000;
-	immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
-	immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
-	immap->im_siu_conf.sc_tescr1   = 0x00004000;
-	immap->im_siu_conf.sc_ltescr1  = 0x00004000;
-
-	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-	/* Initialise 60x bus SDRAM */
-	base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110);
-	memctl->memc_psrt  = CONFIG_SYS_PSRT;
-	memctl->memc_or1   = CONFIG_SYS_60x_OR;
-	memctl->memc_br1   = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR;
-
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
-	*base = 0xFF;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
-	for (i = 0; i < 8; i++)
-		*base = 0xFF;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
-	*base = 0xFF;
-	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
-
-	/* Initialise local bus SDRAM */
-	base = (uchar *)CONFIG_SYS_LSDRAM_BASE;
-	memctl->memc_lsrt  = CONFIG_SYS_LSRT;
-	memctl->memc_or2   = CONFIG_SYS_LOC_OR;
-	memctl->memc_br2   = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR;
-
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
-	*base = 0xFF;
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
-	for (i = 0; i < 8; i++)
-		*base = 0xFF;
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
-	*base = 0xFF;
-	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
-
-	/* We must be able to test a location outsize the maximum legal size
-	 * to find out THAT we are outside; but this address still has to be
-	 * mapped by the controller. That means, that the initial mapping has
-	 * to be (at least) twice as large as the maximum expected size.
-	 */
-	maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
-
-	maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
-
-	memctl->memc_or1 |= ~(maxsize - 1);
-
-	if (maxsize != hwc_main_sdram_size())
-		puts("Oops: memory test has not found all memory!\n");
-#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */
-
-	/* Return total RAM size (size of 60x SDRAM) */
-	return maxsize;
-}
-
-int checkboard(void)
-{
-	char string[32], *id;
-
-	hwc_manufact_date(string);
-	hwc_board_type(&id);
-	printf("Board: Interphase iSPAN %s (#%d %s)\n",
-	       id, hwc_serial_number(), string);
-#ifdef DEBUG
-	printf("Manufacturing date: %s\n", string);
-	printf("Serial number     : %d\n", hwc_serial_number());
-	printf("FLASH size        : %d MB\n", hwc_flash_size() >> 20);
-	printf("Main SDRAM size   : %d MB\n", hwc_main_sdram_size() >> 20);
-	printf("Local SDRAM size  : %d MB\n", hwc_local_sdram_size() >> 20);
-	hwc_mac_address(string);
-	printf("MAC address       : %s\n", string);
-#endif
-	return 0;
-}
-
-int misc_init_r(void)
-{
-	char *s, str[32];
-	int num;
-
-	if ((s = getenv("serial#")) == NULL &&
-	    (num = hwc_serial_number()) != -1) {
-		sprintf(str, "%06d", num);
-		setenv("serial#", str);
-	}
-	if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
-		setenv("ethaddr", str);
-	}
-
-	return 0;
-}
diff --git a/boards.cfg b/boards.cfg
index bd75f7deff..d5e99ba00a 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -1243,8 +1243,6 @@ Orphan  powerpc     mpc824x        -           -               hidden_dragon
 Orphan  powerpc     mpc824x        -           etin            -                   debris                                -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
 Orphan  powerpc     mpc824x        -           etin            -                   kvme080                               -                                                                                                                                 Sangmoon Kim <dogoil@etinsys.com>
 Orphan  powerpc     mpc8260        -           -               ep8248              ep8248                                -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
-Orphan  powerpc     mpc8260        -           -               ispan               ISPAN                                 -                                                                                                                                 Yuli Barcohen <yuli@arabellasw.com>
-Orphan  powerpc     mpc8260        -           -               ispan               ISPAN_REVB                            ISPAN:SYS_REV_B                                                                                                                   Yuli Barcohen <yuli@arabellasw.com>
 Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK                           -                                                                                                                                 Anton Vorontsov <avorontsov@ru.mvista.com>
 Orphan  powerpc     mpc83xx        -           freescale       mpc8360erdk         MPC8360ERDK_33                        MPC8360ERDK:CLKIN_33MHZ                                                                                                           Anton Vorontsov <avorontsov@ru.mvista.com>
 Orphan  powerpc     mpc83xx        -           matrix_vision   mergerbox           MERGERBOX                             -                                                                                                                                 Andre Schwarz <andre.schwarz@matrix-vision.de>
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 306b4fe29b..fc5d271ae1 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,6 +11,7 @@ easily if here is something they might want to dig for...
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+ispan            powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
 rattler          powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
 zpc1900          powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
 mpc8260ads       powerpc     mpc8260        -           -           Yuli Barcohen <yuli@arabellasw.com>
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
deleted file mode 100644
index a2fdfd3274..0000000000
--- a/include/configs/ISPAN.h
+++ /dev/null
@@ -1,330 +0,0 @@
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Interphase iSPAN Communications Controllers
- * (453x and others). Tested on 4532.
- *
- * Derived from iSPAN 4539 port (iphase4539) by
- * Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ISPAN			/* ...on one of Interphase iSPAN boards */
-#define CONFIG_CPM2		1	/* Has a CPM2 */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFE7A0000
-
-/*-----------------------------------------------------------------------
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * If CONFIG_CONS_NONE is defined, then the serial console routines must be
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define	CONFIG_CONS_ON_SMC		/* Define if console on SMC		*/
-#undef	CONFIG_CONS_ON_SCC		/* Define if console on SCC		*/
-#undef	CONFIG_CONS_NONE		/* Define if console on something else	*/
-#define CONFIG_CONS_INDEX	1	/* Which serial channel for console	*/
-
-/*-----------------------------------------------------------------------
- * Select Ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC).
- *
- * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
- * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef	CONFIG_ETHER_ON_SCC		/* Define if Ethernet on SCC		*/
-#define CONFIG_ETHER_ON_FCC		/* Define if Ethernet on FCC		*/
-#undef	CONFIG_ETHER_NONE		/* Define if Ethernet on something else */
-#define CONFIG_ETHER_INDEX	3	/* Which channel for Ethernrt		*/
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#if CONFIG_ETHER_INDEX == 3
-
-#define CONFIG_SYS_PHY_ADDR		0
-#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
-#define CONFIG_SYS_CMXFCR_MASK3		(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-
-#endif /* CONFIG_ETHER_INDEX == 3 */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE	0
-#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#define CONFIG_MII				/* MII PHY management		*/
-#define CONFIG_BITBANGMII			/* Bit-bang MII PHY management	*/
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT		3		/* Port D */
-#define MDIO_DECLARE		volatile ioport_t *iop = ioport_addr ( \
-					(immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE		MDIO_DECLARE
-
-
-#define CONFIG_SYS_MDIO_PIN		0x00040000	/* PD13 */
-#define CONFIG_SYS_MDC_PIN		0x00080000	/* PD12 */
-
-#define MDIO_ACTIVE		(iop->pdir |=  CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE		(iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ		((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
-				else	iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit)		if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
-				else	iop->pdat &= ~CONFIG_SYS_MDC_PIN
-
-#define MIIDELAY		udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#define CONFIG_8260_CLKIN	65536000	/* in Hz */
-#define CONFIG_BAUDRATE		38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-
-#define CONFIG_BOOTDELAY	5		/* autoboot after 5 seconds	*/
-#define CONFIG_BOOTCOMMAND	"bootm fe010000"	/* autoboot command	*/
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
-
-#define CONFIG_BZIP2		/* Include support for bzip2 compressed images  */
-#undef	CONFIG_WATCHDOG		/* Disable platform specific watchdog		*/
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16		/* Max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on		*/
-#define CONFIG_SYS_MEMTEST_END		0x03B00000	/* 1 ... 59 MB in SDRAM		*/
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* Default load address		*/
-
-#define CONFIG_SYS_RESET_ADDRESS	0x09900000
-
-#define CONFIG_MISC_INIT_R			/* We need misc_init_r()	*/
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor   */
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()    */
-#else
-#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 KB for malloc()  */
-#endif /* CONFIG_BZIP2 */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_BASE		0xFE000000
-#define CONFIG_SYS_FLASH_CFI				/* The flash is CFI compatible  */
-#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver        */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max num of memory banks	*/
-#define CONFIG_SYS_MAX_FLASH_SECT	142		/* Max num of sects on one chip */
-
-/* Environment is in flash, there is little space left in Serial EEPROM */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x10000		/* We use one complete sector	*/
-#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-/* 0x1686B245 */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM      | HRCW_BPS01       | HRCW_CIP    |\
-			 HRCW_L2CPC10  | HRCW_ISB110                    |\
-			 HRCW_BMS      | HRCW_MMR11       | HRCW_APPC10 |\
-			 HRCW_CS10PC01 | HRCW_MODCK_H0101                \
-			)
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR		0xF0F00000
-#ifdef CONFIG_SYS_REV_B
-#define CONFIG_SYS_DEFAULT_IMMR	0xFF000000
-#endif /* CONFIG_SYS_REV_B */
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in DPRAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC8260 CPU			*/
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers		2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-				HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL		(HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2		0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register					 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR			RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration					 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR			0xA01C0000
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration				 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR		0x42250000/* 0x4205C000 */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control				 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined (CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-				SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR		(SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-				SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control			 4-40
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_TMCNTSC		(TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control		 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control					 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR		SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration				13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR		0
-
-/*-----------------------------------------------------------------------
- * Init Memory Controller:
- *
- * Bank Bus	Machine PortSize                        Device
- * ---- ---	------- -----------------------------   ------
- *  0	60x	GPCM	 8 bit (Rev.B)/16 bit (Rev.D)   Flash
- *  1	60x	SDRAM	64 bit                          SDRAM
- *  2	Local	SDRAM	32 bit	                        SDRAM
- */
-#define CONFIG_SYS_USE_FIRMWARE	/* If defined - do not initialise memory
-				   controller, rely on initialisation
-				   performed by the Interphase boot firmware.
-				 */
-
-#define CONFIG_SYS_OR0_PRELIM		0xFE000882
-#ifdef CONFIG_SYS_REV_B
-#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_8  | BRx_V)
-#else  /* Rev. D */
-#define CONFIG_SYS_BR0_PRELIM		(CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
-#endif /* CONFIG_SYS_REV_B */
-
-#define CONFIG_SYS_MPTPR		0x7F00
-
-/* Please note that 60x SDRAM MUST start at 0 */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_60x_BR		0x00000041
-#define CONFIG_SYS_60x_OR		0xF0002CD0
-#define CONFIG_SYS_PSDMR		0x0049929A
-#define CONFIG_SYS_PSRT		0x07
-
-#define CONFIG_SYS_LSDRAM_BASE		0xF7000000
-#define CONFIG_SYS_LOC_BR		0x00001861
-#define CONFIG_SYS_LOC_OR		0xFF803280
-#define CONFIG_SYS_LSDMR		0x8285A552
-#define CONFIG_SYS_LSRT		0x07
-
-#endif /* __CONFIG_H */