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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2019-10-30 15:55:41 +0530 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-11-07 18:01:13 -0500 |
| commit | 7a540eeecc14b974e421ccdb26a242ccf87f3d49 (patch) | |
| tree | b36168b1020cfae3f2d37a45c12d2d05cd50b807 | |
| parent | 68c0912bf25d71e48f0775051b58443ad35faf23 (diff) | |
| download | u-boot-7a540eeecc14b974e421ccdb26a242ccf87f3d49.tar.gz u-boot-7a540eeecc14b974e421ccdb26a242ccf87f3d49.tar.xz u-boot-7a540eeecc14b974e421ccdb26a242ccf87f3d49.zip | |
arm: caches: Disable mmu only if mmu is available
As part of disabling caches MMU as well gets disabled. But MMU is not
available on all armv7 cores like R5F. So disable MMU only if it is
available.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| -rw-r--r-- | arch/arm/lib/cache-cp15.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b2913e8165..47c223917a 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -235,12 +235,18 @@ static void cache_disable(uint32_t cache_bit) /* if cache isn;t enabled no need to disable */ if ((reg & CR_C) != CR_C) return; +#ifdef CONFIG_SYS_ARM_MMU /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; +#endif } reg = get_cr(); +#ifdef CONFIG_SYS_ARM_MMU if (cache_bit == (CR_C | CR_M)) +#elif defined(CONFIG_SYS_ARM_MPU) + if (cache_bit == CR_C) +#endif flush_dcache_all(); set_cr(reg & ~cache_bit); } |