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| author | Hou Zhiqiang <Zhiqiang.Hou@nxp.com> | 2016-08-02 19:03:26 +0800 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2016-09-14 14:07:08 -0700 |
| commit | 664b6520582fcea7e150f57258c7a63627837318 (patch) | |
| tree | 12d0456f8dfe80a95eb52f1209d39c1c24f86f50 | |
| parent | c37fdbdbb0dd65cb4aa147c9cf9352901014be3b (diff) | |
| download | u-boot-664b6520582fcea7e150f57258c7a63627837318.tar.gz u-boot-664b6520582fcea7e150f57258c7a63627837318.tar.xz u-boot-664b6520582fcea7e150f57258c7a63627837318.zip | |
fsl: csu: add an API to set R/W permission to PCIe
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 1 | ||||
| -rw-r--r-- | board/freescale/common/ns_access.c | 28 | ||||
| -rw-r--r-- | include/fsl_csu.h | 1 |
3 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h index db76066c80..f46f1d866a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h @@ -6,6 +6,7 @@ #ifndef __FSL_NS_ACCESS_H_ #define __FSL_NS_ACCESS_H_ +#include <fsl_csu.h> enum csu_cslx_ind { CSU_CSLX_PCIE2_IO = 0, diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index c3d7a5e907..81c921122e 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -8,6 +8,7 @@ #include <asm/io.h> #include <fsl_csu.h> #include <asm/arch/ns_access.h> +#include <asm/arch/fsl_serdes.h> void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val) { @@ -40,3 +41,30 @@ void enable_layerscape_ns_access(void) { enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); } + +void set_pcie_ns_access(int pcie, u16 val) +{ + switch (pcie) { +#ifdef CONFIG_PCIE1 + case PCIE1: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE1_IO], val); + return; +#endif +#ifdef CONFIG_PCIE2 + case PCIE2: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE2_IO], val); + return; +#endif +#ifdef CONFIG_PCIE3 + case PCIE3: + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3], val); + set_devices_ns_access(&ns_dev[CSU_CSLX_PCIE3_IO], val); + return; +#endif + default: + debug("The PCIE%d doesn't exist!\n", pcie); + return; + } +} diff --git a/include/fsl_csu.h b/include/fsl_csu.h index 57a99859ee..8582ac0774 100644 --- a/include/fsl_csu.h +++ b/include/fsl_csu.h @@ -31,5 +31,6 @@ struct csu_ns_dev { void enable_layerscape_ns_access(void); void set_devices_ns_access(struct csu_ns_dev *ns_dev, u16 val); +void set_pcie_ns_access(int pcie, u16 val); #endif |