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| author | York Sun <york.sun@nxp.com> | 2018-11-05 18:02:09 +0000 |
|---|---|---|
| committer | York Sun <york.sun@nxp.com> | 2018-12-06 14:37:19 -0800 |
| commit | 56db948b85aa7c03c79b2c796500de4523924a9d (patch) | |
| tree | 66a4244e1f6382be7584687574284be3b92cb71b | |
| parent | 5a73ec6169d1db85eacc4ad2fc74dad92a846c9e (diff) | |
| download | u-boot-56db948b85aa7c03c79b2c796500de4523924a9d.tar.gz u-boot-56db948b85aa7c03c79b2c796500de4523924a9d.tar.xz u-boot-56db948b85aa7c03c79b2c796500de4523924a9d.zip | |
armv8: fsl-layerscape: Update parsing boot source
Workaround of erratum A010539 clears the RCW source field in PORSR1
register, causing failure of detecting boot source using this method.
Use SMC call if U-Boot runs at EL2. If SMC is not implemented or
running at EL3, continue to read PORSR1 and presume QSPI as boot
source if erratum workaround A010539 is enabled and RCW source is
cleared.
Signed-off-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 26 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 |
2 files changed, 23 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ca632ebdaa..36189f7a92 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -693,23 +693,41 @@ enum boot_src __get_boot_src(u32 porsr1) } } #endif + + if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src) + src = BOOT_SOURCE_QSPI_NOR; + debug("%s: src 0x%x\n", __func__, src); return src; } enum boot_src get_boot_src(void) { - u32 porsr1; + struct pt_regs regs; + u32 porsr1 = 0; #if defined(CONFIG_FSL_LSCH3) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; - - porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); #elif defined(CONFIG_FSL_LSCH2) struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +#endif + + if (current_el() == 2) { + regs.regs[0] = SIP_SVC_RCW; - porsr1 = in_be32(&gur->porsr1); + smc_call(®s); + if (!regs.regs[0]) + porsr1 = regs.regs[1]; + } + + if (current_el() == 3 || !porsr1) { +#ifdef CONFIG_FSL_LSCH3 + porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4); +#elif defined(CONFIG_FSL_LSCH2) + porsr1 = in_be32(&gur->porsr1); #endif + } + debug("%s: porsr1 0x%x\n", __func__, porsr1); return __get_boot_src(porsr1); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index ef228b6443..daa1c70b3a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -56,6 +56,7 @@ struct cpu_type { #ifdef CONFIG_TFABOOT #define SMC_DRAM_BANK_INFO (0xC200FF12) +#define SIP_SVC_RCW 0xC200FF18 phys_size_t tfa_get_dram_size(void); |