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authorHiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>2017-03-23 10:35:41 +0900
committerMarek Vasut <marex@denx.de>2018-10-18 19:07:46 +0200
commit4cb71e248f4cee437a5913d0d618f62058ea36ef (patch)
tree1ae208c116b9617be64603832f0eca4e1ab2aad6
parenta14d2d153db7b42b9ad0b03a7b772b32bbd8746f (diff)
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ARM: rmobile: Tidy up SYSC_PWRx define of 3DG on Gen3
Tidy up unused definition related to power control of 3DG. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
-rw-r--r--board/renesas/draak/draak.c6
-rw-r--r--board/renesas/salvator-x/salvator-x.c6
-rw-r--r--board/renesas/ulcb/ulcb.c6
3 files changed, 0 insertions, 18 deletions
diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 71fd5001c4..060343dfe4 100644
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -44,12 +44,6 @@ int board_early_init_f(void)
return 0;
}
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define SYSC_PWRSR2 0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define SYSC_PWRONCR2 0xE618010C
-
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 726a236af3..a1a1531663 100644
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -44,12 +44,6 @@ int board_early_init_f(void)
return 0;
}
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define SYSC_PWRSR2 0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define SYSC_PWRONCR2 0xE618010C
-
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)
diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index a7ca274f34..e549a2efac 100644
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -44,12 +44,6 @@ int board_early_init_f(void)
return 0;
}
-/* SYSC */
-/* R/- 32 Power status register 2(3DG) */
-#define SYSC_PWRSR2 0xE6180100
-/* -/W 32 Power resume control register 2 (3DG) */
-#define SYSC_PWRONCR2 0xE618010C
-
/* HSUSB block registers */
#define HSUSB_REG_LPSTS 0xE6590102
#define HSUSB_REG_LPSTS_SUSPM_NORMAL BIT(14)