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| author | Ian Campbell <ijc@hellion.org.uk> | 2014-05-08 22:26:35 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-05-25 17:23:58 +0200 |
| commit | 49692c5f517d8e44ed9db0de778728fe7d2a300c (patch) | |
| tree | 618b614d0c8d4a635c9631f597e1b22e5f53fe48 | |
| parent | 1857075a7f00ff0a62b13170a78c70ff94e30f96 (diff) | |
| download | u-boot-49692c5f517d8e44ed9db0de778728fe7d2a300c.tar.gz u-boot-49692c5f517d8e44ed9db0de778728fe7d2a300c.tar.xz u-boot-49692c5f517d8e44ed9db0de778728fe7d2a300c.zip | |
net/designware: Make DMA burst length configurable and reduce by default
The correct value for this setting can vary across SoCs and boards, so make it
configurable.
Also reduce the default value to 8, which is the same default as used in the
Linux driver.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Alexey Brodkin <abrodkin@synopsys.com>
| -rw-r--r-- | drivers/net/designware.c | 2 | ||||
| -rw-r--r-- | drivers/net/designware.h | 12 |
2 files changed, 7 insertions, 7 deletions
diff --git a/drivers/net/designware.c b/drivers/net/designware.c index fa816bf2f6..7186e3b491 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -249,7 +249,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) rx_descs_init(dev); tx_descs_init(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, &dma_p->opmode); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index de2fdcb1f2..ce51102052 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -77,18 +77,18 @@ struct eth_dma_regs { #define DW_DMA_BASE_OFFSET (0x1000) +/* Default DMA Burst length */ +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8 +#endif + /* Bus mode register definitions */ #define FIXEDBURST (1 << 16) #define PRIORXTX_41 (3 << 14) #define PRIORXTX_31 (2 << 14) #define PRIORXTX_21 (1 << 14) #define PRIORXTX_11 (0 << 14) -#define BURST_1 (1 << 8) -#define BURST_2 (2 << 8) -#define BURST_4 (4 << 8) -#define BURST_8 (8 << 8) -#define BURST_16 (16 << 8) -#define BURST_32 (32 << 8) +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8) #define RXHIGHPRIO (1 << 1) #define DMAMAC_SRST (1 << 0) |