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| author | Simon Glass <sjg@chromium.org> | 2016-01-18 20:19:18 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 12:07:17 +0800 |
| commit | 1ff4f321b69950acca1b06daed89d872a52a337c (patch) | |
| tree | 2587f3068cabe4f34f2000a6829360ab89bd3d47 | |
| parent | ca831f4933dc68d9ed1b6399cbda90068c520005 (diff) | |
| download | u-boot-1ff4f321b69950acca1b06daed89d872a52a337c.tar.gz u-boot-1ff4f321b69950acca1b06daed89d872a52a337c.tar.xz u-boot-1ff4f321b69950acca1b06daed89d872a52a337c.zip | |
dm: x86: Add a driver for Intel PCH7
At some point we may need to distinguish between different types of PCHs,
but for existing supported platforms we only need to worry about version 7
and version 9 bridges. Add a driver for the PCH7.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | drivers/pch/Makefile | 1 | ||||
| -rw-r--r-- | drivers/pch/pch7.c | 61 | ||||
| -rw-r--r-- | include/pch.h | 4 |
3 files changed, 66 insertions, 0 deletions
diff --git a/drivers/pch/Makefile b/drivers/pch/Makefile index d69a99c226..33aa727017 100644 --- a/drivers/pch/Makefile +++ b/drivers/pch/Makefile @@ -3,3 +3,4 @@ # obj-y += pch-uclass.o +obj-y += pch7.o diff --git a/drivers/pch/pch7.c b/drivers/pch/pch7.c new file mode 100644 index 0000000000..ef724221c2 --- /dev/null +++ b/drivers/pch/pch7.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <pch.h> + +#define BIOS_CTRL 0xd8 + +static int pch7_get_sbase(struct udevice *dev, ulong *sbasep) +{ + u32 rcba; + + dm_pci_read_config32(dev, PCH_RCBA, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ + rcba = rcba & 0xffffc000; + *sbasep = rcba + 0x3020; + + return 0; +} + +static enum pch_version pch7_get_version(struct udevice *dev) +{ + return PCHV_7; +} + +static int pch7_set_spi_protect(struct udevice *dev, bool protect) +{ + uint8_t bios_cntl; + + /* Adjust the BIOS write protect to dis/allow write commands */ + dm_pci_read_config8(dev, BIOS_CTRL, &bios_cntl); + if (protect) + bios_cntl &= ~BIOS_CTRL_BIOSWE; + else + bios_cntl |= BIOS_CTRL_BIOSWE; + dm_pci_write_config8(dev, BIOS_CTRL, bios_cntl); + + return 0; +} + +static const struct pch_ops pch7_ops = { + .get_sbase = pch7_get_sbase, + .get_version = pch7_get_version, + .set_spi_protect = pch7_set_spi_protect, +}; + +static const struct udevice_id pch7_ids[] = { + { .compatible = "intel,pch7" }, + { } +}; + +U_BOOT_DRIVER(pch7_drv) = { + .name = "intel-pch7", + .id = UCLASS_PCH, + .of_match = pch7_ids, + .ops = &pch7_ops, +}; diff --git a/include/pch.h b/include/pch.h index ff26865045..79f49bd5f6 100644 --- a/include/pch.h +++ b/include/pch.h @@ -14,6 +14,10 @@ enum pch_version { PCHV_9, }; +#define PCH_RCBA 0xf0 + +#define BIOS_CTRL_BIOSWE BIT(0) + /* Operations for the Platform Controller Hub */ struct pch_ops { /** |