ARM: dts: Migrate U-boot nodes to U-boot DT files for stm32h7

In order to prepare and ease future DT synchronization with kernel
DT, migrate all U-boot specific nodes/properties/addons to
U-boot DT files.

As sdmmc is not yet supported on kernel side, sdmmc nodes
are located in eval-u-boot and disco-u-boot DT files.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

7 files changed, 183 insertions, 201 deletions

diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 2525035da1..6e5b805a97 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -1,13 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <dt-bindings/memory/stm32-sdram.h>
+
 /{
 	clocks {
 		u-boot,dm-pre-reloc;
 	};
 
+	aliases {
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+		mmc0 = &sdmmc1;
+	};
+
 	soc {
 		u-boot,dm-pre-reloc;
 		pin-controller {
 			u-boot,dm-pre-reloc;
 		};
+
+		fmc: fmc@52004000 {
+			compatible = "st,stm32h7-fmc";
+			reg = <0x52004000 0x1000>;
+			clocks = <&rcc FMC_CK>;
+
+			pinctrl-0 = <&fmc_pins>;
+			pinctrl-names = "default";
+			status = "okay";
+
+			/*
+			 * Memory configuration from sdram datasheet IS42S32800G-6BLI
+			 * firsct bank is bank@0
+			 * second bank is bank@1
+			 */
+			bank1: bank@1 {
+				st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
+						  CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
+				st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
+						  TWR_1 TRCD_1>;
+				st,sdram-refcount = <1539>;
+			};
+		};
+
+		sdmmc1: sdmmc@52007000 {
+			compatible = "st,stm32-sdmmc2";
+			reg = <0x52007000 0x1000>;
+			interrupts = <49>;
+			clocks = <&rcc SDMMC1_CK>;
+			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
+			st,idma = <1>;
+			cap-sd-highspeed;
+			cap-mmc-highspeed;
+		};
 	};
 };
 
@@ -15,21 +68,14 @@
 	u-boot,dm-pre-reloc;
 };
 
-&clk_lse {
-	u-boot,dm-pre-reloc;
-};
-
 &clk_i2s {
 	u-boot,dm-pre-reloc;
 };
 
-&pwrcfg {
+&clk_lse {
 	u-boot,dm-pre-reloc;
 };
 
-&rcc {
-	u-boot,dm-pre-reloc;
-};
 
 &fmc {
 	u-boot,dm-pre-reloc;
@@ -86,3 +132,108 @@
 &gpiok {
 	u-boot,dm-pre-reloc;
 };
+
+&pinctrl {
+	fmc_pins: fmc@0 {
+		  pins {
+			  pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
+				  <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
+				  <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
+				  <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
+				  <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
+				  <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
+				  <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
+
+				  <STM32H7_PE0_FUNC_FMC_NBL0>,
+				  <STM32H7_PE1_FUNC_FMC_NBL1>,
+				  <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
+				  <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
+				  <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
+				  <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
+				  <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
+				  <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
+				  <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
+				  <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
+				  <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
+
+				  <STM32H7_PF0_FUNC_FMC_A0>,
+				  <STM32H7_PF1_FUNC_FMC_A1>,
+				  <STM32H7_PF2_FUNC_FMC_A2>,
+				  <STM32H7_PF3_FUNC_FMC_A3>,
+				  <STM32H7_PF4_FUNC_FMC_A4>,
+				  <STM32H7_PF5_FUNC_FMC_A5>,
+				  <STM32H7_PF11_FUNC_FMC_SDNRAS>,
+				  <STM32H7_PF12_FUNC_FMC_A6>,
+				  <STM32H7_PF13_FUNC_FMC_A7>,
+				  <STM32H7_PF14_FUNC_FMC_A8>,
+				  <STM32H7_PF15_FUNC_FMC_A9>,
+
+				  <STM32H7_PG0_FUNC_FMC_A10>,
+				  <STM32H7_PG1_FUNC_FMC_A11>,
+				  <STM32H7_PG2_FUNC_FMC_A12>,
+				  <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
+				  <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
+				  <STM32H7_PG8_FUNC_FMC_SDCLK>,
+				  <STM32H7_PG15_FUNC_FMC_SDNCAS>,
+
+				  <STM32H7_PH5_FUNC_FMC_SDNWE>,
+				  <STM32H7_PH6_FUNC_FMC_SDNE1>,
+				  <STM32H7_PH7_FUNC_FMC_SDCKE1>,
+				  <STM32H7_PH8_FUNC_FMC_D16>,
+				  <STM32H7_PH9_FUNC_FMC_D17>,
+				  <STM32H7_PH10_FUNC_FMC_D18>,
+				  <STM32H7_PH11_FUNC_FMC_D19>,
+				  <STM32H7_PH12_FUNC_FMC_D20>,
+				  <STM32H7_PH13_FUNC_FMC_D21>,
+				  <STM32H7_PH14_FUNC_FMC_D22>,
+				  <STM32H7_PH15_FUNC_FMC_D23>,
+
+				  <STM32H7_PI0_FUNC_FMC_D24>,
+				  <STM32H7_PI1_FUNC_FMC_D25>,
+				  <STM32H7_PI2_FUNC_FMC_D26>,
+				  <STM32H7_PI3_FUNC_FMC_D27>,
+				  <STM32H7_PI4_FUNC_FMC_NBL2>,
+				  <STM32H7_PI5_FUNC_FMC_NBL3>,
+				  <STM32H7_PI6_FUNC_FMC_D28>,
+				  <STM32H7_PI7_FUNC_FMC_D29>,
+				  <STM32H7_PI9_FUNC_FMC_D30>,
+				  <STM32H7_PI10_FUNC_FMC_D31>;
+
+			  slew-rate = <3>;
+		};
+	};
+
+	pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
+		pins {
+			pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
+				 <STM32H7_PB9_FUNC_SDMMC1_CDIR>,
+				 <STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
+				 <STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
+			drive-push-pull;
+			slew-rate = <3>;
+		};
+	};
+
+	sdmmc1_pins: sdmmc@0 {
+		pins {
+			pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
+				 <STM32H7_PC9_FUNC_SDMMC1_D1>,
+				 <STM32H7_PC10_FUNC_SDMMC1_D2>,
+				 <STM32H7_PC11_FUNC_SDMMC1_D3>,
+				 <STM32H7_PC12_FUNC_SDMMC1_CK>,
+				 <STM32H7_PD2_FUNC_SDMMC1_CMD>;
+
+			slew-rate = <3>;
+			drive-push-pull;
+			bias-disable;
+		};
+	};
+};
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&rcc {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi
index e4f4aa579b..85b96be99b 100644
--- a/arch/arm/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h743-pinctrl.dtsi
@@ -44,7 +44,7 @@
 
 / {
 	soc {
-		pin-controller {
+		pinctrl: pin-controller {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "st,stm32h743-pinctrl";
@@ -175,101 +175,6 @@
 					bias-disable;
 				};
 			};
-
-			fmc_pins: fmc@0 {
-				  pins {
-					  pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
-						  <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
-						  <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
-						  <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
-						  <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
-						  <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
-						  <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
-
-						  <STM32H7_PE0_FUNC_FMC_NBL0>,
-						  <STM32H7_PE1_FUNC_FMC_NBL1>,
-						  <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
-						  <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
-						  <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
-						  <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
-						  <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
-						  <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
-						  <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
-						  <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
-						  <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
-
-						  <STM32H7_PF0_FUNC_FMC_A0>,
-						  <STM32H7_PF1_FUNC_FMC_A1>,
-						  <STM32H7_PF2_FUNC_FMC_A2>,
-						  <STM32H7_PF3_FUNC_FMC_A3>,
-						  <STM32H7_PF4_FUNC_FMC_A4>,
-						  <STM32H7_PF5_FUNC_FMC_A5>,
-						  <STM32H7_PF11_FUNC_FMC_SDNRAS>,
-						  <STM32H7_PF12_FUNC_FMC_A6>,
-						  <STM32H7_PF13_FUNC_FMC_A7>,
-						  <STM32H7_PF14_FUNC_FMC_A8>,
-						  <STM32H7_PF15_FUNC_FMC_A9>,
-
-						  <STM32H7_PG0_FUNC_FMC_A10>,
-						  <STM32H7_PG1_FUNC_FMC_A11>,
-						  <STM32H7_PG2_FUNC_FMC_A12>,
-						  <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
-						  <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
-						  <STM32H7_PG8_FUNC_FMC_SDCLK>,
-						  <STM32H7_PG15_FUNC_FMC_SDNCAS>,
-
-						  <STM32H7_PH5_FUNC_FMC_SDNWE>,
-						  <STM32H7_PH6_FUNC_FMC_SDNE1>,
-						  <STM32H7_PH7_FUNC_FMC_SDCKE1>,
-						  <STM32H7_PH8_FUNC_FMC_D16>,
-						  <STM32H7_PH9_FUNC_FMC_D17>,
-						  <STM32H7_PH10_FUNC_FMC_D18>,
-						  <STM32H7_PH11_FUNC_FMC_D19>,
-						  <STM32H7_PH12_FUNC_FMC_D20>,
-						  <STM32H7_PH13_FUNC_FMC_D21>,
-						  <STM32H7_PH14_FUNC_FMC_D22>,
-						  <STM32H7_PH15_FUNC_FMC_D23>,
-
-						  <STM32H7_PI0_FUNC_FMC_D24>,
-						  <STM32H7_PI1_FUNC_FMC_D25>,
-						  <STM32H7_PI2_FUNC_FMC_D26>,
-						  <STM32H7_PI3_FUNC_FMC_D27>,
-						  <STM32H7_PI4_FUNC_FMC_NBL2>,
-						  <STM32H7_PI5_FUNC_FMC_NBL3>,
-						  <STM32H7_PI6_FUNC_FMC_D28>,
-						  <STM32H7_PI7_FUNC_FMC_D29>,
-						  <STM32H7_PI9_FUNC_FMC_D30>,
-						  <STM32H7_PI10_FUNC_FMC_D31>;
-
-					  slew-rate = <3>;
-				};
-			};
-
-			sdmmc1_pins: sdmmc@0 {
-				pins {
-					pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
-						 <STM32H7_PC9_FUNC_SDMMC1_D1>,
-						 <STM32H7_PC10_FUNC_SDMMC1_D2>,
-						 <STM32H7_PC11_FUNC_SDMMC1_D3>,
-						 <STM32H7_PC12_FUNC_SDMMC1_CK>,
-						 <STM32H7_PD2_FUNC_SDMMC1_CMD>;
-
-					slew-rate = <3>;
-					drive-push-pull;
-					bias-disable;
-				};
-			};
-
-			pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
-				pins {
-					pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
-						 <STM32H7_PB9_FUNC_SDMMC1_CDIR>,
-						 <STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
-						 <STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
-					drive-push-pull;
-					slew-rate = <3>;
-				};
-			};
 		};
 	};
 };
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index d5b8d879ee..23e185cf11 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -104,12 +104,6 @@
 			reg = <0x58024800 0x400>;
 		};
 
-		fmc: fmc@52004000 {
-			compatible = "st,stm32h7-fmc";
-			reg = <0x52004000 0x1000>;
-			clocks = <&rcc FMC_CK>;
-		};
-
 		clk_hsi: clk-hsi {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -121,18 +115,6 @@
 			compatible = "fixed-clock";
 			clock-frequency = <4000000>;
 		};
-
-		sdmmc1: sdmmc@52007000 {
-			compatible = "st,stm32-sdmmc2";
-			reg = <0x52007000 0x1000>;
-			interrupts = <49>;
-			clocks = <&rcc SDMMC1_CK>;
-			resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
-			st,idma = <1>;
-			cap-sd-highspeed;
-			cap-mmc-highspeed;
-			status = "disabled";
-		};
 	};
 };
 
diff --git a/arch/arm/dts/stm32h743i-disco-u-boot.dtsi b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
new file mode 100644
index 0000000000..2d6b41bfb9
--- /dev/null
+++ b/arch/arm/dts/stm32h743i-disco-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32h7-u-boot.dtsi>
+
+&sdmmc1 {
+	status = "okay";
+	pinctrl-0 = <&sdmmc1_pins>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	cd-gpios = <&gpioi 8 1>;
+};
diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts
index 917a859a09..1237a814a4 100644
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ b/arch/arm/dts/stm32h743i-disco.dts
@@ -43,7 +43,6 @@
 /dts-v1/;
 #include "stm32h743.dtsi"
 #include "stm32h743-pinctrl.dtsi"
-#include <dt-bindings/memory/stm32-sdram.h>
 
 / {
 	model = "STMicroelectronics STM32H743i-Discovery board";
@@ -60,18 +59,6 @@
 
 	aliases {
 		serial0 = &usart2;
-		mmc0 = &sdmmc1;
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
 	};
 };
 
@@ -81,29 +68,3 @@
 	status = "okay";
 };
 
-&fmc {
-	pinctrl-0 = <&fmc_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	/*
-	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
-	 * firsct bank is bank@0
-	 * second bank is bank@1
-	 */
-	bank1: bank@1 {
-		st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
-				  CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
-		st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
-				  TWR_1 TRCD_1>;
-		st,sdram-refcount = <1539>;
-	};
-};
-
-&sdmmc1 {
-	status = "okay";
-	pinctrl-0 = <&sdmmc1_pins>;
-	pinctrl-names = "default";
-	bus-width = <4>;
-	cd-gpios = <&gpioi 8 1>;
-};
diff --git a/arch/arm/dts/stm32h743i-eval-u-boot.dtsi b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
new file mode 100644
index 0000000000..220a2d706c
--- /dev/null
+++ b/arch/arm/dts/stm32h743i-eval-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include <stm32h7-u-boot.dtsi>
+
+&sdmmc1 {
+	status = "okay";
+	pinctrl-0 = <&sdmmc1_pins>,
+		    <&pinctrl_sdmmc1_level_shifter>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	st,dirpol;
+};
diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts
index 28c876be27..c8b6dfbdd3 100644
--- a/arch/arm/dts/stm32h743i-eval.dts
+++ b/arch/arm/dts/stm32h743i-eval.dts
@@ -43,7 +43,6 @@
 /dts-v1/;
 #include "stm32h743.dtsi"
 #include "stm32h743-pinctrl.dtsi"
-#include <dt-bindings/memory/stm32-sdram.h>
 
 / {
 	model = "STMicroelectronics STM32H743i-EVAL board";
@@ -60,17 +59,6 @@
 
 	aliases {
 		serial0 = &usart1;
-		gpio0 = &gpioa;
-		gpio1 = &gpiob;
-		gpio2 = &gpioc;
-		gpio3 = &gpiod;
-		gpio4 = &gpioe;
-		gpio5 = &gpiof;
-		gpio6 = &gpiog;
-		gpio7 = &gpioh;
-		gpio8 = &gpioi;
-		gpio9 = &gpioj;
-		gpio10 = &gpiok;
 	};
 };
 
@@ -79,31 +67,3 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
-
-&fmc {
-	pinctrl-0 = <&fmc_pins>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	/*
-	 * Memory configuration from sdram datasheet IS42S32800G-6BLI
-	 * firsct bank is bank@0
-	 * second bank is bank@1
-	 */
-	bank2: bank@1 {
-		st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
-				  CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
-		st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
-				  TWR_1 TRCD_1>;
-		st,sdram-refcount = <1539>;
-	};
-};
-
-&sdmmc1 {
-	status = "okay";
-	pinctrl-0 = <&sdmmc1_pins>,
-		    <&pinctrl_sdmmc1_level_shifter>;
-	pinctrl-names = "default";
-	bus-width = <4>;
-	st,dirpol;
-};