summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
...
* | arm64: zynqmp: Add description for SOM/Kria boardsMichal Simek2021-05-197-0/+1109
| | | | | | | | | | | | | | | | | | | | | | | | The patch contains several DT files for SOM platform. Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC. Files are divided in this way to make sure that SOM can be plugged to different carrier card and all peripherals on SOM (or defined by a spec) can be used by U-Boot. Full DT for SOM+CC can be merged together as overlays. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Add psgtr DT descriptionsMichal Simek2021-05-1910-1/+79
| | | | | | | | | | | | | | | | | | Mainline kernel has psgtr driver that's why it is good to add description to DT files. Some boards are just missing description for USB3 and sata. zc1751-dc1 and p-a2197 are also missing clock descriptions for input clocks. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Add pinctrl descriptionMichal Simek2021-05-1911-1/+2470
| | | | | | | | | | | | | | ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it DT files can be extended by pinctrl configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Add zynqmp firmware specific DT nodesT Karthik Reddy2021-05-192-0/+80
| | | | | | | | | | | | | | Probe zynqmp firmware driver by adding zynqmp firmware, power & ipi mailbox device tree nodes for mini emmc. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
* | arm64: zynqmp: Add missing mio-bank properties to sdhciMichal Simek2021-05-191-0/+1
| | | | | | | | | | | | | | | | | | Add missing xlnx,mio-bank property to sdhci node. Also add properties with 0 value to have it listed in case that files are copied to different projects where default case doesn't need to be handled in the same way. That's why explicitly list them too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Remove comment about clock chipsMichal Simek2021-05-192-10/+10
| | | | | | | | | | | | These comments weren't push to mainline that's why remove them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Add 'i2c-mux-idle-disconnect' propertyRaviteja Narayanam2021-05-193-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C muxes that have the slave devices with same address are falling into the below problem. VCK190 system controller (SC) - zynqmp-e-a2197-00-revA.dts I2C1 (0xff030000) -> Mux1 (@0x74) -> Channel 3 -> 0x50 I2C1 (0xff030000) -> Mux2 (@0x75) -> Channel 0 -> 0x50 1. SC accesses I2C1 - Mux1 (0x74) - Channel 3 and then 2. SC accesses I2C1 - Mux2 (0x75) - Channel 0. Now it results in 2 slave devices with same address (0x50) on the I2C bus, making the communication un-reliable. When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux channel output is disconnected, making none of the channels available to the I2C1. So, there is no question of having the same addressed slave (0x50) present on the bus when we are doing '2'. Same pattern is seen in below two boards also. ZCU208 - zynqmp-zcu208-revA.dts ZCU216 - zynqmp-zcu216-revA.dts Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com>
* | arm64: zynqmp: Add label to all GPIO lines for VCK190 SCSaeed Nowshadi2021-05-191-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | Add label to GPIO lines so the user-level applications can find any line without knowing its physical path on System Controller on VCK190/VMK180. These labels are describing EMIO gpio connection which depends on PL which we normally don't describe but that's only way to go for now. Lately this should be done out of this source code. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk nodeSaeed Nowshadi2021-05-191-1/+2
| | | | | | | | | | | | | | | | The 'silabs,skip-recall' property prevents interruption in operation of the clock while the driver is being probed. Without this property, the DDR DIMM clk can cause a failure during Versal's boot. Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
* | arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodesMichal Simek2021-05-195-3/+8
|/ | | | | | | | | All si570 which are used for ps reference clock generation should contain silabs,skip-recall property not to cause break on ps clock. On Versal boards this will cause hang on Versal cpu when it is booted at the same time with SC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge https://source.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-05-188-151/+281
|\
| * riscv: Group assembly optimized implementation of memory routines into a submenuBin Meng2021-05-171-0/+4
| | | | | | | | | | | | | | | | Currently all assembly optimized implementation of memory routines show up at the top level of the RISC-V architecture Kconfig menu. Let's group them together into a submenu. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * riscv: Fix memmove and optimise memcpy when misalignBin Meng2021-05-172-142/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present U-Boot SPL fails to boot on SiFive Unleashed board, due to a load address misaligned exception happens when loading the FIT image in spl_load_simple_fit(). The exception happens in memmove() which is called by fdt_splice_(). Commit 8f0dc4cfd106 introduces an assembly version of memmove but it does take misalignment into account (it checks if length is a multiple of machine word size but pointers need also be aligned). As a result it will generate misaligned load/store for the majority of cases and causes significant performance regression on hardware that traps misaligned load/store and emulate them using firmware. The current behaviour of memcpy is that it checks if both src and dest pointers are co-aligned (aka congruent modular SZ_REG). If aligned, it will copy data word-by-word after first aligning pointers to word boundary. If src and dst are not co-aligned, however, byte-wise copy will be performed. This patch was taken from the Linux kernel patch [1], which has not been applied at the time being. It fixes the memmove and optimises memcpy for misaligned cases. It will first align destination pointer to word-boundary regardless whether src and dest are co-aligned or not. If they indeed are, then wordwise copy is performed. If they are not co-aligned, then it will load two adjacent words from src and use shifts to assemble a full machine word. Some additional assembly level micro-optimisation is also performed to ensure more instructions can be compressed (e.g. prefer a0 to t6). With this patch, U-Boot boots again on SiFive Unleashed board. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/ Fixes: 8f0dc4cfd106 ("riscv: assembler versions of memcpy, memmove, memset") Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * riscv: Fix arch_fixup_fdt always failing without /chosenSean Anderson2021-05-171-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | If /chosen was missing, chosen_offset would never get updated with the new /chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes this by setting chosen_offset. In addition, log any errors from setting boot-hartid as well. Fixes: 5370478d1c7 ("riscv: Add boot hartid to device tree") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
| * riscv: Split SiFive CLINT support between SPL and U-Boot properBin Meng2021-05-175-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DBKonstantin Porotchkin2021-05-1611-0/+1004
| | | | | | | | | | | | | | | | | | This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN913x DB. This is only the base port with not all interfaces supported fully. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm64: mvebu: extend the mmio regionGrzegorz Jaszczyk2021-05-162-2/+4
| | | | | | | | | | | | | | | | | | Some of the setups including cn9130 opens mmio window starting from 0xc0000000, reflect it in the u-boot code. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm64: mvebu: a8k: move firmware related definitions to fw infoGrzegorz Jaszczyk2021-05-161-0/+3
| | | | | | | | | | Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm64: mvebu: do not map firmware RT service regionGrzegorz Jaszczyk2021-05-162-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is region left by ATF, which needs to remain in memory to provide RT services. To prevent overwriting it by u-boot, do not provide any mapping for this memory region, so any attempt to access it will trigger synchronous exception. Update sr 2021-04-12: Don't update armada3700/cpu.c mmu table, as this has specific changes included in mainline. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | arm64: mvebu: a8k: align memory regionsjinghua2021-05-161-55/+7
|/ | | | | | | | 1. RAM: base address 0x0 size 2Gbytes 2. MMIO: base address 0xf0000000 size 1Gbytes Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge https://source.denx.de/u-boot/custodians/u-boot-shTom Rini2021-05-141-0/+1
|\
| * ARM: renesas: Scrub duplicate memory nodes from DT on Gen3Marek Vasut2021-05-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Scrub duplicate /memory@* node entries here. Some R-Car DTs might contain multiple /memory@* nodes, however fdt_fixup_memory_banks() either generates single /memory node or updates the first /memory node. Any remaining memory nodes are thus potential duplicates. However, it is not possible to delete all the memory nodes right away, since some of those might not be DRAM memory nodes, but some sort of other memory. Thus, delete only the memory nodes which are in the R-Car3 DBSC ranges. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* | Merge tag 'u-boot-amlogic-20210514' of ↵Tom Rini2021-05-142-0/+14
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic - dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro - usb: dwc3-meson-g12a: skip phy on -ENODATA aswell - net: dwmac_meson8b: do not set TX delay in TXID & RXID - net: designware: meson8b: add g12a compatible
| * | ARM: dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-ProNeil Armstrong2021-05-142-0/+14
| | | | | | | | | | | | | | | | | | | | | This lacks the right u-boot specific DT include to make HDMI work. Reported-by: B1oHazard <ty3uk@mail.ua> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | | Revert "riscv: cpu: fu740: clear feature disable CSR"Bin Meng2021-05-141-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bc8bbb77f74f21582b3bfd790334397757f88575. This commit breaks U-Boot booting on SiFive Unleashed board, as there is no such CSR on U54 core. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* | | riscv: Don't reserve AI ram in k210 dtsSean Anderson2021-05-141-12/+0
| | | | | | | | | | | | | | | | | | | | | It is no longer necessary to disallow ai ram, since it is enabled by the sram driver. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | riscv: k210: Use AI as the parent clock of aisram, not PLL1Sean Anderson2021-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Testing showed that disabling AI while leaving PLL1 enabled disabled the aisram. This suggests that AI is a more appropriate clock for that ram bank. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | riscv: k210: Rename airam to aisramSean Anderson2021-05-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is more consistent with the naming of other ram banks, and matches what Linux is doing. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | | riscv: Enable some devices pre-relocationSean Anderson2021-05-141-0/+4
|/ / | | | | | | | | | | | | These devices are necessary for the clock driver, which is required by the sram driver, to run pre-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | am335x: add support for cape detect functionalityKory Maincent2021-05-131-0/+1
| | | | | | | | | | | | | | Update the Kconfig and the board file to make the am335x board compatible with cape detection. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
* | arm: am335x: add support for i2c2 busKory Maincent2021-05-131-0/+1
| | | | | | | | | | | | | | | | | | The am335x from BeagleBone use i2c EEPROM to detect capes. The memory is wired to i2c bus 2 therefore it need to be enabled. Add i2c2 clock, pinmux description and pinmux enable function. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
* | arm: sunxi: add support for DIP detection to CHIP boardKory Maincent2021-05-131-0/+9
| | | | | | | | | | | | | | | | | | | | Add the extension_board_scan specific function to scan the information of the EEPROM on one-wire and fill the extension struct. Add the Kconfig symbol to enable the needs to detect DIPs. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
* | am57xx: add support for cape detect functionalityKory Maincent2021-05-131-0/+1
| | | | | | | | | | | | | | This commit enables using the extension board detection mechanism on AM57xx based platforms. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
* | pytest: add sandbox test for "extension" commandKory Maincent2021-05-134-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | This commit extends the sandbox to implement a dummy extension_board_scan() function and enables the extension command in the sandbox configuration. It then adds a test that checks the proper functionality of the extension command by applying two Device Tree overlays to the sandbox Device Tree. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> [trini: Limit to running on sandbox] Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini2021-05-1223-25/+8922
|\ \ | |/ |/| | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
| * ARM: dts: k3-am642-sk: Add ethernet related DT nodesVignesh Raghavendra2021-05-122-0/+78
| | | | | | | | | | | | | | Add CPSW related nodes for AM642 SK. There are two CPSW ports on the board but U-Boot supports only the first port. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * ARM: dts: k3-am64-main: Add CPSW DT nodesVignesh Raghavendra2021-05-124-0/+185
| | | | | | | | | | | | | | | | | | AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same (based on kernel DT). Disable second port as its by default set to ICSS usage on EVM. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * arm: dts: am642-r5-sk: Add r5 specific dtsLokesh Vutla2021-05-123-1/+2337
| | | | | | | | | | | | | | Add R5 specific dts for AM64 SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
| * arm: dts: am642-sk: Add initial sk dtsLokesh Vutla2021-05-123-1/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AM642 StarterKit (SK) board is a low cost, small form factor board designed for TI’s AM642 SoC. It supports the following interfaces: * 2 GB LPDDR4 RAM * x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode * x1 USB 3.0 Type-A port * x1 UHS-1 capable µSD card slot * 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837 * 512 Mbit OSPI flash * x2 UART through UART-USB bridge * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs * 40-pin Raspberry Pi compatible GPIO header * 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO) * 54-pin header for Programmable Realtime Unit (PRU) IO pins * Interface for remote automation. Includes: * power measurement and reset control * boot mode change Add basic support for AM642 SK. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: am642-evm: Add I2C nodesLokesh Vutla2021-05-123-0/+64
| | | | | | | | | | | | Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am642-r5-evm: Do not use power-domains for I2CLokesh Vutla2021-05-121-0/+5
| | | | | | | | | | | | | | I2C EEPROM will be probed before SYSFW is available. So drop the power-domains property for I2C. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am64-evm: Make chip id available before pre-relocLokesh Vutla2021-05-121-0/+7
| | | | | | | | | | | | | | Chipid will be needed for SoC detection for all stages of U-Boot. So make it u-boot,dm-spl Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: am64x: Add support for selecting DT based on EEPROMLokesh Vutla2021-05-121-0/+26
| | | | | | | | | | | | | | Enable support for selecting DTB within SPL based on EEPROM. This will help to use single defconfig for both EVM and SK Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * board: ti: am64x: Add support for reading eeprom dataLokesh Vutla2021-05-121-0/+3
| | | | | | | | | | | | | | | | | | | | I2C EEPROM data contains the board name and its revision. Add support for: - Reading EEPROM data and store a copy at end of SRAM - Updating env variable with relevant board info - Printing board info during boot. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * arm: dts: k3-am642-r5-evm: Add GPIO DDR VTT regulatorNishanth Menon2021-05-121-0/+28
| | | | | | | | | | | | | | Add DDR VTT regulator. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am64-main: Add GPIO nodesNishanth Menon2021-05-121-0/+44
| | | | | | | | | | | | | | Add main domain GPIO nodes. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: mach-k3: am642: Add support for triggering ddr init from SPLDave Gerlach2021-05-121-0/+6
| | | | | | | | | | | | | | | | In SPL, DDR should be made available by the end of board_init_f() so that apis in board_init_r() can use ddr. Adding support for triggering DDR initialization from board_init_f(). Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add ddr nodeDave Gerlach2021-05-123-0/+4394
| | | | | | | | | | | | | | | | | | Introduce ddr node for am642 needed for all ddr configurations. Also, introduce the 1600MTs DDR4 configuration that is supported on the am642-evm. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add r5 specific dt supportDave Gerlach2021-05-123-1/+229
| | | | | | | | | | | | Add initial support for dt that runs on r5. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * arm: dts: k3-am642: Add initial support for EVMDave Gerlach2021-05-122-0/+247
| | | | | | | | | | | | | | | | | | | | The AM642 EValuation Module (EVM) is a board that provides access to various peripherals available on the AM642 SoC, such as PCIe, USB 2.0, CPSW Ethernet, ADC, and more. Add basic support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
generated by cgit (git 2.34.1) at 2024-06-11 15:57:12 +0000