Merge tag 'ti-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-ti

- Initial support for AM64 EVM and SK
- K3 DDR driver unification for J7 and AM64 platforms.
- Minor fixes for TI clock driver

121 files changed, 57482 insertions, 23609 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index a389be98a2..2538dd3c77 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1060,6 +1060,10 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
 			      k3-j721e-r5-common-proc-board.dtb \
 			      k3-j7200-common-proc-board.dtb \
 			      k3-j7200-r5-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
+			      k3-am642-r5-evm.dtb \
+			      k3-am642-sk.dtb \
+			      k3-am642-r5-sk.dtb
 
 dtb-$(CONFIG_ARCH_MEDIATEK) += \
 	mt7622-rfb.dtb \
diff --git a/arch/arm/dts/k3-am64-ddr.dtsi b/arch/arm/dts/k3-am64-ddr.dtsi
new file mode 100644
index 0000000000..026a547f0e
--- /dev/null
+++ b/arch/arm/dts/k3-am64-ddr.dtsi
@@ -0,0 +1,2205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	memorycontroller: memorycontroller@f300000 {
+		compatible = "ti,am64-ddrss";
+		reg = <0x00 0x0f308000 0x00 0x4000>,
+		      <0x00 0x43014000 0x00 0x100>;
+		reg-names = "cfg", "ctrl_mmr_lp4";
+		power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+			<&k3_pds 55 TI_SCI_PD_SHARED>;
+		clocks = <&k3_clks 138 0>, <&k3_clks 16 4>;
+		ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+		ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+		ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+
+		u-boot,dm-spl;
+
+		ti,ctl-data = <
+			DDRSS_CTL_0_DATA
+			DDRSS_CTL_1_DATA
+			DDRSS_CTL_2_DATA
+			DDRSS_CTL_3_DATA
+			DDRSS_CTL_4_DATA
+			DDRSS_CTL_5_DATA
+			DDRSS_CTL_6_DATA
+			DDRSS_CTL_7_DATA
+			DDRSS_CTL_8_DATA
+			DDRSS_CTL_9_DATA
+			DDRSS_CTL_10_DATA
+			DDRSS_CTL_11_DATA
+			DDRSS_CTL_12_DATA
+			DDRSS_CTL_13_DATA
+			DDRSS_CTL_14_DATA
+			DDRSS_CTL_15_DATA
+			DDRSS_CTL_16_DATA
+			DDRSS_CTL_17_DATA
+			DDRSS_CTL_18_DATA
+			DDRSS_CTL_19_DATA
+			DDRSS_CTL_20_DATA
+			DDRSS_CTL_21_DATA
+			DDRSS_CTL_22_DATA
+			DDRSS_CTL_23_DATA
+			DDRSS_CTL_24_DATA
+			DDRSS_CTL_25_DATA
+			DDRSS_CTL_26_DATA
+			DDRSS_CTL_27_DATA
+			DDRSS_CTL_28_DATA
+			DDRSS_CTL_29_DATA
+			DDRSS_CTL_30_DATA
+			DDRSS_CTL_31_DATA
+			DDRSS_CTL_32_DATA
+			DDRSS_CTL_33_DATA
+			DDRSS_CTL_34_DATA
+			DDRSS_CTL_35_DATA
+			DDRSS_CTL_36_DATA
+			DDRSS_CTL_37_DATA
+			DDRSS_CTL_38_DATA
+			DDRSS_CTL_39_DATA
+			DDRSS_CTL_40_DATA
+			DDRSS_CTL_41_DATA
+			DDRSS_CTL_42_DATA
+			DDRSS_CTL_43_DATA
+			DDRSS_CTL_44_DATA
+			DDRSS_CTL_45_DATA
+			DDRSS_CTL_46_DATA
+			DDRSS_CTL_47_DATA
+			DDRSS_CTL_48_DATA
+			DDRSS_CTL_49_DATA
+			DDRSS_CTL_50_DATA
+			DDRSS_CTL_51_DATA
+			DDRSS_CTL_52_DATA
+			DDRSS_CTL_53_DATA
+			DDRSS_CTL_54_DATA
+			DDRSS_CTL_55_DATA
+			DDRSS_CTL_56_DATA
+			DDRSS_CTL_57_DATA
+			DDRSS_CTL_58_DATA
+			DDRSS_CTL_59_DATA
+			DDRSS_CTL_60_DATA
+			DDRSS_CTL_61_DATA
+			DDRSS_CTL_62_DATA
+			DDRSS_CTL_63_DATA
+			DDRSS_CTL_64_DATA
+			DDRSS_CTL_65_DATA
+			DDRSS_CTL_66_DATA
+			DDRSS_CTL_67_DATA
+			DDRSS_CTL_68_DATA
+			DDRSS_CTL_69_DATA
+			DDRSS_CTL_70_DATA
+			DDRSS_CTL_71_DATA
+			DDRSS_CTL_72_DATA
+			DDRSS_CTL_73_DATA
+			DDRSS_CTL_74_DATA
+			DDRSS_CTL_75_DATA
+			DDRSS_CTL_76_DATA
+			DDRSS_CTL_77_DATA
+			DDRSS_CTL_78_DATA
+			DDRSS_CTL_79_DATA
+			DDRSS_CTL_80_DATA
+			DDRSS_CTL_81_DATA
+			DDRSS_CTL_82_DATA
+			DDRSS_CTL_83_DATA
+			DDRSS_CTL_84_DATA
+			DDRSS_CTL_85_DATA
+			DDRSS_CTL_86_DATA
+			DDRSS_CTL_87_DATA
+			DDRSS_CTL_88_DATA
+			DDRSS_CTL_89_DATA
+			DDRSS_CTL_90_DATA
+			DDRSS_CTL_91_DATA
+			DDRSS_CTL_92_DATA
+			DDRSS_CTL_93_DATA
+			DDRSS_CTL_94_DATA
+			DDRSS_CTL_95_DATA
+			DDRSS_CTL_96_DATA
+			DDRSS_CTL_97_DATA
+			DDRSS_CTL_98_DATA
+			DDRSS_CTL_99_DATA
+			DDRSS_CTL_100_DATA
+			DDRSS_CTL_101_DATA
+			DDRSS_CTL_102_DATA
+			DDRSS_CTL_103_DATA
+			DDRSS_CTL_104_DATA
+			DDRSS_CTL_105_DATA
+			DDRSS_CTL_106_DATA
+			DDRSS_CTL_107_DATA
+			DDRSS_CTL_108_DATA
+			DDRSS_CTL_109_DATA
+			DDRSS_CTL_110_DATA
+			DDRSS_CTL_111_DATA
+			DDRSS_CTL_112_DATA
+			DDRSS_CTL_113_DATA
+			DDRSS_CTL_114_DATA
+			DDRSS_CTL_115_DATA
+			DDRSS_CTL_116_DATA
+			DDRSS_CTL_117_DATA
+			DDRSS_CTL_118_DATA
+			DDRSS_CTL_119_DATA
+			DDRSS_CTL_120_DATA
+			DDRSS_CTL_121_DATA
+			DDRSS_CTL_122_DATA
+			DDRSS_CTL_123_DATA
+			DDRSS_CTL_124_DATA
+			DDRSS_CTL_125_DATA
+			DDRSS_CTL_126_DATA
+			DDRSS_CTL_127_DATA
+			DDRSS_CTL_128_DATA
+			DDRSS_CTL_129_DATA
+			DDRSS_CTL_130_DATA
+			DDRSS_CTL_131_DATA
+			DDRSS_CTL_132_DATA
+			DDRSS_CTL_133_DATA
+			DDRSS_CTL_134_DATA
+			DDRSS_CTL_135_DATA
+			DDRSS_CTL_136_DATA
+			DDRSS_CTL_137_DATA
+			DDRSS_CTL_138_DATA
+			DDRSS_CTL_139_DATA
+			DDRSS_CTL_140_DATA
+			DDRSS_CTL_141_DATA
+			DDRSS_CTL_142_DATA
+			DDRSS_CTL_143_DATA
+			DDRSS_CTL_144_DATA
+			DDRSS_CTL_145_DATA
+			DDRSS_CTL_146_DATA
+			DDRSS_CTL_147_DATA
+			DDRSS_CTL_148_DATA
+			DDRSS_CTL_149_DATA
+			DDRSS_CTL_150_DATA
+			DDRSS_CTL_151_DATA
+			DDRSS_CTL_152_DATA
+			DDRSS_CTL_153_DATA
+			DDRSS_CTL_154_DATA
+			DDRSS_CTL_155_DATA
+			DDRSS_CTL_156_DATA
+			DDRSS_CTL_157_DATA
+			DDRSS_CTL_158_DATA
+			DDRSS_CTL_159_DATA
+			DDRSS_CTL_160_DATA
+			DDRSS_CTL_161_DATA
+			DDRSS_CTL_162_DATA
+			DDRSS_CTL_163_DATA
+			DDRSS_CTL_164_DATA
+			DDRSS_CTL_165_DATA
+			DDRSS_CTL_166_DATA
+			DDRSS_CTL_167_DATA
+			DDRSS_CTL_168_DATA
+			DDRSS_CTL_169_DATA
+			DDRSS_CTL_170_DATA
+			DDRSS_CTL_171_DATA
+			DDRSS_CTL_172_DATA
+			DDRSS_CTL_173_DATA
+			DDRSS_CTL_174_DATA
+			DDRSS_CTL_175_DATA
+			DDRSS_CTL_176_DATA
+			DDRSS_CTL_177_DATA
+			DDRSS_CTL_178_DATA
+			DDRSS_CTL_179_DATA
+			DDRSS_CTL_180_DATA
+			DDRSS_CTL_181_DATA
+			DDRSS_CTL_182_DATA
+			DDRSS_CTL_183_DATA
+			DDRSS_CTL_184_DATA
+			DDRSS_CTL_185_DATA
+			DDRSS_CTL_186_DATA
+			DDRSS_CTL_187_DATA
+			DDRSS_CTL_188_DATA
+			DDRSS_CTL_189_DATA
+			DDRSS_CTL_190_DATA
+			DDRSS_CTL_191_DATA
+			DDRSS_CTL_192_DATA
+			DDRSS_CTL_193_DATA
+			DDRSS_CTL_194_DATA
+			DDRSS_CTL_195_DATA
+			DDRSS_CTL_196_DATA
+			DDRSS_CTL_197_DATA
+			DDRSS_CTL_198_DATA
+			DDRSS_CTL_199_DATA
+			DDRSS_CTL_200_DATA
+			DDRSS_CTL_201_DATA
+			DDRSS_CTL_202_DATA
+			DDRSS_CTL_203_DATA
+			DDRSS_CTL_204_DATA
+			DDRSS_CTL_205_DATA
+			DDRSS_CTL_206_DATA
+			DDRSS_CTL_207_DATA
+			DDRSS_CTL_208_DATA
+			DDRSS_CTL_209_DATA
+			DDRSS_CTL_210_DATA
+			DDRSS_CTL_211_DATA
+			DDRSS_CTL_212_DATA
+			DDRSS_CTL_213_DATA
+			DDRSS_CTL_214_DATA
+			DDRSS_CTL_215_DATA
+			DDRSS_CTL_216_DATA
+			DDRSS_CTL_217_DATA
+			DDRSS_CTL_218_DATA
+			DDRSS_CTL_219_DATA
+			DDRSS_CTL_220_DATA
+			DDRSS_CTL_221_DATA
+			DDRSS_CTL_222_DATA
+			DDRSS_CTL_223_DATA
+			DDRSS_CTL_224_DATA
+			DDRSS_CTL_225_DATA
+			DDRSS_CTL_226_DATA
+			DDRSS_CTL_227_DATA
+			DDRSS_CTL_228_DATA
+			DDRSS_CTL_229_DATA
+			DDRSS_CTL_230_DATA
+			DDRSS_CTL_231_DATA
+			DDRSS_CTL_232_DATA
+			DDRSS_CTL_233_DATA
+			DDRSS_CTL_234_DATA
+			DDRSS_CTL_235_DATA
+			DDRSS_CTL_236_DATA
+			DDRSS_CTL_237_DATA
+			DDRSS_CTL_238_DATA
+			DDRSS_CTL_239_DATA
+			DDRSS_CTL_240_DATA
+			DDRSS_CTL_241_DATA
+			DDRSS_CTL_242_DATA
+			DDRSS_CTL_243_DATA
+			DDRSS_CTL_244_DATA
+			DDRSS_CTL_245_DATA
+			DDRSS_CTL_246_DATA
+			DDRSS_CTL_247_DATA
+			DDRSS_CTL_248_DATA
+			DDRSS_CTL_249_DATA
+			DDRSS_CTL_250_DATA
+			DDRSS_CTL_251_DATA
+			DDRSS_CTL_252_DATA
+			DDRSS_CTL_253_DATA
+			DDRSS_CTL_254_DATA
+			DDRSS_CTL_255_DATA
+			DDRSS_CTL_256_DATA
+			DDRSS_CTL_257_DATA
+			DDRSS_CTL_258_DATA
+			DDRSS_CTL_259_DATA
+			DDRSS_CTL_260_DATA
+			DDRSS_CTL_261_DATA
+			DDRSS_CTL_262_DATA
+			DDRSS_CTL_263_DATA
+			DDRSS_CTL_264_DATA
+			DDRSS_CTL_265_DATA
+			DDRSS_CTL_266_DATA
+			DDRSS_CTL_267_DATA
+			DDRSS_CTL_268_DATA
+			DDRSS_CTL_269_DATA
+			DDRSS_CTL_270_DATA
+			DDRSS_CTL_271_DATA
+			DDRSS_CTL_272_DATA
+			DDRSS_CTL_273_DATA
+			DDRSS_CTL_274_DATA
+			DDRSS_CTL_275_DATA
+			DDRSS_CTL_276_DATA
+			DDRSS_CTL_277_DATA
+			DDRSS_CTL_278_DATA
+			DDRSS_CTL_279_DATA
+			DDRSS_CTL_280_DATA
+			DDRSS_CTL_281_DATA
+			DDRSS_CTL_282_DATA
+			DDRSS_CTL_283_DATA
+			DDRSS_CTL_284_DATA
+			DDRSS_CTL_285_DATA
+			DDRSS_CTL_286_DATA
+			DDRSS_CTL_287_DATA
+			DDRSS_CTL_288_DATA
+			DDRSS_CTL_289_DATA
+			DDRSS_CTL_290_DATA
+			DDRSS_CTL_291_DATA
+			DDRSS_CTL_292_DATA
+			DDRSS_CTL_293_DATA
+			DDRSS_CTL_294_DATA
+			DDRSS_CTL_295_DATA
+			DDRSS_CTL_296_DATA
+			DDRSS_CTL_297_DATA
+			DDRSS_CTL_298_DATA
+			DDRSS_CTL_299_DATA
+			DDRSS_CTL_300_DATA
+			DDRSS_CTL_301_DATA
+			DDRSS_CTL_302_DATA
+			DDRSS_CTL_303_DATA
+			DDRSS_CTL_304_DATA
+			DDRSS_CTL_305_DATA
+			DDRSS_CTL_306_DATA
+			DDRSS_CTL_307_DATA
+			DDRSS_CTL_308_DATA
+			DDRSS_CTL_309_DATA
+			DDRSS_CTL_310_DATA
+			DDRSS_CTL_311_DATA
+			DDRSS_CTL_312_DATA
+			DDRSS_CTL_313_DATA
+			DDRSS_CTL_314_DATA
+			DDRSS_CTL_315_DATA
+			DDRSS_CTL_316_DATA
+			DDRSS_CTL_317_DATA
+			DDRSS_CTL_318_DATA
+			DDRSS_CTL_319_DATA
+			DDRSS_CTL_320_DATA
+			DDRSS_CTL_321_DATA
+			DDRSS_CTL_322_DATA
+			DDRSS_CTL_323_DATA
+			DDRSS_CTL_324_DATA
+			DDRSS_CTL_325_DATA
+			DDRSS_CTL_326_DATA
+			DDRSS_CTL_327_DATA
+			DDRSS_CTL_328_DATA
+			DDRSS_CTL_329_DATA
+			DDRSS_CTL_330_DATA
+			DDRSS_CTL_331_DATA
+			DDRSS_CTL_332_DATA
+			DDRSS_CTL_333_DATA
+			DDRSS_CTL_334_DATA
+			DDRSS_CTL_335_DATA
+			DDRSS_CTL_336_DATA
+			DDRSS_CTL_337_DATA
+			DDRSS_CTL_338_DATA
+			DDRSS_CTL_339_DATA
+			DDRSS_CTL_340_DATA
+			DDRSS_CTL_341_DATA
+			DDRSS_CTL_342_DATA
+			DDRSS_CTL_343_DATA
+			DDRSS_CTL_344_DATA
+			DDRSS_CTL_345_DATA
+			DDRSS_CTL_346_DATA
+			DDRSS_CTL_347_DATA
+			DDRSS_CTL_348_DATA
+			DDRSS_CTL_349_DATA
+			DDRSS_CTL_350_DATA
+			DDRSS_CTL_351_DATA
+			DDRSS_CTL_352_DATA
+			DDRSS_CTL_353_DATA
+			DDRSS_CTL_354_DATA
+			DDRSS_CTL_355_DATA
+			DDRSS_CTL_356_DATA
+			DDRSS_CTL_357_DATA
+			DDRSS_CTL_358_DATA
+			DDRSS_CTL_359_DATA
+			DDRSS_CTL_360_DATA
+			DDRSS_CTL_361_DATA
+			DDRSS_CTL_362_DATA
+			DDRSS_CTL_363_DATA
+			DDRSS_CTL_364_DATA
+			DDRSS_CTL_365_DATA
+			DDRSS_CTL_366_DATA
+			DDRSS_CTL_367_DATA
+			DDRSS_CTL_368_DATA
+			DDRSS_CTL_369_DATA
+			DDRSS_CTL_370_DATA
+			DDRSS_CTL_371_DATA
+			DDRSS_CTL_372_DATA
+			DDRSS_CTL_373_DATA
+			DDRSS_CTL_374_DATA
+			DDRSS_CTL_375_DATA
+			DDRSS_CTL_376_DATA
+			DDRSS_CTL_377_DATA
+			DDRSS_CTL_378_DATA
+			DDRSS_CTL_379_DATA
+			DDRSS_CTL_380_DATA
+			DDRSS_CTL_381_DATA
+			DDRSS_CTL_382_DATA
+			DDRSS_CTL_383_DATA
+			DDRSS_CTL_384_DATA
+			DDRSS_CTL_385_DATA
+			DDRSS_CTL_386_DATA
+			DDRSS_CTL_387_DATA
+			DDRSS_CTL_388_DATA
+			DDRSS_CTL_389_DATA
+			DDRSS_CTL_390_DATA
+			DDRSS_CTL_391_DATA
+			DDRSS_CTL_392_DATA
+			DDRSS_CTL_393_DATA
+			DDRSS_CTL_394_DATA
+			DDRSS_CTL_395_DATA
+			DDRSS_CTL_396_DATA
+			DDRSS_CTL_397_DATA
+			DDRSS_CTL_398_DATA
+			DDRSS_CTL_399_DATA
+			DDRSS_CTL_400_DATA
+			DDRSS_CTL_401_DATA
+			DDRSS_CTL_402_DATA
+			DDRSS_CTL_403_DATA
+			DDRSS_CTL_404_DATA
+			DDRSS_CTL_405_DATA
+			DDRSS_CTL_406_DATA
+			DDRSS_CTL_407_DATA
+			DDRSS_CTL_408_DATA
+			DDRSS_CTL_409_DATA
+			DDRSS_CTL_410_DATA
+			DDRSS_CTL_411_DATA
+			DDRSS_CTL_412_DATA
+			DDRSS_CTL_413_DATA
+			DDRSS_CTL_414_DATA
+			DDRSS_CTL_415_DATA
+			DDRSS_CTL_416_DATA
+			DDRSS_CTL_417_DATA
+			DDRSS_CTL_418_DATA
+			DDRSS_CTL_419_DATA
+			DDRSS_CTL_420_DATA
+			DDRSS_CTL_421_DATA
+			DDRSS_CTL_422_DATA
+		>;
+
+		ti,pi-data = <
+			DDRSS_PI_0_DATA
+			DDRSS_PI_1_DATA
+			DDRSS_PI_2_DATA
+			DDRSS_PI_3_DATA
+			DDRSS_PI_4_DATA
+			DDRSS_PI_5_DATA
+			DDRSS_PI_6_DATA
+			DDRSS_PI_7_DATA
+			DDRSS_PI_8_DATA
+			DDRSS_PI_9_DATA
+			DDRSS_PI_10_DATA
+			DDRSS_PI_11_DATA
+			DDRSS_PI_12_DATA
+			DDRSS_PI_13_DATA
+			DDRSS_PI_14_DATA
+			DDRSS_PI_15_DATA
+			DDRSS_PI_16_DATA
+			DDRSS_PI_17_DATA
+			DDRSS_PI_18_DATA
+			DDRSS_PI_19_DATA
+			DDRSS_PI_20_DATA
+			DDRSS_PI_21_DATA
+			DDRSS_PI_22_DATA
+			DDRSS_PI_23_DATA
+			DDRSS_PI_24_DATA
+			DDRSS_PI_25_DATA
+			DDRSS_PI_26_DATA
+			DDRSS_PI_27_DATA
+			DDRSS_PI_28_DATA
+			DDRSS_PI_29_DATA
+			DDRSS_PI_30_DATA
+			DDRSS_PI_31_DATA
+			DDRSS_PI_32_DATA
+			DDRSS_PI_33_DATA
+			DDRSS_PI_34_DATA
+			DDRSS_PI_35_DATA
+			DDRSS_PI_36_DATA
+			DDRSS_PI_37_DATA
+			DDRSS_PI_38_DATA
+			DDRSS_PI_39_DATA
+			DDRSS_PI_40_DATA
+			DDRSS_PI_41_DATA
+			DDRSS_PI_42_DATA
+			DDRSS_PI_43_DATA
+			DDRSS_PI_44_DATA
+			DDRSS_PI_45_DATA
+			DDRSS_PI_46_DATA
+			DDRSS_PI_47_DATA
+			DDRSS_PI_48_DATA
+			DDRSS_PI_49_DATA
+			DDRSS_PI_50_DATA
+			DDRSS_PI_51_DATA
+			DDRSS_PI_52_DATA
+			DDRSS_PI_53_DATA
+			DDRSS_PI_54_DATA
+			DDRSS_PI_55_DATA
+			DDRSS_PI_56_DATA
+			DDRSS_PI_57_DATA
+			DDRSS_PI_58_DATA
+			DDRSS_PI_59_DATA
+			DDRSS_PI_60_DATA
+			DDRSS_PI_61_DATA
+			DDRSS_PI_62_DATA
+			DDRSS_PI_63_DATA
+			DDRSS_PI_64_DATA
+			DDRSS_PI_65_DATA
+			DDRSS_PI_66_DATA
+			DDRSS_PI_67_DATA
+			DDRSS_PI_68_DATA
+			DDRSS_PI_69_DATA
+			DDRSS_PI_70_DATA
+			DDRSS_PI_71_DATA
+			DDRSS_PI_72_DATA
+			DDRSS_PI_73_DATA
+			DDRSS_PI_74_DATA
+			DDRSS_PI_75_DATA
+			DDRSS_PI_76_DATA
+			DDRSS_PI_77_DATA
+			DDRSS_PI_78_DATA
+			DDRSS_PI_79_DATA
+			DDRSS_PI_80_DATA
+			DDRSS_PI_81_DATA
+			DDRSS_PI_82_DATA
+			DDRSS_PI_83_DATA
+			DDRSS_PI_84_DATA
+			DDRSS_PI_85_DATA
+			DDRSS_PI_86_DATA
+			DDRSS_PI_87_DATA
+			DDRSS_PI_88_DATA
+			DDRSS_PI_89_DATA
+			DDRSS_PI_90_DATA
+			DDRSS_PI_91_DATA
+			DDRSS_PI_92_DATA
+			DDRSS_PI_93_DATA
+			DDRSS_PI_94_DATA
+			DDRSS_PI_95_DATA
+			DDRSS_PI_96_DATA
+			DDRSS_PI_97_DATA
+			DDRSS_PI_98_DATA
+			DDRSS_PI_99_DATA
+			DDRSS_PI_100_DATA
+			DDRSS_PI_101_DATA
+			DDRSS_PI_102_DATA
+			DDRSS_PI_103_DATA
+			DDRSS_PI_104_DATA
+			DDRSS_PI_105_DATA
+			DDRSS_PI_106_DATA
+			DDRSS_PI_107_DATA
+			DDRSS_PI_108_DATA
+			DDRSS_PI_109_DATA
+			DDRSS_PI_110_DATA
+			DDRSS_PI_111_DATA
+			DDRSS_PI_112_DATA
+			DDRSS_PI_113_DATA
+			DDRSS_PI_114_DATA
+			DDRSS_PI_115_DATA
+			DDRSS_PI_116_DATA
+			DDRSS_PI_117_DATA
+			DDRSS_PI_118_DATA
+			DDRSS_PI_119_DATA
+			DDRSS_PI_120_DATA
+			DDRSS_PI_121_DATA
+			DDRSS_PI_122_DATA
+			DDRSS_PI_123_DATA
+			DDRSS_PI_124_DATA
+			DDRSS_PI_125_DATA
+			DDRSS_PI_126_DATA
+			DDRSS_PI_127_DATA
+			DDRSS_PI_128_DATA
+			DDRSS_PI_129_DATA
+			DDRSS_PI_130_DATA
+			DDRSS_PI_131_DATA
+			DDRSS_PI_132_DATA
+			DDRSS_PI_133_DATA
+			DDRSS_PI_134_DATA
+			DDRSS_PI_135_DATA
+			DDRSS_PI_136_DATA
+			DDRSS_PI_137_DATA
+			DDRSS_PI_138_DATA
+			DDRSS_PI_139_DATA
+			DDRSS_PI_140_DATA
+			DDRSS_PI_141_DATA
+			DDRSS_PI_142_DATA
+			DDRSS_PI_143_DATA
+			DDRSS_PI_144_DATA
+			DDRSS_PI_145_DATA
+			DDRSS_PI_146_DATA
+			DDRSS_PI_147_DATA
+			DDRSS_PI_148_DATA
+			DDRSS_PI_149_DATA
+			DDRSS_PI_150_DATA
+			DDRSS_PI_151_DATA
+			DDRSS_PI_152_DATA
+			DDRSS_PI_153_DATA
+			DDRSS_PI_154_DATA
+			DDRSS_PI_155_DATA
+			DDRSS_PI_156_DATA
+			DDRSS_PI_157_DATA
+			DDRSS_PI_158_DATA
+			DDRSS_PI_159_DATA
+			DDRSS_PI_160_DATA
+			DDRSS_PI_161_DATA
+			DDRSS_PI_162_DATA
+			DDRSS_PI_163_DATA
+			DDRSS_PI_164_DATA
+			DDRSS_PI_165_DATA
+			DDRSS_PI_166_DATA
+			DDRSS_PI_167_DATA
+			DDRSS_PI_168_DATA
+			DDRSS_PI_169_DATA
+			DDRSS_PI_170_DATA
+			DDRSS_PI_171_DATA
+			DDRSS_PI_172_DATA
+			DDRSS_PI_173_DATA
+			DDRSS_PI_174_DATA
+			DDRSS_PI_175_DATA
+			DDRSS_PI_176_DATA
+			DDRSS_PI_177_DATA
+			DDRSS_PI_178_DATA
+			DDRSS_PI_179_DATA
+			DDRSS_PI_180_DATA
+			DDRSS_PI_181_DATA
+			DDRSS_PI_182_DATA
+			DDRSS_PI_183_DATA
+			DDRSS_PI_184_DATA
+			DDRSS_PI_185_DATA
+			DDRSS_PI_186_DATA
+			DDRSS_PI_187_DATA
+			DDRSS_PI_188_DATA
+			DDRSS_PI_189_DATA
+			DDRSS_PI_190_DATA
+			DDRSS_PI_191_DATA
+			DDRSS_PI_192_DATA
+			DDRSS_PI_193_DATA
+			DDRSS_PI_194_DATA
+			DDRSS_PI_195_DATA
+			DDRSS_PI_196_DATA
+			DDRSS_PI_197_DATA
+			DDRSS_PI_198_DATA
+			DDRSS_PI_199_DATA
+			DDRSS_PI_200_DATA
+			DDRSS_PI_201_DATA
+			DDRSS_PI_202_DATA
+			DDRSS_PI_203_DATA
+			DDRSS_PI_204_DATA
+			DDRSS_PI_205_DATA
+			DDRSS_PI_206_DATA
+			DDRSS_PI_207_DATA
+			DDRSS_PI_208_DATA
+			DDRSS_PI_209_DATA
+			DDRSS_PI_210_DATA
+			DDRSS_PI_211_DATA
+			DDRSS_PI_212_DATA
+			DDRSS_PI_213_DATA
+			DDRSS_PI_214_DATA
+			DDRSS_PI_215_DATA
+			DDRSS_PI_216_DATA
+			DDRSS_PI_217_DATA
+			DDRSS_PI_218_DATA
+			DDRSS_PI_219_DATA
+			DDRSS_PI_220_DATA
+			DDRSS_PI_221_DATA
+			DDRSS_PI_222_DATA
+			DDRSS_PI_223_DATA
+			DDRSS_PI_224_DATA
+			DDRSS_PI_225_DATA
+			DDRSS_PI_226_DATA
+			DDRSS_PI_227_DATA
+			DDRSS_PI_228_DATA
+			DDRSS_PI_229_DATA
+			DDRSS_PI_230_DATA
+			DDRSS_PI_231_DATA
+			DDRSS_PI_232_DATA
+			DDRSS_PI_233_DATA
+			DDRSS_PI_234_DATA
+			DDRSS_PI_235_DATA
+			DDRSS_PI_236_DATA
+			DDRSS_PI_237_DATA
+			DDRSS_PI_238_DATA
+			DDRSS_PI_239_DATA
+			DDRSS_PI_240_DATA
+			DDRSS_PI_241_DATA
+			DDRSS_PI_242_DATA
+			DDRSS_PI_243_DATA
+			DDRSS_PI_244_DATA
+			DDRSS_PI_245_DATA
+			DDRSS_PI_246_DATA
+			DDRSS_PI_247_DATA
+			DDRSS_PI_248_DATA
+			DDRSS_PI_249_DATA
+			DDRSS_PI_250_DATA
+			DDRSS_PI_251_DATA
+			DDRSS_PI_252_DATA
+			DDRSS_PI_253_DATA
+			DDRSS_PI_254_DATA
+			DDRSS_PI_255_DATA
+			DDRSS_PI_256_DATA
+			DDRSS_PI_257_DATA
+			DDRSS_PI_258_DATA
+			DDRSS_PI_259_DATA
+			DDRSS_PI_260_DATA
+			DDRSS_PI_261_DATA
+			DDRSS_PI_262_DATA
+			DDRSS_PI_263_DATA
+			DDRSS_PI_264_DATA
+			DDRSS_PI_265_DATA
+			DDRSS_PI_266_DATA
+			DDRSS_PI_267_DATA
+			DDRSS_PI_268_DATA
+			DDRSS_PI_269_DATA
+			DDRSS_PI_270_DATA
+			DDRSS_PI_271_DATA
+			DDRSS_PI_272_DATA
+			DDRSS_PI_273_DATA
+			DDRSS_PI_274_DATA
+			DDRSS_PI_275_DATA
+			DDRSS_PI_276_DATA
+			DDRSS_PI_277_DATA
+			DDRSS_PI_278_DATA
+			DDRSS_PI_279_DATA
+			DDRSS_PI_280_DATA
+			DDRSS_PI_281_DATA
+			DDRSS_PI_282_DATA
+			DDRSS_PI_283_DATA
+			DDRSS_PI_284_DATA
+			DDRSS_PI_285_DATA
+			DDRSS_PI_286_DATA
+			DDRSS_PI_287_DATA
+			DDRSS_PI_288_DATA
+			DDRSS_PI_289_DATA
+			DDRSS_PI_290_DATA
+			DDRSS_PI_291_DATA
+			DDRSS_PI_292_DATA
+			DDRSS_PI_293_DATA
+			DDRSS_PI_294_DATA
+			DDRSS_PI_295_DATA
+			DDRSS_PI_296_DATA
+			DDRSS_PI_297_DATA
+			DDRSS_PI_298_DATA
+			DDRSS_PI_299_DATA
+			DDRSS_PI_300_DATA
+			DDRSS_PI_301_DATA
+			DDRSS_PI_302_DATA
+			DDRSS_PI_303_DATA
+			DDRSS_PI_304_DATA
+			DDRSS_PI_305_DATA
+			DDRSS_PI_306_DATA
+			DDRSS_PI_307_DATA
+			DDRSS_PI_308_DATA
+			DDRSS_PI_309_DATA
+			DDRSS_PI_310_DATA
+			DDRSS_PI_311_DATA
+			DDRSS_PI_312_DATA
+			DDRSS_PI_313_DATA
+			DDRSS_PI_314_DATA
+			DDRSS_PI_315_DATA
+			DDRSS_PI_316_DATA
+			DDRSS_PI_317_DATA
+			DDRSS_PI_318_DATA
+			DDRSS_PI_319_DATA
+			DDRSS_PI_320_DATA
+			DDRSS_PI_321_DATA
+			DDRSS_PI_321_DATA
+			DDRSS_PI_322_DATA
+			DDRSS_PI_323_DATA
+			DDRSS_PI_324_DATA
+			DDRSS_PI_325_DATA
+			DDRSS_PI_326_DATA
+			DDRSS_PI_327_DATA
+			DDRSS_PI_328_DATA
+			DDRSS_PI_329_DATA
+			DDRSS_PI_330_DATA
+			DDRSS_PI_331_DATA
+			DDRSS_PI_332_DATA
+			DDRSS_PI_333_DATA
+			DDRSS_PI_334_DATA
+			DDRSS_PI_335_DATA
+			DDRSS_PI_336_DATA
+			DDRSS_PI_337_DATA
+			DDRSS_PI_338_DATA
+			DDRSS_PI_339_DATA
+			DDRSS_PI_340_DATA
+			DDRSS_PI_341_DATA
+			DDRSS_PI_342_DATA
+			DDRSS_PI_343_DATA
+			DDRSS_PI_344_DATA
+		>;
+
+		ti,phy-data = <
+			DDRSS_PHY_0_DATA
+			DDRSS_PHY_1_DATA
+			DDRSS_PHY_2_DATA
+			DDRSS_PHY_3_DATA
+			DDRSS_PHY_4_DATA
+			DDRSS_PHY_5_DATA
+			DDRSS_PHY_6_DATA
+			DDRSS_PHY_7_DATA
+			DDRSS_PHY_8_DATA
+			DDRSS_PHY_9_DATA
+			DDRSS_PHY_10_DATA
+			DDRSS_PHY_11_DATA
+			DDRSS_PHY_12_DATA
+			DDRSS_PHY_13_DATA
+			DDRSS_PHY_14_DATA
+			DDRSS_PHY_15_DATA
+			DDRSS_PHY_16_DATA
+			DDRSS_PHY_17_DATA
+			DDRSS_PHY_18_DATA
+			DDRSS_PHY_19_DATA
+			DDRSS_PHY_20_DATA
+			DDRSS_PHY_21_DATA
+			DDRSS_PHY_22_DATA
+			DDRSS_PHY_23_DATA
+			DDRSS_PHY_24_DATA
+			DDRSS_PHY_25_DATA
+			DDRSS_PHY_26_DATA
+			DDRSS_PHY_27_DATA
+			DDRSS_PHY_28_DATA
+			DDRSS_PHY_29_DATA
+			DDRSS_PHY_30_DATA
+			DDRSS_PHY_31_DATA
+			DDRSS_PHY_32_DATA
+			DDRSS_PHY_33_DATA
+			DDRSS_PHY_34_DATA
+			DDRSS_PHY_35_DATA
+			DDRSS_PHY_36_DATA
+			DDRSS_PHY_37_DATA
+			DDRSS_PHY_38_DATA
+			DDRSS_PHY_39_DATA
+			DDRSS_PHY_40_DATA
+			DDRSS_PHY_41_DATA
+			DDRSS_PHY_42_DATA
+			DDRSS_PHY_43_DATA
+			DDRSS_PHY_44_DATA
+			DDRSS_PHY_45_DATA
+			DDRSS_PHY_46_DATA
+			DDRSS_PHY_47_DATA
+			DDRSS_PHY_48_DATA
+			DDRSS_PHY_49_DATA
+			DDRSS_PHY_50_DATA
+			DDRSS_PHY_51_DATA
+			DDRSS_PHY_52_DATA
+			DDRSS_PHY_53_DATA
+			DDRSS_PHY_54_DATA
+			DDRSS_PHY_55_DATA
+			DDRSS_PHY_56_DATA
+			DDRSS_PHY_57_DATA
+			DDRSS_PHY_58_DATA
+			DDRSS_PHY_59_DATA
+			DDRSS_PHY_60_DATA
+			DDRSS_PHY_61_DATA
+			DDRSS_PHY_62_DATA
+			DDRSS_PHY_63_DATA
+			DDRSS_PHY_64_DATA
+			DDRSS_PHY_65_DATA
+			DDRSS_PHY_66_DATA
+			DDRSS_PHY_67_DATA
+			DDRSS_PHY_68_DATA
+			DDRSS_PHY_69_DATA
+			DDRSS_PHY_70_DATA
+			DDRSS_PHY_71_DATA
+			DDRSS_PHY_72_DATA
+			DDRSS_PHY_73_DATA
+			DDRSS_PHY_74_DATA
+			DDRSS_PHY_75_DATA
+			DDRSS_PHY_76_DATA
+			DDRSS_PHY_77_DATA
+			DDRSS_PHY_78_DATA
+			DDRSS_PHY_79_DATA
+			DDRSS_PHY_80_DATA
+			DDRSS_PHY_81_DATA
+			DDRSS_PHY_82_DATA
+			DDRSS_PHY_83_DATA
+			DDRSS_PHY_84_DATA
+			DDRSS_PHY_85_DATA
+			DDRSS_PHY_86_DATA
+			DDRSS_PHY_87_DATA
+			DDRSS_PHY_88_DATA
+			DDRSS_PHY_89_DATA
+			DDRSS_PHY_90_DATA
+			DDRSS_PHY_91_DATA
+			DDRSS_PHY_92_DATA
+			DDRSS_PHY_93_DATA
+			DDRSS_PHY_94_DATA
+			DDRSS_PHY_95_DATA
+			DDRSS_PHY_96_DATA
+			DDRSS_PHY_97_DATA
+			DDRSS_PHY_98_DATA
+			DDRSS_PHY_99_DATA
+			DDRSS_PHY_100_DATA
+			DDRSS_PHY_101_DATA
+			DDRSS_PHY_102_DATA
+			DDRSS_PHY_103_DATA
+			DDRSS_PHY_104_DATA
+			DDRSS_PHY_105_DATA
+			DDRSS_PHY_106_DATA
+			DDRSS_PHY_107_DATA
+			DDRSS_PHY_108_DATA
+			DDRSS_PHY_109_DATA
+			DDRSS_PHY_110_DATA
+			DDRSS_PHY_111_DATA
+			DDRSS_PHY_112_DATA
+			DDRSS_PHY_113_DATA
+			DDRSS_PHY_114_DATA
+			DDRSS_PHY_115_DATA
+			DDRSS_PHY_116_DATA
+			DDRSS_PHY_117_DATA
+			DDRSS_PHY_118_DATA
+			DDRSS_PHY_119_DATA
+			DDRSS_PHY_120_DATA
+			DDRSS_PHY_121_DATA
+			DDRSS_PHY_122_DATA
+			DDRSS_PHY_123_DATA
+			DDRSS_PHY_124_DATA
+			DDRSS_PHY_125_DATA
+			DDRSS_PHY_126_DATA
+			DDRSS_PHY_127_DATA
+			DDRSS_PHY_128_DATA
+			DDRSS_PHY_129_DATA
+			DDRSS_PHY_130_DATA
+			DDRSS_PHY_131_DATA
+			DDRSS_PHY_132_DATA
+			DDRSS_PHY_133_DATA
+			DDRSS_PHY_134_DATA
+			DDRSS_PHY_135_DATA
+			DDRSS_PHY_136_DATA
+			DDRSS_PHY_137_DATA
+			DDRSS_PHY_138_DATA
+			DDRSS_PHY_139_DATA
+			DDRSS_PHY_140_DATA
+			DDRSS_PHY_141_DATA
+			DDRSS_PHY_142_DATA
+			DDRSS_PHY_143_DATA
+			DDRSS_PHY_144_DATA
+			DDRSS_PHY_145_DATA
+			DDRSS_PHY_146_DATA
+			DDRSS_PHY_147_DATA
+			DDRSS_PHY_148_DATA
+			DDRSS_PHY_149_DATA
+			DDRSS_PHY_150_DATA
+			DDRSS_PHY_151_DATA
+			DDRSS_PHY_152_DATA
+			DDRSS_PHY_153_DATA
+			DDRSS_PHY_154_DATA
+			DDRSS_PHY_155_DATA
+			DDRSS_PHY_156_DATA
+			DDRSS_PHY_157_DATA
+			DDRSS_PHY_158_DATA
+			DDRSS_PHY_159_DATA
+			DDRSS_PHY_160_DATA
+			DDRSS_PHY_161_DATA
+			DDRSS_PHY_162_DATA
+			DDRSS_PHY_163_DATA
+			DDRSS_PHY_164_DATA
+			DDRSS_PHY_165_DATA
+			DDRSS_PHY_166_DATA
+			DDRSS_PHY_167_DATA
+			DDRSS_PHY_168_DATA
+			DDRSS_PHY_169_DATA
+			DDRSS_PHY_170_DATA
+			DDRSS_PHY_171_DATA
+			DDRSS_PHY_172_DATA
+			DDRSS_PHY_173_DATA
+			DDRSS_PHY_174_DATA
+			DDRSS_PHY_175_DATA
+			DDRSS_PHY_176_DATA
+			DDRSS_PHY_177_DATA
+			DDRSS_PHY_178_DATA
+			DDRSS_PHY_179_DATA
+			DDRSS_PHY_180_DATA
+			DDRSS_PHY_181_DATA
+			DDRSS_PHY_182_DATA
+			DDRSS_PHY_183_DATA
+			DDRSS_PHY_184_DATA
+			DDRSS_PHY_185_DATA
+			DDRSS_PHY_186_DATA
+			DDRSS_PHY_187_DATA
+			DDRSS_PHY_188_DATA
+			DDRSS_PHY_189_DATA
+			DDRSS_PHY_190_DATA
+			DDRSS_PHY_191_DATA
+			DDRSS_PHY_192_DATA
+			DDRSS_PHY_193_DATA
+			DDRSS_PHY_194_DATA
+			DDRSS_PHY_195_DATA
+			DDRSS_PHY_196_DATA
+			DDRSS_PHY_197_DATA
+			DDRSS_PHY_198_DATA
+			DDRSS_PHY_199_DATA
+			DDRSS_PHY_200_DATA
+			DDRSS_PHY_201_DATA
+			DDRSS_PHY_202_DATA
+			DDRSS_PHY_203_DATA
+			DDRSS_PHY_204_DATA
+			DDRSS_PHY_205_DATA
+			DDRSS_PHY_206_DATA
+			DDRSS_PHY_207_DATA
+			DDRSS_PHY_208_DATA
+			DDRSS_PHY_209_DATA
+			DDRSS_PHY_210_DATA
+			DDRSS_PHY_211_DATA
+			DDRSS_PHY_212_DATA
+			DDRSS_PHY_213_DATA
+			DDRSS_PHY_214_DATA
+			DDRSS_PHY_215_DATA
+			DDRSS_PHY_216_DATA
+			DDRSS_PHY_217_DATA
+			DDRSS_PHY_218_DATA
+			DDRSS_PHY_219_DATA
+			DDRSS_PHY_220_DATA
+			DDRSS_PHY_221_DATA
+			DDRSS_PHY_222_DATA
+			DDRSS_PHY_223_DATA
+			DDRSS_PHY_224_DATA
+			DDRSS_PHY_225_DATA
+			DDRSS_PHY_226_DATA
+			DDRSS_PHY_227_DATA
+			DDRSS_PHY_228_DATA
+			DDRSS_PHY_229_DATA
+			DDRSS_PHY_230_DATA
+			DDRSS_PHY_231_DATA
+			DDRSS_PHY_232_DATA
+			DDRSS_PHY_233_DATA
+			DDRSS_PHY_234_DATA
+			DDRSS_PHY_235_DATA
+			DDRSS_PHY_236_DATA
+			DDRSS_PHY_237_DATA
+			DDRSS_PHY_238_DATA
+			DDRSS_PHY_239_DATA
+			DDRSS_PHY_240_DATA
+			DDRSS_PHY_241_DATA
+			DDRSS_PHY_242_DATA
+			DDRSS_PHY_243_DATA
+			DDRSS_PHY_244_DATA
+			DDRSS_PHY_245_DATA
+			DDRSS_PHY_246_DATA
+			DDRSS_PHY_247_DATA
+			DDRSS_PHY_248_DATA
+			DDRSS_PHY_249_DATA
+			DDRSS_PHY_250_DATA
+			DDRSS_PHY_251_DATA
+			DDRSS_PHY_252_DATA
+			DDRSS_PHY_253_DATA
+			DDRSS_PHY_254_DATA
+			DDRSS_PHY_255_DATA
+			DDRSS_PHY_256_DATA
+			DDRSS_PHY_257_DATA
+			DDRSS_PHY_258_DATA
+			DDRSS_PHY_259_DATA
+			DDRSS_PHY_260_DATA
+			DDRSS_PHY_261_DATA
+			DDRSS_PHY_262_DATA
+			DDRSS_PHY_263_DATA
+			DDRSS_PHY_264_DATA
+			DDRSS_PHY_265_DATA
+			DDRSS_PHY_266_DATA
+			DDRSS_PHY_267_DATA
+			DDRSS_PHY_268_DATA
+			DDRSS_PHY_269_DATA
+			DDRSS_PHY_270_DATA
+			DDRSS_PHY_271_DATA
+			DDRSS_PHY_272_DATA
+			DDRSS_PHY_273_DATA
+			DDRSS_PHY_274_DATA
+			DDRSS_PHY_275_DATA
+			DDRSS_PHY_276_DATA
+			DDRSS_PHY_277_DATA
+			DDRSS_PHY_278_DATA
+			DDRSS_PHY_279_DATA
+			DDRSS_PHY_280_DATA
+			DDRSS_PHY_281_DATA
+			DDRSS_PHY_282_DATA
+			DDRSS_PHY_283_DATA
+			DDRSS_PHY_284_DATA
+			DDRSS_PHY_285_DATA
+			DDRSS_PHY_286_DATA
+			DDRSS_PHY_287_DATA
+			DDRSS_PHY_288_DATA
+			DDRSS_PHY_289_DATA
+			DDRSS_PHY_290_DATA
+			DDRSS_PHY_291_DATA
+			DDRSS_PHY_292_DATA
+			DDRSS_PHY_293_DATA
+			DDRSS_PHY_294_DATA
+			DDRSS_PHY_295_DATA
+			DDRSS_PHY_296_DATA
+			DDRSS_PHY_297_DATA
+			DDRSS_PHY_298_DATA
+			DDRSS_PHY_299_DATA
+			DDRSS_PHY_300_DATA
+			DDRSS_PHY_301_DATA
+			DDRSS_PHY_302_DATA
+			DDRSS_PHY_303_DATA
+			DDRSS_PHY_304_DATA
+			DDRSS_PHY_305_DATA
+			DDRSS_PHY_306_DATA
+			DDRSS_PHY_307_DATA
+			DDRSS_PHY_308_DATA
+			DDRSS_PHY_309_DATA
+			DDRSS_PHY_310_DATA
+			DDRSS_PHY_311_DATA
+			DDRSS_PHY_312_DATA
+			DDRSS_PHY_313_DATA
+			DDRSS_PHY_314_DATA
+			DDRSS_PHY_315_DATA
+			DDRSS_PHY_316_DATA
+			DDRSS_PHY_317_DATA
+			DDRSS_PHY_318_DATA
+			DDRSS_PHY_319_DATA
+			DDRSS_PHY_320_DATA
+			DDRSS_PHY_321_DATA
+			DDRSS_PHY_322_DATA
+			DDRSS_PHY_323_DATA
+			DDRSS_PHY_324_DATA
+			DDRSS_PHY_325_DATA
+			DDRSS_PHY_326_DATA
+			DDRSS_PHY_327_DATA
+			DDRSS_PHY_328_DATA
+			DDRSS_PHY_329_DATA
+			DDRSS_PHY_330_DATA
+			DDRSS_PHY_331_DATA
+			DDRSS_PHY_332_DATA
+			DDRSS_PHY_333_DATA
+			DDRSS_PHY_334_DATA
+			DDRSS_PHY_335_DATA
+			DDRSS_PHY_336_DATA
+			DDRSS_PHY_337_DATA
+			DDRSS_PHY_338_DATA
+			DDRSS_PHY_339_DATA
+			DDRSS_PHY_340_DATA
+			DDRSS_PHY_341_DATA
+			DDRSS_PHY_342_DATA
+			DDRSS_PHY_343_DATA
+			DDRSS_PHY_344_DATA
+			DDRSS_PHY_345_DATA
+			DDRSS_PHY_346_DATA
+			DDRSS_PHY_347_DATA
+			DDRSS_PHY_348_DATA
+			DDRSS_PHY_349_DATA
+			DDRSS_PHY_350_DATA
+			DDRSS_PHY_351_DATA
+			DDRSS_PHY_352_DATA
+			DDRSS_PHY_353_DATA
+			DDRSS_PHY_354_DATA
+			DDRSS_PHY_355_DATA
+			DDRSS_PHY_356_DATA
+			DDRSS_PHY_357_DATA
+			DDRSS_PHY_358_DATA
+			DDRSS_PHY_359_DATA
+			DDRSS_PHY_360_DATA
+			DDRSS_PHY_361_DATA
+			DDRSS_PHY_362_DATA
+			DDRSS_PHY_363_DATA
+			DDRSS_PHY_364_DATA
+			DDRSS_PHY_365_DATA
+			DDRSS_PHY_366_DATA
+			DDRSS_PHY_367_DATA
+			DDRSS_PHY_368_DATA
+			DDRSS_PHY_369_DATA
+			DDRSS_PHY_370_DATA
+			DDRSS_PHY_371_DATA
+			DDRSS_PHY_372_DATA
+			DDRSS_PHY_373_DATA
+			DDRSS_PHY_374_DATA
+			DDRSS_PHY_375_DATA
+			DDRSS_PHY_376_DATA
+			DDRSS_PHY_377_DATA
+			DDRSS_PHY_378_DATA
+			DDRSS_PHY_379_DATA
+			DDRSS_PHY_380_DATA
+			DDRSS_PHY_381_DATA
+			DDRSS_PHY_382_DATA
+			DDRSS_PHY_383_DATA
+			DDRSS_PHY_384_DATA
+			DDRSS_PHY_385_DATA
+			DDRSS_PHY_386_DATA
+			DDRSS_PHY_387_DATA
+			DDRSS_PHY_388_DATA
+			DDRSS_PHY_389_DATA
+			DDRSS_PHY_390_DATA
+			DDRSS_PHY_391_DATA
+			DDRSS_PHY_392_DATA
+			DDRSS_PHY_393_DATA
+			DDRSS_PHY_394_DATA
+			DDRSS_PHY_395_DATA
+			DDRSS_PHY_396_DATA
+			DDRSS_PHY_397_DATA
+			DDRSS_PHY_398_DATA
+			DDRSS_PHY_399_DATA
+			DDRSS_PHY_400_DATA
+			DDRSS_PHY_401_DATA
+			DDRSS_PHY_402_DATA
+			DDRSS_PHY_403_DATA
+			DDRSS_PHY_404_DATA
+			DDRSS_PHY_405_DATA
+			DDRSS_PHY_406_DATA
+			DDRSS_PHY_407_DATA
+			DDRSS_PHY_408_DATA
+			DDRSS_PHY_409_DATA
+			DDRSS_PHY_410_DATA
+			DDRSS_PHY_411_DATA
+			DDRSS_PHY_412_DATA
+			DDRSS_PHY_413_DATA
+			DDRSS_PHY_414_DATA
+			DDRSS_PHY_415_DATA
+			DDRSS_PHY_416_DATA
+			DDRSS_PHY_417_DATA
+			DDRSS_PHY_418_DATA
+			DDRSS_PHY_419_DATA
+			DDRSS_PHY_420_DATA
+			DDRSS_PHY_421_DATA
+			DDRSS_PHY_422_DATA
+			DDRSS_PHY_423_DATA
+			DDRSS_PHY_424_DATA
+			DDRSS_PHY_425_DATA
+			DDRSS_PHY_426_DATA
+			DDRSS_PHY_427_DATA
+			DDRSS_PHY_428_DATA
+			DDRSS_PHY_429_DATA
+			DDRSS_PHY_430_DATA
+			DDRSS_PHY_431_DATA
+			DDRSS_PHY_432_DATA
+			DDRSS_PHY_433_DATA
+			DDRSS_PHY_434_DATA
+			DDRSS_PHY_435_DATA
+			DDRSS_PHY_436_DATA
+			DDRSS_PHY_437_DATA
+			DDRSS_PHY_438_DATA
+			DDRSS_PHY_439_DATA
+			DDRSS_PHY_440_DATA
+			DDRSS_PHY_441_DATA
+			DDRSS_PHY_442_DATA
+			DDRSS_PHY_443_DATA
+			DDRSS_PHY_444_DATA
+			DDRSS_PHY_445_DATA
+			DDRSS_PHY_446_DATA
+			DDRSS_PHY_447_DATA
+			DDRSS_PHY_448_DATA
+			DDRSS_PHY_449_DATA
+			DDRSS_PHY_450_DATA
+			DDRSS_PHY_451_DATA
+			DDRSS_PHY_452_DATA
+			DDRSS_PHY_453_DATA
+			DDRSS_PHY_454_DATA
+			DDRSS_PHY_455_DATA
+			DDRSS_PHY_456_DATA
+			DDRSS_PHY_457_DATA
+			DDRSS_PHY_458_DATA
+			DDRSS_PHY_459_DATA
+			DDRSS_PHY_460_DATA
+			DDRSS_PHY_461_DATA
+			DDRSS_PHY_462_DATA
+			DDRSS_PHY_463_DATA
+			DDRSS_PHY_464_DATA
+			DDRSS_PHY_465_DATA
+			DDRSS_PHY_466_DATA
+			DDRSS_PHY_467_DATA
+			DDRSS_PHY_468_DATA
+			DDRSS_PHY_469_DATA
+			DDRSS_PHY_470_DATA
+			DDRSS_PHY_471_DATA
+			DDRSS_PHY_472_DATA
+			DDRSS_PHY_473_DATA
+			DDRSS_PHY_474_DATA
+			DDRSS_PHY_475_DATA
+			DDRSS_PHY_476_DATA
+			DDRSS_PHY_477_DATA
+			DDRSS_PHY_478_DATA
+			DDRSS_PHY_479_DATA
+			DDRSS_PHY_480_DATA
+			DDRSS_PHY_481_DATA
+			DDRSS_PHY_482_DATA
+			DDRSS_PHY_483_DATA
+			DDRSS_PHY_484_DATA
+			DDRSS_PHY_485_DATA
+			DDRSS_PHY_486_DATA
+			DDRSS_PHY_487_DATA
+			DDRSS_PHY_488_DATA
+			DDRSS_PHY_489_DATA
+			DDRSS_PHY_490_DATA
+			DDRSS_PHY_491_DATA
+			DDRSS_PHY_492_DATA
+			DDRSS_PHY_493_DATA
+			DDRSS_PHY_494_DATA
+			DDRSS_PHY_495_DATA
+			DDRSS_PHY_496_DATA
+			DDRSS_PHY_497_DATA
+			DDRSS_PHY_498_DATA
+			DDRSS_PHY_499_DATA
+			DDRSS_PHY_500_DATA
+			DDRSS_PHY_501_DATA
+			DDRSS_PHY_502_DATA
+			DDRSS_PHY_503_DATA
+			DDRSS_PHY_504_DATA
+			DDRSS_PHY_505_DATA
+			DDRSS_PHY_506_DATA
+			DDRSS_PHY_507_DATA
+			DDRSS_PHY_508_DATA
+			DDRSS_PHY_509_DATA
+			DDRSS_PHY_510_DATA
+			DDRSS_PHY_511_DATA
+			DDRSS_PHY_512_DATA
+			DDRSS_PHY_513_DATA
+			DDRSS_PHY_514_DATA
+			DDRSS_PHY_515_DATA
+			DDRSS_PHY_516_DATA
+			DDRSS_PHY_517_DATA
+			DDRSS_PHY_518_DATA
+			DDRSS_PHY_519_DATA
+			DDRSS_PHY_520_DATA
+			DDRSS_PHY_521_DATA
+			DDRSS_PHY_522_DATA
+			DDRSS_PHY_523_DATA
+			DDRSS_PHY_524_DATA
+			DDRSS_PHY_525_DATA
+			DDRSS_PHY_526_DATA
+			DDRSS_PHY_527_DATA
+			DDRSS_PHY_528_DATA
+			DDRSS_PHY_529_DATA
+			DDRSS_PHY_530_DATA
+			DDRSS_PHY_531_DATA
+			DDRSS_PHY_532_DATA
+			DDRSS_PHY_533_DATA
+			DDRSS_PHY_534_DATA
+			DDRSS_PHY_535_DATA
+			DDRSS_PHY_536_DATA
+			DDRSS_PHY_537_DATA
+			DDRSS_PHY_538_DATA
+			DDRSS_PHY_539_DATA
+			DDRSS_PHY_540_DATA
+			DDRSS_PHY_541_DATA
+			DDRSS_PHY_542_DATA
+			DDRSS_PHY_543_DATA
+			DDRSS_PHY_544_DATA
+			DDRSS_PHY_545_DATA
+			DDRSS_PHY_546_DATA
+			DDRSS_PHY_547_DATA
+			DDRSS_PHY_548_DATA
+			DDRSS_PHY_549_DATA
+			DDRSS_PHY_550_DATA
+			DDRSS_PHY_551_DATA
+			DDRSS_PHY_552_DATA
+			DDRSS_PHY_553_DATA
+			DDRSS_PHY_554_DATA
+			DDRSS_PHY_555_DATA
+			DDRSS_PHY_556_DATA
+			DDRSS_PHY_557_DATA
+			DDRSS_PHY_558_DATA
+			DDRSS_PHY_559_DATA
+			DDRSS_PHY_560_DATA
+			DDRSS_PHY_561_DATA
+			DDRSS_PHY_562_DATA
+			DDRSS_PHY_563_DATA
+			DDRSS_PHY_564_DATA
+			DDRSS_PHY_565_DATA
+			DDRSS_PHY_566_DATA
+			DDRSS_PHY_567_DATA
+			DDRSS_PHY_568_DATA
+			DDRSS_PHY_569_DATA
+			DDRSS_PHY_570_DATA
+			DDRSS_PHY_571_DATA
+			DDRSS_PHY_572_DATA
+			DDRSS_PHY_573_DATA
+			DDRSS_PHY_574_DATA
+			DDRSS_PHY_575_DATA
+			DDRSS_PHY_576_DATA
+			DDRSS_PHY_577_DATA
+			DDRSS_PHY_578_DATA
+			DDRSS_PHY_579_DATA
+			DDRSS_PHY_580_DATA
+			DDRSS_PHY_581_DATA
+			DDRSS_PHY_582_DATA
+			DDRSS_PHY_583_DATA
+			DDRSS_PHY_584_DATA
+			DDRSS_PHY_585_DATA
+			DDRSS_PHY_586_DATA
+			DDRSS_PHY_587_DATA
+			DDRSS_PHY_588_DATA
+			DDRSS_PHY_589_DATA
+			DDRSS_PHY_590_DATA
+			DDRSS_PHY_591_DATA
+			DDRSS_PHY_592_DATA
+			DDRSS_PHY_593_DATA
+			DDRSS_PHY_594_DATA
+			DDRSS_PHY_595_DATA
+			DDRSS_PHY_596_DATA
+			DDRSS_PHY_597_DATA
+			DDRSS_PHY_598_DATA
+			DDRSS_PHY_599_DATA
+			DDRSS_PHY_600_DATA
+			DDRSS_PHY_601_DATA
+			DDRSS_PHY_602_DATA
+			DDRSS_PHY_603_DATA
+			DDRSS_PHY_604_DATA
+			DDRSS_PHY_605_DATA
+			DDRSS_PHY_606_DATA
+			DDRSS_PHY_607_DATA
+			DDRSS_PHY_608_DATA
+			DDRSS_PHY_609_DATA
+			DDRSS_PHY_610_DATA
+			DDRSS_PHY_611_DATA
+			DDRSS_PHY_612_DATA
+			DDRSS_PHY_613_DATA
+			DDRSS_PHY_614_DATA
+			DDRSS_PHY_615_DATA
+			DDRSS_PHY_616_DATA
+			DDRSS_PHY_617_DATA
+			DDRSS_PHY_618_DATA
+			DDRSS_PHY_619_DATA
+			DDRSS_PHY_620_DATA
+			DDRSS_PHY_621_DATA
+			DDRSS_PHY_622_DATA
+			DDRSS_PHY_623_DATA
+			DDRSS_PHY_624_DATA
+			DDRSS_PHY_625_DATA
+			DDRSS_PHY_626_DATA
+			DDRSS_PHY_627_DATA
+			DDRSS_PHY_628_DATA
+			DDRSS_PHY_629_DATA
+			DDRSS_PHY_630_DATA
+			DDRSS_PHY_631_DATA
+			DDRSS_PHY_632_DATA
+			DDRSS_PHY_633_DATA
+			DDRSS_PHY_634_DATA
+			DDRSS_PHY_635_DATA
+			DDRSS_PHY_636_DATA
+			DDRSS_PHY_637_DATA
+			DDRSS_PHY_638_DATA
+			DDRSS_PHY_639_DATA
+			DDRSS_PHY_640_DATA
+			DDRSS_PHY_641_DATA
+			DDRSS_PHY_642_DATA
+			DDRSS_PHY_643_DATA
+			DDRSS_PHY_644_DATA
+			DDRSS_PHY_645_DATA
+			DDRSS_PHY_646_DATA
+			DDRSS_PHY_647_DATA
+			DDRSS_PHY_648_DATA
+			DDRSS_PHY_649_DATA
+			DDRSS_PHY_650_DATA
+			DDRSS_PHY_651_DATA
+			DDRSS_PHY_652_DATA
+			DDRSS_PHY_653_DATA
+			DDRSS_PHY_654_DATA
+			DDRSS_PHY_655_DATA
+			DDRSS_PHY_656_DATA
+			DDRSS_PHY_657_DATA
+			DDRSS_PHY_658_DATA
+			DDRSS_PHY_659_DATA
+			DDRSS_PHY_660_DATA
+			DDRSS_PHY_661_DATA
+			DDRSS_PHY_662_DATA
+			DDRSS_PHY_663_DATA
+			DDRSS_PHY_664_DATA
+			DDRSS_PHY_665_DATA
+			DDRSS_PHY_666_DATA
+			DDRSS_PHY_667_DATA
+			DDRSS_PHY_668_DATA
+			DDRSS_PHY_669_DATA
+			DDRSS_PHY_670_DATA
+			DDRSS_PHY_671_DATA
+			DDRSS_PHY_672_DATA
+			DDRSS_PHY_673_DATA
+			DDRSS_PHY_674_DATA
+			DDRSS_PHY_675_DATA
+			DDRSS_PHY_676_DATA
+			DDRSS_PHY_677_DATA
+			DDRSS_PHY_678_DATA
+			DDRSS_PHY_679_DATA
+			DDRSS_PHY_680_DATA
+			DDRSS_PHY_681_DATA
+			DDRSS_PHY_682_DATA
+			DDRSS_PHY_683_DATA
+			DDRSS_PHY_684_DATA
+			DDRSS_PHY_685_DATA
+			DDRSS_PHY_686_DATA
+			DDRSS_PHY_687_DATA
+			DDRSS_PHY_688_DATA
+			DDRSS_PHY_689_DATA
+			DDRSS_PHY_690_DATA
+			DDRSS_PHY_691_DATA
+			DDRSS_PHY_692_DATA
+			DDRSS_PHY_693_DATA
+			DDRSS_PHY_694_DATA
+			DDRSS_PHY_695_DATA
+			DDRSS_PHY_696_DATA
+			DDRSS_PHY_697_DATA
+			DDRSS_PHY_698_DATA
+			DDRSS_PHY_699_DATA
+			DDRSS_PHY_700_DATA
+			DDRSS_PHY_701_DATA
+			DDRSS_PHY_702_DATA
+			DDRSS_PHY_703_DATA
+			DDRSS_PHY_704_DATA
+			DDRSS_PHY_705_DATA
+			DDRSS_PHY_706_DATA
+			DDRSS_PHY_707_DATA
+			DDRSS_PHY_708_DATA
+			DDRSS_PHY_709_DATA
+			DDRSS_PHY_710_DATA
+			DDRSS_PHY_711_DATA
+			DDRSS_PHY_712_DATA
+			DDRSS_PHY_713_DATA
+			DDRSS_PHY_714_DATA
+			DDRSS_PHY_715_DATA
+			DDRSS_PHY_716_DATA
+			DDRSS_PHY_717_DATA
+			DDRSS_PHY_718_DATA
+			DDRSS_PHY_719_DATA
+			DDRSS_PHY_720_DATA
+			DDRSS_PHY_721_DATA
+			DDRSS_PHY_722_DATA
+			DDRSS_PHY_723_DATA
+			DDRSS_PHY_724_DATA
+			DDRSS_PHY_725_DATA
+			DDRSS_PHY_726_DATA
+			DDRSS_PHY_727_DATA
+			DDRSS_PHY_728_DATA
+			DDRSS_PHY_729_DATA
+			DDRSS_PHY_730_DATA
+			DDRSS_PHY_731_DATA
+			DDRSS_PHY_732_DATA
+			DDRSS_PHY_733_DATA
+			DDRSS_PHY_734_DATA
+			DDRSS_PHY_735_DATA
+			DDRSS_PHY_736_DATA
+			DDRSS_PHY_737_DATA
+			DDRSS_PHY_738_DATA
+			DDRSS_PHY_739_DATA
+			DDRSS_PHY_740_DATA
+			DDRSS_PHY_741_DATA
+			DDRSS_PHY_742_DATA
+			DDRSS_PHY_743_DATA
+			DDRSS_PHY_744_DATA
+			DDRSS_PHY_745_DATA
+			DDRSS_PHY_746_DATA
+			DDRSS_PHY_747_DATA
+			DDRSS_PHY_748_DATA
+			DDRSS_PHY_749_DATA
+			DDRSS_PHY_750_DATA
+			DDRSS_PHY_751_DATA
+			DDRSS_PHY_752_DATA
+			DDRSS_PHY_753_DATA
+			DDRSS_PHY_754_DATA
+			DDRSS_PHY_755_DATA
+			DDRSS_PHY_756_DATA
+			DDRSS_PHY_757_DATA
+			DDRSS_PHY_758_DATA
+			DDRSS_PHY_759_DATA
+			DDRSS_PHY_760_DATA
+			DDRSS_PHY_761_DATA
+			DDRSS_PHY_762_DATA
+			DDRSS_PHY_763_DATA
+			DDRSS_PHY_764_DATA
+			DDRSS_PHY_765_DATA
+			DDRSS_PHY_766_DATA
+			DDRSS_PHY_767_DATA
+			DDRSS_PHY_768_DATA
+			DDRSS_PHY_769_DATA
+			DDRSS_PHY_770_DATA
+			DDRSS_PHY_771_DATA
+			DDRSS_PHY_772_DATA
+			DDRSS_PHY_773_DATA
+			DDRSS_PHY_774_DATA
+			DDRSS_PHY_775_DATA
+			DDRSS_PHY_776_DATA
+			DDRSS_PHY_777_DATA
+			DDRSS_PHY_778_DATA
+			DDRSS_PHY_779_DATA
+			DDRSS_PHY_780_DATA
+			DDRSS_PHY_781_DATA
+			DDRSS_PHY_782_DATA
+			DDRSS_PHY_783_DATA
+			DDRSS_PHY_784_DATA
+			DDRSS_PHY_785_DATA
+			DDRSS_PHY_786_DATA
+			DDRSS_PHY_787_DATA
+			DDRSS_PHY_788_DATA
+			DDRSS_PHY_789_DATA
+			DDRSS_PHY_790_DATA
+			DDRSS_PHY_791_DATA
+			DDRSS_PHY_792_DATA
+			DDRSS_PHY_793_DATA
+			DDRSS_PHY_794_DATA
+			DDRSS_PHY_795_DATA
+			DDRSS_PHY_796_DATA
+			DDRSS_PHY_797_DATA
+			DDRSS_PHY_798_DATA
+			DDRSS_PHY_799_DATA
+			DDRSS_PHY_800_DATA
+			DDRSS_PHY_801_DATA
+			DDRSS_PHY_802_DATA
+			DDRSS_PHY_803_DATA
+			DDRSS_PHY_804_DATA
+			DDRSS_PHY_805_DATA
+			DDRSS_PHY_806_DATA
+			DDRSS_PHY_807_DATA
+			DDRSS_PHY_808_DATA
+			DDRSS_PHY_809_DATA
+			DDRSS_PHY_810_DATA
+			DDRSS_PHY_811_DATA
+			DDRSS_PHY_812_DATA
+			DDRSS_PHY_813_DATA
+			DDRSS_PHY_814_DATA
+			DDRSS_PHY_815_DATA
+			DDRSS_PHY_816_DATA
+			DDRSS_PHY_817_DATA
+			DDRSS_PHY_818_DATA
+			DDRSS_PHY_819_DATA
+			DDRSS_PHY_820_DATA
+			DDRSS_PHY_821_DATA
+			DDRSS_PHY_822_DATA
+			DDRSS_PHY_823_DATA
+			DDRSS_PHY_824_DATA
+			DDRSS_PHY_825_DATA
+			DDRSS_PHY_826_DATA
+			DDRSS_PHY_827_DATA
+			DDRSS_PHY_828_DATA
+			DDRSS_PHY_829_DATA
+			DDRSS_PHY_830_DATA
+			DDRSS_PHY_831_DATA
+			DDRSS_PHY_832_DATA
+			DDRSS_PHY_833_DATA
+			DDRSS_PHY_834_DATA
+			DDRSS_PHY_835_DATA
+			DDRSS_PHY_836_DATA
+			DDRSS_PHY_837_DATA
+			DDRSS_PHY_838_DATA
+			DDRSS_PHY_839_DATA
+			DDRSS_PHY_840_DATA
+			DDRSS_PHY_841_DATA
+			DDRSS_PHY_842_DATA
+			DDRSS_PHY_843_DATA
+			DDRSS_PHY_844_DATA
+			DDRSS_PHY_845_DATA
+			DDRSS_PHY_846_DATA
+			DDRSS_PHY_847_DATA
+			DDRSS_PHY_848_DATA
+			DDRSS_PHY_849_DATA
+			DDRSS_PHY_850_DATA
+			DDRSS_PHY_851_DATA
+			DDRSS_PHY_852_DATA
+			DDRSS_PHY_853_DATA
+			DDRSS_PHY_854_DATA
+			DDRSS_PHY_855_DATA
+			DDRSS_PHY_856_DATA
+			DDRSS_PHY_857_DATA
+			DDRSS_PHY_858_DATA
+			DDRSS_PHY_859_DATA
+			DDRSS_PHY_860_DATA
+			DDRSS_PHY_861_DATA
+			DDRSS_PHY_862_DATA
+			DDRSS_PHY_863_DATA
+			DDRSS_PHY_864_DATA
+			DDRSS_PHY_865_DATA
+			DDRSS_PHY_866_DATA
+			DDRSS_PHY_867_DATA
+			DDRSS_PHY_868_DATA
+			DDRSS_PHY_869_DATA
+			DDRSS_PHY_870_DATA
+			DDRSS_PHY_871_DATA
+			DDRSS_PHY_872_DATA
+			DDRSS_PHY_873_DATA
+			DDRSS_PHY_874_DATA
+			DDRSS_PHY_875_DATA
+			DDRSS_PHY_876_DATA
+			DDRSS_PHY_877_DATA
+			DDRSS_PHY_878_DATA
+			DDRSS_PHY_879_DATA
+			DDRSS_PHY_880_DATA
+			DDRSS_PHY_881_DATA
+			DDRSS_PHY_882_DATA
+			DDRSS_PHY_883_DATA
+			DDRSS_PHY_884_DATA
+			DDRSS_PHY_885_DATA
+			DDRSS_PHY_886_DATA
+			DDRSS_PHY_887_DATA
+			DDRSS_PHY_888_DATA
+			DDRSS_PHY_889_DATA
+			DDRSS_PHY_890_DATA
+			DDRSS_PHY_891_DATA
+			DDRSS_PHY_892_DATA
+			DDRSS_PHY_893_DATA
+			DDRSS_PHY_894_DATA
+			DDRSS_PHY_895_DATA
+			DDRSS_PHY_896_DATA
+			DDRSS_PHY_897_DATA
+			DDRSS_PHY_898_DATA
+			DDRSS_PHY_899_DATA
+			DDRSS_PHY_900_DATA
+			DDRSS_PHY_901_DATA
+			DDRSS_PHY_902_DATA
+			DDRSS_PHY_903_DATA
+			DDRSS_PHY_904_DATA
+			DDRSS_PHY_905_DATA
+			DDRSS_PHY_906_DATA
+			DDRSS_PHY_907_DATA
+			DDRSS_PHY_908_DATA
+			DDRSS_PHY_909_DATA
+			DDRSS_PHY_910_DATA
+			DDRSS_PHY_911_DATA
+			DDRSS_PHY_912_DATA
+			DDRSS_PHY_913_DATA
+			DDRSS_PHY_914_DATA
+			DDRSS_PHY_915_DATA
+			DDRSS_PHY_916_DATA
+			DDRSS_PHY_917_DATA
+			DDRSS_PHY_918_DATA
+			DDRSS_PHY_919_DATA
+			DDRSS_PHY_920_DATA
+			DDRSS_PHY_921_DATA
+			DDRSS_PHY_922_DATA
+			DDRSS_PHY_923_DATA
+			DDRSS_PHY_924_DATA
+			DDRSS_PHY_925_DATA
+			DDRSS_PHY_926_DATA
+			DDRSS_PHY_927_DATA
+			DDRSS_PHY_928_DATA
+			DDRSS_PHY_929_DATA
+			DDRSS_PHY_930_DATA
+			DDRSS_PHY_931_DATA
+			DDRSS_PHY_932_DATA
+			DDRSS_PHY_933_DATA
+			DDRSS_PHY_934_DATA
+			DDRSS_PHY_935_DATA
+			DDRSS_PHY_936_DATA
+			DDRSS_PHY_937_DATA
+			DDRSS_PHY_938_DATA
+			DDRSS_PHY_939_DATA
+			DDRSS_PHY_940_DATA
+			DDRSS_PHY_941_DATA
+			DDRSS_PHY_942_DATA
+			DDRSS_PHY_943_DATA
+			DDRSS_PHY_944_DATA
+			DDRSS_PHY_945_DATA
+			DDRSS_PHY_946_DATA
+			DDRSS_PHY_947_DATA
+			DDRSS_PHY_948_DATA
+			DDRSS_PHY_949_DATA
+			DDRSS_PHY_950_DATA
+			DDRSS_PHY_951_DATA
+			DDRSS_PHY_952_DATA
+			DDRSS_PHY_953_DATA
+			DDRSS_PHY_954_DATA
+			DDRSS_PHY_955_DATA
+			DDRSS_PHY_956_DATA
+			DDRSS_PHY_957_DATA
+			DDRSS_PHY_958_DATA
+			DDRSS_PHY_959_DATA
+			DDRSS_PHY_960_DATA
+			DDRSS_PHY_961_DATA
+			DDRSS_PHY_962_DATA
+			DDRSS_PHY_963_DATA
+			DDRSS_PHY_964_DATA
+			DDRSS_PHY_965_DATA
+			DDRSS_PHY_966_DATA
+			DDRSS_PHY_967_DATA
+			DDRSS_PHY_968_DATA
+			DDRSS_PHY_969_DATA
+			DDRSS_PHY_970_DATA
+			DDRSS_PHY_971_DATA
+			DDRSS_PHY_972_DATA
+			DDRSS_PHY_973_DATA
+			DDRSS_PHY_974_DATA
+			DDRSS_PHY_975_DATA
+			DDRSS_PHY_976_DATA
+			DDRSS_PHY_977_DATA
+			DDRSS_PHY_978_DATA
+			DDRSS_PHY_979_DATA
+			DDRSS_PHY_980_DATA
+			DDRSS_PHY_981_DATA
+			DDRSS_PHY_982_DATA
+			DDRSS_PHY_983_DATA
+			DDRSS_PHY_984_DATA
+			DDRSS_PHY_985_DATA
+			DDRSS_PHY_986_DATA
+			DDRSS_PHY_987_DATA
+			DDRSS_PHY_988_DATA
+			DDRSS_PHY_989_DATA
+			DDRSS_PHY_990_DATA
+			DDRSS_PHY_991_DATA
+			DDRSS_PHY_992_DATA
+			DDRSS_PHY_993_DATA
+			DDRSS_PHY_994_DATA
+			DDRSS_PHY_995_DATA
+			DDRSS_PHY_996_DATA
+			DDRSS_PHY_997_DATA
+			DDRSS_PHY_998_DATA
+			DDRSS_PHY_999_DATA
+			DDRSS_PHY_1000_DATA
+			DDRSS_PHY_1001_DATA
+			DDRSS_PHY_1002_DATA
+			DDRSS_PHY_1003_DATA
+			DDRSS_PHY_1004_DATA
+			DDRSS_PHY_1005_DATA
+			DDRSS_PHY_1006_DATA
+			DDRSS_PHY_1007_DATA
+			DDRSS_PHY_1008_DATA
+			DDRSS_PHY_1009_DATA
+			DDRSS_PHY_1010_DATA
+			DDRSS_PHY_1011_DATA
+			DDRSS_PHY_1012_DATA
+			DDRSS_PHY_1013_DATA
+			DDRSS_PHY_1014_DATA
+			DDRSS_PHY_1015_DATA
+			DDRSS_PHY_1016_DATA
+			DDRSS_PHY_1017_DATA
+			DDRSS_PHY_1018_DATA
+			DDRSS_PHY_1019_DATA
+			DDRSS_PHY_1020_DATA
+			DDRSS_PHY_1021_DATA
+			DDRSS_PHY_1022_DATA
+			DDRSS_PHY_1023_DATA
+			DDRSS_PHY_1024_DATA
+			DDRSS_PHY_1025_DATA
+			DDRSS_PHY_1026_DATA
+			DDRSS_PHY_1027_DATA
+			DDRSS_PHY_1028_DATA
+			DDRSS_PHY_1029_DATA
+			DDRSS_PHY_1030_DATA
+			DDRSS_PHY_1031_DATA
+			DDRSS_PHY_1032_DATA
+			DDRSS_PHY_1033_DATA
+			DDRSS_PHY_1034_DATA
+			DDRSS_PHY_1035_DATA
+			DDRSS_PHY_1036_DATA
+			DDRSS_PHY_1037_DATA
+			DDRSS_PHY_1038_DATA
+			DDRSS_PHY_1039_DATA
+			DDRSS_PHY_1040_DATA
+			DDRSS_PHY_1041_DATA
+			DDRSS_PHY_1042_DATA
+			DDRSS_PHY_1043_DATA
+			DDRSS_PHY_1044_DATA
+			DDRSS_PHY_1045_DATA
+			DDRSS_PHY_1046_DATA
+			DDRSS_PHY_1047_DATA
+			DDRSS_PHY_1048_DATA
+			DDRSS_PHY_1049_DATA
+			DDRSS_PHY_1050_DATA
+			DDRSS_PHY_1051_DATA
+			DDRSS_PHY_1052_DATA
+			DDRSS_PHY_1053_DATA
+			DDRSS_PHY_1054_DATA
+			DDRSS_PHY_1055_DATA
+			DDRSS_PHY_1056_DATA
+			DDRSS_PHY_1057_DATA
+			DDRSS_PHY_1058_DATA
+			DDRSS_PHY_1059_DATA
+			DDRSS_PHY_1060_DATA
+			DDRSS_PHY_1061_DATA
+			DDRSS_PHY_1062_DATA
+			DDRSS_PHY_1063_DATA
+			DDRSS_PHY_1064_DATA
+			DDRSS_PHY_1065_DATA
+			DDRSS_PHY_1066_DATA
+			DDRSS_PHY_1067_DATA
+			DDRSS_PHY_1068_DATA
+			DDRSS_PHY_1069_DATA
+			DDRSS_PHY_1070_DATA
+			DDRSS_PHY_1071_DATA
+			DDRSS_PHY_1072_DATA
+			DDRSS_PHY_1073_DATA
+			DDRSS_PHY_1074_DATA
+			DDRSS_PHY_1075_DATA
+			DDRSS_PHY_1076_DATA
+			DDRSS_PHY_1077_DATA
+			DDRSS_PHY_1078_DATA
+			DDRSS_PHY_1079_DATA
+			DDRSS_PHY_1080_DATA
+			DDRSS_PHY_1081_DATA
+			DDRSS_PHY_1082_DATA
+			DDRSS_PHY_1083_DATA
+			DDRSS_PHY_1084_DATA
+			DDRSS_PHY_1085_DATA
+			DDRSS_PHY_1086_DATA
+			DDRSS_PHY_1087_DATA
+			DDRSS_PHY_1088_DATA
+			DDRSS_PHY_1089_DATA
+			DDRSS_PHY_1090_DATA
+			DDRSS_PHY_1091_DATA
+			DDRSS_PHY_1092_DATA
+			DDRSS_PHY_1093_DATA
+			DDRSS_PHY_1094_DATA
+			DDRSS_PHY_1095_DATA
+			DDRSS_PHY_1096_DATA
+			DDRSS_PHY_1097_DATA
+			DDRSS_PHY_1098_DATA
+			DDRSS_PHY_1099_DATA
+			DDRSS_PHY_1100_DATA
+			DDRSS_PHY_1101_DATA
+			DDRSS_PHY_1102_DATA
+			DDRSS_PHY_1103_DATA
+			DDRSS_PHY_1104_DATA
+			DDRSS_PHY_1105_DATA
+			DDRSS_PHY_1106_DATA
+			DDRSS_PHY_1107_DATA
+			DDRSS_PHY_1108_DATA
+			DDRSS_PHY_1109_DATA
+			DDRSS_PHY_1110_DATA
+			DDRSS_PHY_1111_DATA
+			DDRSS_PHY_1112_DATA
+			DDRSS_PHY_1113_DATA
+			DDRSS_PHY_1114_DATA
+			DDRSS_PHY_1115_DATA
+			DDRSS_PHY_1116_DATA
+			DDRSS_PHY_1117_DATA
+			DDRSS_PHY_1118_DATA
+			DDRSS_PHY_1119_DATA
+			DDRSS_PHY_1120_DATA
+			DDRSS_PHY_1121_DATA
+			DDRSS_PHY_1122_DATA
+			DDRSS_PHY_1123_DATA
+			DDRSS_PHY_1124_DATA
+			DDRSS_PHY_1125_DATA
+			DDRSS_PHY_1126_DATA
+			DDRSS_PHY_1127_DATA
+			DDRSS_PHY_1128_DATA
+			DDRSS_PHY_1129_DATA
+			DDRSS_PHY_1130_DATA
+			DDRSS_PHY_1131_DATA
+			DDRSS_PHY_1132_DATA
+			DDRSS_PHY_1133_DATA
+			DDRSS_PHY_1134_DATA
+			DDRSS_PHY_1135_DATA
+			DDRSS_PHY_1136_DATA
+			DDRSS_PHY_1137_DATA
+			DDRSS_PHY_1138_DATA
+			DDRSS_PHY_1139_DATA
+			DDRSS_PHY_1140_DATA
+			DDRSS_PHY_1141_DATA
+			DDRSS_PHY_1142_DATA
+			DDRSS_PHY_1143_DATA
+			DDRSS_PHY_1144_DATA
+			DDRSS_PHY_1145_DATA
+			DDRSS_PHY_1146_DATA
+			DDRSS_PHY_1147_DATA
+			DDRSS_PHY_1148_DATA
+			DDRSS_PHY_1149_DATA
+			DDRSS_PHY_1150_DATA
+			DDRSS_PHY_1151_DATA
+			DDRSS_PHY_1152_DATA
+			DDRSS_PHY_1153_DATA
+			DDRSS_PHY_1154_DATA
+			DDRSS_PHY_1155_DATA
+			DDRSS_PHY_1156_DATA
+			DDRSS_PHY_1157_DATA
+			DDRSS_PHY_1158_DATA
+			DDRSS_PHY_1159_DATA
+			DDRSS_PHY_1160_DATA
+			DDRSS_PHY_1161_DATA
+			DDRSS_PHY_1162_DATA
+			DDRSS_PHY_1163_DATA
+			DDRSS_PHY_1164_DATA
+			DDRSS_PHY_1165_DATA
+			DDRSS_PHY_1166_DATA
+			DDRSS_PHY_1167_DATA
+			DDRSS_PHY_1168_DATA
+			DDRSS_PHY_1169_DATA
+			DDRSS_PHY_1170_DATA
+			DDRSS_PHY_1171_DATA
+			DDRSS_PHY_1172_DATA
+			DDRSS_PHY_1173_DATA
+			DDRSS_PHY_1174_DATA
+			DDRSS_PHY_1175_DATA
+			DDRSS_PHY_1176_DATA
+			DDRSS_PHY_1177_DATA
+			DDRSS_PHY_1178_DATA
+			DDRSS_PHY_1179_DATA
+			DDRSS_PHY_1180_DATA
+			DDRSS_PHY_1181_DATA
+			DDRSS_PHY_1182_DATA
+			DDRSS_PHY_1183_DATA
+			DDRSS_PHY_1184_DATA
+			DDRSS_PHY_1185_DATA
+			DDRSS_PHY_1186_DATA
+			DDRSS_PHY_1187_DATA
+			DDRSS_PHY_1188_DATA
+			DDRSS_PHY_1189_DATA
+			DDRSS_PHY_1190_DATA
+			DDRSS_PHY_1191_DATA
+			DDRSS_PHY_1192_DATA
+			DDRSS_PHY_1193_DATA
+			DDRSS_PHY_1194_DATA
+			DDRSS_PHY_1195_DATA
+			DDRSS_PHY_1196_DATA
+			DDRSS_PHY_1197_DATA
+			DDRSS_PHY_1198_DATA
+			DDRSS_PHY_1199_DATA
+			DDRSS_PHY_1200_DATA
+			DDRSS_PHY_1201_DATA
+			DDRSS_PHY_1202_DATA
+			DDRSS_PHY_1203_DATA
+			DDRSS_PHY_1204_DATA
+			DDRSS_PHY_1205_DATA
+			DDRSS_PHY_1206_DATA
+			DDRSS_PHY_1207_DATA
+			DDRSS_PHY_1208_DATA
+			DDRSS_PHY_1209_DATA
+			DDRSS_PHY_1210_DATA
+			DDRSS_PHY_1211_DATA
+			DDRSS_PHY_1212_DATA
+			DDRSS_PHY_1213_DATA
+			DDRSS_PHY_1214_DATA
+			DDRSS_PHY_1215_DATA
+			DDRSS_PHY_1216_DATA
+			DDRSS_PHY_1217_DATA
+			DDRSS_PHY_1218_DATA
+			DDRSS_PHY_1219_DATA
+			DDRSS_PHY_1220_DATA
+			DDRSS_PHY_1221_DATA
+			DDRSS_PHY_1222_DATA
+			DDRSS_PHY_1223_DATA
+			DDRSS_PHY_1224_DATA
+			DDRSS_PHY_1225_DATA
+			DDRSS_PHY_1226_DATA
+			DDRSS_PHY_1227_DATA
+			DDRSS_PHY_1228_DATA
+			DDRSS_PHY_1229_DATA
+			DDRSS_PHY_1230_DATA
+			DDRSS_PHY_1231_DATA
+			DDRSS_PHY_1232_DATA
+			DDRSS_PHY_1233_DATA
+			DDRSS_PHY_1234_DATA
+			DDRSS_PHY_1235_DATA
+			DDRSS_PHY_1236_DATA
+			DDRSS_PHY_1237_DATA
+			DDRSS_PHY_1238_DATA
+			DDRSS_PHY_1239_DATA
+			DDRSS_PHY_1240_DATA
+			DDRSS_PHY_1241_DATA
+			DDRSS_PHY_1242_DATA
+			DDRSS_PHY_1243_DATA
+			DDRSS_PHY_1244_DATA
+			DDRSS_PHY_1245_DATA
+			DDRSS_PHY_1246_DATA
+			DDRSS_PHY_1247_DATA
+			DDRSS_PHY_1248_DATA
+			DDRSS_PHY_1249_DATA
+			DDRSS_PHY_1250_DATA
+			DDRSS_PHY_1251_DATA
+			DDRSS_PHY_1252_DATA
+			DDRSS_PHY_1253_DATA
+			DDRSS_PHY_1254_DATA
+			DDRSS_PHY_1255_DATA
+			DDRSS_PHY_1256_DATA
+			DDRSS_PHY_1257_DATA
+			DDRSS_PHY_1258_DATA
+			DDRSS_PHY_1259_DATA
+			DDRSS_PHY_1260_DATA
+			DDRSS_PHY_1261_DATA
+			DDRSS_PHY_1262_DATA
+			DDRSS_PHY_1263_DATA
+			DDRSS_PHY_1264_DATA
+			DDRSS_PHY_1265_DATA
+			DDRSS_PHY_1266_DATA
+			DDRSS_PHY_1267_DATA
+			DDRSS_PHY_1268_DATA
+			DDRSS_PHY_1269_DATA
+			DDRSS_PHY_1270_DATA
+			DDRSS_PHY_1271_DATA
+			DDRSS_PHY_1272_DATA
+			DDRSS_PHY_1273_DATA
+			DDRSS_PHY_1274_DATA
+			DDRSS_PHY_1275_DATA
+			DDRSS_PHY_1276_DATA
+			DDRSS_PHY_1277_DATA
+			DDRSS_PHY_1278_DATA
+			DDRSS_PHY_1279_DATA
+			DDRSS_PHY_1280_DATA
+			DDRSS_PHY_1281_DATA
+			DDRSS_PHY_1282_DATA
+			DDRSS_PHY_1283_DATA
+			DDRSS_PHY_1284_DATA
+			DDRSS_PHY_1285_DATA
+			DDRSS_PHY_1286_DATA
+			DDRSS_PHY_1287_DATA
+			DDRSS_PHY_1288_DATA
+			DDRSS_PHY_1289_DATA
+			DDRSS_PHY_1290_DATA
+			DDRSS_PHY_1291_DATA
+			DDRSS_PHY_1292_DATA
+			DDRSS_PHY_1293_DATA
+			DDRSS_PHY_1294_DATA
+			DDRSS_PHY_1295_DATA
+			DDRSS_PHY_1296_DATA
+			DDRSS_PHY_1297_DATA
+			DDRSS_PHY_1298_DATA
+			DDRSS_PHY_1299_DATA
+			DDRSS_PHY_1300_DATA
+			DDRSS_PHY_1301_DATA
+			DDRSS_PHY_1302_DATA
+			DDRSS_PHY_1303_DATA
+			DDRSS_PHY_1304_DATA
+			DDRSS_PHY_1305_DATA
+			DDRSS_PHY_1306_DATA
+			DDRSS_PHY_1307_DATA
+			DDRSS_PHY_1308_DATA
+			DDRSS_PHY_1309_DATA
+			DDRSS_PHY_1310_DATA
+			DDRSS_PHY_1311_DATA
+			DDRSS_PHY_1312_DATA
+			DDRSS_PHY_1313_DATA
+			DDRSS_PHY_1314_DATA
+			DDRSS_PHY_1315_DATA
+			DDRSS_PHY_1316_DATA
+			DDRSS_PHY_1317_DATA
+			DDRSS_PHY_1318_DATA
+			DDRSS_PHY_1319_DATA
+			DDRSS_PHY_1320_DATA
+			DDRSS_PHY_1321_DATA
+			DDRSS_PHY_1322_DATA
+			DDRSS_PHY_1323_DATA
+			DDRSS_PHY_1324_DATA
+			DDRSS_PHY_1325_DATA
+			DDRSS_PHY_1326_DATA
+			DDRSS_PHY_1327_DATA
+			DDRSS_PHY_1328_DATA
+			DDRSS_PHY_1329_DATA
+			DDRSS_PHY_1330_DATA
+			DDRSS_PHY_1331_DATA
+			DDRSS_PHY_1332_DATA
+			DDRSS_PHY_1333_DATA
+			DDRSS_PHY_1334_DATA
+			DDRSS_PHY_1335_DATA
+			DDRSS_PHY_1336_DATA
+			DDRSS_PHY_1337_DATA
+			DDRSS_PHY_1338_DATA
+			DDRSS_PHY_1339_DATA
+			DDRSS_PHY_1340_DATA
+			DDRSS_PHY_1341_DATA
+			DDRSS_PHY_1342_DATA
+			DDRSS_PHY_1343_DATA
+			DDRSS_PHY_1344_DATA
+			DDRSS_PHY_1345_DATA
+			DDRSS_PHY_1346_DATA
+			DDRSS_PHY_1347_DATA
+			DDRSS_PHY_1348_DATA
+			DDRSS_PHY_1349_DATA
+			DDRSS_PHY_1350_DATA
+			DDRSS_PHY_1351_DATA
+			DDRSS_PHY_1352_DATA
+			DDRSS_PHY_1353_DATA
+			DDRSS_PHY_1354_DATA
+			DDRSS_PHY_1355_DATA
+			DDRSS_PHY_1356_DATA
+			DDRSS_PHY_1357_DATA
+			DDRSS_PHY_1358_DATA
+			DDRSS_PHY_1359_DATA
+			DDRSS_PHY_1360_DATA
+			DDRSS_PHY_1361_DATA
+			DDRSS_PHY_1362_DATA
+			DDRSS_PHY_1363_DATA
+			DDRSS_PHY_1364_DATA
+			DDRSS_PHY_1365_DATA
+			DDRSS_PHY_1366_DATA
+			DDRSS_PHY_1367_DATA
+			DDRSS_PHY_1368_DATA
+			DDRSS_PHY_1369_DATA
+			DDRSS_PHY_1370_DATA
+			DDRSS_PHY_1371_DATA
+			DDRSS_PHY_1372_DATA
+			DDRSS_PHY_1373_DATA
+			DDRSS_PHY_1374_DATA
+			DDRSS_PHY_1375_DATA
+			DDRSS_PHY_1376_DATA
+			DDRSS_PHY_1377_DATA
+			DDRSS_PHY_1378_DATA
+			DDRSS_PHY_1379_DATA
+			DDRSS_PHY_1380_DATA
+			DDRSS_PHY_1381_DATA
+			DDRSS_PHY_1382_DATA
+			DDRSS_PHY_1383_DATA
+			DDRSS_PHY_1384_DATA
+			DDRSS_PHY_1385_DATA
+			DDRSS_PHY_1386_DATA
+			DDRSS_PHY_1387_DATA
+			DDRSS_PHY_1388_DATA
+			DDRSS_PHY_1389_DATA
+			DDRSS_PHY_1390_DATA
+			DDRSS_PHY_1391_DATA
+			DDRSS_PHY_1392_DATA
+			DDRSS_PHY_1393_DATA
+			DDRSS_PHY_1394_DATA
+			DDRSS_PHY_1395_DATA
+			DDRSS_PHY_1396_DATA
+			DDRSS_PHY_1397_DATA
+			DDRSS_PHY_1398_DATA
+			DDRSS_PHY_1399_DATA
+			DDRSS_PHY_1400_DATA
+			DDRSS_PHY_1401_DATA
+			DDRSS_PHY_1402_DATA
+			DDRSS_PHY_1403_DATA
+			DDRSS_PHY_1404_DATA
+			DDRSS_PHY_1405_DATA
+		>;
+	};
+};
diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
new file mode 100644
index 0000000000..9a008df750
--- /dev/null
+++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
@@ -0,0 +1,2187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated by the AM64x_DDR4_RegConfig_Tool, Revision: 0.6.0
+ * This file was generated on Oct 26 2020
+ * DDR4 Frequency = 800MHz (1600MTs)
+ * Density: 16Gb
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000A00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x000890B8
+#define DDRSS_CTL_8_DATA 0x00000000
+#define DDRSS_CTL_9_DATA 0x00000000
+#define DDRSS_CTL_10_DATA 0x00000000
+#define DDRSS_CTL_11_DATA 0x000890B8
+#define DDRSS_CTL_12_DATA 0x00000000
+#define DDRSS_CTL_13_DATA 0x00000000
+#define DDRSS_CTL_14_DATA 0x00000000
+#define DDRSS_CTL_15_DATA 0x000890B8
+#define DDRSS_CTL_16_DATA 0x00000000
+#define DDRSS_CTL_17_DATA 0x00000000
+#define DDRSS_CTL_18_DATA 0x00000000
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01000100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x00027100
+#define DDRSS_CTL_24_DATA 0x00061A80
+#define DDRSS_CTL_25_DATA 0x02550255
+#define DDRSS_CTL_26_DATA 0x00000255
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00000000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x00000000
+#define DDRSS_CTL_35_DATA 0x00000000
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x04000918
+#define DDRSS_CTL_39_DATA 0x1C1C1C1C
+#define DDRSS_CTL_40_DATA 0x04000918
+#define DDRSS_CTL_41_DATA 0x1C1C1C1C
+#define DDRSS_CTL_42_DATA 0x04000918
+#define DDRSS_CTL_43_DATA 0x1C1C1C1C
+#define DDRSS_CTL_44_DATA 0x05050404
+#define DDRSS_CTL_45_DATA 0x00002706
+#define DDRSS_CTL_46_DATA 0x0602001D
+#define DDRSS_CTL_47_DATA 0x05001D0B
+#define DDRSS_CTL_48_DATA 0x00270605
+#define DDRSS_CTL_49_DATA 0x0602001D
+#define DDRSS_CTL_50_DATA 0x05001D0B
+#define DDRSS_CTL_51_DATA 0x00270605
+#define DDRSS_CTL_52_DATA 0x0602001D
+#define DDRSS_CTL_53_DATA 0x07001D0B
+#define DDRSS_CTL_54_DATA 0x00180807
+#define DDRSS_CTL_55_DATA 0x0400DB60
+#define DDRSS_CTL_56_DATA 0x07070009
+#define DDRSS_CTL_57_DATA 0x00001808
+#define DDRSS_CTL_58_DATA 0x0400DB60
+#define DDRSS_CTL_59_DATA 0x07070009
+#define DDRSS_CTL_60_DATA 0x00001808
+#define DDRSS_CTL_61_DATA 0x0400DB60
+#define DDRSS_CTL_62_DATA 0x03000009
+#define DDRSS_CTL_63_DATA 0x0D0C0002
+#define DDRSS_CTL_64_DATA 0x0D0C0D0C
+#define DDRSS_CTL_65_DATA 0x01010000
+#define DDRSS_CTL_66_DATA 0x03191919
+#define DDRSS_CTL_67_DATA 0x0B0B0B0B
+#define DDRSS_CTL_68_DATA 0x00000B0B
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x01180803
+#define DDRSS_CTL_73_DATA 0x00001860
+#define DDRSS_CTL_74_DATA 0x00000118
+#define DDRSS_CTL_75_DATA 0x00001860
+#define DDRSS_CTL_76_DATA 0x00000118
+#define DDRSS_CTL_77_DATA 0x00001860
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x00000000
+#define DDRSS_CTL_80_DATA 0x00000000
+#define DDRSS_CTL_81_DATA 0x00000000
+#define DDRSS_CTL_82_DATA 0x00000000
+#define DDRSS_CTL_83_DATA 0x00000000
+#define DDRSS_CTL_84_DATA 0x00000000
+#define DDRSS_CTL_85_DATA 0x00000000
+#define DDRSS_CTL_86_DATA 0x00000000
+#define DDRSS_CTL_87_DATA 0x00090009
+#define DDRSS_CTL_88_DATA 0x00000009
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x00000000
+#define DDRSS_CTL_93_DATA 0x00000000
+#define DDRSS_CTL_94_DATA 0x00010001
+#define DDRSS_CTL_95_DATA 0x00025501
+#define DDRSS_CTL_96_DATA 0x02550120
+#define DDRSS_CTL_97_DATA 0x02550120
+#define DDRSS_CTL_98_DATA 0x01200120
+#define DDRSS_CTL_99_DATA 0x01200120
+#define DDRSS_CTL_100_DATA 0x00000000
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00000000
+#define DDRSS_CTL_103_DATA 0x00000000
+#define DDRSS_CTL_104_DATA 0x00000000
+#define DDRSS_CTL_105_DATA 0x00000000
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00061800
+#define DDRSS_CTL_120_DATA 0x00061800
+#define DDRSS_CTL_121_DATA 0x00061800
+#define DDRSS_CTL_122_DATA 0x00061800
+#define DDRSS_CTL_123_DATA 0x00061800
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000AAA0
+#define DDRSS_CTL_126_DATA 0x00061800
+#define DDRSS_CTL_127_DATA 0x00061800
+#define DDRSS_CTL_128_DATA 0x00061800
+#define DDRSS_CTL_129_DATA 0x00061800
+#define DDRSS_CTL_130_DATA 0x00061800
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x0000AAA0
+#define DDRSS_CTL_133_DATA 0x00061800
+#define DDRSS_CTL_134_DATA 0x00061800
+#define DDRSS_CTL_135_DATA 0x00061800
+#define DDRSS_CTL_136_DATA 0x00061800
+#define DDRSS_CTL_137_DATA 0x00061800
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x0000AAA0
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x080C0000
+#define DDRSS_CTL_157_DATA 0x080C080C
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x07010A09
+#define DDRSS_CTL_160_DATA 0x000E0A09
+#define DDRSS_CTL_161_DATA 0x010A0900
+#define DDRSS_CTL_162_DATA 0x0E0A0907
+#define DDRSS_CTL_163_DATA 0x0A090000
+#define DDRSS_CTL_164_DATA 0x0A090701
+#define DDRSS_CTL_165_DATA 0x0000000E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000000
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x00000000
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00041400
+#define DDRSS_CTL_205_DATA 0x00000301
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000414
+#define DDRSS_CTL_208_DATA 0x00000301
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000414
+#define DDRSS_CTL_211_DATA 0x00000301
+#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_213_DATA 0x00000414
+#define DDRSS_CTL_214_DATA 0x00000301
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000414
+#define DDRSS_CTL_217_DATA 0x00000301
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000414
+#define DDRSS_CTL_220_DATA 0x00000301
+#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000000
+#define DDRSS_CTL_228_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0x00000000
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000401
+#define DDRSS_CTL_237_DATA 0x00000401
+#define DDRSS_CTL_238_DATA 0x00000401
+#define DDRSS_CTL_239_DATA 0x00000401
+#define DDRSS_CTL_240_DATA 0x00000401
+#define DDRSS_CTL_241_DATA 0x00000401
+#define DDRSS_CTL_242_DATA 0x00000493
+#define DDRSS_CTL_243_DATA 0x00000493
+#define DDRSS_CTL_244_DATA 0x00000493
+#define DDRSS_CTL_245_DATA 0x00000493
+#define DDRSS_CTL_246_DATA 0x00000493
+#define DDRSS_CTL_247_DATA 0x00000493
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x00000000
+#define DDRSS_CTL_258_DATA 0x00000000
+#define DDRSS_CTL_259_DATA 0x00000000
+#define DDRSS_CTL_260_DATA 0x00000000
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x00000000
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x00000000
+#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_268_DATA 0x00000000
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_271_DATA 0x00000000
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000000
+#define DDRSS_CTL_275_DATA 0x00000000
+#define DDRSS_CTL_276_DATA 0x00000000
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00040000
+#define DDRSS_CTL_306_DATA 0x00800200
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x02000400
+#define DDRSS_CTL_309_DATA 0x00000080
+#define DDRSS_CTL_310_DATA 0x00040000
+#define DDRSS_CTL_311_DATA 0x00800200
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x00000000
+#define DDRSS_CTL_314_DATA 0x00000000
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_322_DATA 0x0A000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x00000000
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_331_DATA 0x01000000
+#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_333_DATA 0x00010000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x0C000000
+#define DDRSS_CTL_371_DATA 0x060C0606
+#define DDRSS_CTL_372_DATA 0x06060C06
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x02000000
+#define DDRSS_CTL_375_DATA 0x03020101
+#define DDRSS_CTL_376_DATA 0x00000303
+#define DDRSS_CTL_377_DATA 0x02020200
+#define DDRSS_CTL_378_DATA 0x02020202
+#define DDRSS_CTL_379_DATA 0x02020202
+#define DDRSS_CTL_380_DATA 0x02020202
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x04000100
+#define DDRSS_CTL_384_DATA 0x1E000004
+#define DDRSS_CTL_385_DATA 0x000030C0
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x0000DB60
+#define DDRSS_CTL_391_DATA 0x0001E780
+#define DDRSS_CTL_392_DATA 0x0A0B0302
+#define DDRSS_CTL_393_DATA 0x001E090A
+#define DDRSS_CTL_394_DATA 0x000030C0
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x0000DB60
+#define DDRSS_CTL_400_DATA 0x0001E780
+#define DDRSS_CTL_401_DATA 0x0A0B0302
+#define DDRSS_CTL_402_DATA 0x001E090A
+#define DDRSS_CTL_403_DATA 0x000030C0
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x0000DB60
+#define DDRSS_CTL_409_DATA 0x0001E780
+#define DDRSS_CTL_410_DATA 0x0A0B0302
+#define DDRSS_CTL_411_DATA 0x0000090A
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x00000000
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000A00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000000
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x00000000
+#define DDRSS_PI_15_DATA 0x00010001
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x280D0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x00060602
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x00000055
+#define DDRSS_PI_36_DATA 0x000000AA
+#define DDRSS_PI_37_DATA 0x000000AD
+#define DDRSS_PI_38_DATA 0x00000052
+#define DDRSS_PI_39_DATA 0x0000006A
+#define DDRSS_PI_40_DATA 0x00000095
+#define DDRSS_PI_41_DATA 0x00000095
+#define DDRSS_PI_42_DATA 0x000000AD
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x00000000
+#define DDRSS_PI_55_DATA 0x00010000
+#define DDRSS_PI_56_DATA 0x00000000
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x00001400
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x01000000
+#define DDRSS_PI_63_DATA 0x00000404
+#define DDRSS_PI_64_DATA 0x00000001
+#define DDRSS_PI_65_DATA 0x0001010E
+#define DDRSS_PI_66_DATA 0x02040100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000005
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x04000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000300
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010100
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00027100
+#define DDRSS_PI_137_DATA 0x00061A80
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00007800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00141414
+#define DDRSS_PI_167_DATA 0x00000038
+#define DDRSS_PI_168_DATA 0x00000038
+#define DDRSS_PI_169_DATA 0x00040038
+#define DDRSS_PI_170_DATA 0x04000400
+#define DDRSS_PI_171_DATA 0xC8040009
+#define DDRSS_PI_172_DATA 0x04000918
+#define DDRSS_PI_173_DATA 0x000918C8
+#define DDRSS_PI_174_DATA 0x0018C804
+#define DDRSS_PI_175_DATA 0x00000118
+#define DDRSS_PI_176_DATA 0x00001860
+#define DDRSS_PI_177_DATA 0x00000118
+#define DDRSS_PI_178_DATA 0x00001860
+#define DDRSS_PI_179_DATA 0x00000118
+#define DDRSS_PI_180_DATA 0x04001860
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001901
+#define DDRSS_PI_183_DATA 0x00190019
+#define DDRSS_PI_184_DATA 0x010C010C
+#define DDRSS_PI_185_DATA 0x0000010C
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x03000000
+#define DDRSS_PI_188_DATA 0x01010303
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x00181818
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x0B000000
+#define DDRSS_PI_194_DATA 0x0A0A0B0B
+#define DDRSS_PI_195_DATA 0x0303030A
+#define DDRSS_PI_196_DATA 0x00000000
+#define DDRSS_PI_197_DATA 0x00000000
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x00000000
+#define DDRSS_PI_200_DATA 0x00000000
+#define DDRSS_PI_201_DATA 0x00000000
+#define DDRSS_PI_202_DATA 0x00000000
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x00000000
+#define DDRSS_PI_206_DATA 0x00000000
+#define DDRSS_PI_207_DATA 0x00000000
+#define DDRSS_PI_208_DATA 0x00000000
+#define DDRSS_PI_209_DATA 0x0D090000
+#define DDRSS_PI_210_DATA 0x0D09000D
+#define DDRSS_PI_211_DATA 0x0D09000D
+#define DDRSS_PI_212_DATA 0x0000000D
+#define DDRSS_PI_213_DATA 0x00000000
+#define DDRSS_PI_214_DATA 0x00000000
+#define DDRSS_PI_215_DATA 0x00000000
+#define DDRSS_PI_216_DATA 0x00000000
+#define DDRSS_PI_217_DATA 0x16000000
+#define DDRSS_PI_218_DATA 0x001600C8
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x010100C8
+#define DDRSS_PI_221_DATA 0x00001B01
+#define DDRSS_PI_222_DATA 0x1F0F0051
+#define DDRSS_PI_223_DATA 0x03000001
+#define DDRSS_PI_224_DATA 0x001B0A0B
+#define DDRSS_PI_225_DATA 0x1F0F0051
+#define DDRSS_PI_226_DATA 0x03000001
+#define DDRSS_PI_227_DATA 0x001B0A0B
+#define DDRSS_PI_228_DATA 0x1F0F0051
+#define DDRSS_PI_229_DATA 0x03000001
+#define DDRSS_PI_230_DATA 0x00000A0B
+#define DDRSS_PI_231_DATA 0x0C0B0700
+#define DDRSS_PI_232_DATA 0x000D0605
+#define DDRSS_PI_233_DATA 0x0000C570
+#define DDRSS_PI_234_DATA 0x0000001D
+#define DDRSS_PI_235_DATA 0x180A0800
+#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_237_DATA 0x0D06050C
+#define DDRSS_PI_238_DATA 0x0000C570
+#define DDRSS_PI_239_DATA 0x0000001D
+#define DDRSS_PI_240_DATA 0x180A0800
+#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_242_DATA 0x0D06050C
+#define DDRSS_PI_243_DATA 0x0000C570
+#define DDRSS_PI_244_DATA 0x0000001D
+#define DDRSS_PI_245_DATA 0x180A0800
+#define DDRSS_PI_246_DATA 0x00001C1C
+#define DDRSS_PI_247_DATA 0x000030C0
+#define DDRSS_PI_248_DATA 0x0001E780
+#define DDRSS_PI_249_DATA 0x000030C0
+#define DDRSS_PI_250_DATA 0x0001E780
+#define DDRSS_PI_251_DATA 0x000030C0
+#define DDRSS_PI_252_DATA 0x0001E780
+#define DDRSS_PI_253_DATA 0x02550255
+#define DDRSS_PI_254_DATA 0x03030255
+#define DDRSS_PI_255_DATA 0x00025503
+#define DDRSS_PI_256_DATA 0x02550255
+#define DDRSS_PI_257_DATA 0x0C080C08
+#define DDRSS_PI_258_DATA 0x00000C08
+#define DDRSS_PI_259_DATA 0x000890B8
+#define DDRSS_PI_260_DATA 0x00000000
+#define DDRSS_PI_261_DATA 0x00000000
+#define DDRSS_PI_262_DATA 0x00000000
+#define DDRSS_PI_263_DATA 0x00000120
+#define DDRSS_PI_264_DATA 0x000890B8
+#define DDRSS_PI_265_DATA 0x00000000
+#define DDRSS_PI_266_DATA 0x00000000
+#define DDRSS_PI_267_DATA 0x00000000
+#define DDRSS_PI_268_DATA 0x00000120
+#define DDRSS_PI_269_DATA 0x000890B8
+#define DDRSS_PI_270_DATA 0x00000000
+#define DDRSS_PI_271_DATA 0x00000000
+#define DDRSS_PI_272_DATA 0x00000000
+#define DDRSS_PI_273_DATA 0x02000120
+#define DDRSS_PI_274_DATA 0x00000080
+#define DDRSS_PI_275_DATA 0x00020000
+#define DDRSS_PI_276_DATA 0x00000080
+#define DDRSS_PI_277_DATA 0x00020000
+#define DDRSS_PI_278_DATA 0x00000080
+#define DDRSS_PI_279_DATA 0x00000000
+#define DDRSS_PI_280_DATA 0x00000000
+#define DDRSS_PI_281_DATA 0x00040404
+#define DDRSS_PI_282_DATA 0x00000000
+#define DDRSS_PI_283_DATA 0x02010102
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000202
+#define DDRSS_PI_286_DATA 0x00000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x00000000
+#define DDRSS_PI_289_DATA 0x00000000
+#define DDRSS_PI_290_DATA 0x00000000
+#define DDRSS_PI_291_DATA 0x0D100F00
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000414
+#define DDRSS_PI_298_DATA 0x00000301
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000000
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000401
+#define DDRSS_PI_303_DATA 0x00000493
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000414
+#define DDRSS_PI_306_DATA 0x00000301
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x00000000
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000401
+#define DDRSS_PI_311_DATA 0x00000493
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x00000414
+#define DDRSS_PI_314_DATA 0x00000301
+#define DDRSS_PI_315_DATA 0x00000000
+#define DDRSS_PI_316_DATA 0x00000000
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000401
+#define DDRSS_PI_319_DATA 0x00000493
+#define DDRSS_PI_320_DATA 0x00000000
+#define DDRSS_PI_321_DATA 0x00000414
+#define DDRSS_PI_322_DATA 0x00000301
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000000
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000401
+#define DDRSS_PI_327_DATA 0x00000493
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000414
+#define DDRSS_PI_330_DATA 0x00000301
+#define DDRSS_PI_331_DATA 0x00000000
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000401
+#define DDRSS_PI_335_DATA 0x00000493
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x00000414
+#define DDRSS_PI_338_DATA 0x00000301
+#define DDRSS_PI_339_DATA 0x00000000
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000401
+#define DDRSS_PI_343_DATA 0x00000493
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PHY_0_DATA 0x04C00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00000200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x00000000
+#define DDRSS_PHY_6_DATA 0x00000000
+#define DDRSS_PHY_7_DATA 0x00000000
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x010101FF
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00004
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660201
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00070820
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CCB001
+#define DDRSS_PHY_75_DATA 0x2000CCB0
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x10100303
+#define DDRSS_PHY_80_DATA 0x10101010
+#define DDRSS_PHY_81_DATA 0x10101010
+#define DDRSS_PHY_82_DATA 0x00021010
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51515041
+#define DDRSS_PHY_89_DATA 0x31804000
+#define DDRSS_PHY_90_DATA 0x04BF0340
+#define DDRSS_PHY_91_DATA 0x01008080
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C14
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x02800280
+#define DDRSS_PHY_106_DATA 0x02800280
+#define DDRSS_PHY_107_DATA 0x02800280
+#define DDRSS_PHY_108_DATA 0x02800280
+#define DDRSS_PHY_109_DATA 0x00000280
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01000080
+#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x00000000
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04C00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00000200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x00000000
+#define DDRSS_PHY_262_DATA 0x00000000
+#define DDRSS_PHY_263_DATA 0x00000000
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x010101FF
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00004
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660201
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00070820
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CCB001
+#define DDRSS_PHY_331_DATA 0x2000CCB0
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x10100303
+#define DDRSS_PHY_336_DATA 0x10101010
+#define DDRSS_PHY_337_DATA 0x10101010
+#define DDRSS_PHY_338_DATA 0x00021010
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51515041
+#define DDRSS_PHY_345_DATA 0x31804000
+#define DDRSS_PHY_346_DATA 0x04BF0340
+#define DDRSS_PHY_347_DATA 0x01008080
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C14
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x02800280
+#define DDRSS_PHY_362_DATA 0x02800280
+#define DDRSS_PHY_363_DATA 0x02800280
+#define DDRSS_PHY_364_DATA 0x02800280
+#define DDRSS_PHY_365_DATA 0x00000280
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01000080
+#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x00000000
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000100
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000000
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x00000000
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x00000000
+#define DDRSS_PHY_527_DATA 0x00000000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x00000000
+#define DDRSS_PHY_533_DATA 0x00000000
+#define DDRSS_PHY_534_DATA 0x00000000
+#define DDRSS_PHY_535_DATA 0x00000000
+#define DDRSS_PHY_536_DATA 0x00000000
+#define DDRSS_PHY_537_DATA 0x00000000
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x103F0000
+#define DDRSS_PHY_542_DATA 0x000F0100
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000003E
+#define DDRSS_PHY_553_DATA 0x00000000
+#define DDRSS_PHY_554_DATA 0x00000000
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000100
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000000
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x00000000
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x00000000
+#define DDRSS_PHY_783_DATA 0x00000000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x00000000
+#define DDRSS_PHY_789_DATA 0x00000000
+#define DDRSS_PHY_790_DATA 0x00000000
+#define DDRSS_PHY_791_DATA 0x00000000
+#define DDRSS_PHY_792_DATA 0x00000000
+#define DDRSS_PHY_793_DATA 0x00000000
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x16A4A0E6
+#define DDRSS_PHY_797_DATA 0x103F0000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000003E
+#define DDRSS_PHY_809_DATA 0x00000000
+#define DDRSS_PHY_810_DATA 0x00000000
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000100
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000000
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00000000
+#define DDRSS_PHY_1036_DATA 0x00000000
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x00000000
+#define DDRSS_PHY_1039_DATA 0x00000000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x00000000
+#define DDRSS_PHY_1046_DATA 0x00000000
+#define DDRSS_PHY_1047_DATA 0x00000000
+#define DDRSS_PHY_1048_DATA 0x00000000
+#define DDRSS_PHY_1049_DATA 0x00000000
+#define DDRSS_PHY_1050_DATA 0x00000000
+#define DDRSS_PHY_1051_DATA 0x00000000
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10030000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000003E
+#define DDRSS_PHY_1065_DATA 0x00000000
+#define DDRSS_PHY_1066_DATA 0x00000000
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000100
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x01002000
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x00010100
+#define DDRSS_PHY_1297_DATA 0x00000001
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00040000
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07070001
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000046
+#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00000098
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000100
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020400
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03900390
+#define DDRSS_PHY_1382_DATA 0x03900390
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x31823FC7
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000D3F
+#define DDRSS_PHY_1390_DATA 0x30000D3F
+#define DDRSS_PHY_1391_DATA 0x300D3F11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x000D3FCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x300D3F11
+#define DDRSS_PHY_1396_DATA 0x01990000
+#define DDRSS_PHY_1397_DATA 0x300C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x300C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x300D3F11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x300D3F11
+#define DDRSS_PHY_1404_DATA 0x01990000
+#define DDRSS_PHY_1405_DATA 0x20040001
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
new file mode 100644
index 0000000000..a65011b396
--- /dev/null
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -0,0 +1,567 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+	oc_sram: sram@70000000 {
+		compatible = "mmio-sram";
+		reg = <0x00 0x70000000 0x00 0x200000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x00 0x70000000 0x200000>;
+
+		atf-sram@0 {
+			reg = <0x0 0x1a000>;
+		};
+	};
+
+	gic500: interrupt-controller@1800000 {
+		compatible = "arm,gic-v3";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */
+		      <0x00 0x01840000 0x00 0xC0000>;	/* GICR */
+		/*
+		 * vcpumntirq:
+		 * virtual CPU interface maintenance interrupt
+		 */
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+		gic_its: msi-controller@1820000 {
+			compatible = "arm,gic-v3-its";
+			reg = <0x00 0x01820000 0x00 0x10000>;
+			socionext,synquacer-pre-its = <0x1000000 0x400000>;
+			msi-controller;
+			#msi-cells = <1>;
+		};
+	};
+
+	dmss: dmss {
+		compatible = "simple-mfd";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-ranges;
+		ranges;
+
+		ti,sci-dev-id = <25>;
+
+		secure_proxy_main: mailbox@4d000000 {
+			compatible = "ti,am654-secure-proxy";
+			#mbox-cells = <1>;
+			reg-names = "target_data", "rt", "scfg";
+			reg = <0x00 0x4d000000 0x00 0x80000>,
+			      <0x00 0x4a600000 0x00 0x80000>,
+			      <0x00 0x4a400000 0x00 0x80000>;
+			interrupt-names = "rx_012";
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		inta_main_dmss: interrupt-controller@48000000 {
+			compatible = "ti,sci-inta";
+			reg = <0x00 0x48000000 0x00 0x100000>;
+			#interrupt-cells = <0>;
+			interrupt-controller;
+			interrupt-parent = <&gic500>;
+			msi-controller;
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <28>;
+			ti,interrupt-ranges = <4 68 36>;
+			ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+		};
+
+		main_bcdma: dma-controller@485c0100 {
+			compatible = "ti,am64-dmss-bcdma";
+			reg = <0x00 0x485c0100 0x00 0x100>,
+			      <0x00 0x4c000000 0x00 0x20000>,
+			      <0x00 0x4a820000 0x00 0x20000>,
+			      <0x00 0x4aa40000 0x00 0x20000>,
+			      <0x00 0x4bc00000 0x00 0x100000>;
+			reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+			msi-parent = <&inta_main_dmss>;
+			#dma-cells = <3>;
+
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <26>;
+			ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+			ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+			ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+		};
+
+		main_pktdma: dma-controller@485c0000 {
+			compatible = "ti,am64-dmss-pktdma";
+			reg = <0x00 0x485c0000 0x00 0x100>,
+			      <0x00 0x4a800000 0x00 0x20000>,
+			      <0x00 0x4aa00000 0x00 0x40000>,
+			      <0x00 0x4b800000 0x00 0x400000>;
+			reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+			msi-parent = <&inta_main_dmss>;
+			#dma-cells = <2>;
+
+			ti,sci = <&dmsc>;
+			ti,sci-dev-id = <30>;
+			ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+						<0x24>, /* CPSW_TX_CHAN */
+						<0x25>, /* SAUL_TX_0_CHAN */
+						<0x26>, /* SAUL_TX_1_CHAN */
+						<0x27>, /* ICSSG_0_TX_CHAN */
+						<0x28>; /* ICSSG_1_TX_CHAN */
+			ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+						<0x11>, /* RING_CPSW_TX_CHAN */
+						<0x12>, /* RING_SAUL_TX_0_CHAN */
+						<0x13>, /* RING_SAUL_TX_1_CHAN */
+						<0x14>, /* RING_ICSSG_0_TX_CHAN */
+						<0x15>; /* RING_ICSSG_1_TX_CHAN */
+			ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+						<0x2b>, /* CPSW_RX_CHAN */
+						<0x2d>, /* SAUL_RX_0_CHAN */
+						<0x2f>, /* SAUL_RX_1_CHAN */
+						<0x31>, /* SAUL_RX_2_CHAN */
+						<0x33>, /* SAUL_RX_3_CHAN */
+						<0x35>, /* ICSSG_0_RX_CHAN */
+						<0x37>; /* ICSSG_1_RX_CHAN */
+			ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+						<0x2c>, /* FLOW_CPSW_RX_CHAN */
+						<0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+						<0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
+						<0x36>, /* FLOW_ICSSG_0_RX_CHAN */
+						<0x38>; /* FLOW_ICSSG_1_RX_CHAN */
+		};
+	};
+
+	dmsc: dmsc@44043000 {
+		compatible = "ti,k2g-sci";
+		ti,host-id = <12>;
+		mbox-names = "rx", "tx";
+		mboxes= <&secure_proxy_main 12>,
+			<&secure_proxy_main 13>;
+		reg-names = "debug_messages";
+		reg = <0x00 0x44043000 0x00 0xfe0>;
+
+		k3_pds: power-controller {
+			compatible = "ti,sci-pm-domain";
+			#power-domain-cells = <2>;
+		};
+
+		k3_clks: clocks {
+			compatible = "ti,k2g-sci-clk";
+			#clock-cells = <2>;
+		};
+
+		k3_reset: reset-controller {
+			compatible = "ti,sci-reset";
+			#reset-cells = <2>;
+		};
+	};
+
+	main_pmx0: pinctrl@f4000 {
+		compatible = "pinctrl-single";
+		reg = <0x00 0xf4000 0x00 0x2d0>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xffffffff>;
+	};
+
+	main_conf: syscon@43000000 {
+		compatible = "syscon", "simple-mfd";
+		reg = <0x00 0x43000000 0x00 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x00 0x00 0x43000000 0x20000>;
+
+		chipid@14 {
+			compatible = "ti,am654-chipid";
+			reg = <0x00000014 0x4>;
+		};
+
+		phy_gmii_sel: phy@4044 {
+			compatible = "ti,am654-phy-gmii-sel";
+			reg = <0x4044 0x8>;
+			#phy-cells = <1>;
+		};
+	};
+
+	main_uart0: serial@2800000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02800000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 146 0>;
+		clock-names = "fclk";
+	};
+
+	main_uart1: serial@2810000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02810000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 152 0>;
+		clock-names = "fclk";
+	};
+
+	main_uart2: serial@2820000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02820000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 153 0>;
+		clock-names = "fclk";
+	};
+
+	main_uart3: serial@2830000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02830000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 154 0>;
+		clock-names = "fclk";
+	};
+
+	main_uart4: serial@2840000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02840000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 155 0>;
+		clock-names = "fclk";
+	};
+
+	main_uart5: serial@2850000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02850000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 156 0>;
+		clock-names = "fclk";
+	};
+
+	main_uart6: serial@2860000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x02860000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 158 0>;
+		clock-names = "fclk";
+	};
+
+	main_i2c0: i2c@20000000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20000000 0x00 0x100>;
+		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 102 2>;
+		clock-names = "fck";
+	};
+
+	main_i2c1: i2c@20010000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20010000 0x00 0x100>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 103 2>;
+		clock-names = "fck";
+	};
+
+	main_i2c2: i2c@20020000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20020000 0x00 0x100>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 104 2>;
+		clock-names = "fck";
+	};
+
+	main_i2c3: i2c@20030000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20030000 0x00 0x100>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 105 2>;
+		clock-names = "fck";
+	};
+
+	main_spi0: spi@20100000 {
+		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+		reg = <0x00 0x20100000 0x00 0x400>;
+		interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 141 0>;
+		dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
+		dma-names = "tx0", "rx0";
+	};
+
+	main_spi1: spi@20110000 {
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+		reg = <0x00 0x20110000 0x00 0x400>;
+		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 142 0>;
+	};
+
+	main_spi2: spi@20120000 {
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+		reg = <0x00 0x20120000 0x00 0x400>;
+		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 143 0>;
+	};
+
+	main_spi3: spi@20130000 {
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+		reg = <0x00 0x20130000 0x00 0x400>;
+		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 144 0>;
+	};
+
+	main_spi4: spi@20140000 {
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+		reg = <0x00 0x20140000 0x00 0x400>;
+		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 145 0>;
+	};
+
+	sdhci0: mmc@fa10000 {
+		compatible = "ti,am64-sdhci-8bit";
+		reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
+		clock-names = "clk_ahb", "clk_xin";
+		mmc-ddr-1_8v;
+		mmc-hs200-1_8v;
+		mmc-hs400-1_8v;
+		ti,trm-icp = <0x2>;
+		ti,otap-del-sel-legacy = <0x0>;
+		ti,otap-del-sel-mmc-hs = <0x0>;
+		ti,otap-del-sel-ddr52 = <0x6>;
+		ti,otap-del-sel-hs200 = <0x7>;
+		ti,otap-del-sel-hs400 = <0x4>;
+	};
+
+	sdhci1: mmc@fa00000 {
+		compatible = "ti,am64-sdhci-4bit";
+		reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
+		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
+		clock-names = "clk_ahb", "clk_xin";
+		ti,trm-icp = <0x2>;
+		ti,otap-del-sel-legacy = <0x0>;
+		ti,otap-del-sel-sd-hs = <0xf>;
+		ti,otap-del-sel-sdr12 = <0xf>;
+		ti,otap-del-sel-sdr25 = <0xf>;
+		ti,otap-del-sel-sdr50 = <0xc>;
+		ti,otap-del-sel-sdr104 = <0x6>;
+		ti,otap-del-sel-ddr50 = <0x9>;
+		ti,clkbuf-sel = <0x7>;
+	};
+
+	cpsw3g: ethernet@8000000 {
+		compatible = "ti,am642-cpsw-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x0 0x8000000 0x0 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+		clocks = <&k3_clks 13 0>;
+		assigned-clocks = <&k3_clks 13 1>;
+		assigned-clock-parents = <&k3_clks 13 9>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&main_pktdma 0xC500 15>,
+		       <&main_pktdma 0xC501 15>,
+		       <&main_pktdma 0xC502 15>,
+		       <&main_pktdma 0xC503 15>,
+		       <&main_pktdma 0xC504 15>,
+		       <&main_pktdma 0xC505 15>,
+		       <&main_pktdma 0xC506 15>,
+		       <&main_pktdma 0xC507 15>,
+		       <&main_pktdma 0x4500 15>;
+		dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+			    "tx7", "rx";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			cpsw_port1: port@1 {
+				reg = <1>;
+				ti,mac-only;
+				label = "port1";
+				phys = <&phy_gmii_sel 1>;
+				mac-address = [00 00 de ad be ef];
+			};
+
+			cpsw_port2: port@2 {
+				reg = <2>;
+				ti,mac-only;
+				label = "port2";
+				phys = <&phy_gmii_sel 2>;
+				mac-address = [00 01 de ad be ef];
+			};
+		};
+
+		cpsw3g_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+			reg = <0x0 0xf00 0x0 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 13 0>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts@3d000 {
+			compatible = "ti,j721e-cpts";
+			reg = <0x0 0x3d000 0x0 0x400>;
+			clocks = <&k3_clks 13 1>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+	};
+
+	main_gpio0: gpio@600000 {
+		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+		reg = <0x00 0x00600000 0x00 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
+			     <77 1 IRQ_TYPE_EDGE_RISING>,
+			     <77 2 IRQ_TYPE_EDGE_RISING>,
+			     <77 3 IRQ_TYPE_EDGE_RISING>,
+			     <77 4 IRQ_TYPE_EDGE_RISING>,
+			     <77 5 IRQ_TYPE_EDGE_RISING>,
+			     <77 6 IRQ_TYPE_EDGE_RISING>,
+			     <77 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		ti,ngpio = <69>;
+		ti,davinci-gpio-unbanked = <0>;
+		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 77 0>;
+		clock-names = "gpio";
+	};
+
+	main_gpio1: gpio@601000 {
+		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+		reg = <0x00 0x00601000 0x00 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
+			     <78 1 IRQ_TYPE_EDGE_RISING>,
+			     <78 2 IRQ_TYPE_EDGE_RISING>,
+			     <78 3 IRQ_TYPE_EDGE_RISING>,
+			     <78 4 IRQ_TYPE_EDGE_RISING>,
+			     <78 5 IRQ_TYPE_EDGE_RISING>,
+			     <78 6 IRQ_TYPE_EDGE_RISING>,
+			     <78 7 IRQ_TYPE_EDGE_RISING>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		ti,ngpio = <69>;
+		ti,davinci-gpio-unbanked = <0>;
+		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 78 0>;
+		clock-names = "gpio";
+	};
+
+	main_i2c0: i2c@20000000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x0 0x20000000 0x0 0x100>;
+		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "fck";
+		clocks = <&k3_clks 102 2>;
+		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+	};
+
+	main_i2c1: i2c@20010000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x0 0x20010000 0x0 0x100>;
+		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "fck";
+		clocks = <&k3_clks 103 2>;
+		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+	};
+
+	main_i2c2: i2c@20020000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20020000 0x0 0x100>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "fck";
+		clocks = <&k3_clks 104 2>;
+		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+	};
+
+	main_i2c3: i2c@20030000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x20030000 0x0 0x100>;
+		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clock-names = "fck";
+		clocks = <&k3_clks 105 2>;
+		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+	};
+};
diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi
new file mode 100644
index 0000000000..1d2be485a6
--- /dev/null
+++ b/arch/arm/dts/k3-am64-mcu.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM64 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+	mcu_uart0: serial@4a00000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x04a00000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 149 0>;
+		clock-names = "fclk";
+	};
+
+	mcu_uart1: serial@4a10000 {
+		compatible = "ti,am64-uart", "ti,am654-uart";
+		reg = <0x00 0x04a10000 0x00 0x100>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 160 0>;
+		clock-names = "fclk";
+	};
+
+	mcu_i2c0: i2c@4900000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x04900000 0x00 0x100>;
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 106 2>;
+		clock-names = "fck";
+	};
+
+	mcu_i2c1: i2c@4910000 {
+		compatible = "ti,am64-i2c", "ti,omap4-i2c";
+		reg = <0x00 0x04910000 0x00 0x100>;
+		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 107 2>;
+		clock-names = "fck";
+	};
+
+	mcu_spi0: spi@4b00000 {
+		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+		reg = <0x00 0x04b00000 0x00 0x400>;
+		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 147 0>;
+	};
+
+	mcu_spi1: spi@4b10000 {
+		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+		reg = <0x00 0x04b10000 0x00 0x400>;
+		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 148 0>;
+	};
+};
diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
new file mode 100644
index 0000000000..64a159f6d0
--- /dev/null
+++ b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
@@ -0,0 +1,2190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the
+ * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.06.00
+ * Mon Apr 26 2021 20:47:47 GMT-0500 (Central Daylight Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz    F1 = 666.7MHz    F2 = 666.7MHz
+ * Density (per channel): 16Gb
+ * Number of Ranks: 1
+*/
+
+#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FREQUENCY_1 333350000
+#define DDRSS_PLL_FREQUENCY_2 333350000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x000208D6
+#define DDRSS_CTL_12_DATA 0x00145856
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000536
+#define DDRSS_CTL_15_DATA 0x000208D6
+#define DDRSS_CTL_16_DATA 0x00145856
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000536
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x02000010
+#define DDRSS_CTL_35_DATA 0x00001B1B
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0000040C
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x05000804
+#define DDRSS_CTL_45_DATA 0x00000700
+#define DDRSS_CTL_46_DATA 0x09090004
+#define DDRSS_CTL_47_DATA 0x00000203
+#define DDRSS_CTL_48_DATA 0x00290006
+#define DDRSS_CTL_49_DATA 0x0909001D
+#define DDRSS_CTL_50_DATA 0x0000150C
+#define DDRSS_CTL_51_DATA 0x00290006
+#define DDRSS_CTL_52_DATA 0x0909001D
+#define DDRSS_CTL_53_DATA 0x0900150C
+#define DDRSS_CTL_54_DATA 0x000A0A09
+#define DDRSS_CTL_55_DATA 0x040006DB
+#define DDRSS_CTL_56_DATA 0x09092004
+#define DDRSS_CTL_57_DATA 0x00000A0A
+#define DDRSS_CTL_58_DATA 0x05005B68
+#define DDRSS_CTL_59_DATA 0x09092005
+#define DDRSS_CTL_60_DATA 0x00000A0A
+#define DDRSS_CTL_61_DATA 0x05005B68
+#define DDRSS_CTL_62_DATA 0x03042005
+#define DDRSS_CTL_63_DATA 0x04050002
+#define DDRSS_CTL_64_DATA 0x0E0D0E0D
+#define DDRSS_CTL_65_DATA 0x01010008
+#define DDRSS_CTL_66_DATA 0x041A1A07
+#define DDRSS_CTL_67_DATA 0x030E0E03
+#define DDRSS_CTL_68_DATA 0x00000E0E
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x00130803
+#define DDRSS_CTL_73_DATA 0x000000BB
+#define DDRSS_CTL_74_DATA 0x000000FE
+#define DDRSS_CTL_75_DATA 0x00000A20
+#define DDRSS_CTL_76_DATA 0x000000FE
+#define DDRSS_CTL_77_DATA 0x00000A20
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x0000000A
+#define DDRSS_CTL_80_DATA 0x00000010
+#define DDRSS_CTL_81_DATA 0x0000007F
+#define DDRSS_CTL_82_DATA 0x0000013D
+#define DDRSS_CTL_83_DATA 0x0000007F
+#define DDRSS_CTL_84_DATA 0x0000013D
+#define DDRSS_CTL_85_DATA 0x03004000
+#define DDRSS_CTL_86_DATA 0x00001201
+#define DDRSS_CTL_87_DATA 0x00050005
+#define DDRSS_CTL_88_DATA 0x00000005
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x05101008
+#define DDRSS_CTL_91_DATA 0x05030A05
+#define DDRSS_CTL_92_DATA 0x05030A05
+#define DDRSS_CTL_93_DATA 0x01030A05
+#define DDRSS_CTL_94_DATA 0x02010201
+#define DDRSS_CTL_95_DATA 0x00001401
+#define DDRSS_CTL_96_DATA 0x01030014
+#define DDRSS_CTL_97_DATA 0x01030103
+#define DDRSS_CTL_98_DATA 0x00000103
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x05010303
+#define DDRSS_CTL_101_DATA 0x0A040505
+#define DDRSS_CTL_102_DATA 0x05050203
+#define DDRSS_CTL_103_DATA 0x030A0505
+#define DDRSS_CTL_104_DATA 0x05050502
+#define DDRSS_CTL_105_DATA 0x03030305
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00002EC0
+#define DDRSS_CTL_120_DATA 0x00002EC0
+#define DDRSS_CTL_121_DATA 0x00002EC0
+#define DDRSS_CTL_122_DATA 0x00002EC0
+#define DDRSS_CTL_123_DATA 0x00002EC0
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000051D
+#define DDRSS_CTL_126_DATA 0x00028800
+#define DDRSS_CTL_127_DATA 0x00028800
+#define DDRSS_CTL_128_DATA 0x00028800
+#define DDRSS_CTL_129_DATA 0x00028800
+#define DDRSS_CTL_130_DATA 0x00028800
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x000046E0
+#define DDRSS_CTL_133_DATA 0x00028800
+#define DDRSS_CTL_134_DATA 0x00028800
+#define DDRSS_CTL_135_DATA 0x00028800
+#define DDRSS_CTL_136_DATA 0x00028800
+#define DDRSS_CTL_137_DATA 0x00028800
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x000046E0
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x03050000
+#define DDRSS_CTL_157_DATA 0x03050305
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x07010A09
+#define DDRSS_CTL_160_DATA 0x000E0A09
+#define DDRSS_CTL_161_DATA 0x010A0900
+#define DDRSS_CTL_162_DATA 0x0E0A0907
+#define DDRSS_CTL_163_DATA 0x0A090000
+#define DDRSS_CTL_164_DATA 0x0A090701
+#define DDRSS_CTL_165_DATA 0x0000000E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000002
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x0005000A
+#define DDRSS_CTL_193_DATA 0x0404000D
+#define DDRSS_CTL_194_DATA 0x0000000D
+#define DDRSS_CTL_195_DATA 0x00430086
+#define DDRSS_CTL_196_DATA 0x050500A7
+#define DDRSS_CTL_197_DATA 0x000000A7
+#define DDRSS_CTL_198_DATA 0x00430086
+#define DDRSS_CTL_199_DATA 0x050500A7
+#define DDRSS_CTL_200_DATA 0x000000A7
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000004
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000024
+#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000024
+#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000004
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000024
+#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000024
+#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x00000031
+#define DDRSS_CTL_226_DATA 0x00000031
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x00000031
+#define DDRSS_CTL_229_DATA 0x00000031
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x66006666
+#define DDRSS_CTL_255_DATA 0x00002766
+#define DDRSS_CTL_256_DATA 0x00000027
+#define DDRSS_CTL_257_DATA 0x00000027
+#define DDRSS_CTL_258_DATA 0x00000027
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x0000000F
+#define DDRSS_CTL_264_DATA 0x0000000F
+#define DDRSS_CTL_265_DATA 0x0000000F
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_271_DATA 0x00000015
+#define DDRSS_CTL_272_DATA 0x00000015
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000015
+#define DDRSS_CTL_275_DATA 0x00000015
+#define DDRSS_CTL_276_DATA 0x00000020
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000100
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00020000
+#define DDRSS_CTL_306_DATA 0x00400100
+#define DDRSS_CTL_307_DATA 0x00080032
+#define DDRSS_CTL_308_DATA 0x01000200
+#define DDRSS_CTL_309_DATA 0x029B0040
+#define DDRSS_CTL_310_DATA 0x00020014
+#define DDRSS_CTL_311_DATA 0x00400100
+#define DDRSS_CTL_312_DATA 0x0014029B
+#define DDRSS_CTL_313_DATA 0x00030000
+#define DDRSS_CTL_314_DATA 0x00220022
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_322_DATA 0x0B000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x01000100
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_331_DATA 0x01030303
+#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x01000101
+#define DDRSS_CTL_372_DATA 0x01010001
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_375_DATA 0x05020201
+#define DDRSS_CTL_376_DATA 0x08080B0B
+#define DDRSS_CTL_377_DATA 0x00080308
+#define DDRSS_CTL_378_DATA 0x000C030E
+#define DDRSS_CTL_379_DATA 0x000C0310
+#define DDRSS_CTL_380_DATA 0x0C0C0810
+#define DDRSS_CTL_381_DATA 0x01000000
+#define DDRSS_CTL_382_DATA 0x03010301
+#define DDRSS_CTL_383_DATA 0x04000101
+#define DDRSS_CTL_384_DATA 0x1B000004
+#define DDRSS_CTL_385_DATA 0x00000176
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x00000693
+#define DDRSS_CTL_391_DATA 0x00000E9C
+#define DDRSS_CTL_392_DATA 0x03050202
+#define DDRSS_CTL_393_DATA 0x00240201
+#define DDRSS_CTL_394_DATA 0x00001440
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00005B20
+#define DDRSS_CTL_400_DATA 0x0000CA80
+#define DDRSS_CTL_401_DATA 0x080D0402
+#define DDRSS_CTL_402_DATA 0x00240405
+#define DDRSS_CTL_403_DATA 0x00001440
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00005B20
+#define DDRSS_CTL_409_DATA 0x0000CA80
+#define DDRSS_CTL_410_DATA 0x080D0402
+#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x10100600
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000007
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00010000
+#define DDRSS_PI_24_DATA 0x280A0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x01010102
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x03000000
+#define DDRSS_PI_55_DATA 0x00000000
+#define DDRSS_PI_56_DATA 0x00001701
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x01000210
+#define DDRSS_PI_63_DATA 0x05000404
+#define DDRSS_PI_64_DATA 0x00010001
+#define DDRSS_PI_65_DATA 0x0001000E
+#define DDRSS_PI_66_DATA 0x01010100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x08000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x0000000A
+#define DDRSS_PI_137_DATA 0x000186A0
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000800
+#define DDRSS_PI_165_DATA 0x00640064
+#define DDRSS_PI_166_DATA 0x000E0E01
+#define DDRSS_PI_167_DATA 0x00000034
+#define DDRSS_PI_168_DATA 0x00000042
+#define DDRSS_PI_169_DATA 0x00020042
+#define DDRSS_PI_170_DATA 0x02000200
+#define DDRSS_PI_171_DATA 0x00000004
+#define DDRSS_PI_172_DATA 0x0000080C
+#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_174_DATA 0x001C0000
+#define DDRSS_PI_175_DATA 0x00000013
+#define DDRSS_PI_176_DATA 0x000000BB
+#define DDRSS_PI_177_DATA 0x000000FE
+#define DDRSS_PI_178_DATA 0x00000A20
+#define DDRSS_PI_179_DATA 0x000000FE
+#define DDRSS_PI_180_DATA 0x04000A20
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001501
+#define DDRSS_PI_183_DATA 0x001B001B
+#define DDRSS_PI_184_DATA 0x01000100
+#define DDRSS_PI_185_DATA 0x00000100
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_188_DATA 0x01010B0B
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x000C0C0A
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x04000000
+#define DDRSS_PI_194_DATA 0x04020909
+#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_196_DATA 0x00090031
+#define DDRSS_PI_197_DATA 0x000F0037
+#define DDRSS_PI_198_DATA 0x000F0037
+#define DDRSS_PI_199_DATA 0x01010101
+#define DDRSS_PI_200_DATA 0x0001000D
+#define DDRSS_PI_201_DATA 0x000100A7
+#define DDRSS_PI_202_DATA 0x010000A7
+#define DDRSS_PI_203_DATA 0x000E000E
+#define DDRSS_PI_204_DATA 0x00A80100
+#define DDRSS_PI_205_DATA 0x010000A8
+#define DDRSS_PI_206_DATA 0x00A800A8
+#define DDRSS_PI_207_DATA 0x32103200
+#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_209_DATA 0x0A070601
+#define DDRSS_PI_210_DATA 0x0B08070D
+#define DDRSS_PI_211_DATA 0x0B08070D
+#define DDRSS_PI_212_DATA 0x000C000D
+#define DDRSS_PI_213_DATA 0x00001000
+#define DDRSS_PI_214_DATA 0x00000C00
+#define DDRSS_PI_215_DATA 0x00001000
+#define DDRSS_PI_216_DATA 0x00000C00
+#define DDRSS_PI_217_DATA 0x02001000
+#define DDRSS_PI_218_DATA 0x0015000D
+#define DDRSS_PI_219_DATA 0x001500A7
+#define DDRSS_PI_220_DATA 0x000000A7
+#define DDRSS_PI_221_DATA 0x00001900
+#define DDRSS_PI_222_DATA 0x32000056
+#define DDRSS_PI_223_DATA 0x06000301
+#define DDRSS_PI_224_DATA 0x001D0204
+#define DDRSS_PI_225_DATA 0x32120059
+#define DDRSS_PI_226_DATA 0x05000301
+#define DDRSS_PI_227_DATA 0x001D0409
+#define DDRSS_PI_228_DATA 0x32120059
+#define DDRSS_PI_229_DATA 0x05000301
+#define DDRSS_PI_230_DATA 0x00000409
+#define DDRSS_PI_231_DATA 0x05030900
+#define DDRSS_PI_232_DATA 0x00040900
+#define DDRSS_PI_233_DATA 0x0000062B
+#define DDRSS_PI_234_DATA 0x20010004
+#define DDRSS_PI_235_DATA 0x0A0A0A03
+#define DDRSS_PI_236_DATA 0x0E090000
+#define DDRSS_PI_237_DATA 0x0E09000D
+#define DDRSS_PI_238_DATA 0x00005244
+#define DDRSS_PI_239_DATA 0x2003001D
+#define DDRSS_PI_240_DATA 0x0A0A0A0A
+#define DDRSS_PI_241_DATA 0x0E090000
+#define DDRSS_PI_242_DATA 0x0E09000D
+#define DDRSS_PI_243_DATA 0x00005244
+#define DDRSS_PI_244_DATA 0x2003001D
+#define DDRSS_PI_245_DATA 0x0A0A0A0A
+#define DDRSS_PI_246_DATA 0x00000000
+#define DDRSS_PI_247_DATA 0x00000176
+#define DDRSS_PI_248_DATA 0x00000E9C
+#define DDRSS_PI_249_DATA 0x00001440
+#define DDRSS_PI_250_DATA 0x0000CA80
+#define DDRSS_PI_251_DATA 0x00001440
+#define DDRSS_PI_252_DATA 0x0000CA80
+#define DDRSS_PI_253_DATA 0x01030014
+#define DDRSS_PI_254_DATA 0x03030103
+#define DDRSS_PI_255_DATA 0x00000003
+#define DDRSS_PI_256_DATA 0x00000000
+#define DDRSS_PI_257_DATA 0x05030503
+#define DDRSS_PI_258_DATA 0x00000503
+#define DDRSS_PI_259_DATA 0x00002710
+#define DDRSS_PI_260_DATA 0x000186A0
+#define DDRSS_PI_261_DATA 0x00000005
+#define DDRSS_PI_262_DATA 0x00000064
+#define DDRSS_PI_263_DATA 0x00000014
+#define DDRSS_PI_264_DATA 0x000208D6
+#define DDRSS_PI_265_DATA 0x000186A0
+#define DDRSS_PI_266_DATA 0x00000005
+#define DDRSS_PI_267_DATA 0x00000536
+#define DDRSS_PI_268_DATA 0x00000103
+#define DDRSS_PI_269_DATA 0x000208D6
+#define DDRSS_PI_270_DATA 0x000186A0
+#define DDRSS_PI_271_DATA 0x00000005
+#define DDRSS_PI_272_DATA 0x00000536
+#define DDRSS_PI_273_DATA 0x01000103
+#define DDRSS_PI_274_DATA 0x00320040
+#define DDRSS_PI_275_DATA 0x00010008
+#define DDRSS_PI_276_DATA 0x029B0040
+#define DDRSS_PI_277_DATA 0x00010014
+#define DDRSS_PI_278_DATA 0x029B0040
+#define DDRSS_PI_279_DATA 0x00000314
+#define DDRSS_PI_280_DATA 0x00280021
+#define DDRSS_PI_281_DATA 0x03040404
+#define DDRSS_PI_282_DATA 0x00000303
+#define DDRSS_PI_283_DATA 0x02020101
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000000
+#define DDRSS_PI_286_DATA 0x55000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x3C00005A
+#define DDRSS_PI_289_DATA 0x00005500
+#define DDRSS_PI_290_DATA 0x00005A00
+#define DDRSS_PI_291_DATA 0x0D100F3C
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000000
+#define DDRSS_PI_298_DATA 0x00000004
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000031
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000F27
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x00000024
+#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_308_DATA 0x00000031
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000000
+#define DDRSS_PI_311_DATA 0x66000000
+#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_313_DATA 0x00000000
+#define DDRSS_PI_314_DATA 0x00000024
+#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_316_DATA 0x00000031
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000000
+#define DDRSS_PI_319_DATA 0x66000000
+#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000004
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000031
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000F27
+#define DDRSS_PI_329_DATA 0x00000000
+#define DDRSS_PI_330_DATA 0x00000024
+#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_332_DATA 0x00000031
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x66000000
+#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_337_DATA 0x00000000
+#define DDRSS_PI_338_DATA 0x00000024
+#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_340_DATA 0x00000031
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000000
+#define DDRSS_PI_343_DATA 0x66000000
+#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01000000
+#define DDRSS_PHY_6_DATA 0x03000400
+#define DDRSS_PHY_7_DATA 0x00000001
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01010000
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00001
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660601
+#define DDRSS_PHY_16_DATA 0x00000003
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00071020
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000001
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CC0B01
+#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x00100303
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00021000
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02000010
+#define DDRSS_PHY_88_DATA 0x51516041
+#define DDRSS_PHY_89_DATA 0x31C06000
+#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_91_DATA 0x0100C0C0
+#define DDRSS_PHY_92_DATA 0x03040000
+#define DDRSS_PHY_93_DATA 0x00000403
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C1A
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x00660120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001AA
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000004
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x032A032A
+#define DDRSS_PHY_106_DATA 0x032A032A
+#define DDRSS_PHY_107_DATA 0x032A032A
+#define DDRSS_PHY_108_DATA 0x032A032A
+#define DDRSS_PHY_109_DATA 0x0000032A
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01190080
+#define DDRSS_PHY_120_DATA 0x01A00001
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x0000F0F0
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01000000
+#define DDRSS_PHY_262_DATA 0x03000400
+#define DDRSS_PHY_263_DATA 0x00000001
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01010000
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00001
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660601
+#define DDRSS_PHY_272_DATA 0x00000003
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00071020
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CC0B01
+#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x00100303
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00021000
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02000010
+#define DDRSS_PHY_344_DATA 0x51516041
+#define DDRSS_PHY_345_DATA 0x31C06000
+#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_347_DATA 0x0100C0C0
+#define DDRSS_PHY_348_DATA 0x03040000
+#define DDRSS_PHY_349_DATA 0x00000403
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C1A
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x00660120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001AA
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000004
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x032A032A
+#define DDRSS_PHY_362_DATA 0x032A032A
+#define DDRSS_PHY_363_DATA 0x032A032A
+#define DDRSS_PHY_364_DATA 0x032A032A
+#define DDRSS_PHY_365_DATA 0x0000032A
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01190080
+#define DDRSS_PHY_376_DATA 0x01A00001
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x0000F0F0
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000200
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00400000
+#define DDRSS_PHY_524_DATA 0x00000080
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x03000000
+#define DDRSS_PHY_527_DATA 0x00200000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x0000002A
+#define DDRSS_PHY_533_DATA 0x00000015
+#define DDRSS_PHY_534_DATA 0x00000015
+#define DDRSS_PHY_535_DATA 0x0000002A
+#define DDRSS_PHY_536_DATA 0x00000033
+#define DDRSS_PHY_537_DATA 0x0000000C
+#define DDRSS_PHY_538_DATA 0x0000000C
+#define DDRSS_PHY_539_DATA 0x00000033
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x003F0000
+#define DDRSS_PHY_542_DATA 0x000F013F
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x000002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000803E
+#define DDRSS_PHY_553_DATA 0x00000003
+#define DDRSS_PHY_554_DATA 0x00000002
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000200
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00400000
+#define DDRSS_PHY_780_DATA 0x00000080
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x03000000
+#define DDRSS_PHY_783_DATA 0x00200000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x0000002A
+#define DDRSS_PHY_789_DATA 0x00000015
+#define DDRSS_PHY_790_DATA 0x00000015
+#define DDRSS_PHY_791_DATA 0x0000002A
+#define DDRSS_PHY_792_DATA 0x00000033
+#define DDRSS_PHY_793_DATA 0x0000000C
+#define DDRSS_PHY_794_DATA 0x0000000C
+#define DDRSS_PHY_795_DATA 0x00000033
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x000002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000803E
+#define DDRSS_PHY_809_DATA 0x00000003
+#define DDRSS_PHY_810_DATA 0x00000002
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x0000002A
+#define DDRSS_PHY_1045_DATA 0x00000015
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x0000002A
+#define DDRSS_PHY_1048_DATA 0x00000033
+#define DDRSS_PHY_1049_DATA 0x0000000C
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x00000033
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10000000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x000002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000803E
+#define DDRSS_PHY_1065_DATA 0x00000003
+#define DDRSS_PHY_1066_DATA 0x00000002
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000000
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x00002001
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x01010100
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00041B42
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07030101
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000076
+#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00040198
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1372_DATA 0x00000002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x030207AB
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03000300
+#define DDRSS_PHY_1382_DATA 0x03000300
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000DFF
+#define DDRSS_PHY_1390_DATA 0x30000DFF
+#define DDRSS_PHY_1391_DATA 0x3F0DFF11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x00018011
+#define DDRSS_PHY_1396_DATA 0x0089FF00
+#define DDRSS_PHY_1397_DATA 0x000C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x3F0DFF11
+#define DDRSS_PHY_1402_DATA 0x019900E0
+#define DDRSS_PHY_1403_DATA 0x00018011
+#define DDRSS_PHY_1404_DATA 0x0089FF00
+#define DDRSS_PHY_1405_DATA 0x20040001
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
new file mode 100644
index 0000000000..6b2d0803b4
--- /dev/null
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+	model = "Texas Instruments K3 AM642 SoC";
+	compatible = "ti,am642";
+	interrupt-parent = <&gic500>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &mcu_uart0;
+		serial1 = &mcu_uart1;
+		serial2 = &main_uart0;
+		serial3 = &main_uart1;
+		serial4 = &main_uart2;
+		serial5 = &main_uart3;
+		serial6 = &main_uart4;
+		serial7 = &main_uart5;
+		serial8 = &main_uart6;
+		i2c0 = &main_i2c0;
+		i2c1 = &main_i2c1;
+		ethernet0 = &cpsw_port1;
+		ethernet1 = &cpsw_port2;
+	};
+
+	chosen { };
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+
+		psci: psci {
+			compatible = "arm,psci-1.0";
+			method = "smc";
+		};
+	};
+
+	a53_timer0: timer-cl0-cpu0 {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+	};
+
+	pmu: pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	cbass_main: bus@f4000 {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
+			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+			 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
+			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
+			 <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
+			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+			 <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
+			 <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
+			 <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
+			 <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
+			 <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
+			 <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
+			 <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
+			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
+			 <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
+			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+			 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
+			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
+			 <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
+			 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
+			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+			 /* MCU Domain Range */
+			 <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
+
+		cbass_mcu: bus@4000000 {
+			compatible = "simple-bus";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
+		};
+	};
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am64-main.dtsi"
+#include "k3-am64-mcu.dtsi"
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
new file mode 100644
index 0000000000..9b0ba6b721
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+};
+
+&cbass_main{
+	u-boot,dm-spl;
+	timer1: timer@2400000 {
+		compatible = "ti,omap5430-timer";
+		reg = <0x0 0x2400000 0x0 0x80>;
+		ti,timer-alwon;
+		clock-frequency = <250000000>;
+		u-boot,dm-spl;
+	};
+};
+
+&main_conf {
+	u-boot,dm-spl;
+	chipid@14 {
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+		>;
+	};
+};
+
+&main_i2c0 {
+	u-boot,dm-spl;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&main_uart0 {
+	u-boot,dm-spl;
+};
+
+&dmss {
+	u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+	u-boot,dm-spl;
+};
+
+&dmsc {
+	u-boot,dm-spl;
+};
+
+&k3_pds {
+	u-boot,dm-spl;
+};
+
+&k3_clks {
+	u-boot,dm-spl;
+};
+
+&k3_reset {
+	u-boot,dm-spl;
+};
+
+&sdhci0 {
+	u-boot,dm-spl;
+};
+
+&sdhci1 {
+	u-boot,dm-spl;
+};
+
+&cpsw3g {
+	reg = <0x0 0x8000000 0x0 0x200000>,
+	      <0x0 0x43000200 0x0 0x8>;
+	reg-names = "cpsw_nuss", "mac_efuse";
+	/delete-property/ ranges;
+
+	cpsw-phy-sel@04044 {
+		compatible = "ti,am64-phy-gmii-sel";
+		reg = <0x0 0x43004044 0x0 0x8>;
+	};
+};
+
+&cpsw_port2 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
new file mode 100644
index 0000000000..dc3482bea4
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am642.dtsi"
+
+/ {
+	compatible =  "ti,am642-evm", "ti,am642";
+	model = "Texas Instruments AM642 EVM";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	evm_12v0: fixedregulator-evm12v0 {
+		/* main DC jack */
+		compatible = "regulator-fixed";
+		regulator-name = "evm_12v0";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_5v0: fixedregulator-vsys5v0 {
+		/* output of LM5140 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_5v0";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&evm_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vsys_3v3: fixedregulator-vsys3v3 {
+		/* output of LM5140 */
+		compatible = "regulator-fixed";
+		regulator-name = "vsys_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&evm_12v0>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_mmc1: fixed-regulator-sd {
+		/* TPS2051BD */
+		compatible = "regulator-fixed";
+		regulator-name = "vdd_mmc1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		enable-active-high;
+		vin-supply = <&vsys_3v3>;
+		gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
+	};
+
+	vddb: fixedregulator-vddb {
+		compatible = "regulator-fixed";
+		regulator-name = "vddb_3v3_display";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vsys_3v3>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			label = "am64-evm:red:heartbeat";
+			gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			function = LED_FUNCTION_HEARTBEAT;
+			default-state = "off";
+		};
+	};
+
+	mdio_mux: mux-controller {
+		compatible = "gpio-mux";
+		#mux-control-cells = <0>;
+
+		mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
+	};
+
+	mdio-mux-1 {
+		compatible = "mdio-mux-multiplexer";
+		mux-controls = <&mdio_mux>;
+		mdio-parent-bus = <&cpsw3g_mdio>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mdio@1 {
+			reg = <0x1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			cpsw3g_phy3: ethernet-phy@3 {
+				reg = <3>;
+			};
+		};
+	};
+};
+
+&main_pmx0 {
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+			AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
+			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
+		>;
+	};
+
+	main_uart0_pins_default: main-uart0-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
+			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
+		>;
+	};
+
+	mdio1_pins_default: mdio1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+		>;
+	};
+
+	rgmii1_pins_default: rgmii1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
+			AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
+			AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
+			AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
+			AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
+			AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
+			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+		>;
+	};
+
+       rgmii2_pins_default: rgmii2-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+		>;
+	};
+};
+
+&main_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+/* main_uart1 is reserved for firmware usage */
+&main_uart1 {
+	status = "reserved";
+};
+
+&main_uart2 {
+	status = "disabled";
+};
+
+&main_uart3 {
+	status = "disabled";
+};
+
+&main_uart4 {
+	status = "disabled";
+};
+
+&main_uart5 {
+	status = "disabled";
+};
+
+&main_uart6 {
+	status = "disabled";
+};
+
+&mcu_uart0 {
+	status = "disabled";
+};
+
+&mcu_uart1 {
+	status = "disabled";
+};
+
+&main_i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c1_pins_default>;
+	clock-frequency = <400000>;
+
+	exp1: gpio@22 {
+		compatible = "ti,tca6424";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
+				  "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
+				  "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
+				  "MMC1_SD_EN", "FSI_FET_SEL",
+				  "MCAN0_STB_3V3", "MCAN1_STB_3V3",
+				  "CPSW_FET_SEL", "CPSW_FET2_SEL",
+				  "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
+				  "GPIO_OLED_RESETn", "VPP_LDO_EN",
+				  "TEST_LED1", "TP92", "TP90", "TP88",
+				  "TP87", "TP86", "TP89", "TP91";
+	};
+
+	/* osd9616p0899-10 */
+	display@3c {
+		compatible = "solomon,ssd1306fb-i2c";
+		reg = <0x3c>;
+		reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
+		vbat-supply = <&vddb>;
+		solomon,height = <16>;
+		solomon,width = <96>;
+		solomon,com-seq;
+		solomon,com-invdir;
+		solomon,page-offset = <0>;
+		solomon,prechargep1 = <2>;
+		solomon,prechargep2 = <13>;
+	};
+};
+
+&mcu_i2c0 {
+	status = "disabled";
+};
+
+&mcu_i2c1 {
+	status = "disabled";
+};
+
+&mcu_spi0 {
+	status = "disabled";
+};
+
+&mcu_spi1 {
+	status = "disabled";
+};
+
+&cpsw3g {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio1_pins_default
+		     &rgmii1_pins_default
+		     &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy3>;
+};
+
+&cpsw3g_mdio {
+	cpsw3g_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+};
+
+&sdhci0 {
+	/* emmc */
+	bus-width = <8>;
+	non-removable;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&sdhci1 {
+	/* SD/MMC */
+	vmmc-supply = <&vdd_mmc1>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
new file mode 100644
index 0000000000..1fbf6d2c23
--- /dev/null
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am642.dtsi"
+#include "k3-am64-evm-ddr4-1600MTs.dtsi"
+#include "k3-am64-ddr.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1000000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		u-boot,dm-spl;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	clk_200mhz: dummy-clock-200mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		u-boot,dm-spl;
+	};
+
+	vtt_supply: vtt-supply {
+		compatible = "regulator-gpio";
+		regulator-name = "vtt";
+		regulator-min-microvolt = <0>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
+		states = <0 0x0 3300000 0x1>;
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-system-controller";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
+		mbox-names = "tx", "rx";
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+	main_uart0_pins_default: main-uart0-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0238, PIN_INPUT, 0)		/* (B16) UART0_CTSn */
+			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0)		/* (A16) UART0_RTSn */
+			AM64X_IOPAD(0x0230, PIN_INPUT, 0)		/* (D15) UART0_RXD */
+			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0)		/* (C16) UART0_TXD */
+		>;
+	};
+
+	main_uart1_pins_default: main-uart1-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0248, PIN_INPUT, 0)		/* (D16) UART1_CTSn */
+			AM64X_IOPAD(0x024c, PIN_OUTPUT, 0)		/* (E16) UART1_RTSn */
+			AM64X_IOPAD(0x0240, PIN_INPUT, 0)		/* (E15) UART1_RXD */
+			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0)		/* (E14) UART1_TXD */
+		>;
+	};
+
+	main_mmc0_pins_default: main-mmc0-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)	/* (B25) MMC0_CLK */
+			AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)	/* (B27) MMC0_CMD */
+			AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)	/* (A26) MMC0_DAT0 */
+			AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)	/* (E25) MMC0_DAT1 */
+			AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)	/* (C26) MMC0_DAT2 */
+			AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)	/* (A25) MMC0_DAT3 */
+			AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)	/* (E24) MMC0_DAT4 */
+			AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)	/* (A24) MMC0_DAT5 */
+			AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)	/* (B26) MMC0_DAT6 */
+			AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)	/* (D25) MMC0_DAT7 */
+			AM64X_IOPAD(0x01b0, PIN_INPUT, 0)		/* (C25) MMC0_DS */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0)	/* (J19) MMC1_CMD */
+			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0)	/* (L20) MMC1_CLK */
+			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0)	/* (K21) MMC1_DAT0 */
+			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0)	/* (L21) MMC1_DAT1 */
+			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0)	/* (K19) MMC1_DAT2 */
+			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0)	/* (K18) MMC1_DAT3 */
+			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0)	/* (D19) MMC1_SDCD */
+			AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0)	/* (C20) MMC1_SDWP */
+		>;
+	};
+
+	ddr_vtt_pins_default: ddr-vtt-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7)	/* (L18) OSPI0_CSN1.GPIO0_12 */
+		>;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&main_uart0 {
+	/delete-property/ power-domains;
+	/delete-property/ clocks;
+	/delete-property/ clock-names;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	status = "okay";
+};
+
+&main_uart1 {
+	u-boot,dm-spl;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&memorycontroller {
+	vtt-supply = <&vtt_supply>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ddr_vtt_pins_default>;
+};
+
+&sdhci0 {
+	/delete-property/ power-domains;
+	clocks = <&clk_200mhz>;
+	clock-names = "clk_xin";
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+	pinctrl-0 = <&main_mmc0_pins_default>;
+};
+
+&sdhci1 {
+	/delete-property/ power-domains;
+	clocks = <&clk_200mhz>;
+	clock-names = "clk_xin";
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+	pinctrl-0 = <&main_mmc1_pins_default>;
+};
+
+&main_gpio0 {
+	u-boot,dm-spl;
+	/delete-property/ power-domains;
+};
+
+/* EEPROM might be read before SYSFW is available */
+&main_i2c0 {
+	/delete-property/ power-domains;
+};
+
+#include "k3-am642-evm-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
new file mode 100644
index 0000000000..79eff8259f
--- /dev/null
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am642.dtsi"
+#include "k3-am64-sk-lp4-1333MTs.dtsi"
+#include "k3-am64-ddr.dtsi"
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+
+	aliases {
+		remoteproc0 = &sysctrler;
+		remoteproc1 = &a53_0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+	};
+
+	a53_0: a53@0 {
+		compatible = "ti,am654-rproc";
+		reg = <0x00 0x00a90000 0x00 0x10>;
+		power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+				<&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+		resets = <&k3_reset 135 0>;
+		clocks = <&k3_clks 61 0>;
+		assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+		assigned-clock-parents = <&k3_clks 61 2>;
+		assigned-clock-rates = <200000000>, <1000000000>;
+		ti,sci = <&dmsc>;
+		ti,sci-proc-id = <32>;
+		ti,sci-host-id = <10>;
+		u-boot,dm-spl;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+
+	clk_200mhz: dummy-clock-200mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <200000000>;
+		u-boot,dm-spl;
+	};
+};
+
+&cbass_main {
+	sysctrler: sysctrler {
+		compatible = "ti,am654-system-controller";
+		mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
+		mbox-names = "tx", "rx";
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+	main_uart0_pins_default: main-uart0-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0238, PIN_INPUT, 0)		/* (B16) UART0_CTSn */
+			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0)		/* (A16) UART0_RTSn */
+			AM64X_IOPAD(0x0230, PIN_INPUT, 0)		/* (D15) UART0_RXD */
+			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0)		/* (C16) UART0_TXD */
+		>;
+	};
+
+	main_uart1_pins_default: main-uart1-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0248, PIN_INPUT, 0)		/* (D16) UART1_CTSn */
+			AM64X_IOPAD(0x024c, PIN_OUTPUT, 0)		/* (E16) UART1_RTSn */
+			AM64X_IOPAD(0x0240, PIN_INPUT, 0)		/* (E15) UART1_RXD */
+			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0)		/* (E14) UART1_TXD */
+		>;
+	};
+
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0)	/* (J19) MMC1_CMD */
+			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0)	/* (L20) MMC1_CLK */
+			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0)	/* (K21) MMC1_DAT0 */
+			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0)	/* (L21) MMC1_DAT1 */
+			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0)	/* (K19) MMC1_DAT2 */
+			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0)	/* (K18) MMC1_DAT3 */
+			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0)	/* (D19) MMC1_SDCD */
+			AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0)	/* (C20) MMC1_SDWP */
+		>;
+	};
+};
+
+&dmsc {
+	mboxes= <&secure_proxy_main 0>,
+		<&secure_proxy_main 1>,
+		<&secure_proxy_main 0>;
+	mbox-names = "rx", "tx", "notify";
+	ti,host-id = <35>;
+	ti,secure-host;
+};
+
+&main_uart0 {
+	/delete-property/ power-domains;
+	/delete-property/ clocks;
+	/delete-property/ clock-names;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart0_pins_default>;
+	status = "okay";
+};
+
+&main_uart1 {
+	u-boot,dm-spl;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&sdhci1 {
+	/delete-property/ power-domains;
+	clocks = <&clk_200mhz>;
+	clock-names = "clk_xin";
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+	pinctrl-0 = <&main_mmc1_pins_default>;
+};
+
+#include "k3-am642-sk-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
new file mode 100644
index 0000000000..4ac7f5db91
--- /dev/null
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+	chosen {
+		stdout-path = "serial2:115200n8";
+		tick-timer = &timer1;
+	};
+};
+
+&cbass_main{
+	u-boot,dm-spl;
+	timer1: timer@2400000 {
+		compatible = "ti,omap5430-timer";
+		reg = <0x0 0x2400000 0x0 0x80>;
+		ti,timer-alwon;
+		clock-frequency = <250000000>;
+		u-boot,dm-spl;
+	};
+};
+
+&main_conf {
+	u-boot,dm-spl;
+	chipid@14 {
+		u-boot,dm-spl;
+	};
+};
+
+&main_pmx0 {
+	u-boot,dm-spl;
+	main_i2c0_pins_default: main-i2c0-pins-default {
+		u-boot,dm-spl;
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+		>;
+	};
+};
+
+&main_i2c0 {
+	u-boot,dm-spl;
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_i2c0_pins_default>;
+	clock-frequency = <400000>;
+};
+
+&main_uart0 {
+	u-boot,dm-spl;
+};
+
+&dmss {
+	u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+	u-boot,dm-spl;
+};
+
+&dmsc {
+	u-boot,dm-spl;
+};
+
+&k3_pds {
+	u-boot,dm-spl;
+};
+
+&k3_clks {
+	u-boot,dm-spl;
+};
+
+&k3_reset {
+	u-boot,dm-spl;
+};
+
+&sdhci0 {
+	u-boot,dm-spl;
+};
+
+&sdhci1 {
+	u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+	u-boot,dm-spl;
+};
+
+&cpsw3g {
+	reg = <0x0 0x8000000 0x0 0x200000>,
+	      <0x0 0x43000200 0x0 0x8>;
+	reg-names = "cpsw_nuss", "mac_efuse";
+	/delete-property/ ranges;
+
+	cpsw-phy-sel@04044 {
+		compatible = "ti,am64-phy-gmii-sel";
+		reg = <0x0 0x43004044 0x0 0x8>;
+	};
+};
+
+&cpsw_port2 {
+	status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
new file mode 100644
index 0000000000..df76c6e0b9
--- /dev/null
+++ b/arch/arm/dts/k3-am642-sk.dts
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am642.dtsi"
+
+/ {
+	compatible =  "ti,am642-sk", "ti,am642";
+	model = "Texas Instruments AM642 SK";
+
+	chosen {
+		stdout-path = "serial2:115200n8";
+		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* 2G RAM */
+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secure_ddr: optee@9e800000 {
+			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+			alignment = <0x1000>;
+			no-map;
+		};
+	};
+};
+
+&main_pmx0 {
+	main_mmc1_pins_default: main-mmc1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
+			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
+			AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
+			AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
+			AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
+			AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
+			AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
+			AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
+		>;
+	};
+
+	main_i2c1_pins_default: main-i2c1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
+			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
+		>;
+	};
+
+	mdio1_pins_default: mdio1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+		>;
+	};
+
+	rgmii1_pins_default: rgmii1-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
+			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
+			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
+			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
+			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
+			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
+			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+		>;
+	};
+
+       rgmii2_pins_default: rgmii2-pins-default {
+		pinctrl-single,pins = <
+			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+		>;
+	};
+};
+
+&main_uart1 {
+	/* main_uart1 is reserved for firmware usage */
+	status = "reserved";
+};
+
+&main_uart2 {
+	status = "disabled";
+};
+
+&main_uart3 {
+	status = "disabled";
+};
+
+&main_uart4 {
+	status = "disabled";
+};
+
+&main_uart5 {
+	status = "disabled";
+};
+
+&main_uart6 {
+	status = "disabled";
+};
+
+&sdhci1 {
+	/* SD/MMC */
+	pinctrl-names = "default";
+	bus-width = <4>;
+	pinctrl-0 = <&main_mmc1_pins_default>;
+	ti,driver-strength-ohm = <50>;
+	disable-wp;
+};
+
+&cpsw3g {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio1_pins_default
+		     &rgmii1_pins_default
+		     &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw3g_mdio {
+	cpsw3g_phy0: ethernet-phy@0 {
+		reg = <0>;
+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+	};
+};
diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi
new file mode 100644
index 0000000000..e2b397c884
--- /dev/null
+++ b/arch/arm/dts/k3-am642.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC family in Dual core configuration
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am64.dtsi"
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0: cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x001>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&L2_0>;
+		};
+	};
+
+	L2_0: l2-cache0 {
+		compatible = "cache";
+		cache-level = <2>;
+		cache-size = <0x40000>;
+		cache-line-size = <64>;
+		cache-sets = <512>;
+	};
+};
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index c7d186149b..bfbce44bfa 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -10,6 +10,9 @@ config SOC_K3_AM6
 config SOC_K3_J721E
 	bool "TI's K3 based J721E SoC Family Support"
 
+config SOC_K3_AM642
+	bool "TI's K3 based AM642 SoC Family Support"
+
 endchoice
 
 config SYS_SOC
@@ -19,16 +22,18 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
 	hex
 	default 0x80000 if SOC_K3_AM6
 	default 0x100000 if SOC_K3_J721E
+	default 0x1c0000 if SOC_K3_AM642
 	help
-	  Describes the total size of the MCU MSRAM. This doesn't
-	  specify the total size of SPL as ROM can use some part
-	  of this RAM. Once ROM gives control to SPL then this
-	  complete size can be usable.
+	  Describes the total size of the MCU or OCMC MSRAM present on
+	  the SoC in use. This doesn't specify the total size of SPL as
+	  ROM can use some part of this RAM. Once ROM gives control to
+	  SPL then this complete size can be usable.
 
 config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 	hex
 	default 0x58000 if SOC_K3_AM6
 	default 0xc0000 if SOC_K3_J721E
+	default 0x180000 if SOC_K3_AM642
 	help
 	  Describes the maximum size of the image that ROM can download
 	  from any boot media.
@@ -51,6 +56,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
 	hex
 	default 0x41c7fbfc if SOC_K3_AM6
 	default 0x41cffbfc if SOC_K3_J721E
+	default 0x701bebfc if SOC_K3_AM642
 	help
 	  Address at which ROM stores the value which determines if SPL
 	  is booted up by primary boot media or secondary boot media.
@@ -142,5 +148,6 @@ config SYS_K3_SPL_ATF
 	  after SPL from R5.
 
 source "board/ti/am65x/Kconfig"
+source "board/ti/am64x/Kconfig"
 source "board/ti/j721e/Kconfig"
 endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 7572f56925..890d1498d0 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -5,6 +5,7 @@
 
 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
 obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
new file mode 100644
index 0000000000..885f181d58
--- /dev/null
+++ b/arch/arm/mach-k3/am642_init.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM642: SoC specific initialization
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ *	Dave Gerlach <d-gerlach@ti.com>
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <mmc.h>
+#include <dm/root.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+static void ctrl_mmr_unlock(void)
+{
+	/* Unlock all PADCFG_MMR1 module registers */
+	mmr_unlock(PADCFG_MMR1_BASE, 1);
+
+	/* Unlock all CTRL_MMR0 module registers */
+	mmr_unlock(CTRL_MMR0_BASE, 0);
+	mmr_unlock(CTRL_MMR0_BASE, 1);
+	mmr_unlock(CTRL_MMR0_BASE, 2);
+	mmr_unlock(CTRL_MMR0_BASE, 3);
+	mmr_unlock(CTRL_MMR0_BASE, 5);
+	mmr_unlock(CTRL_MMR0_BASE, 6);
+}
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(.data);
+
+static void store_boot_info_from_rom(void)
+{
+	bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+	memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
+	       sizeof(struct rom_extended_boot_data));
+}
+
+#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
+void k3_mmc_stop_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc->saved_clock = mmc->clock;
+		mmc_set_clock(mmc, 0, true);
+	}
+}
+
+void k3_mmc_restart_clock(void)
+{
+	if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+		struct mmc *mmc = find_mmc_device(0);
+
+		if (!mmc)
+			return;
+
+		mmc_set_clock(mmc, mmc->saved_clock, false);
+	}
+}
+#else
+void k3_mmc_stop_clock(void) {}
+void k3_mmc_restart_clock(void) {}
+#endif
+
+#ifdef CONFIG_SPL_OF_LIST
+void do_dt_magic(void)
+{
+	int ret, rescan;
+
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+		do_board_detect();
+
+	/*
+	 * Board detection has been done.
+	 * Let us see if another dtb wouldn't be a better match
+	 * for our board
+	 */
+	if (IS_ENABLED(CONFIG_CPU_V7R)) {
+		ret = fdtdec_resetup(&rescan);
+		if (!ret && rescan) {
+			dm_uninit();
+			dm_init_and_scan(true);
+		}
+	}
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_K3_LOAD_SYSFW)
+	struct udevice *dev;
+	int ret;
+#endif
+
+#if defined(CONFIG_CPU_V7R)
+	setup_k3_mpu_regions();
+#endif
+
+	/*
+	 * Cannot delay this further as there is a chance that
+	 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+	 */
+	store_boot_info_from_rom();
+
+	ctrl_mmr_unlock();
+
+	/* Init DM early */
+	spl_early_init();
+
+	preloader_console_init();
+
+	do_dt_magic();
+
+#if defined(CONFIG_K3_LOAD_SYSFW)
+	/*
+	 * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
+	 * regardless of the result of pinctrl. Do this without probing the
+	 * device, but instead by searching the device that would request the
+	 * given sequence number if probed. The UART will be used by the system
+	 * firmware (SYSFW) image for various purposes and SYSFW depends on us
+	 * to initialize its pin settings.
+	 */
+	ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
+	if (!ret)
+		pinctrl_select_state(dev, "default");
+
+	/*
+	 * Load, start up, and configure system controller firmware.
+	 * This will determine whether or not ROM has already loaded
+	 * system firmware and if so, will only perform needed config
+	 * and not attempt to load firmware again.
+	 */
+	k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
+			k3_mmc_restart_clock);
+#endif
+
+	/* Output System Firmware version info */
+	k3_sysfw_print_ver();
+
+#if defined(CONFIG_K3_AM64_DDRSS)
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret)
+		panic("DRAM init failed: %d\n", ret);
+#endif
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_EMMCBOOT;
+
+	case BOOT_DEVICE_MMC2:
+		return MMCSD_MODE_FS;
+
+	default:
+		return MMCSD_MODE_RAW;
+	}
+}
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+	u32 bkup_bootmode =
+	    (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+	    MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+	u32 bkup_bootmode_cfg =
+	    (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+	    MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+	switch (bkup_bootmode) {
+	case BACKUP_BOOT_DEVICE_UART:
+		return BOOT_DEVICE_UART;
+
+	case BACKUP_BOOT_DEVICE_USB:
+		return BOOT_DEVICE_USB;
+
+	case BACKUP_BOOT_DEVICE_ETHERNET:
+		return BOOT_DEVICE_ETHERNET;
+
+	case BACKUP_BOOT_DEVICE_MMC:
+		if (bkup_bootmode_cfg)
+			return BOOT_DEVICE_MMC2;
+		return BOOT_DEVICE_MMC1;
+
+	case BACKUP_BOOT_DEVICE_SPI:
+		return BOOT_DEVICE_SPI;
+
+	case BACKUP_BOOT_DEVICE_I2C:
+		return BOOT_DEVICE_I2C;
+	};
+
+	return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat)
+{
+	u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+	    MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+	u32 bootmode_cfg =
+	    (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+	    MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+	switch (bootmode) {
+	case BOOT_DEVICE_OSPI:
+		fallthrough;
+	case BOOT_DEVICE_QSPI:
+		fallthrough;
+	case BOOT_DEVICE_XSPI:
+		fallthrough;
+	case BOOT_DEVICE_SPI:
+		return BOOT_DEVICE_SPI;
+
+	case BOOT_DEVICE_ETHERNET_RGMII:
+		fallthrough;
+	case BOOT_DEVICE_ETHERNET_RMII:
+		return BOOT_DEVICE_ETHERNET;
+
+	case BOOT_DEVICE_EMMC:
+		return BOOT_DEVICE_MMC1;
+
+	case BOOT_DEVICE_MMC:
+		if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+		     MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+			return BOOT_DEVICE_MMC2;
+		return BOOT_DEVICE_MMC1;
+
+	case BOOT_DEVICE_NOBOOT:
+		return BOOT_DEVICE_RAM;
+	}
+
+	return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+	if (bootindex == K3_PRIMARY_BOOTMODE)
+		return __get_primary_bootmedia(devstat);
+	else
+		return __get_backup_bootmedia(devstat);
+}
+#endif
+
+#if defined(CONFIG_SYS_K3_SPL_ATF)
+
+#define AM64X_DEV_RTI8			127
+#define AM64X_DEV_RTI9			128
+#define AM64X_DEV_R5FSS0_CORE0		121
+#define AM64X_DEV_R5FSS0_CORE1		122
+
+void release_resources_for_core_shutdown(void)
+{
+	struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+	struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+	struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+	int ret;
+	u32 i;
+
+	const u32 put_device_ids[] = {
+		AM64X_DEV_RTI9,
+		AM64X_DEV_RTI8,
+	};
+
+	/* Iterate through list of devices to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+		u32 id = put_device_ids[i];
+
+		ret = dev_ops->put_device(ti_sci, id);
+		if (ret)
+			panic("Failed to put device %u (%d)\n", id, ret);
+	}
+
+	const u32 put_core_ids[] = {
+		AM64X_DEV_R5FSS0_CORE1,
+		AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
+	};
+
+	/* Iterate through list of cores to put (shutdown) */
+	for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+		u32 id = put_core_ids[i];
+
+		/*
+		 * Queue up the core shutdown request. Note that this call
+		 * needs to be followed up by an actual invocation of an WFE
+		 * or WFI CPU instruction.
+		 */
+		ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+		if (ret)
+			panic("Failed sending core %u shutdown message (%d)\n",
+			      id, ret);
+	}
+}
+#endif
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index a0da3df593..94242e1e5c 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -180,3 +180,44 @@ struct mm_region *mem_map = j7200_mem_map;
 #endif /* CONFIG_TARGET_J7200_A72_EVM */
 
 #endif /* CONFIG_SOC_K3_J721E */
+
+#ifdef CONFIG_SOC_K3_AM642
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 3)
+
+/* ToDo: Add 64bit IO */
+struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x880000000UL,
+		.phys = 0x880000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x500000000UL,
+		.phys = 0x500000000UL,
+		.size = 0x400000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = am64_mem_map;
+#endif /* CONFIG_SOC_K3_AM642 */
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
new file mode 100644
index 0000000000..c368aa7e6b
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM64 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM64_HARDWARE_H
+#define __ASM_ARCH_AM64_HARDWARE_H
+
+#include <config.h>
+
+#define CTRL_MMR0_BASE					0x43000000
+#define CTRLMMR_MAIN_DEVSTAT				(CTRL_MMR0_BASE + 0x30)
+
+#define PADCFG_MMR1_BASE				0xf0000
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK		0x00000078
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT		3
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK		0x00000380
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT		7
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK		0x00001c00
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT		10
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK		0x00002000
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT		13
+
+/* After the cfg mask and shifts have been applied */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT		2
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK		0x04
+
+/*
+ * The CTRL_MMR and PADCFG_MMR memory space is divided into several
+ * equally-spaced partitions, so defining the partition size allows us to
+ * determine register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE			0x4000
+
+/*
+ * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0				0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL			0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK		BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT		0
+#define CTRLMMR_LOCK_KICK1				0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL			0xd172bc5a
+
+#define ROM_ENTENDED_BOOT_DATA_INFO			0x701beb00
+
+/* Use Last 1K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START		0x701bfc00
+
+#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h
new file mode 100644
index 0000000000..36826cfc4e
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ */
+#ifndef _ASM_ARCH_AM64_SPL_H_
+#define _ASM_ARCH_AM64_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM			0x00
+#define BOOT_DEVICE_OSPI		0x01
+#define BOOT_DEVICE_QSPI		0x02
+#define BOOT_DEVICE_SPI			0x03
+#define BOOT_DEVICE_ETHERNET		0x04
+#define BOOT_DEVICE_ETHERNET_RGMII	0x04
+#define BOOT_DEVICE_ETHERNET_RMII	0x05
+#define BOOT_DEVICE_I2C			0x06
+#define BOOT_DEVICE_UART		0x07
+#define BOOT_DEVICE_MMC			0x08
+#define BOOT_DEVICE_EMMC		0x09
+
+#define BOOT_DEVICE_USB			0x0A
+#define BOOT_DEVICE_GPMC_NOR		0x0C
+#define BOOT_DEVICE_PCIE		0x0D
+#define BOOT_DEVICE_XSPI		0x0E
+
+#define BOOT_DEVICE_NOBOOT		0x0F
+
+#define BOOT_DEVICE_MMC2		0x08
+#define BOOT_DEVICE_MMC1		0x09
+/* INVALID */
+#define BOOT_DEVICE_MMC2_2		0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_USB		0x01
+#define BACKUP_BOOT_DEVICE_UART		0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET	0x04
+#define BACKUP_BOOT_DEVICE_MMC		0x05
+#define BACKUP_BOOT_DEVICE_SPI		0x06
+#define BACKUP_BOOT_DEVICE_I2C		0x07
+
+#define K3_PRIMARY_BOOTMODE		0x0
+
+#endif
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 02b3df0e1b..8725e7d51a 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -14,6 +14,10 @@
 #include "j721e_hardware.h"
 #endif
 
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_hardware.h"
+#endif
+
 /* Assuming these addresses and definitions stay common across K3 devices */
 #define CTRLMMR_WKUP_JTAG_ID	0x43000014
 #define JTAG_ID_VARIANT_SHIFT	28
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index a26c8ecdd5..ef1c3fb8ca 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -13,4 +13,8 @@
 #ifdef CONFIG_SOC_K3_J721E
 #include "j721e_spl.h"
 #endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_spl.h"
+#endif
 #endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index fe26ced31d..5ca3bc502a 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -45,7 +45,6 @@
 		fdt-dummy1 = "/translation-test@8000/dev@1,100";
 		fdt-dummy2 = "/translation-test@8000/dev@2,200";
 		fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
-		fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
 		usb0 = &usb_0;
 		usb1 = &usb_1;
 		usb2 = &usb_2;
@@ -1270,7 +1269,6 @@
 			  1 0x100 0x9000 0x1000
 			  2 0x200 0xA000 0x1000
 			  3 0x300 0xB000 0x1000
-			  4 0x400 0xC000 0x1000
 			 >;
 
 		dma-ranges = <0 0x000 0x10000000 0x1000
@@ -1307,25 +1305,6 @@
 				reg = <0x42>;
 			};
 		};
-
-		xlatebus@4,400 {
-			compatible = "sandbox,zero-size-cells-bus";
-			reg = <4 0x400 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0 4 0x400 0x1000>;
-
-			devs {
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				dev@19 {
-					compatible = "denx,u-boot-fdt-dummy";
-					reg = <0x19>;
-				};
-			};
-		};
-
 	};
 
 	osd {
diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig
new file mode 100644
index 0000000000..d4ec759d7f
--- /dev/null
+++ b/board/ti/am64x/Kconfig
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+
+choice
+	prompt "K3 AM64 based boards"
+	optional
+
+config TARGET_AM642_A53_EVM
+	bool "TI K3 based AM642 EVM running on A53"
+	select ARM64
+	select SOC_K3_AM642
+	imply BOARD
+	imply SPL_BOARD
+	imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM642_R5_EVM
+	bool "TI K3 based AM642 EVM running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select SOC_K3_AM642
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	imply SYS_K3_SPL_ATF
+	imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_AM642_A53_EVM
+
+config SYS_BOARD
+       default "am64x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am64x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM642_R5_EVM
+
+config SYS_BOARD
+       default "am64x"
+
+config SYS_VENDOR
+       default "ti"
+
+config SYS_CONFIG_NAME
+       default "am64x_evm"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/am64x/MAINTAINERS b/board/ti/am64x/MAINTAINERS
new file mode 100644
index 0000000000..d384a330df
--- /dev/null
+++ b/board/ti/am64x/MAINTAINERS
@@ -0,0 +1,8 @@
+AM64x BOARD
+M:	Dave Gerlach <d-gerlach@ti.com>
+M:	Lokesh Vutla <lokeshvutla@ti.com>
+S:	Maintained
+F:	board/ti/am64x/
+F:	include/configs/am64x_evm.h
+F:	configs/am64x_evm_r5_defconfig
+F:	configs/am64x_evm_a53_defconfig
diff --git a/board/ti/am64x/Makefile b/board/ti/am64x/Makefile
new file mode 100644
index 0000000000..8b98e6f5fd
--- /dev/null
+++ b/board/ti/am64x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+#	Keerthy <j-keerthy@ti.com>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y	+= evm.o
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
new file mode 100644
index 0000000000..35cd9e027c
--- /dev/null
+++ b/board/ti/am64x/evm.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM642 EVM
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+
+#include "../common/board_detect.h"
+
+#define board_is_am64x_gpevm()	board_ti_k3_is("AM64-GPEVM")
+#define board_is_am64x_skevm()	board_ti_k3_is("AM64-SKEVM")
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = 0x80000000;
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	/* Bank 0 declares the memory available in the DDR low region */
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = 0x80000000;
+	gd->ram_size = 0x80000000;
+
+	return 0;
+}
+
+#if defined(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+	bool eeprom_read = board_ti_was_eeprom_read();
+
+	if (!eeprom_read || board_is_am64x_gpevm()) {
+		if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm"))
+			return 0;
+	} else if (board_is_am64x_skevm()) {
+		if (!strcmp(name, "k3-am642-r5-sk") || !strcmp(name, "k3-am642-sk"))
+			return 0;
+	}
+
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+	int ret;
+
+	ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+					 CONFIG_EEPROM_CHIP_ADDRESS);
+	if (ret) {
+		printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+			CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+						 CONFIG_EEPROM_CHIP_ADDRESS + 1);
+		if (ret)
+			pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+			       CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+	}
+
+	return ret;
+}
+
+int checkboard(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+	if (!do_board_detect())
+		printf("Board: %s rev %s\n", ep->name, ep->version);
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static void setup_board_eeprom_env(void)
+{
+	char *name = "am64x_gpevm";
+
+	if (do_board_detect())
+		goto invalid_eeprom;
+
+	if (board_is_am64x_gpevm())
+		name = "am64x_gpevm";
+	else if (board_is_am64x_skevm())
+		name = "am64x_skevm";
+	else
+		printf("Unidentified board claims %s in eeprom header\n",
+		       board_ti_get_name());
+
+invalid_eeprom:
+	set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+	unsigned long board_serial;
+	char *endp;
+	char serial_string[17] = { 0 };
+
+	if (env_get("serial#"))
+		return;
+
+	board_serial = simple_strtoul(ep->serial, &endp, 16);
+	if (*endp != '\0') {
+		pr_err("Error: Can't set serial# to %s\n", ep->serial);
+		return;
+	}
+
+	snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+	env_set("serial#", serial_string);
+}
+#endif
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+	if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+		struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+		setup_board_eeprom_env();
+		setup_serial();
+		/*
+		 * The first MAC address for ethernet a.k.a. ethernet0 comes from
+		 * efuse populated via the am654 gigabit eth switch subsystem driver.
+		 * All the other ones are populated via EEPROM, hence continue with
+		 * an index of 1.
+		 */
+		board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
+	}
+
+	return 0;
+}
+#endif
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 2cbe2b2481..c28752a658 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -23,7 +23,7 @@ config TARGET_J721E_R5_EVM
 	select K3_LOAD_SYSFW
 	select RAM
 	select SPL_RAM
-	select K3_J721E_DDRSS
+	select K3_DDRSS
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
@@ -43,7 +43,7 @@ config TARGET_J7200_R5_EVM
 	select K3_LOAD_SYSFW
 	select RAM
 	select SPL_RAM
-	select K3_J721E_DDRSS
+	select K3_DDRSS
 	imply SYS_K3_SPL_ATF
 	imply TI_I2C_BOARD_DETECT
 
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 7eb5ba3bb2..695d8e134a 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -20,8 +20,6 @@
 #include <exports.h>
 #include <fdtdec.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /**
  * fdt_getprop_u32_default_node - Return a node's property or a default
  *
@@ -1001,8 +999,8 @@ void fdt_del_node_and_alias(void *blob, const char *alias)
 /* Max address size we deal with */
 #define OF_MAX_ADDR_CELLS	4
 #define OF_BAD_ADDR	FDT_ADDR_T_NONE
-#define OF_CHECK_COUNTS(na, ns) (((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) && \
-			 ((ns) > 0 || gd_size_cells_0()))
+#define OF_CHECK_COUNTS(na, ns)	((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
+			(ns) > 0)
 
 /* Debug utility */
 #ifdef DEBUG
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
new file mode 100644
index 0000000000..0e942e36b4
--- /dev/null
+++ b/configs/am64x_evm_a53_defconfig
@@ -0,0 +1,104 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM642=y
+CONFIG_TARGET_AM642_A53_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_TIME=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-am642-evm k3-am642-sk"
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
new file mode 100644
index 0000000000..31d2238320
--- /dev/null
+++ b/configs/am64x_evm_r5_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SOC_K3_AM642=y
+CONFIG_TARGET_AM642_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x70020000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x190000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_GPIO=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
index 873a0e7ae7..c4cf26eaa4 100644
--- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
+++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
@@ -9,7 +9,8 @@ DDRSS device node:
 ==================
 Required properties:
 --------------------
-- compatible:		Shall be: "ti,j721e-ddrss"
+- compatible:		Shall be: "ti,j721e-ddrss" for j721e, j7200
+				  "ti,am64-ddrss" for am642
 - reg-names 		cfg - Map the controller configuration region
 			ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
 - reg:			Contains the register map per reg-names.
diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c
index 90b4cc69ef..916d308034 100644
--- a/drivers/clk/ti/clk-am3-dpll.c
+++ b/drivers/clk/ti/clk-am3-dpll.c
@@ -17,15 +17,16 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
+#include "clk.h"
 
 struct clk_ti_am3_dpll_drv_data {
 	ulong max_rate;
 };
 
 struct clk_ti_am3_dpll_priv {
-	fdt_addr_t clkmode_reg;
-	fdt_addr_t idlest_reg;
-	fdt_addr_t clksel_reg;
+	struct clk_ti_reg clkmode_reg;
+	struct clk_ti_reg idlest_reg;
+	struct clk_ti_reg clksel_reg;
 	struct clk clk_bypass;
 	struct clk clk_ref;
 	u16 last_rounded_mult;
@@ -75,6 +76,37 @@ static ulong clk_ti_am3_dpll_round_rate(struct clk *clk, ulong rate)
 	return ret;
 }
 
+static void clk_ti_am3_dpll_clken(struct clk_ti_am3_dpll_priv *priv,
+				  u8 clken_bits)
+{
+	u32 v;
+
+	v = clk_ti_readl(&priv->clkmode_reg);
+	v &= ~CM_CLKMODE_DPLL_DPLL_EN_MASK;
+	v |= clken_bits << CM_CLKMODE_DPLL_EN_SHIFT;
+	clk_ti_writel(v, &priv->clkmode_reg);
+}
+
+static int clk_ti_am3_dpll_state(struct clk *clk, u8 state)
+{
+	struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+	u32 i = 0, v;
+
+	do {
+		v = clk_ti_readl(&priv->idlest_reg) & ST_DPLL_CLK_MASK;
+		if (v == state) {
+			dev_dbg(clk->dev, "transition to '%s' in %d loops\n",
+				state ? "locked" : "bypassed", i);
+			return 1;
+		}
+
+	} while (++i < LDELAY);
+
+	dev_err(clk->dev, "failed transition to '%s'\n",
+		state ? "locked" : "bypassed");
+	return 0;
+}
+
 static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
 {
 	struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
@@ -85,16 +117,13 @@ static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
 	if (IS_ERR_VALUE(round_rate))
 		return round_rate;
 
-	v = readl(priv->clksel_reg);
+	v = clk_ti_readl(&priv->clksel_reg);
 
 	/* enter bypass mode */
-	clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
-			DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+	clk_ti_am3_dpll_clken(priv, DPLL_EN_MN_BYPASS);
 
 	/* wait for bypass mode */
-	if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
-			   (void *)priv->idlest_reg, LDELAY))
-		dev_err(clk->dev, "failed bypassing dpll\n");
+	clk_ti_am3_dpll_state(clk, 0);
 
 	/* set M & N */
 	v &= ~CM_CLKSEL_DPLL_M_MASK;
@@ -105,18 +134,14 @@ static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
 	v |= ((priv->last_rounded_div - 1) << CM_CLKSEL_DPLL_N_SHIFT) &
 		CM_CLKSEL_DPLL_N_MASK;
 
-	writel(v, priv->clksel_reg);
+	clk_ti_writel(v, &priv->clksel_reg);
 
 	/* lock dpll */
-	clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
-			DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+	clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
 
 	/* wait till the dpll locks */
-	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
-			   (void *)priv->idlest_reg, LDELAY)) {
-		dev_err(clk->dev, "failed locking dpll\n");
+	if (!clk_ti_am3_dpll_state(clk, ST_DPLL_CLK_MASK))
 		hang();
-	}
 
 	return round_rate;
 }
@@ -128,7 +153,7 @@ static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
 	u32 m, n, v;
 
 	/* Return bypass rate if DPLL is bypassed */
-	v = readl(priv->clkmode_reg);
+	v = clk_ti_readl(&priv->clkmode_reg);
 	v &= CM_CLKMODE_DPLL_EN_MASK;
 	v >>= CM_CLKMODE_DPLL_EN_SHIFT;
 
@@ -141,7 +166,7 @@ static ulong clk_ti_am3_dpll_get_rate(struct clk *clk)
 		return rate;
 	}
 
-	v = readl(priv->clksel_reg);
+	v = clk_ti_readl(&priv->clksel_reg);
 	m = v & CM_CLKSEL_DPLL_M_MASK;
 	m >>= CM_CLKSEL_DPLL_M_SHIFT;
 	n = v & CM_CLKSEL_DPLL_N_MASK;
@@ -204,33 +229,28 @@ static int clk_ti_am3_dpll_of_to_plat(struct udevice *dev)
 	struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
 	struct clk_ti_am3_dpll_drv_data *data =
 		(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+	int err;
 
 	priv->max_rate = data->max_rate;
 
-	priv->clkmode_reg = dev_read_addr_index(dev, 0);
-	if (priv->clkmode_reg == FDT_ADDR_T_NONE) {
-		dev_err(dev, "failed to get clkmode register\n");
-		return -EINVAL;
+	err = clk_ti_get_reg_addr(dev, 0, &priv->clkmode_reg);
+	if (err) {
+		dev_err(dev, "failed to get clkmode register address\n");
+		return err;
 	}
 
-	dev_dbg(dev, "clkmode_reg=0x%08lx\n", priv->clkmode_reg);
-
-	priv->idlest_reg = dev_read_addr_index(dev, 1);
-	if (priv->idlest_reg == FDT_ADDR_T_NONE) {
+	err = clk_ti_get_reg_addr(dev, 1, &priv->idlest_reg);
+	if (err) {
 		dev_err(dev, "failed to get idlest register\n");
 		return -EINVAL;
 	}
 
-	dev_dbg(dev, "idlest_reg=0x%08lx\n", priv->idlest_reg);
-
-	priv->clksel_reg = dev_read_addr_index(dev, 2);
-	if (priv->clksel_reg == FDT_ADDR_T_NONE) {
+	err = clk_ti_get_reg_addr(dev, 2, &priv->clksel_reg);
+	if (err) {
 		dev_err(dev, "failed to get clksel register\n");
-		return -EINVAL;
+		return err;
 	}
 
-	dev_dbg(dev, "clksel_reg=0x%08lx\n", priv->clksel_reg);
-
 	return 0;
 }
 
diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c
index 270f2fbdf0..15941f1781 100644
--- a/drivers/clk/ti/clk-divider.c
+++ b/drivers/clk/ti/clk-divider.c
@@ -27,7 +27,7 @@
 
 struct clk_ti_divider_priv {
 	struct clk parent;
-	fdt_addr_t reg;
+	struct clk_ti_reg reg;
 	const struct clk_div_table *table;
 	u8 shift;
 	u8 flags;
@@ -200,11 +200,11 @@ static ulong clk_ti_divider_set_rate(struct clk *clk, ulong rate)
 
 	val = _get_val(priv->table, priv->div_flags, div);
 
-	v = readl(priv->reg);
+	v = clk_ti_readl(&priv->reg);
 	v &= ~(priv->mask << priv->shift);
 	v |= val << priv->shift;
-	writel(v, priv->reg);
-	clk_ti_latch(priv->reg, priv->latch);
+	clk_ti_writel(v, &priv->reg);
+	clk_ti_latch(&priv->reg, priv->latch);
 
 	return clk_get_rate(clk);
 }
@@ -220,7 +220,7 @@ static ulong clk_ti_divider_get_rate(struct clk *clk)
 	if (IS_ERR_VALUE(parent_rate))
 		return parent_rate;
 
-	v = readl(priv->reg) >> priv->shift;
+	v = clk_ti_readl(&priv->reg) >> priv->shift;
 	v &= priv->mask;
 
 	div = _get_div(priv->table, priv->div_flags, v);
@@ -287,10 +287,14 @@ static int clk_ti_divider_of_to_plat(struct udevice *dev)
 	u32 min_div = 0;
 	u32 max_val, max_div = 0;
 	u16 mask;
-	int i, div_num;
+	int i, div_num, err;
+
+	err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
+	if (err) {
+		dev_err(dev, "failed to get register address\n");
+		return err;
+	}
 
-	priv->reg = dev_read_addr(dev);
-	dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
 	priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
 	priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
 	if (dev_read_bool(dev, "ti,index-starts-at-one"))
diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c
index 0ca453c8de..eb15f6243f 100644
--- a/drivers/clk/ti/clk-gate.c
+++ b/drivers/clk/ti/clk-gate.c
@@ -13,9 +13,10 @@
 #include <clk-uclass.h>
 #include <asm/io.h>
 #include <linux/clk-provider.h>
+#include "clk.h"
 
 struct clk_ti_gate_priv {
-	fdt_addr_t reg;
+	struct clk_ti_reg reg;
 	u8 enable_bit;
 	u32 flags;
 	bool invert_enable;
@@ -26,13 +27,13 @@ static int clk_ti_gate_disable(struct clk *clk)
 	struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
 	u32 v;
 
-	v = readl(priv->reg);
+	v = clk_ti_readl(&priv->reg);
 	if (priv->invert_enable)
 		v |= (1 << priv->enable_bit);
 	else
 		v &= ~(1 << priv->enable_bit);
 
-	writel(v, priv->reg);
+	clk_ti_writel(v, &priv->reg);
 	/* No OCP barrier needed here since it is a disable operation */
 	return 0;
 }
@@ -42,29 +43,29 @@ static int clk_ti_gate_enable(struct clk *clk)
 	struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
 	u32 v;
 
-	v = readl(priv->reg);
+	v = clk_ti_readl(&priv->reg);
 	if (priv->invert_enable)
 		v &= ~(1 << priv->enable_bit);
 	else
 		v |= (1 << priv->enable_bit);
 
-	writel(v, priv->reg);
+	clk_ti_writel(v, &priv->reg);
 	/* OCP barrier */
-	v = readl(priv->reg);
+	v = clk_ti_readl(&priv->reg);
 	return 0;
 }
 
 static int clk_ti_gate_of_to_plat(struct udevice *dev)
 {
 	struct clk_ti_gate_priv *priv = dev_get_priv(dev);
+	int err;
 
-	priv->reg = dev_read_addr(dev);
-	if (priv->reg == FDT_ADDR_T_NONE) {
-		dev_err(dev, "failed to get control register\n");
-		return -EINVAL;
+	err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
+	if (err) {
+		dev_err(dev, "failed to get control register address\n");
+		return err;
 	}
 
-	dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
 	priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0);
 	if (dev_read_bool(dev, "ti,set-rate-parent"))
 		priv->flags |= CLK_SET_RATE_PARENT;
diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c
index bb5e49e114..215241b161 100644
--- a/drivers/clk/ti/clk-mux.c
+++ b/drivers/clk/ti/clk-mux.c
@@ -17,7 +17,7 @@
 
 struct clk_ti_mux_priv {
 	struct clk_bulk parents;
-	fdt_addr_t reg;
+	struct clk_ti_reg reg;
 	u32 flags;
 	u32 mux_flags;
 	u32 mask;
@@ -58,7 +58,7 @@ static int clk_ti_mux_get_index(struct clk *clk)
 	struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
 	u32 val;
 
-	val = readl(priv->reg);
+	val = clk_ti_readl(&priv->reg);
 	val >>= priv->shift;
 	val &= priv->mask;
 
@@ -91,13 +91,13 @@ static int clk_ti_mux_set_parent(struct clk *clk, struct clk *parent)
 	if (priv->flags & CLK_MUX_HIWORD_MASK) {
 		val = priv->mask << (priv->shift + 16);
 	} else {
-		val = readl(priv->reg);
+		val = clk_ti_readl(&priv->reg);
 		val &= ~(priv->mask << priv->shift);
 	}
 
 	val |= index << priv->shift;
-	writel(val, priv->reg);
-	clk_ti_latch(priv->reg, priv->latch);
+	clk_ti_writel(val, &priv->reg);
+	clk_ti_latch(&priv->reg, priv->latch);
 	return 0;
 }
 
@@ -215,14 +215,14 @@ static int clk_ti_mux_probe(struct udevice *dev)
 static int clk_ti_mux_of_to_plat(struct udevice *dev)
 {
 	struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+	int err;
 
-	priv->reg = dev_read_addr(dev);
-	if (priv->reg == FDT_ADDR_T_NONE) {
-		dev_err(dev, "failed to get register\n");
-		return -EINVAL;
+	err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
+	if (err) {
+		dev_err(dev, "failed to get register address\n");
+		return err;
 	}
 
-	dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
 	priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
 	priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
 
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index c999df213a..6e5cc90f0f 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -6,21 +6,34 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <fdtdec.h>
+#include <regmap.h>
 #include <asm/io.h>
+#include <dm/device_compat.h>
 #include "clk.h"
 
-static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
+#define CLK_MAX_MEMMAPS           10
+
+struct clk_iomap {
+	struct regmap *regmap;
+	ofnode node;
+};
+
+static unsigned int clk_memmaps_num;
+static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
+
+static void clk_ti_rmw(u32 val, u32 mask, struct clk_ti_reg *reg)
 {
 	u32 v;
 
-	v = readl(reg);
+	v = clk_ti_readl(reg);
 	v &= ~mask;
 	v |= val;
-	writel(v, reg);
+	clk_ti_writel(v, reg);
 }
 
-void clk_ti_latch(fdt_addr_t reg, s8 shift)
+void clk_ti_latch(struct clk_ti_reg *reg, s8 shift)
 {
 	u32 latch;
 
@@ -31,5 +44,77 @@ void clk_ti_latch(fdt_addr_t reg, s8 shift)
 
 	clk_ti_rmw(latch, latch, reg);
 	clk_ti_rmw(0, latch, reg);
-	readl(reg);		/* OCP barrier */
+	clk_ti_readl(reg);		/* OCP barrier */
+}
+
+void clk_ti_writel(u32 val, struct clk_ti_reg *reg)
+{
+	struct clk_iomap *io = &clk_memmaps[reg->index];
+
+	regmap_write(io->regmap, reg->offset, val);
+}
+
+u32 clk_ti_readl(struct clk_ti_reg *reg)
+{
+	struct clk_iomap *io = &clk_memmaps[reg->index];
+	u32 val;
+
+	regmap_read(io->regmap, reg->offset, &val);
+	return val;
+}
+
+static ofnode clk_ti_get_regmap_node(struct udevice *dev)
+{
+	ofnode node = dev_ofnode(dev), parent;
+
+	if (!ofnode_valid(node))
+		return ofnode_null();
+
+	parent = ofnode_get_parent(node);
+	if (strcmp(ofnode_get_name(parent), "clocks"))
+		return ofnode_null();
+
+	return ofnode_get_parent(parent);
+}
+
+int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg)
+{
+	ofnode node;
+	int i, ret;
+	u32 val;
+
+	ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", index, &val);
+	if (ret) {
+		dev_err(dev, "%s must have reg[%d]\n", ofnode_get_name(node),
+			index);
+		return ret;
+	}
+
+	/* parent = ofnode_get_parent(parent); */
+	node = clk_ti_get_regmap_node(dev);
+	if (!ofnode_valid(node)) {
+		dev_err(dev, "failed to get regmap node\n");
+		return -EFAULT;
+	}
+
+	for (i = 0; i < clk_memmaps_num; i++) {
+		if (ofnode_equal(clk_memmaps[i].node, node))
+			break;
+	}
+
+	if (i == clk_memmaps_num) {
+		if (i == CLK_MAX_MEMMAPS)
+			return -ENOMEM;
+
+		ret = regmap_init_mem(node, &clk_memmaps[i].regmap);
+		if (ret)
+			return ret;
+
+		clk_memmaps[i].node = node;
+		clk_memmaps_num++;
+	}
+
+	reg->index = i;
+	reg->offset = val;
+	return 0;
 }
diff --git a/drivers/clk/ti/clk.h b/drivers/clk/ti/clk.h
index 601c3823f7..96859f9dea 100644
--- a/drivers/clk/ti/clk.h
+++ b/drivers/clk/ti/clk.h
@@ -8,6 +8,19 @@
 #ifndef _CLK_TI_H
 #define _CLK_TI_H
 
-void clk_ti_latch(fdt_addr_t reg, s8 shift);
+/**
+ * struct clk_ti_reg - TI register declaration
+ * @offset: offset from the master IP module base address
+ * @index: index of the master IP module
+ */
+struct clk_ti_reg {
+	u16 offset;
+	u8 index;
+};
+
+void clk_ti_latch(struct clk_ti_reg *reg, s8 shift);
+void clk_ti_writel(u32 val, struct clk_ti_reg *reg);
+u32 clk_ti_readl(struct clk_ti_reg *reg);
+int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg);
 
 #endif /* #ifndef _CLK_TI_H */
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index a7c3120860..d618e1637b 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -271,18 +271,6 @@ config OF_TRANSLATE
 	  used for the address translation. This function is faster and
 	  smaller in size than fdt_translate_address().
 
-config OF_TRANSLATE_ZERO_SIZE_CELLS
-	bool "Enable translation for zero size cells"
-	depends on OF_TRANSLATE
-	default n
-	help
-	  The routine used to translate an FDT address into a physical CPU
-	  address was developed by IBM. It considers that crossing any level
-	  with #size-cells = <0> makes translation impossible, even if it is
-	  not the way it was specified.
-	  Enabling this option makes translation possible even in the case
-	  of crossing levels with #size-cells = <0>.
-
 config SPL_OF_TRANSLATE
 	bool "Translate addresses using fdt_translate_address in SPL"
 	depends on SPL_DM && SPL_OF_CONTROL
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 83a50b6a3a..b9874c743d 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -50,7 +50,7 @@ fdt_addr_t devfdt_get_addr_index(const struct udevice *dev, int index)
 
 		reg += index * (na + ns);
 
-		if (ns || gd_size_cells_0()) {
+		if (ns) {
 			/*
 			 * Use the full-fledged translate function for complex
 			 * bus setups.
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index b3e384d2ee..9b77308182 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -18,8 +18,7 @@
 /* Max address size we deal with */
 #define OF_MAX_ADDR_CELLS	4
 #define OF_CHECK_ADDR_COUNT(na)	((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
-#define OF_CHECK_COUNTS(na, ns)	(OF_CHECK_ADDR_COUNT(na) && \
-				 ((ns) > 0 || gd_size_cells_0()))
+#define OF_CHECK_COUNTS(na, ns)	(OF_CHECK_ADDR_COUNT(na) && (ns) > 0)
 
 static struct of_bus *of_match_bus(struct device_node *np);
 
@@ -163,6 +162,11 @@ const __be32 *of_get_address(const struct device_node *dev, int index,
 }
 EXPORT_SYMBOL(of_get_address);
 
+static int of_empty_ranges_quirk(const struct device_node *np)
+{
+	return false;
+}
+
 static int of_translate_one(const struct device_node *parent,
 			    struct of_bus *bus, struct of_bus *pbus,
 			    __be32 *addr, int na, int ns, int pna,
@@ -189,8 +193,11 @@ static int of_translate_one(const struct device_node *parent,
 	 * As far as we know, this damage only exists on Apple machines, so
 	 * This code is only enabled on powerpc. --gcl
 	 */
-
 	ranges = of_get_property(parent, rprop, &rlen);
+	if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
+		debug("no ranges; cannot translate\n");
+		return 1;
+	}
 	if (ranges == NULL || rlen == 0) {
 		offset = of_read_number(addr, na);
 		memset(addr, 0, pna * 4);
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index d50533338e..6c771e364f 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -319,8 +319,7 @@ fdt_addr_t ofnode_get_addr_size_index(ofnode node, int index, fdt_size_t *size)
 
 		ns = of_n_size_cells(ofnode_to_np(node));
 
-		if (IS_ENABLED(CONFIG_OF_TRANSLATE) &&
-		    (ns > 0 || gd_size_cells_0())) {
+		if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) {
 			return of_translate_address(ofnode_to_np(node), prop_val);
 		} else {
 			na = of_n_addr_cells(ofnode_to_np(node));
@@ -703,10 +702,8 @@ fdt_addr_t ofnode_get_addr_size(ofnode node, const char *property,
 		ns = of_n_size_cells(np);
 		*sizep = of_read_number(prop + na, ns);
 
-		if (CONFIG_IS_ENABLED(OF_TRANSLATE) &&
-		    (ns > 0 || gd_size_cells_0())) {
+		if (CONFIG_IS_ENABLED(OF_TRANSLATE) && ns > 0)
 			return of_translate_address(np, prop);
-		}
 		else
 			return of_read_number(prop, na);
 	} else {
diff --git a/drivers/core/root.c b/drivers/core/root.c
index f852d867db..fe0562cd6f 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -164,9 +164,6 @@ int dm_init(bool of_live)
 {
 	int ret;
 
-	if (IS_ENABLED(CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS))
-		gd->dm_flags |= GD_DM_FLG_SIZE_CELLS_0;
-
 	if (gd->dm_root) {
 		dm_warn("Virtual root driver already exists!\n");
 		return -EINVAL;
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 4ea9c626cc..0391cd3d80 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
 k3-psil-data-y += k3-psil.o
 k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
 k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
diff --git a/drivers/dma/ti/k3-psil-am64.c b/drivers/dma/ti/k3-psil-am64.c
new file mode 100644
index 0000000000..15742c3723
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am64.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ *  Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x)					\
+	{							\
+		.thread_id = x,					\
+		.ep_config = {					\
+			.ep_type = PSIL_EP_PDMA_XY,		\
+			.mapped_channel_id = -1,		\
+		},						\
+	}
+
+#define PSIL_PDMA_XY_PKT(x)					\
+	{							\
+		.thread_id = x,					\
+		.ep_config = {					\
+			.ep_type = PSIL_EP_PDMA_XY,		\
+			.mapped_channel_id = -1,		\
+			.pkt_mode = 1,				\
+		},						\
+	}
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt)		\
+	{							\
+		.thread_id = x,					\
+		.ep_config = {					\
+			.ep_type = PSIL_EP_NATIVE,		\
+			.pkt_mode = 1,				\
+			.needs_epib = 1,			\
+			.psd_size = 16,				\
+			.mapped_channel_id = ch,		\
+			.flow_start = flow_base,		\
+			.flow_num = flow_cnt,			\
+			.default_flow_id = flow_base,		\
+		},						\
+	}
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx)	\
+	{							\
+		.thread_id = x,					\
+		.ep_config = {					\
+			.ep_type = PSIL_EP_NATIVE,		\
+			.pkt_mode = 1,				\
+			.needs_epib = 1,			\
+			.psd_size = 64,				\
+			.mapped_channel_id = ch,		\
+			.flow_start = flow_base,		\
+			.flow_num = flow_cnt,			\
+			.default_flow_id = default_flow,	\
+			.notdpkt = tx,				\
+		},						\
+	}
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am64_src_ep_map[] = {
+	/* SAUL */
+	PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
+	PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
+	PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
+	PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
+	/* ICSS_G0 */
+	PSIL_ETHERNET(0x4100, 21, 48, 16),
+	PSIL_ETHERNET(0x4101, 22, 64, 16),
+	PSIL_ETHERNET(0x4102, 23, 80, 16),
+	PSIL_ETHERNET(0x4103, 24, 96, 16),
+	/* ICSS_G1 */
+	PSIL_ETHERNET(0x4200, 25, 112, 16),
+	PSIL_ETHERNET(0x4201, 26, 128, 16),
+	PSIL_ETHERNET(0x4202, 27, 144, 16),
+	PSIL_ETHERNET(0x4203, 28, 160, 16),
+	/* PDMA_MAIN0 - SPI0-3 */
+	PSIL_PDMA_XY_PKT(0x4300),
+	PSIL_PDMA_XY_PKT(0x4301),
+	PSIL_PDMA_XY_PKT(0x4302),
+	PSIL_PDMA_XY_PKT(0x4303),
+	PSIL_PDMA_XY_PKT(0x4304),
+	PSIL_PDMA_XY_PKT(0x4305),
+	PSIL_PDMA_XY_PKT(0x4306),
+	PSIL_PDMA_XY_PKT(0x4307),
+	PSIL_PDMA_XY_PKT(0x4308),
+	PSIL_PDMA_XY_PKT(0x4309),
+	PSIL_PDMA_XY_PKT(0x430a),
+	PSIL_PDMA_XY_PKT(0x430b),
+	PSIL_PDMA_XY_PKT(0x430c),
+	PSIL_PDMA_XY_PKT(0x430d),
+	PSIL_PDMA_XY_PKT(0x430e),
+	PSIL_PDMA_XY_PKT(0x430f),
+	/* PDMA_MAIN0 - USART0-1 */
+	PSIL_PDMA_XY_PKT(0x4310),
+	PSIL_PDMA_XY_PKT(0x4311),
+	/* PDMA_MAIN1 - SPI4 */
+	PSIL_PDMA_XY_PKT(0x4400),
+	PSIL_PDMA_XY_PKT(0x4401),
+	PSIL_PDMA_XY_PKT(0x4402),
+	PSIL_PDMA_XY_PKT(0x4403),
+	/* PDMA_MAIN1 - USART2-6 */
+	PSIL_PDMA_XY_PKT(0x4404),
+	PSIL_PDMA_XY_PKT(0x4405),
+	PSIL_PDMA_XY_PKT(0x4406),
+	PSIL_PDMA_XY_PKT(0x4407),
+	PSIL_PDMA_XY_PKT(0x4408),
+	/* PDMA_MAIN1 - ADCs */
+	PSIL_PDMA_XY_TR(0x440f),
+	PSIL_PDMA_XY_TR(0x4410),
+	/* CPSW2 */
+	PSIL_ETHERNET(0x4500, 16, 16, 16),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am64_dst_ep_map[] = {
+	/* SAUL */
+	PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
+	PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
+	/* ICSS_G0 */
+	PSIL_ETHERNET(0xc100, 26, 96, 1),
+	PSIL_ETHERNET(0xc101, 27, 97, 1),
+	PSIL_ETHERNET(0xc102, 28, 98, 1),
+	PSIL_ETHERNET(0xc103, 29, 99, 1),
+	PSIL_ETHERNET(0xc104, 30, 100, 1),
+	PSIL_ETHERNET(0xc105, 31, 101, 1),
+	PSIL_ETHERNET(0xc106, 32, 102, 1),
+	PSIL_ETHERNET(0xc107, 33, 103, 1),
+	/* ICSS_G1 */
+	PSIL_ETHERNET(0xc200, 34, 104, 1),
+	PSIL_ETHERNET(0xc201, 35, 105, 1),
+	PSIL_ETHERNET(0xc202, 36, 106, 1),
+	PSIL_ETHERNET(0xc203, 37, 107, 1),
+	PSIL_ETHERNET(0xc204, 38, 108, 1),
+	PSIL_ETHERNET(0xc205, 39, 109, 1),
+	PSIL_ETHERNET(0xc206, 40, 110, 1),
+	PSIL_ETHERNET(0xc207, 41, 111, 1),
+	/* CPSW2 */
+	PSIL_ETHERNET(0xc500, 16, 16, 8),
+	PSIL_ETHERNET(0xc501, 17, 24, 8),
+	PSIL_ETHERNET(0xc502, 18, 32, 8),
+	PSIL_ETHERNET(0xc503, 19, 40, 8),
+	PSIL_ETHERNET(0xc504, 20, 48, 8),
+	PSIL_ETHERNET(0xc505, 21, 56, 8),
+	PSIL_ETHERNET(0xc506, 22, 64, 8),
+	PSIL_ETHERNET(0xc507, 23, 72, 8),
+};
+
+struct psil_ep_map am64_ep_map = {
+	.name = "am64",
+	.src = am64_src_ep_map,
+	.src_count = ARRAY_SIZE(am64_src_ep_map),
+	.dst = am64_dst_ep_map,
+	.dst_count = ARRAY_SIZE(am64_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c
index f95d99cfd3..d16c07566b 100644
--- a/drivers/dma/ti/k3-psil-am654.c
+++ b/drivers/dma/ti/k3-psil-am654.c
@@ -44,40 +44,22 @@ static struct psil_ep am654_src_ep_map[] = {
 static struct psil_ep am654_dst_ep_map[] = {
 	/* PRU_ICSSG0 */
 	PSIL_ETHERNET(0xc100),
-	PSIL_ETHERNET(0xc101),
-	PSIL_ETHERNET(0xc102),
-	PSIL_ETHERNET(0xc103),
+	/* PSIL: 0xc101 - 0xc103 unused */
 	PSIL_ETHERNET(0xc104),
-	PSIL_ETHERNET(0xc105),
-	PSIL_ETHERNET(0xc106),
-	PSIL_ETHERNET(0xc107),
+	/* PSIL: 0xc105 - 0xc107 unused */
 	/* PRU_ICSSG1 */
 	PSIL_ETHERNET(0xc200),
-	PSIL_ETHERNET(0xc201),
-	PSIL_ETHERNET(0xc202),
-	PSIL_ETHERNET(0xc203),
+	/* PSIL: 0xc201 - 0xc203 unused */
 	PSIL_ETHERNET(0xc204),
-	PSIL_ETHERNET(0xc205),
-	PSIL_ETHERNET(0xc206),
-	PSIL_ETHERNET(0xc207),
+	/* PSIL: 0xc205 - 0xc207 unused */
 	/* PRU_ICSSG2 */
 	PSIL_ETHERNET(0xc300),
-	PSIL_ETHERNET(0xc301),
-	PSIL_ETHERNET(0xc302),
-	PSIL_ETHERNET(0xc303),
+	/* PSIL: 0xc301 - 0xc303 unused */
 	PSIL_ETHERNET(0xc304),
-	PSIL_ETHERNET(0xc305),
-	PSIL_ETHERNET(0xc306),
-	PSIL_ETHERNET(0xc307),
+	/* PSIL: 0xc305 - 0xc307 unused */
 	/* CPSW0 */
 	PSIL_ETHERNET(0xf000),
-	PSIL_ETHERNET(0xf001),
-	PSIL_ETHERNET(0xf002),
-	PSIL_ETHERNET(0xf003),
-	PSIL_ETHERNET(0xf004),
-	PSIL_ETHERNET(0xf005),
-	PSIL_ETHERNET(0xf006),
-	PSIL_ETHERNET(0xf007),
+	/* PSIL: 0xf001 - 0xf007 unused */
 };
 
 struct psil_ep_map am654_ep_map = {
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index d3a38322b1..02d1c201a9 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -39,5 +39,6 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id);
 /* SoC PSI-L endpoint maps */
 extern struct psil_ep_map am654_ep_map;
 extern struct psil_ep_map j721e_ep_map;
+extern struct psil_ep_map am64_ep_map;
 
 #endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index b5c92b2829..e82f807541 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -20,6 +20,8 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
 			soc_ep_map = &am654_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
 			soc_ep_map = &j721e_ep_map;
+		else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
+			soc_ep_map = &am64_ep_map;
 	}
 
 	if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h
index 53c61b4595..1e0fe06c0a 100644
--- a/drivers/dma/ti/k3-psil.h
+++ b/drivers/dma/ti/k3-psil.h
@@ -50,6 +50,15 @@ enum psil_endpoint_type {
  * @channel_tpl:	Desired throughput level for the channel
  * @pdma_acc32:		ACC32 must be enabled on the PDMA side
  * @pdma_burst:		BURST must be enabled on the PDMA side
+ * @mapped_channel_id:	PKTDMA thread to channel mapping for mapped
+ *			channels. The thread must be serviced by the specified
+ *			channel if mapped_channel_id is >= 0 in case of PKTDMA
+ * @flow_start:		PKTDMA flow range start of mapped channel. Unmapped
+ *			channels use flow_id == chan_id
+ * @flow_num:		PKTDMA flow count of mapped channel. Unmapped
+ *			channels use flow_id == chan_id
+ * @default_flow_id:	PKTDMA default (r)flow index of mapped channel.
+ *			Must be within the flow range of the mapped channel.
  */
 struct psil_endpoint_config {
 	enum psil_endpoint_type ep_type;
@@ -63,5 +72,12 @@ struct psil_endpoint_config {
 	/* PDMA properties, valid for PSIL_EP_PDMA_* */
 	unsigned pdma_acc32:1;
 	unsigned pdma_burst:1;
+
+	/* PKTDMA mapped channel */
+	int mapped_channel_id;
+	/* PKTDMA tflow and rflow ranges for mapped channel */
+	u16 flow_start;
+	u16 flow_num;
+	u16 default_flow_id;
 };
 #endif /* K3_PSIL_H_ */
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f3ec827897..601868d7fc 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -28,6 +28,7 @@
 #include <linux/soc/ti/cppi5.h>
 #include <linux/soc/ti/ti-udma.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/soc/ti/cppi5.h>
 
 #include "k3-udma-hwdef.h"
 #include "k3-psil-priv.h"
@@ -36,15 +37,25 @@
 
 struct udma_chan;
 
+enum k3_dma_type {
+	DMA_TYPE_UDMA = 0,
+	DMA_TYPE_BCDMA,
+	DMA_TYPE_PKTDMA,
+};
+
 enum udma_mmr {
 	MMR_GCFG = 0,
+	MMR_BCHANRT,
 	MMR_RCHANRT,
 	MMR_TCHANRT,
 	MMR_LAST,
 };
 
 static const char * const mmr_names[] = {
-	"gcfg", "rchanrt", "tchanrt"
+	[MMR_GCFG] = "gcfg",
+	[MMR_BCHANRT] = "bchanrt",
+	[MMR_RCHANRT] = "rchanrt",
+	[MMR_TCHANRT] = "tchanrt",
 };
 
 struct udma_tchan {
@@ -53,6 +64,16 @@ struct udma_tchan {
 	int id;
 	struct k3_nav_ring *t_ring; /* Transmit ring */
 	struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
+	int tflow_id; /* applicable only for PKTDMA */
+
+};
+
+#define udma_bchan udma_tchan
+
+struct udma_rflow {
+	int id;
+	struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
+	struct k3_nav_ring *r_ring; /* Receive ring */
 };
 
 struct udma_rchan {
@@ -61,32 +82,45 @@ struct udma_rchan {
 	int id;
 };
 
+struct udma_oes_offsets {
+	/* K3 UDMA Output Event Offset */
+	u32 udma_rchan;
+
+	/* BCDMA Output Event Offsets */
+	u32 bcdma_bchan_data;
+	u32 bcdma_bchan_ring;
+	u32 bcdma_tchan_data;
+	u32 bcdma_tchan_ring;
+	u32 bcdma_rchan_data;
+	u32 bcdma_rchan_ring;
+
+	/* PKTDMA Output Event Offsets */
+	u32 pktdma_tchan_flow;
+	u32 pktdma_rchan_flow;
+};
+
 #define UDMA_FLAG_PDMA_ACC32		BIT(0)
 #define UDMA_FLAG_PDMA_BURST		BIT(1)
 #define UDMA_FLAG_TDTYPE		BIT(2)
 
 struct udma_match_data {
+	enum k3_dma_type type;
 	u32 psil_base;
 	bool enable_memcpy_support;
 	u32 flags;
 	u32 statictr_z_mask;
-	u32 rchan_oes_offset;
+	struct udma_oes_offsets oes;
 
 	u8 tpl_levels;
 	u32 level_start_idx[];
 };
 
-struct udma_rflow {
-	int id;
-
-	struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
-	struct k3_nav_ring *r_ring; /* Receive ring*/
-};
-
 enum udma_rm_range {
-	RM_RANGE_TCHAN = 0,
+	RM_RANGE_BCHAN = 0,
+	RM_RANGE_TCHAN,
 	RM_RANGE_RCHAN,
 	RM_RANGE_RFLOW,
+	RM_RANGE_TFLOW,
 	RM_RANGE_LAST,
 };
 
@@ -111,15 +145,21 @@ struct udma_dev {
 
 	u32 features;
 
+	int bchan_cnt;
 	int tchan_cnt;
 	int echan_cnt;
 	int rchan_cnt;
 	int rflow_cnt;
+	int tflow_cnt;
+	unsigned long *bchan_map;
 	unsigned long *tchan_map;
 	unsigned long *rchan_map;
 	unsigned long *rflow_map;
 	unsigned long *rflow_map_reserved;
+	unsigned long *rflow_in_use;
+	unsigned long *tflow_map;
 
+	struct udma_bchan *bchans;
 	struct udma_tchan *tchans;
 	struct udma_rchan *rchans;
 	struct udma_rflow *rflows;
@@ -143,6 +183,11 @@ struct udma_chan_config {
 	enum psil_endpoint_type ep_type;
 	enum udma_tp_level channel_tpl; /* Channel Throughput Level */
 
+	/* PKTDMA mapped channel */
+	int mapped_channel_id;
+	/* PKTDMA default tflow or rflow for mapped channel */
+	int default_flow_id;
+
 	enum dma_direction dir;
 
 	unsigned int pkt_mode:1; /* TR or packet */
@@ -156,6 +201,7 @@ struct udma_chan {
 	struct udma_dev *ud;
 	char name[20];
 
+	struct udma_bchan *bchan;
 	struct udma_tchan *tchan;
 	struct udma_rchan *rchan;
 	struct udma_rflow *rflow;
@@ -289,6 +335,14 @@ static inline char *udma_get_dir_text(enum dma_direction dir)
 	return "invalid";
 }
 
+static void udma_reset_uchan(struct udma_chan *uc)
+{
+	memset(&uc->config, 0, sizeof(uc->config));
+	uc->config.remote_thread_id = -1;
+	uc->config.mapped_channel_id = -1;
+	uc->config.default_flow_id = -1;
+}
+
 static inline bool udma_is_chan_running(struct udma_chan *uc)
 {
 	u32 trt_ctl = 0;
@@ -371,7 +425,7 @@ static void udma_reset_rings(struct udma_chan *uc)
 	}
 
 	if (ring1)
-		k3_nav_ringacc_ring_reset_dma(ring1, 0);
+		k3_nav_ringacc_ring_reset_dma(ring1, k3_nav_ringacc_ring_get_occ(ring1));
 	if (ring2)
 		k3_nav_ringacc_ring_reset(ring2);
 }
@@ -390,8 +444,10 @@ static void udma_reset_counters(struct udma_chan *uc)
 		val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
 		udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
 
-		val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
-		udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
+		if (!uc->bchan) {
+			val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
+			udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
+		}
 	}
 
 	if (uc->rchan) {
@@ -640,10 +696,32 @@ static int udma_get_tchan(struct udma_chan *uc)
 		return 0;
 	}
 
-	uc->tchan = __udma_reserve_tchan(ud, -1);
+	uc->tchan = __udma_reserve_tchan(ud, uc->config.mapped_channel_id);
 	if (IS_ERR(uc->tchan))
 		return PTR_ERR(uc->tchan);
 
+	if (ud->tflow_cnt) {
+		int tflow_id;
+
+		/* Only PKTDMA have support for tx flows */
+		if (uc->config.default_flow_id >= 0)
+			tflow_id = uc->config.default_flow_id;
+		else
+			tflow_id = uc->tchan->id;
+
+		if (test_bit(tflow_id, ud->tflow_map)) {
+			dev_err(ud->dev, "tflow%d is in use\n", tflow_id);
+			__clear_bit(uc->tchan->id, ud->tchan_map);
+			uc->tchan = NULL;
+			return -ENOENT;
+		}
+
+		uc->tchan->tflow_id = tflow_id;
+		__set_bit(tflow_id, ud->tflow_map);
+	} else {
+		uc->tchan->tflow_id = -1;
+	}
+
 	pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
 
 	return 0;
@@ -659,7 +737,7 @@ static int udma_get_rchan(struct udma_chan *uc)
 		return 0;
 	}
 
-	uc->rchan = __udma_reserve_rchan(ud, -1);
+	uc->rchan = __udma_reserve_rchan(ud, uc->config.mapped_channel_id);
 	if (IS_ERR(uc->rchan))
 		return PTR_ERR(uc->rchan);
 
@@ -751,6 +829,8 @@ static void udma_put_tchan(struct udma_chan *uc)
 		dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
 			uc->tchan->id);
 		__clear_bit(uc->tchan->id, ud->tchan_map);
+		if (uc->tchan->tflow_id >= 0)
+			__clear_bit(uc->tchan->tflow_id, ud->tflow_map);
 		uc->tchan = NULL;
 	}
 }
@@ -855,15 +935,24 @@ static int udma_alloc_rx_resources(struct udma_chan *uc)
 	if (uc->config.dir == DMA_MEM_TO_MEM)
 		return 0;
 
-	ret = udma_get_rflow(uc, uc->rchan->id);
+	if (uc->config.default_flow_id >= 0)
+		ret = udma_get_rflow(uc, uc->config.default_flow_id);
+	else
+		ret = udma_get_rflow(uc, uc->rchan->id);
+
 	if (ret) {
 		ret = -EBUSY;
 		goto err_rflow;
 	}
 
-	fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id;
-
 	rflow = uc->rflow;
+	if (ud->tflow_cnt) {
+		fd_ring_id = ud->tflow_cnt + rflow->id;
+	} else {
+		fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
+			uc->rchan->id;
+	}
+
 	ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
 						&rflow->fd_ring, &rflow->r_ring);
 	if (ret) {
@@ -950,9 +1039,7 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
 
 	req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
 			TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
-			TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
-			TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
-			TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
+			TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID;
 	req.nav_id = tisci_rm->tisci_dev_id;
 	req.index = uc->rchan->id;
 	req.rx_chan_type = mode;
@@ -965,9 +1052,13 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
 							  0) >> 2;
 		req.rxcq_qnum = rx_ring;
 	}
-	if (uc->rflow->id != uc->rchan->id && uc->config.dir != DMA_MEM_TO_MEM) {
+	if (ud->match_data->type == DMA_TYPE_UDMA &&
+	    uc->rflow->id != uc->rchan->id &&
+	    uc->config.dir != DMA_MEM_TO_MEM) {
 		req.flowid_start = uc->rflow->id;
 		req.flowid_cnt = 1;
+		req.valid_params |= TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
+				    TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
 	}
 
 	ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
@@ -1150,12 +1241,58 @@ static void udma_free_chan_resources(struct udma_chan *uc)
 	uc->config.dir = DMA_MEM_TO_MEM;
 }
 
+static const char * const range_names[] = {
+	[RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
+	[RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
+	[RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan",
+	[RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow",
+	[RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
+};
+
 static int udma_get_mmrs(struct udevice *dev)
 {
 	struct udma_dev *ud = dev_get_priv(dev);
+	u32 cap2, cap3, cap4;
 	int i;
 
-	for (i = 0; i < MMR_LAST; i++) {
+	ud->mmrs[MMR_GCFG] = (uint32_t *)devfdt_get_addr_name(dev, mmr_names[MMR_GCFG]);
+	if (!ud->mmrs[MMR_GCFG])
+		return -EINVAL;
+
+	cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
+	cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		ud->rflow_cnt = cap3 & 0x3fff;
+		ud->tchan_cnt = cap2 & 0x1ff;
+		ud->echan_cnt = (cap2 >> 9) & 0x1ff;
+		ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+		break;
+	case DMA_TYPE_BCDMA:
+		ud->bchan_cnt = cap2 & 0x1ff;
+		ud->tchan_cnt = (cap2 >> 9) & 0x1ff;
+		ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+		break;
+	case DMA_TYPE_PKTDMA:
+		cap4 = udma_read(ud->mmrs[MMR_GCFG], 0x30);
+		ud->tchan_cnt = cap2 & 0x1ff;
+		ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+		ud->rflow_cnt = cap3 & 0x3fff;
+		ud->tflow_cnt = cap4 & 0x3fff;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	for (i = 1; i < MMR_LAST; i++) {
+		if (i == MMR_BCHANRT && ud->bchan_cnt == 0)
+			continue;
+		if (i == MMR_TCHANRT && ud->tchan_cnt == 0)
+			continue;
+		if (i == MMR_RCHANRT && ud->rchan_cnt == 0)
+			continue;
+
 		ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
 				mmr_names[i]);
 		if (!ud->mmrs[i])
@@ -1168,23 +1305,10 @@ static int udma_get_mmrs(struct udevice *dev)
 static int udma_setup_resources(struct udma_dev *ud)
 {
 	struct udevice *dev = ud->dev;
-	int ch_count, i;
-	u32 cap2, cap3;
+	int i;
 	struct ti_sci_resource_desc *rm_desc;
 	struct ti_sci_resource *rm_res;
 	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
-	static const char * const range_names[] = { "ti,sci-rm-range-tchan",
-						    "ti,sci-rm-range-rchan",
-						    "ti,sci-rm-range-rflow" };
-
-	cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
-	cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
-
-	ud->rflow_cnt = cap3 & 0x3fff;
-	ud->tchan_cnt = cap2 & 0x1ff;
-	ud->echan_cnt = (cap2 >> 9) & 0x1ff;
-	ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
-	ch_count  = ud->tchan_cnt + ud->rchan_cnt;
 
 	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
 					   sizeof(unsigned long), GFP_KERNEL);
@@ -1215,11 +1339,15 @@ static int udma_setup_resources(struct udma_dev *ud)
 	bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
 
 	/* Get resource ranges from tisci */
-	for (i = 0; i < RM_RANGE_LAST; i++)
+	for (i = 0; i < RM_RANGE_LAST; i++) {
+		if (i == RM_RANGE_BCHAN || i == RM_RANGE_TFLOW)
+			continue;
+
 		tisci_rm->rm_ranges[i] =
 			devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
 						    tisci_rm->tisci_dev_id,
 						    (char *)range_names[i]);
+	}
 
 	/* tchan ranges */
 	rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
@@ -1266,6 +1394,229 @@ static int udma_setup_resources(struct udma_dev *ud)
 		}
 	}
 
+	return 0;
+}
+
+static int bcdma_setup_resources(struct udma_dev *ud)
+{
+	int i;
+	struct udevice *dev = ud->dev;
+	struct ti_sci_resource_desc *rm_desc;
+	struct ti_sci_resource *rm_res;
+	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
+	ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
+					   sizeof(unsigned long), GFP_KERNEL);
+	ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
+				  GFP_KERNEL);
+	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+					   sizeof(unsigned long), GFP_KERNEL);
+	ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+				  GFP_KERNEL);
+	ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+					   sizeof(unsigned long), GFP_KERNEL);
+	ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+				  GFP_KERNEL);
+	/* BCDMA do not really have flows, but the driver expect it */
+	ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
+					sizeof(unsigned long),
+					GFP_KERNEL);
+	ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
+				  GFP_KERNEL);
+
+	if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
+	    !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans ||
+	    !ud->rflows)
+		return -ENOMEM;
+
+	/* Get resource ranges from tisci */
+	for (i = 0; i < RM_RANGE_LAST; i++) {
+		if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW)
+			continue;
+
+		tisci_rm->rm_ranges[i] =
+			devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
+						    tisci_rm->tisci_dev_id,
+						    (char *)range_names[i]);
+	}
+
+	/* bchan ranges */
+	rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN];
+	if (IS_ERR(rm_res)) {
+		bitmap_zero(ud->bchan_map, ud->bchan_cnt);
+	} else {
+		bitmap_fill(ud->bchan_map, ud->bchan_cnt);
+		for (i = 0; i < rm_res->sets; i++) {
+			rm_desc = &rm_res->desc[i];
+			bitmap_clear(ud->bchan_map, rm_desc->start,
+				     rm_desc->num);
+			dev_dbg(dev, "ti-sci-res: bchan: %d:%d\n",
+				rm_desc->start, rm_desc->num);
+		}
+	}
+
+	/* tchan ranges */
+	rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
+	if (IS_ERR(rm_res)) {
+		bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+	} else {
+		bitmap_fill(ud->tchan_map, ud->tchan_cnt);
+		for (i = 0; i < rm_res->sets; i++) {
+			rm_desc = &rm_res->desc[i];
+			bitmap_clear(ud->tchan_map, rm_desc->start,
+				     rm_desc->num);
+			dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
+				rm_desc->start, rm_desc->num);
+		}
+	}
+
+	/* rchan ranges */
+	rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
+	if (IS_ERR(rm_res)) {
+		bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+	} else {
+		bitmap_fill(ud->rchan_map, ud->rchan_cnt);
+		for (i = 0; i < rm_res->sets; i++) {
+			rm_desc = &rm_res->desc[i];
+			bitmap_clear(ud->rchan_map, rm_desc->start,
+				     rm_desc->num);
+			dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
+				rm_desc->start, rm_desc->num);
+		}
+	}
+
+	return 0;
+}
+
+static int pktdma_setup_resources(struct udma_dev *ud)
+{
+	int i;
+	struct udevice *dev = ud->dev;
+	struct ti_sci_resource *rm_res;
+	struct ti_sci_resource_desc *rm_desc;
+	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
+	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+					   sizeof(unsigned long), GFP_KERNEL);
+	ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+				  GFP_KERNEL);
+	ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+					   sizeof(unsigned long), GFP_KERNEL);
+	ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+				  GFP_KERNEL);
+	ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
+					sizeof(unsigned long),
+					GFP_KERNEL);
+	ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
+				  GFP_KERNEL);
+	ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
+					   sizeof(unsigned long), GFP_KERNEL);
+
+	if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
+	    !ud->rchans || !ud->rflows || !ud->rflow_in_use)
+		return -ENOMEM;
+
+	/* Get resource ranges from tisci */
+	for (i = 0; i < RM_RANGE_LAST; i++) {
+		if (i == RM_RANGE_BCHAN)
+			continue;
+
+		tisci_rm->rm_ranges[i] =
+			devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
+						    tisci_rm->tisci_dev_id,
+						    (char *)range_names[i]);
+	}
+
+	/* tchan ranges */
+	rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
+	if (IS_ERR(rm_res)) {
+		bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+	} else {
+		bitmap_fill(ud->tchan_map, ud->tchan_cnt);
+		for (i = 0; i < rm_res->sets; i++) {
+			rm_desc = &rm_res->desc[i];
+			bitmap_clear(ud->tchan_map, rm_desc->start,
+				     rm_desc->num);
+			dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
+				rm_desc->start, rm_desc->num);
+		}
+	}
+
+	/* rchan ranges */
+	rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
+	if (IS_ERR(rm_res)) {
+		bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+	} else {
+		bitmap_fill(ud->rchan_map, ud->rchan_cnt);
+		for (i = 0; i < rm_res->sets; i++) {
+			rm_desc = &rm_res->desc[i];
+			bitmap_clear(ud->rchan_map, rm_desc->start,
+				     rm_desc->num);
+			dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
+				rm_desc->start, rm_desc->num);
+		}
+	}
+
+	/* rflow ranges */
+	rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
+	if (IS_ERR(rm_res)) {
+		/* all rflows are assigned exclusively to Linux */
+		bitmap_zero(ud->rflow_in_use, ud->rflow_cnt);
+	} else {
+		bitmap_fill(ud->rflow_in_use, ud->rflow_cnt);
+		for (i = 0; i < rm_res->sets; i++) {
+			rm_desc = &rm_res->desc[i];
+			bitmap_clear(ud->rflow_in_use, rm_desc->start,
+				     rm_desc->num);
+			dev_dbg(dev, "ti-sci-res: rflow: %d:%d\n",
+				rm_desc->start, rm_desc->num);
+		}
+	}
+
+	/* tflow ranges */
+	rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW];
+	if (IS_ERR(rm_res)) {
+		/* all tflows are assigned exclusively to Linux */
+		bitmap_zero(ud->tflow_map, ud->tflow_cnt);
+	} else {
+		bitmap_fill(ud->tflow_map, ud->tflow_cnt);
+		for (i = 0; i < rm_res->sets; i++) {
+			rm_desc = &rm_res->desc[i];
+			bitmap_clear(ud->tflow_map, rm_desc->start,
+				     rm_desc->num);
+			dev_dbg(dev, "ti-sci-res: tflow: %d:%d\n",
+				rm_desc->start, rm_desc->num);
+		}
+	}
+
+	return 0;
+}
+
+static int setup_resources(struct udma_dev *ud)
+{
+	struct udevice *dev = ud->dev;
+	int ch_count, ret;
+
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		ret = udma_setup_resources(ud);
+		break;
+	case DMA_TYPE_BCDMA:
+		ret = bcdma_setup_resources(ud);
+		break;
+	case DMA_TYPE_PKTDMA:
+		ret = pktdma_setup_resources(ud);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (ret)
+		return ret;
+
+	ch_count  = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
+	if (ud->bchan_cnt)
+		ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
 	ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
 	ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
 	if (!ch_count)
@@ -1276,13 +1627,45 @@ static int udma_setup_resources(struct udma_dev *ud)
 	if (!ud->channels)
 		return -ENOMEM;
 
-	dev_info(dev,
-		 "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n",
-		 ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
-		 ud->rflow_cnt);
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		dev_dbg(dev,
+			"Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
+			ch_count,
+			ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+						      ud->tchan_cnt),
+			ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+						      ud->rchan_cnt),
+			ud->rflow_cnt - bitmap_weight(ud->rflow_map,
+						      ud->rflow_cnt));
+		break;
+	case DMA_TYPE_BCDMA:
+		dev_dbg(dev,
+			"Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
+			ch_count,
+			ud->bchan_cnt - bitmap_weight(ud->bchan_map,
+						      ud->bchan_cnt),
+			ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+						      ud->tchan_cnt),
+			ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+						      ud->rchan_cnt));
+		break;
+	case DMA_TYPE_PKTDMA:
+		dev_dbg(dev,
+			"Channels: %d (tchan: %u, rchan: %u)\n",
+			ch_count,
+			ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+						      ud->tchan_cnt),
+			ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+						      ud->rchan_cnt));
+		break;
+	default:
+		break;
+	}
 
 	return ch_count;
 }
+
 static int udma_probe(struct udevice *dev)
 {
 	struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -1294,17 +1677,11 @@ static int udma_probe(struct udevice *dev)
 	ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
 
 
+	ud->match_data = (void *)dev_get_driver_data(dev);
 	ret = udma_get_mmrs(dev);
 	if (ret)
 		return ret;
 
-	ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
-					   "ti,ringacc", &tmp);
-	ud->ringacc = dev_get_priv(tmp);
-	if (IS_ERR(ud->ringacc))
-		return PTR_ERR(ud->ringacc);
-
-	ud->match_data = (void *)dev_get_driver_data(dev);
 	ud->psil_base = ud->match_data->psil_base;
 
 	ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
@@ -1335,16 +1712,40 @@ static int udma_probe(struct udevice *dev)
 	tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
 	tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
 
+	if (ud->match_data->type == DMA_TYPE_UDMA) {
+		ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
+						   "ti,ringacc", &tmp);
+		ud->ringacc = dev_get_priv(tmp);
+	} else {
+		struct k3_ringacc_init_data ring_init_data;
+
+		ring_init_data.tisci = ud->tisci_rm.tisci;
+		ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
+		if (ud->match_data->type == DMA_TYPE_BCDMA) {
+			ring_init_data.num_rings = ud->bchan_cnt +
+						   ud->tchan_cnt +
+						   ud->rchan_cnt;
+		} else {
+			ring_init_data.num_rings = ud->rflow_cnt +
+						   ud->tflow_cnt;
+		}
+
+		ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
+	}
+	if (IS_ERR(ud->ringacc))
+		return PTR_ERR(ud->ringacc);
+
 	ud->dev = dev;
-	ud->ch_count = udma_setup_resources(ud);
+	ud->ch_count = setup_resources(ud);
 	if (ud->ch_count <= 0)
 		return ud->ch_count;
 
-	dev_info(dev,
-		 "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
-		 ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
-		 tisci_rm->tisci_dev_id);
-	dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
+	for (i = 0; i < ud->bchan_cnt; i++) {
+		struct udma_bchan *bchan = &ud->bchans[i];
+
+		bchan->id = i;
+		bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
+	}
 
 	for (i = 0; i < ud->tchan_cnt; i++) {
 		struct udma_tchan *tchan = &ud->tchans[i];
@@ -1372,15 +1773,19 @@ static int udma_probe(struct udevice *dev)
 		uc->ud = ud;
 		uc->id = i;
 		uc->config.remote_thread_id = -1;
+		uc->bchan = NULL;
 		uc->tchan = NULL;
 		uc->rchan = NULL;
+		uc->config.mapped_channel_id = -1;
+		uc->config.default_flow_id = -1;
 		uc->config.dir = DMA_MEM_TO_MEM;
 		sprintf(uc->name, "UDMA chan%d\n", i);
 		if (!i)
 			uc->in_use = true;
 	}
 
-	pr_debug("UDMA(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+	pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+		 dev->name,
 		 udma_read(ud->mmrs[MMR_GCFG], 0),
 		 udma_read(ud->mmrs[MMR_GCFG], 0x20),
 		 udma_read(ud->mmrs[MMR_GCFG], 0x24),
@@ -1496,6 +1901,379 @@ static int *udma_prep_dma_memcpy(struct udma_chan *uc, dma_addr_t dest,
 	return 0;
 }
 
+#define TISCI_BCDMA_BCHAN_VALID_PARAMS (			\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID)
+
+#define TISCI_BCDMA_TCHAN_VALID_PARAMS (			\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID)
+
+#define TISCI_BCDMA_RCHAN_VALID_PARAMS (			\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID)
+
+#define TISCI_UDMA_TCHAN_VALID_PARAMS (				\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |		\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |		\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |		\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
+
+#define TISCI_UDMA_RCHAN_VALID_PARAMS (				\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |		\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |		\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |		\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID |	\
+	TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
+
+static int bcdma_tisci_m2m_channel_config(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+	const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+	struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
+	struct udma_bchan *bchan = uc->bchan;
+	int ret = 0;
+
+	req_tx.valid_params = TISCI_BCDMA_BCHAN_VALID_PARAMS;
+	req_tx.nav_id = tisci_rm->tisci_dev_id;
+	req_tx.extended_ch_type = TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN;
+	req_tx.index = bchan->id;
+
+	ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
+	if (ret)
+		dev_err(ud->dev, "bchan%d cfg failed %d\n", bchan->id, ret);
+
+	return ret;
+}
+
+static struct udma_bchan *__bcdma_reserve_bchan(struct udma_dev *ud, int id)
+{
+	if (id >= 0) {
+		if (test_bit(id, ud->bchan_map)) {
+			dev_err(ud->dev, "bchan%d is in use\n", id);
+			return ERR_PTR(-ENOENT);
+		}
+	} else {
+		id = find_next_zero_bit(ud->bchan_map, ud->bchan_cnt, 0);
+		if (id == ud->bchan_cnt)
+			return ERR_PTR(-ENOENT);
+	}
+	__set_bit(id, ud->bchan_map);
+	return &ud->bchans[id];
+}
+
+static int bcdma_get_bchan(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+
+	if (uc->bchan) {
+		dev_err(ud->dev, "chan%d: already have bchan%d allocated\n",
+			uc->id, uc->bchan->id);
+		return 0;
+	}
+
+	uc->bchan = __bcdma_reserve_bchan(ud, -1);
+	if (IS_ERR(uc->bchan))
+		return PTR_ERR(uc->bchan);
+
+	uc->tchan = uc->bchan;
+
+	return 0;
+}
+
+static void bcdma_put_bchan(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+
+	if (uc->bchan) {
+		dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id,
+			uc->bchan->id);
+		__clear_bit(uc->bchan->id, ud->bchan_map);
+		uc->bchan = NULL;
+		uc->tchan = NULL;
+	}
+}
+
+static void bcdma_free_bchan_resources(struct udma_chan *uc)
+{
+	if (!uc->bchan)
+		return;
+
+	k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
+	k3_nav_ringacc_ring_free(uc->bchan->t_ring);
+	uc->bchan->tc_ring = NULL;
+	uc->bchan->t_ring = NULL;
+
+	bcdma_put_bchan(uc);
+}
+
+static int bcdma_alloc_bchan_resources(struct udma_chan *uc)
+{
+	struct k3_nav_ring_cfg ring_cfg;
+	struct udma_dev *ud = uc->ud;
+	int ret;
+
+	ret = bcdma_get_bchan(uc);
+	if (ret)
+		return ret;
+
+	ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
+						&uc->bchan->t_ring,
+						&uc->bchan->tc_ring);
+	if (ret) {
+		ret = -EBUSY;
+		goto err_ring;
+	}
+
+	memset(&ring_cfg, 0, sizeof(ring_cfg));
+	ring_cfg.size = 16;
+	ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
+	ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
+
+	ret = k3_nav_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
+	if (ret)
+		goto err_ringcfg;
+
+	return 0;
+
+err_ringcfg:
+	k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
+	uc->bchan->tc_ring = NULL;
+	k3_nav_ringacc_ring_free(uc->bchan->t_ring);
+	uc->bchan->t_ring = NULL;
+err_ring:
+	bcdma_put_bchan(uc);
+
+	return ret;
+}
+
+static int bcdma_tisci_tx_channel_config(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+	const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+	struct udma_tchan *tchan = uc->tchan;
+	struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
+	int ret = 0;
+
+	req_tx.valid_params = TISCI_BCDMA_TCHAN_VALID_PARAMS;
+	req_tx.nav_id = tisci_rm->tisci_dev_id;
+	req_tx.index = tchan->id;
+	req_tx.tx_supr_tdpkt = uc->config.notdpkt;
+	if (uc->config.ep_type == PSIL_EP_PDMA_XY &&
+	    ud->match_data->flags & UDMA_FLAG_TDTYPE) {
+		/* wait for peer to complete the teardown for PDMAs */
+		req_tx.valid_params |=
+				TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID;
+		req_tx.tx_tdtype = 1;
+	}
+
+	ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
+	if (ret)
+		dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
+
+	return ret;
+}
+
+#define pktdma_tisci_tx_channel_config bcdma_tisci_tx_channel_config
+
+static int pktdma_tisci_rx_channel_config(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+	struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+	const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+	struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
+	struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
+	int ret = 0;
+
+	req_rx.valid_params = TISCI_BCDMA_RCHAN_VALID_PARAMS;
+	req_rx.nav_id = tisci_rm->tisci_dev_id;
+	req_rx.index = uc->rchan->id;
+
+	ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
+	if (ret) {
+		dev_err(ud->dev, "rchan%d cfg failed %d\n", uc->rchan->id, ret);
+		return ret;
+	}
+
+	flow_req.valid_params =
+		TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
+		TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
+		TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID;
+
+	flow_req.nav_id = tisci_rm->tisci_dev_id;
+	flow_req.flow_index = uc->rflow->id;
+
+	if (uc->config.needs_epib)
+		flow_req.rx_einfo_present = 1;
+	else
+		flow_req.rx_einfo_present = 0;
+	if (uc->config.psd_size)
+		flow_req.rx_psinfo_present = 1;
+	else
+		flow_req.rx_psinfo_present = 0;
+	flow_req.rx_error_handling = 1;
+
+	ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
+
+	if (ret)
+		dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id,
+			ret);
+
+	return ret;
+}
+
+static int bcdma_alloc_chan_resources(struct udma_chan *uc)
+{
+	int ret;
+
+	uc->config.pkt_mode = false;
+
+	switch (uc->config.dir) {
+	case DMA_MEM_TO_MEM:
+		/* Non synchronized - mem to mem type of transfer */
+		dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
+			uc->id);
+
+		ret = bcdma_alloc_bchan_resources(uc);
+		if (ret)
+			return ret;
+
+		ret = bcdma_tisci_m2m_channel_config(uc);
+		break;
+	default:
+		/* Can not happen */
+		dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+			__func__, uc->id, uc->config.dir);
+		return -EINVAL;
+	}
+
+	/* check if the channel configuration was successful */
+	if (ret)
+		goto err_res_free;
+
+	if (udma_is_chan_running(uc)) {
+		dev_warn(uc->ud->dev, "chan%d: is running!\n", uc->id);
+		udma_stop(uc);
+		if (udma_is_chan_running(uc)) {
+			dev_err(uc->ud->dev, "chan%d: won't stop!\n", uc->id);
+			goto err_res_free;
+		}
+	}
+
+	udma_reset_rings(uc);
+
+	return 0;
+
+err_res_free:
+	bcdma_free_bchan_resources(uc);
+	udma_free_tx_resources(uc);
+	udma_free_rx_resources(uc);
+
+	udma_reset_uchan(uc);
+
+	return ret;
+}
+
+static int pktdma_alloc_chan_resources(struct udma_chan *uc)
+{
+	struct udma_dev *ud = uc->ud;
+	int ret;
+
+	switch (uc->config.dir) {
+	case DMA_MEM_TO_DEV:
+		/* Slave transfer synchronized - mem to dev (TX) trasnfer */
+		dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+			uc->id);
+
+		ret = udma_alloc_tx_resources(uc);
+		if (ret) {
+			uc->config.remote_thread_id = -1;
+			return ret;
+		}
+
+		uc->config.src_thread = ud->psil_base + uc->tchan->id;
+		uc->config.dst_thread = uc->config.remote_thread_id;
+		uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
+
+		ret = pktdma_tisci_tx_channel_config(uc);
+		break;
+	case DMA_DEV_TO_MEM:
+		/* Slave transfer synchronized - dev to mem (RX) trasnfer */
+		dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+			uc->id);
+
+		ret = udma_alloc_rx_resources(uc);
+		if (ret) {
+			uc->config.remote_thread_id = -1;
+			return ret;
+		}
+
+		uc->config.src_thread = uc->config.remote_thread_id;
+		uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
+					K3_PSIL_DST_THREAD_ID_OFFSET;
+
+		ret = pktdma_tisci_rx_channel_config(uc);
+		break;
+	default:
+		/* Can not happen */
+		dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+			__func__, uc->id, uc->config.dir);
+		return -EINVAL;
+	}
+
+	/* check if the channel configuration was successful */
+	if (ret)
+		goto err_res_free;
+
+	/* PSI-L pairing */
+	ret = udma_navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
+	if (ret) {
+		dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
+			uc->config.src_thread, uc->config.dst_thread);
+		goto err_res_free;
+	}
+
+	if (udma_is_chan_running(uc)) {
+		dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+		udma_stop(uc);
+		if (udma_is_chan_running(uc)) {
+			dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+			goto err_res_free;
+		}
+	}
+
+	udma_reset_rings(uc);
+
+	if (uc->tchan)
+		dev_dbg(ud->dev,
+			"chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
+			uc->id, uc->tchan->id, uc->tchan->tflow_id,
+			uc->config.remote_thread_id);
+	else if (uc->rchan)
+		dev_dbg(ud->dev,
+			"chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
+			uc->id, uc->rchan->id, uc->rflow->id,
+			uc->config.remote_thread_id);
+	return 0;
+
+err_res_free:
+	udma_free_tx_resources(uc);
+	udma_free_rx_resources(uc);
+
+	udma_reset_uchan(uc);
+
+	return ret;
+}
+
 static int udma_transfer(struct udevice *dev, int direction,
 			 void *dst, void *src, size_t len)
 {
@@ -1505,7 +2283,16 @@ static int udma_transfer(struct udevice *dev, int direction,
 	dma_addr_t paddr = 0;
 	int ret;
 
-	ret = udma_alloc_chan_resources(uc);
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		ret = udma_alloc_chan_resources(uc);
+		break;
+	case DMA_TYPE_BCDMA:
+		ret = bcdma_alloc_chan_resources(uc);
+		break;
+	default:
+		return -EINVAL;
+	};
 	if (ret)
 		return ret;
 
@@ -1514,7 +2301,17 @@ static int udma_transfer(struct udevice *dev, int direction,
 	udma_poll_completion(uc, &paddr);
 	udma_stop(uc);
 
-	udma_free_chan_resources(uc);
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		udma_free_chan_resources(uc);
+		break;
+	case DMA_TYPE_BCDMA:
+		bcdma_free_bchan_resources(uc);
+		break;
+	default:
+		return -EINVAL;
+	};
+
 	return 0;
 }
 
@@ -1533,7 +2330,19 @@ static int udma_request(struct dma *dma)
 
 	uc = &ud->channels[dma->id];
 	ucc = &uc->config;
-	ret = udma_alloc_chan_resources(uc);
+	switch (ud->match_data->type) {
+	case DMA_TYPE_UDMA:
+		ret = udma_alloc_chan_resources(uc);
+		break;
+	case DMA_TYPE_BCDMA:
+		ret = bcdma_alloc_chan_resources(uc);
+		break;
+	case DMA_TYPE_PKTDMA:
+		ret = pktdma_alloc_chan_resources(uc);
+		break;
+	default:
+		return -EINVAL;
+	}
 	if (ret) {
 		dev_err(dma->dev, "alloc dma res failed %d\n", ret);
 		return -EINVAL;
@@ -1573,7 +2382,14 @@ static int udma_rfree(struct dma *dma)
 
 	if (udma_is_chan_running(uc))
 		udma_stop(uc);
-	udma_free_chan_resources(uc);
+
+	udma_navss_psil_unpair(ud, uc->config.src_thread,
+			       uc->config.dst_thread);
+
+	bcdma_free_bchan_resources(uc);
+	udma_free_tx_resources(uc);
+	udma_free_rx_resources(uc);
+	udma_reset_uchan(uc);
 
 	uc->in_use = false;
 
@@ -1764,6 +2580,15 @@ static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
 	ucc->notdpkt = ep_config->notdpkt;
 	ucc->ep_type = ep_config->ep_type;
 
+	if (ud->match_data->type == DMA_TYPE_PKTDMA &&
+	    ep_config->mapped_channel_id >= 0) {
+		ucc->mapped_channel_id = ep_config->mapped_channel_id;
+		ucc->default_flow_id = ep_config->default_flow_id;
+	} else {
+		ucc->mapped_channel_id = -1;
+		ucc->default_flow_id = -1;
+	}
+
 	ucc->needs_epib = ep_config->needs_epib;
 	ucc->psd_size = ep_config->psd_size;
 	ucc->metadata_size = (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + ucc->psd_size;
@@ -1859,10 +2684,13 @@ static const struct dma_ops udma_ops = {
 };
 
 static struct udma_match_data am654_main_data = {
+	.type = DMA_TYPE_UDMA,
 	.psil_base = 0x1000,
 	.enable_memcpy_support = true,
 	.statictr_z_mask = GENMASK(11, 0),
-	.rchan_oes_offset = 0x200,
+	.oes = {
+		.udma_rchan = 0x200,
+	},
 	.tpl_levels = 2,
 	.level_start_idx = {
 		[0] = 8, /* Normal channels */
@@ -1871,10 +2699,13 @@ static struct udma_match_data am654_main_data = {
 };
 
 static struct udma_match_data am654_mcu_data = {
+	.type = DMA_TYPE_UDMA,
 	.psil_base = 0x6000,
 	.enable_memcpy_support = true,
 	.statictr_z_mask = GENMASK(11, 0),
-	.rchan_oes_offset = 0x200,
+	.oes = {
+		.udma_rchan = 0x200,
+	},
 	.tpl_levels = 2,
 	.level_start_idx = {
 		[0] = 2, /* Normal channels */
@@ -1883,11 +2714,14 @@ static struct udma_match_data am654_mcu_data = {
 };
 
 static struct udma_match_data j721e_main_data = {
+	.type = DMA_TYPE_UDMA,
 	.psil_base = 0x1000,
 	.enable_memcpy_support = true,
 	.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
 	.statictr_z_mask = GENMASK(23, 0),
-	.rchan_oes_offset = 0x400,
+	.oes = {
+		.udma_rchan = 0x400,
+	},
 	.tpl_levels = 3,
 	.level_start_idx = {
 		[0] = 16, /* Normal channels */
@@ -1897,11 +2731,14 @@ static struct udma_match_data j721e_main_data = {
 };
 
 static struct udma_match_data j721e_mcu_data = {
+	.type = DMA_TYPE_UDMA,
 	.psil_base = 0x6000,
 	.enable_memcpy_support = true,
 	.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
 	.statictr_z_mask = GENMASK(23, 0),
-	.rchan_oes_offset = 0x400,
+	.oes = {
+		.udma_rchan = 0x400,
+	},
 	.tpl_levels = 2,
 	.level_start_idx = {
 		[0] = 2, /* Normal channels */
@@ -1909,6 +2746,36 @@ static struct udma_match_data j721e_mcu_data = {
 	},
 };
 
+static struct udma_match_data am64_bcdma_data = {
+	.type = DMA_TYPE_BCDMA,
+	.psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
+	.enable_memcpy_support = true, /* Supported via bchan */
+	.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+	.statictr_z_mask = GENMASK(23, 0),
+	.oes = {
+		.bcdma_bchan_data = 0x2200,
+		.bcdma_bchan_ring = 0x2400,
+		.bcdma_tchan_data = 0x2800,
+		.bcdma_tchan_ring = 0x2a00,
+		.bcdma_rchan_data = 0x2e00,
+		.bcdma_rchan_ring = 0x3000,
+	},
+	/* No throughput levels */
+};
+
+static struct udma_match_data am64_pktdma_data = {
+	.type = DMA_TYPE_PKTDMA,
+	.psil_base = 0x1000,
+	.enable_memcpy_support = false,
+	.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+	.statictr_z_mask = GENMASK(23, 0),
+	.oes = {
+		.pktdma_tchan_flow = 0x1200,
+		.pktdma_rchan_flow = 0x1600,
+	},
+	/* No throughput levels */
+};
+
 static const struct udevice_id udma_ids[] = {
 	{
 		.compatible = "ti,am654-navss-main-udmap",
@@ -1924,6 +2791,14 @@ static const struct udevice_id udma_ids[] = {
 		.compatible = "ti,j721e-navss-mcu-udmap",
 		.data = (ulong)&j721e_mcu_data,
 	},
+	{
+		.compatible = "ti,am64-dmss-bcdma",
+		.data = (ulong)&am64_bcdma_data,
+	},
+	{
+		.compatible = "ti,am64-dmss-pktdma",
+		.data = (ulong)&am64_pktdma_data,
+	},
 	{ /* Sentinel */ },
 };
 
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 0cdfb0e91a..2aec2e34d3 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -2466,6 +2466,9 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(
 	req.tx_orderid = params->tx_orderid;
 	req.fdepth = params->fdepth;
 	req.tx_sched_priority = params->tx_sched_priority;
+	req.tx_burst_size = params->tx_burst_size;
+	req.tx_tdtype = params->tx_tdtype;
+	req.extended_ch_type = params->extended_ch_type;
 
 	ret = ti_sci_do_xfer(info, xfer);
 	if (ret) {
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 327bb820f3..eec488f065 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -998,6 +998,9 @@ struct ti_sci_msg_psil_unpair {
  *   11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
  *   12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
  *   13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
+ *   14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
+ *   15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
+ *   16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
  *
  * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
  *
@@ -1058,6 +1061,18 @@ struct ti_sci_msg_psil_unpair {
  * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
  * configuration to be programmed into the priority field of the channel's
  * TCHAN_TST_SCHED register.
+ *
+ * @tx_burst_size: UDMAP transmit channel burst size configuration to be
+ * programmed into the tx_burst_size field of the TCHAN_TCFG register.
+ *
+ * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
+ * programmed into the tdtype field of the TCHAN_TCFG register:
+ * 0 - Return immediately
+ * 1 - Wait for completion message from remote peer
+ *
+ * @extended_ch_type: Valid for BCDMA.
+ * 0 - the channel is split tx channel (tchan)
+ * 1 - the channel is block copy channel (bchan)
  */
 struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
 	struct ti_sci_msg_hdr hdr;
@@ -1078,6 +1093,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
 	u8 tx_orderid;
 	u16 fdepth;
 	u8 tx_sched_priority;
+	u8 tx_burst_size;
+	u8 tx_tdtype;
+	u8 extended_ch_type;
 } __packed;
 
 /**
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index ff21a08388..88f320515a 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -409,15 +409,7 @@ static int k3_sec_proxy_remove(struct udevice *dev)
 	return 0;
 }
 
-/*
- * Thread ID #4: ROM request
- * Thread ID #5: ROM response, SYSFW notify
- * Thread ID #6: SYSFW request response
- * Thread ID #7: SYSFW request high priority
- * Thread ID #8: SYSFW request low priority
- * Thread ID #9: SYSFW notify response
- */
-static const u32 am6x_valid_threads[] = { 4, 5, 6, 7, 8, 9, 11, 13 };
+static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13 };
 
 static const struct k3_sec_proxy_desc am654_desc = {
 	.thread_count = 90,
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 11dcde134c..a86d96aacd 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -470,6 +470,16 @@ const struct am654_driver_data j721e_4bit_drv_data = {
 	.flags = IOMUX_PRESENT,
 };
 
+static const struct am654_driver_data sdhci_am64_8bit_drvdata = {
+	.ops = &am654_sdhci_ops,
+	.flags = DLL_PRESENT | DLL_CALIB,
+};
+
+static const struct am654_driver_data sdhci_am64_4bit_drvdata = {
+	.ops = &j721e_4bit_sdhci_ops,
+	.flags = IOMUX_PRESENT,
+};
+
 const struct soc_attr am654_sdhci_soc_attr[] = {
 	{ .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
 	{/* sentinel */}
@@ -651,6 +661,14 @@ static const struct udevice_id am654_sdhci_ids[] = {
 		.compatible = "ti,j721e-sdhci-4bit",
 		.data = (ulong)&j721e_4bit_drv_data,
 	},
+	{
+		.compatible = "ti,am64-sdhci-8bit",
+		.data = (ulong)&sdhci_am64_8bit_drvdata,
+	},
+	{
+		.compatible = "ti,am64-sdhci-4bit",
+		.data = (ulong)&sdhci_am64_4bit_drvdata,
+	},
 	{ }
 };
 
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index e6954b64b7..3ab6a30828 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -26,7 +26,7 @@
 
 #include "cpsw_mdio.h"
 
-#define AM65_CPSW_CPSWNU_MAX_PORTS 2
+#define AM65_CPSW_CPSWNU_MAX_PORTS 9
 
 #define AM65_CPSW_SS_BASE		0x0
 #define AM65_CPSW_SGMII_BASE	0x100
@@ -719,11 +719,11 @@ static int am65_cpsw_probe_cpsw(struct udevice *dev)
 		if (!port_id)
 			continue;
 
-		priv->port_id = port_id;
 		cpsw_common->ports[port_id].disabled = disabled;
 		if (disabled)
 			continue;
 
+		priv->port_id = port_id;
 		ret = am65_cpsw_ofdata_parse_phy(dev, node);
 		if (ret)
 			goto out;
@@ -782,6 +782,7 @@ out:
 static const struct udevice_id am65_cpsw_nuss_ids[] = {
 	{ .compatible = "ti,am654-cpsw-nuss" },
 	{ .compatible = "ti,j721e-cpsw-nuss" },
+	{ .compatible = "ti,am642-cpsw-nuss" },
 	{ }
 };
 
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index a270e13b26..a79594d351 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -54,9 +54,19 @@ config K3_AM654_DDRSS
 	  config add support for the initialization of the external
 	  SDRAM devices connected to DDR subsystem.
 
+config K3_DDRSS
+	bool "Enable K3 DDRSS support"
+	depends on RAM
+
+choice
+	depends on K3_DDRSS
+	prompt "K3 DDRSS Arch Support"
+
+	default K3_J721E_DDRSS if SOC_K3_J721E
+	default K3_AM64_DDRSS if SOC_K3_AM642
+
 config K3_J721E_DDRSS
 	bool "Enable J721E DDRSS support"
-	depends on RAM
 	help
 	  The J721E DDR subsystem comprises DDR controller, DDR PHY and
 	  wrapper logic to integrate these blocks in the device. The DDR
@@ -65,6 +75,18 @@ config K3_J721E_DDRSS
 	  Enabling this config adds support for the DDR memory controller
 	  on J721E family of SoCs.
 
+config K3_AM64_DDRSS
+	bool "Enable AM64 DDRSS support"
+	help
+	  The AM64 DDR subsystem comprises DDR controller, DDR PHY and
+	  wrapper logic to integrate these blocks in the device. The DDR
+	  subsystem is used to provide an interface to external SDRAM
+	  devices which can be utilized for storing program or data.
+	  Enabling this config adds support for the DDR memory controller
+	  on AM642 family of SoCs.
+
+endchoice
+
 config IMXRT_SDRAM
 	bool "Enable i.MXRT SDRAM support"
 	depends on RAM
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 209a78c06f..5a39611349 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
 obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
 obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
+obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
 
 obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
 
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
new file mode 100644
index 0000000000..94202c9d94
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_IF_H
+#define LPDDR4_16BIT_IF_H
+
+#include <linux/types.h>
+
+#define LPDDR4_INTR_MAX_CS (2U)
+
+#define LPDDR4_INTR_CTL_REG_COUNT (423U)
+
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+
+#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
+
+typedef enum {
+	LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT			= 0U,
+	LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH			= 1U,
+	LPDDR4_INTR_TIMEOUT_ZQ_CALSTART			= 2U,
+	LPDDR4_INTR_TIMEOUT_MRR_TEMP			= 3U,
+	LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ			= 4U,
+	LPDDR4_INTR_TIMEOUT_DFI_UPDATE			= 5U,
+	LPDDR4_INTR_TIMEOUT_LP_WAKEUP			= 6U,
+	LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX		= 7U,
+	LPDDR4_INTR_ECC_ERROR				= 8U,
+	LPDDR4_INTR_LP_DONE				= 9U,
+	LPDDR4_INTR_LP_TIMEOUT				= 10U,
+	LPDDR4_INTR_PORT_TIMEOUT			= 11U,
+	LPDDR4_INTR_RFIFO_TIMEOUT			= 12U,
+	LPDDR4_INTR_TRAINING_ZQ_STATUS			= 13U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_DONE		= 14U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE	= 15U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW		= 16U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT		= 17U,
+	LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS		= 18U,
+	LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS	= 19U,
+	LPDDR4_INTR_USERIF_PORT_CMD_ERROR		= 20U,
+	LPDDR4_INTR_USERIF_WRAP				= 21U,
+	LPDDR4_INTR_USERIF_INVAL_SETTING		= 22U,
+	LPDDR4_INTR_MISC_MRR_TRAFFIC			= 23U,
+	LPDDR4_INTR_MISC_SW_REQ_MODE			= 24U,
+	LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH		= 25U,
+	LPDDR4_INTR_MISC_TEMP_ALERT			= 26U,
+	LPDDR4_INTR_MISC_REFRESH_STATUS			= 27U,
+	LPDDR4_INTR_BIST_DONE				= 28U,
+	LPDDR4_INTR_CRC					= 29U,
+	LPDDR4_INTR_DFI_UPDATE_ERROR			= 30U,
+	LPDDR4_INTR_DFI_PHY_ERROR			= 31U,
+	LPDDR4_INTR_DFI_BUS_ERROR			= 32U,
+	LPDDR4_INTR_DFI_STATE_CHANGE			= 33U,
+	LPDDR4_INTR_DFI_DLL_SYNC_DONE			= 34U,
+	LPDDR4_INTR_DFI_TIMEOUT				= 35U,
+	LPDDR4_INTR_DIMM				= 36U,
+	LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE		= 37U,
+	LPDDR4_INTR_FREQ_DFS_HW_TERMINATE		= 38U,
+	LPDDR4_INTR_FREQ_DFS_HW_DONE			= 39U,
+	LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE		= 40U,
+	LPDDR4_INTR_FREQ_DFS_SW_TERMINATE		= 41U,
+	LPDDR4_INTR_FREQ_DFS_SW_DONE			= 42U,
+	LPDDR4_INTR_INIT_MEM_RESET_DONE			= 43U,
+	LPDDR4_INTR_MC_INIT_DONE			= 44U,
+	LPDDR4_INTR_INIT_POWER_ON_STATE			= 45U,
+	LPDDR4_INTR_MRR_ERROR				= 46U,
+	LPDDR4_INTR_MR_READ_DONE			= 47U,
+	LPDDR4_INTR_MR_WRITE_DONE			= 48U,
+	LPDDR4_INTR_PARITY_ERROR			= 49U,
+	LPDDR4_INTR_LOR_BITS				= 50U
+} lpddr4_intr_ctlinterrupt;
+
+typedef enum {
+	LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT		= 0U,
+	LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT		= 1U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT		= 2U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT		= 3U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT		= 4U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT		= 5U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT		= 6U,
+	LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT		= 7U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT		= 8U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT	= 9U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT		= 10U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT		= 11U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT		= 12U,
+	LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT		= 13U,
+	LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT		= 14U,
+	LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT	= 15U,
+	LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U,
+	LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT		= 17U,
+	LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT		= 18U,
+	LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT	= 19U,
+	LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT	= 20U,
+	LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT	= 21U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT		= 22U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT		= 23U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT		= 24U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT		= 25U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT		= 26U,
+	LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT		= 27U,
+	LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT		= 28U
+} lpddr4_intr_phyindepinterrupt;
+
+#endif  /* LPDDR4_16BIT_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
new file mode 100644
index 0000000000..6c57dd9d00
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_OBJ_IF_H
+#define LPDDR4_16BIT_OBJ_IF_H
+
+#include "lpddr4_16bit_if.h"
+
+#endif  /* LPDDR4_16BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
new file mode 100644
index 0000000000..52973484ec
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_STRUCTS_IF_H
+#define LPDDR4_16BIT_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_16bit_if.h"
+
+#endif  /* LPDDR4_16BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
new file mode 100644
index 0000000000..f22a20a07c
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_512_READ_MASK                             0x000107FFU
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH    11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_512
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET           0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_512
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH               3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_512
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_513_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH              32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_513
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_514_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH         16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT   24U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH    4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_515_READ_MASK                             0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK  0x007F0000U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH          7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH         8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_516_READ_MASK                             0x01000707U
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH         3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET              0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_516
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOSET                   0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_517_READ_MASK                             0x011F7F7FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_MASK          0x0000007FU
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_WIDTH                  7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_MASK    0x00007F00U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_WIDTH            7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH             5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOSET               0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_518_READ_MASK                             0x01070301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH     1U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR     0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET     0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_MASK                  0x00000300U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_WIDTH                          2U
+#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK      0x00070000U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH              3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_MASK               0x01000000U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOSET                       0U
+#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_519_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_MASK              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_WIDTH                     27U
+#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_519
+#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_520_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_WIDTH                      6U
+#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_520
+#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_521_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_521
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_522_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH        32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_522
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_523_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_WIDTH                  11U
+#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_523
+#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0
+
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_MASK      0x07FF0000U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH             11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_523
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0
+
+#define LPDDR4__DENALI_PHY_524_READ_MASK                             0x000007FFU
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_WIDTH                    11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_524
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0
+
+#define LPDDR4__DENALI_PHY_525_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_525
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_526_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_526
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_MASK       0x03000000U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH               2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_526
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0
+
+#define LPDDR4__DENALI_PHY_527_READ_MASK                             0x01FF0F03U
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH            2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0
+
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH           4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT  16U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH   9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_528_READ_MASK                             0x07000001U
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET              0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_528
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_528
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET            0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_528
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0
+
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH              3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_528
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_529_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_0__REG DENALI_PHY_529
+#define LPDDR4__PHY_ADR_CALVL_OBS0_0__FLD LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0
+
+#define LPDDR4__DENALI_PHY_530_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_530
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0
+
+#define LPDDR4__DENALI_PHY_531_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_531
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0
+
+#define LPDDR4__DENALI_PHY_532_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_532
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0
+
+#define LPDDR4__DENALI_PHY_533_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_533
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0
+
+#define LPDDR4__DENALI_PHY_534_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_534
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0
+
+#define LPDDR4__DENALI_PHY_535_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_535
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0
+
+#define LPDDR4__DENALI_PHY_536_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_536
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0
+
+#define LPDDR4__DENALI_PHY_537_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_537
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0
+
+#define LPDDR4__DENALI_PHY_538_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_538
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0
+
+#define LPDDR4__DENALI_PHY_539_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_539
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0
+
+#define LPDDR4__DENALI_PHY_540_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_WIDTH                     30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_540
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0
+
+#define LPDDR4__DENALI_PHY_541_READ_MASK                             0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK    0x000003FFU
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_WIDTH                      6U
+#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0
+
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_WIDTH                      6U
+#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0
+
+#define LPDDR4__DENALI_PHY_542_READ_MASK                             0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH              6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH              6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_MASK    0x000F0000U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH            4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_WIDTH                  6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_543_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_543
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_544_READ_MASK                             0x0707FFFFU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_WIDTH                   8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_MASK            0x0007FF00U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_WIDTH                   11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK   0x07000000U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH           3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_545_READ_MASK                             0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK      0x0000001FU
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK   0x0007FF00U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_546_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_546
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_546
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_547_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_547
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_547
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_548_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_548
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_548
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_549_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_549
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_549
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_550_READ_MASK                             0x000F07FFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_550
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_WIDTH                4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_550
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_551_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_WIDTH           11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_MASK     0x003F0000U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH             6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_MASK     0xFF000000U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH             8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_552_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH     8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK      0x0003FF00U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH             10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET           0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_553_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_WIDTH                4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_553
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_554_READ_MASK                             0x0000010FU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK                            0x0000010FU
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH             4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_554
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET          0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_554
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
new file mode 100644
index 0000000000..df5ab95166
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_768_READ_MASK                             0x000107FFU
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH    11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_768
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET           0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_768
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH               3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_768
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_769_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH              32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_769
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_770_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH         16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT   24U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH    4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_771_READ_MASK                             0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK  0x007F0000U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH          7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH         8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_772_READ_MASK                             0x01000707U
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH         3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET              0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_772
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOSET                   0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_773_READ_MASK                             0x011F7F7FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_MASK          0x0000007FU
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_WIDTH                  7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_MASK    0x00007F00U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_WIDTH            7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH             5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOSET               0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_774_READ_MASK                             0x01070301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH     1U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR     0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET     0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_MASK                  0x00000300U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_WIDTH                          2U
+#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK      0x00070000U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH              3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_MASK               0x01000000U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOSET                       0U
+#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_775_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_MASK              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_WIDTH                     27U
+#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_775
+#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_776_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_WIDTH                      6U
+#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_776
+#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_777_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_WIDTH                 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_777
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_778_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH        32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_778
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_779_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_WIDTH                  11U
+#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_779
+#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1
+
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_MASK      0x07FF0000U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH             11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_779
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1
+
+#define LPDDR4__DENALI_PHY_780_READ_MASK                             0x000007FFU
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_WIDTH                    11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_780
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1
+
+#define LPDDR4__DENALI_PHY_781_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_781
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_782_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_782
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_MASK       0x03000000U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH               2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_782
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1
+
+#define LPDDR4__DENALI_PHY_783_READ_MASK                             0x01FF0F03U
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH            2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1
+
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH           4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT  16U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH   9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_784_READ_MASK                             0x07000001U
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET              0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_784
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_784
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH            1U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR            0U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET            0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_784
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1
+
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH              3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_784
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_785_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_1__REG DENALI_PHY_785
+#define LPDDR4__PHY_ADR_CALVL_OBS0_1__FLD LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1
+
+#define LPDDR4__DENALI_PHY_786_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_786
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1
+
+#define LPDDR4__DENALI_PHY_787_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_787
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1
+
+#define LPDDR4__DENALI_PHY_788_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_788
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1
+
+#define LPDDR4__DENALI_PHY_789_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_789
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1
+
+#define LPDDR4__DENALI_PHY_790_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_790
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1
+
+#define LPDDR4__DENALI_PHY_791_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_791
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1
+
+#define LPDDR4__DENALI_PHY_792_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_792
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1
+
+#define LPDDR4__DENALI_PHY_793_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_793
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1
+
+#define LPDDR4__DENALI_PHY_794_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_794
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1
+
+#define LPDDR4__DENALI_PHY_795_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_795
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1
+
+#define LPDDR4__DENALI_PHY_796_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_WIDTH                     30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_796
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1
+
+#define LPDDR4__DENALI_PHY_797_READ_MASK                             0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK    0x000003FFU
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH           10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_WIDTH                      6U
+#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1
+
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_WIDTH                      6U
+#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1
+
+#define LPDDR4__DENALI_PHY_798_READ_MASK                             0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH              6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH              6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_MASK    0x000F0000U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH            4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_WIDTH                  6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_799_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_799
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_800_READ_MASK                             0x0707FFFFU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_WIDTH                   8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_MASK            0x0007FF00U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_WIDTH                   11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK   0x07000000U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH           3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_801_READ_MASK                             0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK      0x0000001FU
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK   0x0007FF00U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_802_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_802
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_802
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_803_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_803
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_803
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_804_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_804
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_804
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_805_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_805
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_805
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_806_READ_MASK                             0x000F07FFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_806
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_WIDTH                4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_806
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_807_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_WIDTH           11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_MASK     0x003F0000U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH             6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_MASK     0xFF000000U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH             8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_808_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH     8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK      0x0003FF00U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH             10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET           0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_809_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_WIDTH                4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_809
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_810_READ_MASK                             0x0000010FU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK                            0x0000010FU
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH             4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_810
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET          0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_810
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
new file mode 100644
index 0000000000..924013e355
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1024_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_WRITE_MASK                           0x000107FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH   11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET          0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH              3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1024
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_1025_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH             32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1025
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1026_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH        16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK  0x00FF0000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH          8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT  24U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH   4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1027_READ_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_WRITE_MASK                           0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH         11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH         7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT       24U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH        8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1028_READ_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_1028_WRITE_MASK                           0x01000707U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT       8U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH       3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET             0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1028
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOSET                  0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1029_READ_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_WRITE_MASK                           0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_MASK         0x0000007FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_WIDTH                 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_MASK   0x00007F00U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_WIDTH           7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH            5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOSET              0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1030_READ_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_1030_WRITE_MASK                           0x01070301U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET    0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_MASK                 0x00000300U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_WIDTH                         2U
+#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK     0x00070000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH             3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOSET                      0U
+#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_1031_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_WRITE_MASK                           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_MASK             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_WIDTH                    27U
+#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1031
+#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_1032_READ_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_WRITE_MASK                           0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1032
+#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_1033_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_WIDTH                32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1033
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_1034_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH       32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1034
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_1035_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_MASK          0x000007FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_WIDTH                 11U
+#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2
+
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH            11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2
+
+#define LPDDR4__DENALI_PHY_1036_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_WIDTH                   11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1036
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2
+
+#define LPDDR4__DENALI_PHY_1037_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1037
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_1038_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_MASK      0x03000000U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH              2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1039_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_WRITE_MASK                           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH           2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK  0x00000F00U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH          4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH  9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_1040_READ_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_1040_WRITE_MASK                           0x07000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET             0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET          0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2
+
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_MASK     0x07000000U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH             3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1041_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_2__REG DENALI_PHY_1041
+#define LPDDR4__PHY_ADR_CALVL_OBS0_2__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2
+
+#define LPDDR4__DENALI_PHY_1042_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1042
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2
+
+#define LPDDR4__DENALI_PHY_1043_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1043
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2
+
+#define LPDDR4__DENALI_PHY_1044_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1044
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2
+
+#define LPDDR4__DENALI_PHY_1045_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1045
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2
+
+#define LPDDR4__DENALI_PHY_1046_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1046
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2
+
+#define LPDDR4__DENALI_PHY_1047_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1047
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2
+
+#define LPDDR4__DENALI_PHY_1048_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1048
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2
+
+#define LPDDR4__DENALI_PHY_1049_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1049
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2
+
+#define LPDDR4__DENALI_PHY_1050_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1050
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2
+
+#define LPDDR4__DENALI_PHY_1051_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1051
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2
+
+#define LPDDR4__DENALI_PHY_1052_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_WIDTH                    30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1052
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2
+
+#define LPDDR4__DENALI_PHY_1053_READ_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK                           0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH          10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_MASK             0x003F0000U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2
+
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_MASK             0x3F000000U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054_READ_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1054_WRITE_MASK                           0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH             6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH             6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH           4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1055_READ_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_1055_WRITE_MASK                           0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_MASK        0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH                6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1056_READ_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1056_WRITE_MASK                           0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_WIDTH                  8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_MASK           0x0007FF00U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_WIDTH                  11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK  0x07000000U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH          3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_1057_READ_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1057_WRITE_MASK                           0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK     0x0000001FU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK     0x1F000000U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1058_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1058_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1059_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1059_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1060_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1061_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1062_READ_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK                           0x000F07FFU
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_WIDTH               4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_1063_READ_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1063_WRITE_MASK                           0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_MASK    0x003F0000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH            6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH            8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_1064_READ_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK                           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH    8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK     0x0003FF00U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH            10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET          0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_1065_READ_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK                           0x0000000FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_WIDTH               4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1066_READ_MASK                            0x0000010FU
+#define LPDDR4__DENALI_PHY_1066_WRITE_MASK                           0x0000010FU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH            4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT         8U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH         1U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR         0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET         0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
new file mode 100644
index 0000000000..21e96c9a90
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
@@ -0,0 +1,1306 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_CTL_REGS_H_
+#define REG_LPDDR4_CTL_REGS_H_
+
+#include "lpddr4_ddr_controller_macros.h"
+#include "lpddr4_pi_macros.h"
+#include "lpddr4_data_slice_0_macros.h"
+#include "lpddr4_data_slice_1_macros.h"
+#include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_address_slice_1_macros.h"
+#include "lpddr4_address_slice_2_macros.h"
+#include "lpddr4_phy_core_macros.h"
+
+typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
+	volatile u32 DENALI_CTL_0;
+	volatile u32 DENALI_CTL_1;
+	volatile u32 DENALI_CTL_2;
+	volatile u32 DENALI_CTL_3;
+	volatile u32 DENALI_CTL_4;
+	volatile u32 DENALI_CTL_5;
+	volatile u32 DENALI_CTL_6;
+	volatile u32 DENALI_CTL_7;
+	volatile u32 DENALI_CTL_8;
+	volatile u32 DENALI_CTL_9;
+	volatile u32 DENALI_CTL_10;
+	volatile u32 DENALI_CTL_11;
+	volatile u32 DENALI_CTL_12;
+	volatile u32 DENALI_CTL_13;
+	volatile u32 DENALI_CTL_14;
+	volatile u32 DENALI_CTL_15;
+	volatile u32 DENALI_CTL_16;
+	volatile u32 DENALI_CTL_17;
+	volatile u32 DENALI_CTL_18;
+	volatile u32 DENALI_CTL_19;
+	volatile u32 DENALI_CTL_20;
+	volatile u32 DENALI_CTL_21;
+	volatile u32 DENALI_CTL_22;
+	volatile u32 DENALI_CTL_23;
+	volatile u32 DENALI_CTL_24;
+	volatile u32 DENALI_CTL_25;
+	volatile u32 DENALI_CTL_26;
+	volatile u32 DENALI_CTL_27;
+	volatile u32 DENALI_CTL_28;
+	volatile u32 DENALI_CTL_29;
+	volatile u32 DENALI_CTL_30;
+	volatile u32 DENALI_CTL_31;
+	volatile u32 DENALI_CTL_32;
+	volatile u32 DENALI_CTL_33;
+	volatile u32 DENALI_CTL_34;
+	volatile u32 DENALI_CTL_35;
+	volatile u32 DENALI_CTL_36;
+	volatile u32 DENALI_CTL_37;
+	volatile u32 DENALI_CTL_38;
+	volatile u32 DENALI_CTL_39;
+	volatile u32 DENALI_CTL_40;
+	volatile u32 DENALI_CTL_41;
+	volatile u32 DENALI_CTL_42;
+	volatile u32 DENALI_CTL_43;
+	volatile u32 DENALI_CTL_44;
+	volatile u32 DENALI_CTL_45;
+	volatile u32 DENALI_CTL_46;
+	volatile u32 DENALI_CTL_47;
+	volatile u32 DENALI_CTL_48;
+	volatile u32 DENALI_CTL_49;
+	volatile u32 DENALI_CTL_50;
+	volatile u32 DENALI_CTL_51;
+	volatile u32 DENALI_CTL_52;
+	volatile u32 DENALI_CTL_53;
+	volatile u32 DENALI_CTL_54;
+	volatile u32 DENALI_CTL_55;
+	volatile u32 DENALI_CTL_56;
+	volatile u32 DENALI_CTL_57;
+	volatile u32 DENALI_CTL_58;
+	volatile u32 DENALI_CTL_59;
+	volatile u32 DENALI_CTL_60;
+	volatile u32 DENALI_CTL_61;
+	volatile u32 DENALI_CTL_62;
+	volatile u32 DENALI_CTL_63;
+	volatile u32 DENALI_CTL_64;
+	volatile u32 DENALI_CTL_65;
+	volatile u32 DENALI_CTL_66;
+	volatile u32 DENALI_CTL_67;
+	volatile u32 DENALI_CTL_68;
+	volatile u32 DENALI_CTL_69;
+	volatile u32 DENALI_CTL_70;
+	volatile u32 DENALI_CTL_71;
+	volatile u32 DENALI_CTL_72;
+	volatile u32 DENALI_CTL_73;
+	volatile u32 DENALI_CTL_74;
+	volatile u32 DENALI_CTL_75;
+	volatile u32 DENALI_CTL_76;
+	volatile u32 DENALI_CTL_77;
+	volatile u32 DENALI_CTL_78;
+	volatile u32 DENALI_CTL_79;
+	volatile u32 DENALI_CTL_80;
+	volatile u32 DENALI_CTL_81;
+	volatile u32 DENALI_CTL_82;
+	volatile u32 DENALI_CTL_83;
+	volatile u32 DENALI_CTL_84;
+	volatile u32 DENALI_CTL_85;
+	volatile u32 DENALI_CTL_86;
+	volatile u32 DENALI_CTL_87;
+	volatile u32 DENALI_CTL_88;
+	volatile u32 DENALI_CTL_89;
+	volatile u32 DENALI_CTL_90;
+	volatile u32 DENALI_CTL_91;
+	volatile u32 DENALI_CTL_92;
+	volatile u32 DENALI_CTL_93;
+	volatile u32 DENALI_CTL_94;
+	volatile u32 DENALI_CTL_95;
+	volatile u32 DENALI_CTL_96;
+	volatile u32 DENALI_CTL_97;
+	volatile u32 DENALI_CTL_98;
+	volatile u32 DENALI_CTL_99;
+	volatile u32 DENALI_CTL_100;
+	volatile u32 DENALI_CTL_101;
+	volatile u32 DENALI_CTL_102;
+	volatile u32 DENALI_CTL_103;
+	volatile u32 DENALI_CTL_104;
+	volatile u32 DENALI_CTL_105;
+	volatile u32 DENALI_CTL_106;
+	volatile u32 DENALI_CTL_107;
+	volatile u32 DENALI_CTL_108;
+	volatile u32 DENALI_CTL_109;
+	volatile u32 DENALI_CTL_110;
+	volatile u32 DENALI_CTL_111;
+	volatile u32 DENALI_CTL_112;
+	volatile u32 DENALI_CTL_113;
+	volatile u32 DENALI_CTL_114;
+	volatile u32 DENALI_CTL_115;
+	volatile u32 DENALI_CTL_116;
+	volatile u32 DENALI_CTL_117;
+	volatile u32 DENALI_CTL_118;
+	volatile u32 DENALI_CTL_119;
+	volatile u32 DENALI_CTL_120;
+	volatile u32 DENALI_CTL_121;
+	volatile u32 DENALI_CTL_122;
+	volatile u32 DENALI_CTL_123;
+	volatile u32 DENALI_CTL_124;
+	volatile u32 DENALI_CTL_125;
+	volatile u32 DENALI_CTL_126;
+	volatile u32 DENALI_CTL_127;
+	volatile u32 DENALI_CTL_128;
+	volatile u32 DENALI_CTL_129;
+	volatile u32 DENALI_CTL_130;
+	volatile u32 DENALI_CTL_131;
+	volatile u32 DENALI_CTL_132;
+	volatile u32 DENALI_CTL_133;
+	volatile u32 DENALI_CTL_134;
+	volatile u32 DENALI_CTL_135;
+	volatile u32 DENALI_CTL_136;
+	volatile u32 DENALI_CTL_137;
+	volatile u32 DENALI_CTL_138;
+	volatile u32 DENALI_CTL_139;
+	volatile u32 DENALI_CTL_140;
+	volatile u32 DENALI_CTL_141;
+	volatile u32 DENALI_CTL_142;
+	volatile u32 DENALI_CTL_143;
+	volatile u32 DENALI_CTL_144;
+	volatile u32 DENALI_CTL_145;
+	volatile u32 DENALI_CTL_146;
+	volatile u32 DENALI_CTL_147;
+	volatile u32 DENALI_CTL_148;
+	volatile u32 DENALI_CTL_149;
+	volatile u32 DENALI_CTL_150;
+	volatile u32 DENALI_CTL_151;
+	volatile u32 DENALI_CTL_152;
+	volatile u32 DENALI_CTL_153;
+	volatile u32 DENALI_CTL_154;
+	volatile u32 DENALI_CTL_155;
+	volatile u32 DENALI_CTL_156;
+	volatile u32 DENALI_CTL_157;
+	volatile u32 DENALI_CTL_158;
+	volatile u32 DENALI_CTL_159;
+	volatile u32 DENALI_CTL_160;
+	volatile u32 DENALI_CTL_161;
+	volatile u32 DENALI_CTL_162;
+	volatile u32 DENALI_CTL_163;
+	volatile u32 DENALI_CTL_164;
+	volatile u32 DENALI_CTL_165;
+	volatile u32 DENALI_CTL_166;
+	volatile u32 DENALI_CTL_167;
+	volatile u32 DENALI_CTL_168;
+	volatile u32 DENALI_CTL_169;
+	volatile u32 DENALI_CTL_170;
+	volatile u32 DENALI_CTL_171;
+	volatile u32 DENALI_CTL_172;
+	volatile u32 DENALI_CTL_173;
+	volatile u32 DENALI_CTL_174;
+	volatile u32 DENALI_CTL_175;
+	volatile u32 DENALI_CTL_176;
+	volatile u32 DENALI_CTL_177;
+	volatile u32 DENALI_CTL_178;
+	volatile u32 DENALI_CTL_179;
+	volatile u32 DENALI_CTL_180;
+	volatile u32 DENALI_CTL_181;
+	volatile u32 DENALI_CTL_182;
+	volatile u32 DENALI_CTL_183;
+	volatile u32 DENALI_CTL_184;
+	volatile u32 DENALI_CTL_185;
+	volatile u32 DENALI_CTL_186;
+	volatile u32 DENALI_CTL_187;
+	volatile u32 DENALI_CTL_188;
+	volatile u32 DENALI_CTL_189;
+	volatile u32 DENALI_CTL_190;
+	volatile u32 DENALI_CTL_191;
+	volatile u32 DENALI_CTL_192;
+	volatile u32 DENALI_CTL_193;
+	volatile u32 DENALI_CTL_194;
+	volatile u32 DENALI_CTL_195;
+	volatile u32 DENALI_CTL_196;
+	volatile u32 DENALI_CTL_197;
+	volatile u32 DENALI_CTL_198;
+	volatile u32 DENALI_CTL_199;
+	volatile u32 DENALI_CTL_200;
+	volatile u32 DENALI_CTL_201;
+	volatile u32 DENALI_CTL_202;
+	volatile u32 DENALI_CTL_203;
+	volatile u32 DENALI_CTL_204;
+	volatile u32 DENALI_CTL_205;
+	volatile u32 DENALI_CTL_206;
+	volatile u32 DENALI_CTL_207;
+	volatile u32 DENALI_CTL_208;
+	volatile u32 DENALI_CTL_209;
+	volatile u32 DENALI_CTL_210;
+	volatile u32 DENALI_CTL_211;
+	volatile u32 DENALI_CTL_212;
+	volatile u32 DENALI_CTL_213;
+	volatile u32 DENALI_CTL_214;
+	volatile u32 DENALI_CTL_215;
+	volatile u32 DENALI_CTL_216;
+	volatile u32 DENALI_CTL_217;
+	volatile u32 DENALI_CTL_218;
+	volatile u32 DENALI_CTL_219;
+	volatile u32 DENALI_CTL_220;
+	volatile u32 DENALI_CTL_221;
+	volatile u32 DENALI_CTL_222;
+	volatile u32 DENALI_CTL_223;
+	volatile u32 DENALI_CTL_224;
+	volatile u32 DENALI_CTL_225;
+	volatile u32 DENALI_CTL_226;
+	volatile u32 DENALI_CTL_227;
+	volatile u32 DENALI_CTL_228;
+	volatile u32 DENALI_CTL_229;
+	volatile u32 DENALI_CTL_230;
+	volatile u32 DENALI_CTL_231;
+	volatile u32 DENALI_CTL_232;
+	volatile u32 DENALI_CTL_233;
+	volatile u32 DENALI_CTL_234;
+	volatile u32 DENALI_CTL_235;
+	volatile u32 DENALI_CTL_236;
+	volatile u32 DENALI_CTL_237;
+	volatile u32 DENALI_CTL_238;
+	volatile u32 DENALI_CTL_239;
+	volatile u32 DENALI_CTL_240;
+	volatile u32 DENALI_CTL_241;
+	volatile u32 DENALI_CTL_242;
+	volatile u32 DENALI_CTL_243;
+	volatile u32 DENALI_CTL_244;
+	volatile u32 DENALI_CTL_245;
+	volatile u32 DENALI_CTL_246;
+	volatile u32 DENALI_CTL_247;
+	volatile u32 DENALI_CTL_248;
+	volatile u32 DENALI_CTL_249;
+	volatile u32 DENALI_CTL_250;
+	volatile u32 DENALI_CTL_251;
+	volatile u32 DENALI_CTL_252;
+	volatile u32 DENALI_CTL_253;
+	volatile u32 DENALI_CTL_254;
+	volatile u32 DENALI_CTL_255;
+	volatile u32 DENALI_CTL_256;
+	volatile u32 DENALI_CTL_257;
+	volatile u32 DENALI_CTL_258;
+	volatile u32 DENALI_CTL_259;
+	volatile u32 DENALI_CTL_260;
+	volatile u32 DENALI_CTL_261;
+	volatile u32 DENALI_CTL_262;
+	volatile u32 DENALI_CTL_263;
+	volatile u32 DENALI_CTL_264;
+	volatile u32 DENALI_CTL_265;
+	volatile u32 DENALI_CTL_266;
+	volatile u32 DENALI_CTL_267;
+	volatile u32 DENALI_CTL_268;
+	volatile u32 DENALI_CTL_269;
+	volatile u32 DENALI_CTL_270;
+	volatile u32 DENALI_CTL_271;
+	volatile u32 DENALI_CTL_272;
+	volatile u32 DENALI_CTL_273;
+	volatile u32 DENALI_CTL_274;
+	volatile u32 DENALI_CTL_275;
+	volatile u32 DENALI_CTL_276;
+	volatile u32 DENALI_CTL_277;
+	volatile u32 DENALI_CTL_278;
+	volatile u32 DENALI_CTL_279;
+	volatile u32 DENALI_CTL_280;
+	volatile u32 DENALI_CTL_281;
+	volatile u32 DENALI_CTL_282;
+	volatile u32 DENALI_CTL_283;
+	volatile u32 DENALI_CTL_284;
+	volatile u32 DENALI_CTL_285;
+	volatile u32 DENALI_CTL_286;
+	volatile u32 DENALI_CTL_287;
+	volatile u32 DENALI_CTL_288;
+	volatile u32 DENALI_CTL_289;
+	volatile u32 DENALI_CTL_290;
+	volatile u32 DENALI_CTL_291;
+	volatile u32 DENALI_CTL_292;
+	volatile u32 DENALI_CTL_293;
+	volatile u32 DENALI_CTL_294;
+	volatile u32 DENALI_CTL_295;
+	volatile u32 DENALI_CTL_296;
+	volatile u32 DENALI_CTL_297;
+	volatile u32 DENALI_CTL_298;
+	volatile u32 DENALI_CTL_299;
+	volatile u32 DENALI_CTL_300;
+	volatile u32 DENALI_CTL_301;
+	volatile u32 DENALI_CTL_302;
+	volatile u32 DENALI_CTL_303;
+	volatile u32 DENALI_CTL_304;
+	volatile u32 DENALI_CTL_305;
+	volatile u32 DENALI_CTL_306;
+	volatile u32 DENALI_CTL_307;
+	volatile u32 DENALI_CTL_308;
+	volatile u32 DENALI_CTL_309;
+	volatile u32 DENALI_CTL_310;
+	volatile u32 DENALI_CTL_311;
+	volatile u32 DENALI_CTL_312;
+	volatile u32 DENALI_CTL_313;
+	volatile u32 DENALI_CTL_314;
+	volatile u32 DENALI_CTL_315;
+	volatile u32 DENALI_CTL_316;
+	volatile u32 DENALI_CTL_317;
+	volatile u32 DENALI_CTL_318;
+	volatile u32 DENALI_CTL_319;
+	volatile u32 DENALI_CTL_320;
+	volatile u32 DENALI_CTL_321;
+	volatile u32 DENALI_CTL_322;
+	volatile u32 DENALI_CTL_323;
+	volatile u32 DENALI_CTL_324;
+	volatile u32 DENALI_CTL_325;
+	volatile u32 DENALI_CTL_326;
+	volatile u32 DENALI_CTL_327;
+	volatile u32 DENALI_CTL_328;
+	volatile u32 DENALI_CTL_329;
+	volatile u32 DENALI_CTL_330;
+	volatile u32 DENALI_CTL_331;
+	volatile u32 DENALI_CTL_332;
+	volatile u32 DENALI_CTL_333;
+	volatile u32 DENALI_CTL_334;
+	volatile u32 DENALI_CTL_335;
+	volatile u32 DENALI_CTL_336;
+	volatile u32 DENALI_CTL_337;
+	volatile u32 DENALI_CTL_338;
+	volatile u32 DENALI_CTL_339;
+	volatile u32 DENALI_CTL_340;
+	volatile u32 DENALI_CTL_341;
+	volatile u32 DENALI_CTL_342;
+	volatile u32 DENALI_CTL_343;
+	volatile u32 DENALI_CTL_344;
+	volatile u32 DENALI_CTL_345;
+	volatile u32 DENALI_CTL_346;
+	volatile u32 DENALI_CTL_347;
+	volatile u32 DENALI_CTL_348;
+	volatile u32 DENALI_CTL_349;
+	volatile u32 DENALI_CTL_350;
+	volatile u32 DENALI_CTL_351;
+	volatile u32 DENALI_CTL_352;
+	volatile u32 DENALI_CTL_353;
+	volatile u32 DENALI_CTL_354;
+	volatile u32 DENALI_CTL_355;
+	volatile u32 DENALI_CTL_356;
+	volatile u32 DENALI_CTL_357;
+	volatile u32 DENALI_CTL_358;
+	volatile u32 DENALI_CTL_359;
+	volatile u32 DENALI_CTL_360;
+	volatile u32 DENALI_CTL_361;
+	volatile u32 DENALI_CTL_362;
+	volatile u32 DENALI_CTL_363;
+	volatile u32 DENALI_CTL_364;
+	volatile u32 DENALI_CTL_365;
+	volatile u32 DENALI_CTL_366;
+	volatile u32 DENALI_CTL_367;
+	volatile u32 DENALI_CTL_368;
+	volatile u32 DENALI_CTL_369;
+	volatile u32 DENALI_CTL_370;
+	volatile u32 DENALI_CTL_371;
+	volatile u32 DENALI_CTL_372;
+	volatile u32 DENALI_CTL_373;
+	volatile u32 DENALI_CTL_374;
+	volatile u32 DENALI_CTL_375;
+	volatile u32 DENALI_CTL_376;
+	volatile u32 DENALI_CTL_377;
+	volatile u32 DENALI_CTL_378;
+	volatile u32 DENALI_CTL_379;
+	volatile u32 DENALI_CTL_380;
+	volatile u32 DENALI_CTL_381;
+	volatile u32 DENALI_CTL_382;
+	volatile u32 DENALI_CTL_383;
+	volatile u32 DENALI_CTL_384;
+	volatile u32 DENALI_CTL_385;
+	volatile u32 DENALI_CTL_386;
+	volatile u32 DENALI_CTL_387;
+	volatile u32 DENALI_CTL_388;
+	volatile u32 DENALI_CTL_389;
+	volatile u32 DENALI_CTL_390;
+	volatile u32 DENALI_CTL_391;
+	volatile u32 DENALI_CTL_392;
+	volatile u32 DENALI_CTL_393;
+	volatile u32 DENALI_CTL_394;
+	volatile u32 DENALI_CTL_395;
+	volatile u32 DENALI_CTL_396;
+	volatile u32 DENALI_CTL_397;
+	volatile u32 DENALI_CTL_398;
+	volatile u32 DENALI_CTL_399;
+	volatile u32 DENALI_CTL_400;
+	volatile u32 DENALI_CTL_401;
+	volatile u32 DENALI_CTL_402;
+	volatile u32 DENALI_CTL_403;
+	volatile u32 DENALI_CTL_404;
+	volatile u32 DENALI_CTL_405;
+	volatile u32 DENALI_CTL_406;
+	volatile u32 DENALI_CTL_407;
+	volatile u32 DENALI_CTL_408;
+	volatile u32 DENALI_CTL_409;
+	volatile u32 DENALI_CTL_410;
+	volatile u32 DENALI_CTL_411;
+	volatile u32 DENALI_CTL_412;
+	volatile u32 DENALI_CTL_413;
+	volatile u32 DENALI_CTL_414;
+	volatile u32 DENALI_CTL_415;
+	volatile u32 DENALI_CTL_416;
+	volatile u32 DENALI_CTL_417;
+	volatile u32 DENALI_CTL_418;
+	volatile u32 DENALI_CTL_419;
+	volatile u32 DENALI_CTL_420;
+	volatile u32 DENALI_CTL_421;
+	volatile u32 DENALI_CTL_422;
+	volatile char pad__0[0x1964U];
+	volatile u32 DENALI_PI_0;
+	volatile u32 DENALI_PI_1;
+	volatile u32 DENALI_PI_2;
+	volatile u32 DENALI_PI_3;
+	volatile u32 DENALI_PI_4;
+	volatile u32 DENALI_PI_5;
+	volatile u32 DENALI_PI_6;
+	volatile u32 DENALI_PI_7;
+	volatile u32 DENALI_PI_8;
+	volatile u32 DENALI_PI_9;
+	volatile u32 DENALI_PI_10;
+	volatile u32 DENALI_PI_11;
+	volatile u32 DENALI_PI_12;
+	volatile u32 DENALI_PI_13;
+	volatile u32 DENALI_PI_14;
+	volatile u32 DENALI_PI_15;
+	volatile u32 DENALI_PI_16;
+	volatile u32 DENALI_PI_17;
+	volatile u32 DENALI_PI_18;
+	volatile u32 DENALI_PI_19;
+	volatile u32 DENALI_PI_20;
+	volatile u32 DENALI_PI_21;
+	volatile u32 DENALI_PI_22;
+	volatile u32 DENALI_PI_23;
+	volatile u32 DENALI_PI_24;
+	volatile u32 DENALI_PI_25;
+	volatile u32 DENALI_PI_26;
+	volatile u32 DENALI_PI_27;
+	volatile u32 DENALI_PI_28;
+	volatile u32 DENALI_PI_29;
+	volatile u32 DENALI_PI_30;
+	volatile u32 DENALI_PI_31;
+	volatile u32 DENALI_PI_32;
+	volatile u32 DENALI_PI_33;
+	volatile u32 DENALI_PI_34;
+	volatile u32 DENALI_PI_35;
+	volatile u32 DENALI_PI_36;
+	volatile u32 DENALI_PI_37;
+	volatile u32 DENALI_PI_38;
+	volatile u32 DENALI_PI_39;
+	volatile u32 DENALI_PI_40;
+	volatile u32 DENALI_PI_41;
+	volatile u32 DENALI_PI_42;
+	volatile u32 DENALI_PI_43;
+	volatile u32 DENALI_PI_44;
+	volatile u32 DENALI_PI_45;
+	volatile u32 DENALI_PI_46;
+	volatile u32 DENALI_PI_47;
+	volatile u32 DENALI_PI_48;
+	volatile u32 DENALI_PI_49;
+	volatile u32 DENALI_PI_50;
+	volatile u32 DENALI_PI_51;
+	volatile u32 DENALI_PI_52;
+	volatile u32 DENALI_PI_53;
+	volatile u32 DENALI_PI_54;
+	volatile u32 DENALI_PI_55;
+	volatile u32 DENALI_PI_56;
+	volatile u32 DENALI_PI_57;
+	volatile u32 DENALI_PI_58;
+	volatile u32 DENALI_PI_59;
+	volatile u32 DENALI_PI_60;
+	volatile u32 DENALI_PI_61;
+	volatile u32 DENALI_PI_62;
+	volatile u32 DENALI_PI_63;
+	volatile u32 DENALI_PI_64;
+	volatile u32 DENALI_PI_65;
+	volatile u32 DENALI_PI_66;
+	volatile u32 DENALI_PI_67;
+	volatile u32 DENALI_PI_68;
+	volatile u32 DENALI_PI_69;
+	volatile u32 DENALI_PI_70;
+	volatile u32 DENALI_PI_71;
+	volatile u32 DENALI_PI_72;
+	volatile u32 DENALI_PI_73;
+	volatile u32 DENALI_PI_74;
+	volatile u32 DENALI_PI_75;
+	volatile u32 DENALI_PI_76;
+	volatile u32 DENALI_PI_77;
+	volatile u32 DENALI_PI_78;
+	volatile u32 DENALI_PI_79;
+	volatile u32 DENALI_PI_80;
+	volatile u32 DENALI_PI_81;
+	volatile u32 DENALI_PI_82;
+	volatile u32 DENALI_PI_83;
+	volatile u32 DENALI_PI_84;
+	volatile u32 DENALI_PI_85;
+	volatile u32 DENALI_PI_86;
+	volatile u32 DENALI_PI_87;
+	volatile u32 DENALI_PI_88;
+	volatile u32 DENALI_PI_89;
+	volatile u32 DENALI_PI_90;
+	volatile u32 DENALI_PI_91;
+	volatile u32 DENALI_PI_92;
+	volatile u32 DENALI_PI_93;
+	volatile u32 DENALI_PI_94;
+	volatile u32 DENALI_PI_95;
+	volatile u32 DENALI_PI_96;
+	volatile u32 DENALI_PI_97;
+	volatile u32 DENALI_PI_98;
+	volatile u32 DENALI_PI_99;
+	volatile u32 DENALI_PI_100;
+	volatile u32 DENALI_PI_101;
+	volatile u32 DENALI_PI_102;
+	volatile u32 DENALI_PI_103;
+	volatile u32 DENALI_PI_104;
+	volatile u32 DENALI_PI_105;
+	volatile u32 DENALI_PI_106;
+	volatile u32 DENALI_PI_107;
+	volatile u32 DENALI_PI_108;
+	volatile u32 DENALI_PI_109;
+	volatile u32 DENALI_PI_110;
+	volatile u32 DENALI_PI_111;
+	volatile u32 DENALI_PI_112;
+	volatile u32 DENALI_PI_113;
+	volatile u32 DENALI_PI_114;
+	volatile u32 DENALI_PI_115;
+	volatile u32 DENALI_PI_116;
+	volatile u32 DENALI_PI_117;
+	volatile u32 DENALI_PI_118;
+	volatile u32 DENALI_PI_119;
+	volatile u32 DENALI_PI_120;
+	volatile u32 DENALI_PI_121;
+	volatile u32 DENALI_PI_122;
+	volatile u32 DENALI_PI_123;
+	volatile u32 DENALI_PI_124;
+	volatile u32 DENALI_PI_125;
+	volatile u32 DENALI_PI_126;
+	volatile u32 DENALI_PI_127;
+	volatile u32 DENALI_PI_128;
+	volatile u32 DENALI_PI_129;
+	volatile u32 DENALI_PI_130;
+	volatile u32 DENALI_PI_131;
+	volatile u32 DENALI_PI_132;
+	volatile u32 DENALI_PI_133;
+	volatile u32 DENALI_PI_134;
+	volatile u32 DENALI_PI_135;
+	volatile u32 DENALI_PI_136;
+	volatile u32 DENALI_PI_137;
+	volatile u32 DENALI_PI_138;
+	volatile u32 DENALI_PI_139;
+	volatile u32 DENALI_PI_140;
+	volatile u32 DENALI_PI_141;
+	volatile u32 DENALI_PI_142;
+	volatile u32 DENALI_PI_143;
+	volatile u32 DENALI_PI_144;
+	volatile u32 DENALI_PI_145;
+	volatile u32 DENALI_PI_146;
+	volatile u32 DENALI_PI_147;
+	volatile u32 DENALI_PI_148;
+	volatile u32 DENALI_PI_149;
+	volatile u32 DENALI_PI_150;
+	volatile u32 DENALI_PI_151;
+	volatile u32 DENALI_PI_152;
+	volatile u32 DENALI_PI_153;
+	volatile u32 DENALI_PI_154;
+	volatile u32 DENALI_PI_155;
+	volatile u32 DENALI_PI_156;
+	volatile u32 DENALI_PI_157;
+	volatile u32 DENALI_PI_158;
+	volatile u32 DENALI_PI_159;
+	volatile u32 DENALI_PI_160;
+	volatile u32 DENALI_PI_161;
+	volatile u32 DENALI_PI_162;
+	volatile u32 DENALI_PI_163;
+	volatile u32 DENALI_PI_164;
+	volatile u32 DENALI_PI_165;
+	volatile u32 DENALI_PI_166;
+	volatile u32 DENALI_PI_167;
+	volatile u32 DENALI_PI_168;
+	volatile u32 DENALI_PI_169;
+	volatile u32 DENALI_PI_170;
+	volatile u32 DENALI_PI_171;
+	volatile u32 DENALI_PI_172;
+	volatile u32 DENALI_PI_173;
+	volatile u32 DENALI_PI_174;
+	volatile u32 DENALI_PI_175;
+	volatile u32 DENALI_PI_176;
+	volatile u32 DENALI_PI_177;
+	volatile u32 DENALI_PI_178;
+	volatile u32 DENALI_PI_179;
+	volatile u32 DENALI_PI_180;
+	volatile u32 DENALI_PI_181;
+	volatile u32 DENALI_PI_182;
+	volatile u32 DENALI_PI_183;
+	volatile u32 DENALI_PI_184;
+	volatile u32 DENALI_PI_185;
+	volatile u32 DENALI_PI_186;
+	volatile u32 DENALI_PI_187;
+	volatile u32 DENALI_PI_188;
+	volatile u32 DENALI_PI_189;
+	volatile u32 DENALI_PI_190;
+	volatile u32 DENALI_PI_191;
+	volatile u32 DENALI_PI_192;
+	volatile u32 DENALI_PI_193;
+	volatile u32 DENALI_PI_194;
+	volatile u32 DENALI_PI_195;
+	volatile u32 DENALI_PI_196;
+	volatile u32 DENALI_PI_197;
+	volatile u32 DENALI_PI_198;
+	volatile u32 DENALI_PI_199;
+	volatile u32 DENALI_PI_200;
+	volatile u32 DENALI_PI_201;
+	volatile u32 DENALI_PI_202;
+	volatile u32 DENALI_PI_203;
+	volatile u32 DENALI_PI_204;
+	volatile u32 DENALI_PI_205;
+	volatile u32 DENALI_PI_206;
+	volatile u32 DENALI_PI_207;
+	volatile u32 DENALI_PI_208;
+	volatile u32 DENALI_PI_209;
+	volatile u32 DENALI_PI_210;
+	volatile u32 DENALI_PI_211;
+	volatile u32 DENALI_PI_212;
+	volatile u32 DENALI_PI_213;
+	volatile u32 DENALI_PI_214;
+	volatile u32 DENALI_PI_215;
+	volatile u32 DENALI_PI_216;
+	volatile u32 DENALI_PI_217;
+	volatile u32 DENALI_PI_218;
+	volatile u32 DENALI_PI_219;
+	volatile u32 DENALI_PI_220;
+	volatile u32 DENALI_PI_221;
+	volatile u32 DENALI_PI_222;
+	volatile u32 DENALI_PI_223;
+	volatile u32 DENALI_PI_224;
+	volatile u32 DENALI_PI_225;
+	volatile u32 DENALI_PI_226;
+	volatile u32 DENALI_PI_227;
+	volatile u32 DENALI_PI_228;
+	volatile u32 DENALI_PI_229;
+	volatile u32 DENALI_PI_230;
+	volatile u32 DENALI_PI_231;
+	volatile u32 DENALI_PI_232;
+	volatile u32 DENALI_PI_233;
+	volatile u32 DENALI_PI_234;
+	volatile u32 DENALI_PI_235;
+	volatile u32 DENALI_PI_236;
+	volatile u32 DENALI_PI_237;
+	volatile u32 DENALI_PI_238;
+	volatile u32 DENALI_PI_239;
+	volatile u32 DENALI_PI_240;
+	volatile u32 DENALI_PI_241;
+	volatile u32 DENALI_PI_242;
+	volatile u32 DENALI_PI_243;
+	volatile u32 DENALI_PI_244;
+	volatile u32 DENALI_PI_245;
+	volatile u32 DENALI_PI_246;
+	volatile u32 DENALI_PI_247;
+	volatile u32 DENALI_PI_248;
+	volatile u32 DENALI_PI_249;
+	volatile u32 DENALI_PI_250;
+	volatile u32 DENALI_PI_251;
+	volatile u32 DENALI_PI_252;
+	volatile u32 DENALI_PI_253;
+	volatile u32 DENALI_PI_254;
+	volatile u32 DENALI_PI_255;
+	volatile u32 DENALI_PI_256;
+	volatile u32 DENALI_PI_257;
+	volatile u32 DENALI_PI_258;
+	volatile u32 DENALI_PI_259;
+	volatile u32 DENALI_PI_260;
+	volatile u32 DENALI_PI_261;
+	volatile u32 DENALI_PI_262;
+	volatile u32 DENALI_PI_263;
+	volatile u32 DENALI_PI_264;
+	volatile u32 DENALI_PI_265;
+	volatile u32 DENALI_PI_266;
+	volatile u32 DENALI_PI_267;
+	volatile u32 DENALI_PI_268;
+	volatile u32 DENALI_PI_269;
+	volatile u32 DENALI_PI_270;
+	volatile u32 DENALI_PI_271;
+	volatile u32 DENALI_PI_272;
+	volatile u32 DENALI_PI_273;
+	volatile u32 DENALI_PI_274;
+	volatile u32 DENALI_PI_275;
+	volatile u32 DENALI_PI_276;
+	volatile u32 DENALI_PI_277;
+	volatile u32 DENALI_PI_278;
+	volatile u32 DENALI_PI_279;
+	volatile u32 DENALI_PI_280;
+	volatile u32 DENALI_PI_281;
+	volatile u32 DENALI_PI_282;
+	volatile u32 DENALI_PI_283;
+	volatile u32 DENALI_PI_284;
+	volatile u32 DENALI_PI_285;
+	volatile u32 DENALI_PI_286;
+	volatile u32 DENALI_PI_287;
+	volatile u32 DENALI_PI_288;
+	volatile u32 DENALI_PI_289;
+	volatile u32 DENALI_PI_290;
+	volatile u32 DENALI_PI_291;
+	volatile u32 DENALI_PI_292;
+	volatile u32 DENALI_PI_293;
+	volatile u32 DENALI_PI_294;
+	volatile u32 DENALI_PI_295;
+	volatile u32 DENALI_PI_296;
+	volatile u32 DENALI_PI_297;
+	volatile u32 DENALI_PI_298;
+	volatile u32 DENALI_PI_299;
+	volatile u32 DENALI_PI_300;
+	volatile u32 DENALI_PI_301;
+	volatile u32 DENALI_PI_302;
+	volatile u32 DENALI_PI_303;
+	volatile u32 DENALI_PI_304;
+	volatile u32 DENALI_PI_305;
+	volatile u32 DENALI_PI_306;
+	volatile u32 DENALI_PI_307;
+	volatile u32 DENALI_PI_308;
+	volatile u32 DENALI_PI_309;
+	volatile u32 DENALI_PI_310;
+	volatile u32 DENALI_PI_311;
+	volatile u32 DENALI_PI_312;
+	volatile u32 DENALI_PI_313;
+	volatile u32 DENALI_PI_314;
+	volatile u32 DENALI_PI_315;
+	volatile u32 DENALI_PI_316;
+	volatile u32 DENALI_PI_317;
+	volatile u32 DENALI_PI_318;
+	volatile u32 DENALI_PI_319;
+	volatile u32 DENALI_PI_320;
+	volatile u32 DENALI_PI_321;
+	volatile u32 DENALI_PI_322;
+	volatile u32 DENALI_PI_323;
+	volatile u32 DENALI_PI_324;
+	volatile u32 DENALI_PI_325;
+	volatile u32 DENALI_PI_326;
+	volatile u32 DENALI_PI_327;
+	volatile u32 DENALI_PI_328;
+	volatile u32 DENALI_PI_329;
+	volatile u32 DENALI_PI_330;
+	volatile u32 DENALI_PI_331;
+	volatile u32 DENALI_PI_332;
+	volatile u32 DENALI_PI_333;
+	volatile u32 DENALI_PI_334;
+	volatile u32 DENALI_PI_335;
+	volatile u32 DENALI_PI_336;
+	volatile u32 DENALI_PI_337;
+	volatile u32 DENALI_PI_338;
+	volatile u32 DENALI_PI_339;
+	volatile u32 DENALI_PI_340;
+	volatile u32 DENALI_PI_341;
+	volatile u32 DENALI_PI_342;
+	volatile u32 DENALI_PI_343;
+	volatile u32 DENALI_PI_344;
+	volatile char pad__1[0x1A9CU];
+	volatile u32 DENALI_PHY_0;
+	volatile u32 DENALI_PHY_1;
+	volatile u32 DENALI_PHY_2;
+	volatile u32 DENALI_PHY_3;
+	volatile u32 DENALI_PHY_4;
+	volatile u32 DENALI_PHY_5;
+	volatile u32 DENALI_PHY_6;
+	volatile u32 DENALI_PHY_7;
+	volatile u32 DENALI_PHY_8;
+	volatile u32 DENALI_PHY_9;
+	volatile u32 DENALI_PHY_10;
+	volatile u32 DENALI_PHY_11;
+	volatile u32 DENALI_PHY_12;
+	volatile u32 DENALI_PHY_13;
+	volatile u32 DENALI_PHY_14;
+	volatile u32 DENALI_PHY_15;
+	volatile u32 DENALI_PHY_16;
+	volatile u32 DENALI_PHY_17;
+	volatile u32 DENALI_PHY_18;
+	volatile u32 DENALI_PHY_19;
+	volatile u32 DENALI_PHY_20;
+	volatile u32 DENALI_PHY_21;
+	volatile u32 DENALI_PHY_22;
+	volatile u32 DENALI_PHY_23;
+	volatile u32 DENALI_PHY_24;
+	volatile u32 DENALI_PHY_25;
+	volatile u32 DENALI_PHY_26;
+	volatile u32 DENALI_PHY_27;
+	volatile u32 DENALI_PHY_28;
+	volatile u32 DENALI_PHY_29;
+	volatile u32 DENALI_PHY_30;
+	volatile u32 DENALI_PHY_31;
+	volatile u32 DENALI_PHY_32;
+	volatile u32 DENALI_PHY_33;
+	volatile u32 DENALI_PHY_34;
+	volatile u32 DENALI_PHY_35;
+	volatile u32 DENALI_PHY_36;
+	volatile u32 DENALI_PHY_37;
+	volatile u32 DENALI_PHY_38;
+	volatile u32 DENALI_PHY_39;
+	volatile u32 DENALI_PHY_40;
+	volatile u32 DENALI_PHY_41;
+	volatile u32 DENALI_PHY_42;
+	volatile u32 DENALI_PHY_43;
+	volatile u32 DENALI_PHY_44;
+	volatile u32 DENALI_PHY_45;
+	volatile u32 DENALI_PHY_46;
+	volatile u32 DENALI_PHY_47;
+	volatile u32 DENALI_PHY_48;
+	volatile u32 DENALI_PHY_49;
+	volatile u32 DENALI_PHY_50;
+	volatile u32 DENALI_PHY_51;
+	volatile u32 DENALI_PHY_52;
+	volatile u32 DENALI_PHY_53;
+	volatile u32 DENALI_PHY_54;
+	volatile u32 DENALI_PHY_55;
+	volatile u32 DENALI_PHY_56;
+	volatile u32 DENALI_PHY_57;
+	volatile u32 DENALI_PHY_58;
+	volatile u32 DENALI_PHY_59;
+	volatile u32 DENALI_PHY_60;
+	volatile u32 DENALI_PHY_61;
+	volatile u32 DENALI_PHY_62;
+	volatile u32 DENALI_PHY_63;
+	volatile u32 DENALI_PHY_64;
+	volatile u32 DENALI_PHY_65;
+	volatile u32 DENALI_PHY_66;
+	volatile u32 DENALI_PHY_67;
+	volatile u32 DENALI_PHY_68;
+	volatile u32 DENALI_PHY_69;
+	volatile u32 DENALI_PHY_70;
+	volatile u32 DENALI_PHY_71;
+	volatile u32 DENALI_PHY_72;
+	volatile u32 DENALI_PHY_73;
+	volatile u32 DENALI_PHY_74;
+	volatile u32 DENALI_PHY_75;
+	volatile u32 DENALI_PHY_76;
+	volatile u32 DENALI_PHY_77;
+	volatile u32 DENALI_PHY_78;
+	volatile u32 DENALI_PHY_79;
+	volatile u32 DENALI_PHY_80;
+	volatile u32 DENALI_PHY_81;
+	volatile u32 DENALI_PHY_82;
+	volatile u32 DENALI_PHY_83;
+	volatile u32 DENALI_PHY_84;
+	volatile u32 DENALI_PHY_85;
+	volatile u32 DENALI_PHY_86;
+	volatile u32 DENALI_PHY_87;
+	volatile u32 DENALI_PHY_88;
+	volatile u32 DENALI_PHY_89;
+	volatile u32 DENALI_PHY_90;
+	volatile u32 DENALI_PHY_91;
+	volatile u32 DENALI_PHY_92;
+	volatile u32 DENALI_PHY_93;
+	volatile u32 DENALI_PHY_94;
+	volatile u32 DENALI_PHY_95;
+	volatile u32 DENALI_PHY_96;
+	volatile u32 DENALI_PHY_97;
+	volatile u32 DENALI_PHY_98;
+	volatile u32 DENALI_PHY_99;
+	volatile u32 DENALI_PHY_100;
+	volatile u32 DENALI_PHY_101;
+	volatile u32 DENALI_PHY_102;
+	volatile u32 DENALI_PHY_103;
+	volatile u32 DENALI_PHY_104;
+	volatile u32 DENALI_PHY_105;
+	volatile u32 DENALI_PHY_106;
+	volatile u32 DENALI_PHY_107;
+	volatile u32 DENALI_PHY_108;
+	volatile u32 DENALI_PHY_109;
+	volatile u32 DENALI_PHY_110;
+	volatile u32 DENALI_PHY_111;
+	volatile u32 DENALI_PHY_112;
+	volatile u32 DENALI_PHY_113;
+	volatile u32 DENALI_PHY_114;
+	volatile u32 DENALI_PHY_115;
+	volatile u32 DENALI_PHY_116;
+	volatile u32 DENALI_PHY_117;
+	volatile u32 DENALI_PHY_118;
+	volatile u32 DENALI_PHY_119;
+	volatile u32 DENALI_PHY_120;
+	volatile u32 DENALI_PHY_121;
+	volatile u32 DENALI_PHY_122;
+	volatile u32 DENALI_PHY_123;
+	volatile u32 DENALI_PHY_124;
+	volatile u32 DENALI_PHY_125;
+	volatile char pad__2[0x208U];
+	volatile u32 DENALI_PHY_256;
+	volatile u32 DENALI_PHY_257;
+	volatile u32 DENALI_PHY_258;
+	volatile u32 DENALI_PHY_259;
+	volatile u32 DENALI_PHY_260;
+	volatile u32 DENALI_PHY_261;
+	volatile u32 DENALI_PHY_262;
+	volatile u32 DENALI_PHY_263;
+	volatile u32 DENALI_PHY_264;
+	volatile u32 DENALI_PHY_265;
+	volatile u32 DENALI_PHY_266;
+	volatile u32 DENALI_PHY_267;
+	volatile u32 DENALI_PHY_268;
+	volatile u32 DENALI_PHY_269;
+	volatile u32 DENALI_PHY_270;
+	volatile u32 DENALI_PHY_271;
+	volatile u32 DENALI_PHY_272;
+	volatile u32 DENALI_PHY_273;
+	volatile u32 DENALI_PHY_274;
+	volatile u32 DENALI_PHY_275;
+	volatile u32 DENALI_PHY_276;
+	volatile u32 DENALI_PHY_277;
+	volatile u32 DENALI_PHY_278;
+	volatile u32 DENALI_PHY_279;
+	volatile u32 DENALI_PHY_280;
+	volatile u32 DENALI_PHY_281;
+	volatile u32 DENALI_PHY_282;
+	volatile u32 DENALI_PHY_283;
+	volatile u32 DENALI_PHY_284;
+	volatile u32 DENALI_PHY_285;
+	volatile u32 DENALI_PHY_286;
+	volatile u32 DENALI_PHY_287;
+	volatile u32 DENALI_PHY_288;
+	volatile u32 DENALI_PHY_289;
+	volatile u32 DENALI_PHY_290;
+	volatile u32 DENALI_PHY_291;
+	volatile u32 DENALI_PHY_292;
+	volatile u32 DENALI_PHY_293;
+	volatile u32 DENALI_PHY_294;
+	volatile u32 DENALI_PHY_295;
+	volatile u32 DENALI_PHY_296;
+	volatile u32 DENALI_PHY_297;
+	volatile u32 DENALI_PHY_298;
+	volatile u32 DENALI_PHY_299;
+	volatile u32 DENALI_PHY_300;
+	volatile u32 DENALI_PHY_301;
+	volatile u32 DENALI_PHY_302;
+	volatile u32 DENALI_PHY_303;
+	volatile u32 DENALI_PHY_304;
+	volatile u32 DENALI_PHY_305;
+	volatile u32 DENALI_PHY_306;
+	volatile u32 DENALI_PHY_307;
+	volatile u32 DENALI_PHY_308;
+	volatile u32 DENALI_PHY_309;
+	volatile u32 DENALI_PHY_310;
+	volatile u32 DENALI_PHY_311;
+	volatile u32 DENALI_PHY_312;
+	volatile u32 DENALI_PHY_313;
+	volatile u32 DENALI_PHY_314;
+	volatile u32 DENALI_PHY_315;
+	volatile u32 DENALI_PHY_316;
+	volatile u32 DENALI_PHY_317;
+	volatile u32 DENALI_PHY_318;
+	volatile u32 DENALI_PHY_319;
+	volatile u32 DENALI_PHY_320;
+	volatile u32 DENALI_PHY_321;
+	volatile u32 DENALI_PHY_322;
+	volatile u32 DENALI_PHY_323;
+	volatile u32 DENALI_PHY_324;
+	volatile u32 DENALI_PHY_325;
+	volatile u32 DENALI_PHY_326;
+	volatile u32 DENALI_PHY_327;
+	volatile u32 DENALI_PHY_328;
+	volatile u32 DENALI_PHY_329;
+	volatile u32 DENALI_PHY_330;
+	volatile u32 DENALI_PHY_331;
+	volatile u32 DENALI_PHY_332;
+	volatile u32 DENALI_PHY_333;
+	volatile u32 DENALI_PHY_334;
+	volatile u32 DENALI_PHY_335;
+	volatile u32 DENALI_PHY_336;
+	volatile u32 DENALI_PHY_337;
+	volatile u32 DENALI_PHY_338;
+	volatile u32 DENALI_PHY_339;
+	volatile u32 DENALI_PHY_340;
+	volatile u32 DENALI_PHY_341;
+	volatile u32 DENALI_PHY_342;
+	volatile u32 DENALI_PHY_343;
+	volatile u32 DENALI_PHY_344;
+	volatile u32 DENALI_PHY_345;
+	volatile u32 DENALI_PHY_346;
+	volatile u32 DENALI_PHY_347;
+	volatile u32 DENALI_PHY_348;
+	volatile u32 DENALI_PHY_349;
+	volatile u32 DENALI_PHY_350;
+	volatile u32 DENALI_PHY_351;
+	volatile u32 DENALI_PHY_352;
+	volatile u32 DENALI_PHY_353;
+	volatile u32 DENALI_PHY_354;
+	volatile u32 DENALI_PHY_355;
+	volatile u32 DENALI_PHY_356;
+	volatile u32 DENALI_PHY_357;
+	volatile u32 DENALI_PHY_358;
+	volatile u32 DENALI_PHY_359;
+	volatile u32 DENALI_PHY_360;
+	volatile u32 DENALI_PHY_361;
+	volatile u32 DENALI_PHY_362;
+	volatile u32 DENALI_PHY_363;
+	volatile u32 DENALI_PHY_364;
+	volatile u32 DENALI_PHY_365;
+	volatile u32 DENALI_PHY_366;
+	volatile u32 DENALI_PHY_367;
+	volatile u32 DENALI_PHY_368;
+	volatile u32 DENALI_PHY_369;
+	volatile u32 DENALI_PHY_370;
+	volatile u32 DENALI_PHY_371;
+	volatile u32 DENALI_PHY_372;
+	volatile u32 DENALI_PHY_373;
+	volatile u32 DENALI_PHY_374;
+	volatile u32 DENALI_PHY_375;
+	volatile u32 DENALI_PHY_376;
+	volatile u32 DENALI_PHY_377;
+	volatile u32 DENALI_PHY_378;
+	volatile u32 DENALI_PHY_379;
+	volatile u32 DENALI_PHY_380;
+	volatile u32 DENALI_PHY_381;
+	volatile char pad__3[0x208U];
+	volatile u32 DENALI_PHY_512;
+	volatile u32 DENALI_PHY_513;
+	volatile u32 DENALI_PHY_514;
+	volatile u32 DENALI_PHY_515;
+	volatile u32 DENALI_PHY_516;
+	volatile u32 DENALI_PHY_517;
+	volatile u32 DENALI_PHY_518;
+	volatile u32 DENALI_PHY_519;
+	volatile u32 DENALI_PHY_520;
+	volatile u32 DENALI_PHY_521;
+	volatile u32 DENALI_PHY_522;
+	volatile u32 DENALI_PHY_523;
+	volatile u32 DENALI_PHY_524;
+	volatile u32 DENALI_PHY_525;
+	volatile u32 DENALI_PHY_526;
+	volatile u32 DENALI_PHY_527;
+	volatile u32 DENALI_PHY_528;
+	volatile u32 DENALI_PHY_529;
+	volatile u32 DENALI_PHY_530;
+	volatile u32 DENALI_PHY_531;
+	volatile u32 DENALI_PHY_532;
+	volatile u32 DENALI_PHY_533;
+	volatile u32 DENALI_PHY_534;
+	volatile u32 DENALI_PHY_535;
+	volatile u32 DENALI_PHY_536;
+	volatile u32 DENALI_PHY_537;
+	volatile u32 DENALI_PHY_538;
+	volatile u32 DENALI_PHY_539;
+	volatile u32 DENALI_PHY_540;
+	volatile u32 DENALI_PHY_541;
+	volatile u32 DENALI_PHY_542;
+	volatile u32 DENALI_PHY_543;
+	volatile u32 DENALI_PHY_544;
+	volatile u32 DENALI_PHY_545;
+	volatile u32 DENALI_PHY_546;
+	volatile u32 DENALI_PHY_547;
+	volatile u32 DENALI_PHY_548;
+	volatile u32 DENALI_PHY_549;
+	volatile u32 DENALI_PHY_550;
+	volatile u32 DENALI_PHY_551;
+	volatile u32 DENALI_PHY_552;
+	volatile u32 DENALI_PHY_553;
+	volatile u32 DENALI_PHY_554;
+	volatile char pad__4[0x354U];
+	volatile u32 DENALI_PHY_768;
+	volatile u32 DENALI_PHY_769;
+	volatile u32 DENALI_PHY_770;
+	volatile u32 DENALI_PHY_771;
+	volatile u32 DENALI_PHY_772;
+	volatile u32 DENALI_PHY_773;
+	volatile u32 DENALI_PHY_774;
+	volatile u32 DENALI_PHY_775;
+	volatile u32 DENALI_PHY_776;
+	volatile u32 DENALI_PHY_777;
+	volatile u32 DENALI_PHY_778;
+	volatile u32 DENALI_PHY_779;
+	volatile u32 DENALI_PHY_780;
+	volatile u32 DENALI_PHY_781;
+	volatile u32 DENALI_PHY_782;
+	volatile u32 DENALI_PHY_783;
+	volatile u32 DENALI_PHY_784;
+	volatile u32 DENALI_PHY_785;
+	volatile u32 DENALI_PHY_786;
+	volatile u32 DENALI_PHY_787;
+	volatile u32 DENALI_PHY_788;
+	volatile u32 DENALI_PHY_789;
+	volatile u32 DENALI_PHY_790;
+	volatile u32 DENALI_PHY_791;
+	volatile u32 DENALI_PHY_792;
+	volatile u32 DENALI_PHY_793;
+	volatile u32 DENALI_PHY_794;
+	volatile u32 DENALI_PHY_795;
+	volatile u32 DENALI_PHY_796;
+	volatile u32 DENALI_PHY_797;
+	volatile u32 DENALI_PHY_798;
+	volatile u32 DENALI_PHY_799;
+	volatile u32 DENALI_PHY_800;
+	volatile u32 DENALI_PHY_801;
+	volatile u32 DENALI_PHY_802;
+	volatile u32 DENALI_PHY_803;
+	volatile u32 DENALI_PHY_804;
+	volatile u32 DENALI_PHY_805;
+	volatile u32 DENALI_PHY_806;
+	volatile u32 DENALI_PHY_807;
+	volatile u32 DENALI_PHY_808;
+	volatile u32 DENALI_PHY_809;
+	volatile u32 DENALI_PHY_810;
+	volatile char pad__5[0x354U];
+	volatile u32 DENALI_PHY_1024;
+	volatile u32 DENALI_PHY_1025;
+	volatile u32 DENALI_PHY_1026;
+	volatile u32 DENALI_PHY_1027;
+	volatile u32 DENALI_PHY_1028;
+	volatile u32 DENALI_PHY_1029;
+	volatile u32 DENALI_PHY_1030;
+	volatile u32 DENALI_PHY_1031;
+	volatile u32 DENALI_PHY_1032;
+	volatile u32 DENALI_PHY_1033;
+	volatile u32 DENALI_PHY_1034;
+	volatile u32 DENALI_PHY_1035;
+	volatile u32 DENALI_PHY_1036;
+	volatile u32 DENALI_PHY_1037;
+	volatile u32 DENALI_PHY_1038;
+	volatile u32 DENALI_PHY_1039;
+	volatile u32 DENALI_PHY_1040;
+	volatile u32 DENALI_PHY_1041;
+	volatile u32 DENALI_PHY_1042;
+	volatile u32 DENALI_PHY_1043;
+	volatile u32 DENALI_PHY_1044;
+	volatile u32 DENALI_PHY_1045;
+	volatile u32 DENALI_PHY_1046;
+	volatile u32 DENALI_PHY_1047;
+	volatile u32 DENALI_PHY_1048;
+	volatile u32 DENALI_PHY_1049;
+	volatile u32 DENALI_PHY_1050;
+	volatile u32 DENALI_PHY_1051;
+	volatile u32 DENALI_PHY_1052;
+	volatile u32 DENALI_PHY_1053;
+	volatile u32 DENALI_PHY_1054;
+	volatile u32 DENALI_PHY_1055;
+	volatile u32 DENALI_PHY_1056;
+	volatile u32 DENALI_PHY_1057;
+	volatile u32 DENALI_PHY_1058;
+	volatile u32 DENALI_PHY_1059;
+	volatile u32 DENALI_PHY_1060;
+	volatile u32 DENALI_PHY_1061;
+	volatile u32 DENALI_PHY_1062;
+	volatile u32 DENALI_PHY_1063;
+	volatile u32 DENALI_PHY_1064;
+	volatile u32 DENALI_PHY_1065;
+	volatile u32 DENALI_PHY_1066;
+	volatile char pad__6[0x354U];
+	volatile u32 DENALI_PHY_1280;
+	volatile u32 DENALI_PHY_1281;
+	volatile u32 DENALI_PHY_1282;
+	volatile u32 DENALI_PHY_1283;
+	volatile u32 DENALI_PHY_1284;
+	volatile u32 DENALI_PHY_1285;
+	volatile u32 DENALI_PHY_1286;
+	volatile u32 DENALI_PHY_1287;
+	volatile u32 DENALI_PHY_1288;
+	volatile u32 DENALI_PHY_1289;
+	volatile u32 DENALI_PHY_1290;
+	volatile u32 DENALI_PHY_1291;
+	volatile u32 DENALI_PHY_1292;
+	volatile u32 DENALI_PHY_1293;
+	volatile u32 DENALI_PHY_1294;
+	volatile u32 DENALI_PHY_1295;
+	volatile u32 DENALI_PHY_1296;
+	volatile u32 DENALI_PHY_1297;
+	volatile u32 DENALI_PHY_1298;
+	volatile u32 DENALI_PHY_1299;
+	volatile u32 DENALI_PHY_1300;
+	volatile u32 DENALI_PHY_1301;
+	volatile u32 DENALI_PHY_1302;
+	volatile u32 DENALI_PHY_1303;
+	volatile u32 DENALI_PHY_1304;
+	volatile u32 DENALI_PHY_1305;
+	volatile u32 DENALI_PHY_1306;
+	volatile u32 DENALI_PHY_1307;
+	volatile u32 DENALI_PHY_1308;
+	volatile u32 DENALI_PHY_1309;
+	volatile u32 DENALI_PHY_1310;
+	volatile u32 DENALI_PHY_1311;
+	volatile u32 DENALI_PHY_1312;
+	volatile u32 DENALI_PHY_1313;
+	volatile u32 DENALI_PHY_1314;
+	volatile u32 DENALI_PHY_1315;
+	volatile u32 DENALI_PHY_1316;
+	volatile u32 DENALI_PHY_1317;
+	volatile u32 DENALI_PHY_1318;
+	volatile u32 DENALI_PHY_1319;
+	volatile u32 DENALI_PHY_1320;
+	volatile u32 DENALI_PHY_1321;
+	volatile u32 DENALI_PHY_1322;
+	volatile u32 DENALI_PHY_1323;
+	volatile u32 DENALI_PHY_1324;
+	volatile u32 DENALI_PHY_1325;
+	volatile u32 DENALI_PHY_1326;
+	volatile u32 DENALI_PHY_1327;
+	volatile u32 DENALI_PHY_1328;
+	volatile u32 DENALI_PHY_1329;
+	volatile u32 DENALI_PHY_1330;
+	volatile u32 DENALI_PHY_1331;
+	volatile u32 DENALI_PHY_1332;
+	volatile u32 DENALI_PHY_1333;
+	volatile u32 DENALI_PHY_1334;
+	volatile u32 DENALI_PHY_1335;
+	volatile u32 DENALI_PHY_1336;
+	volatile u32 DENALI_PHY_1337;
+	volatile u32 DENALI_PHY_1338;
+	volatile u32 DENALI_PHY_1339;
+	volatile u32 DENALI_PHY_1340;
+	volatile u32 DENALI_PHY_1341;
+	volatile u32 DENALI_PHY_1342;
+	volatile u32 DENALI_PHY_1343;
+	volatile u32 DENALI_PHY_1344;
+	volatile u32 DENALI_PHY_1345;
+	volatile u32 DENALI_PHY_1346;
+	volatile u32 DENALI_PHY_1347;
+	volatile u32 DENALI_PHY_1348;
+	volatile u32 DENALI_PHY_1349;
+	volatile u32 DENALI_PHY_1350;
+	volatile u32 DENALI_PHY_1351;
+	volatile u32 DENALI_PHY_1352;
+	volatile u32 DENALI_PHY_1353;
+	volatile u32 DENALI_PHY_1354;
+	volatile u32 DENALI_PHY_1355;
+	volatile u32 DENALI_PHY_1356;
+	volatile u32 DENALI_PHY_1357;
+	volatile u32 DENALI_PHY_1358;
+	volatile u32 DENALI_PHY_1359;
+	volatile u32 DENALI_PHY_1360;
+	volatile u32 DENALI_PHY_1361;
+	volatile u32 DENALI_PHY_1362;
+	volatile u32 DENALI_PHY_1363;
+	volatile u32 DENALI_PHY_1364;
+	volatile u32 DENALI_PHY_1365;
+	volatile u32 DENALI_PHY_1366;
+	volatile u32 DENALI_PHY_1367;
+	volatile u32 DENALI_PHY_1368;
+	volatile u32 DENALI_PHY_1369;
+	volatile u32 DENALI_PHY_1370;
+	volatile u32 DENALI_PHY_1371;
+	volatile u32 DENALI_PHY_1372;
+	volatile u32 DENALI_PHY_1373;
+	volatile u32 DENALI_PHY_1374;
+	volatile u32 DENALI_PHY_1375;
+	volatile u32 DENALI_PHY_1376;
+	volatile u32 DENALI_PHY_1377;
+	volatile u32 DENALI_PHY_1378;
+	volatile u32 DENALI_PHY_1379;
+	volatile u32 DENALI_PHY_1380;
+	volatile u32 DENALI_PHY_1381;
+	volatile u32 DENALI_PHY_1382;
+	volatile u32 DENALI_PHY_1383;
+	volatile u32 DENALI_PHY_1384;
+	volatile u32 DENALI_PHY_1385;
+	volatile u32 DENALI_PHY_1386;
+	volatile u32 DENALI_PHY_1387;
+	volatile u32 DENALI_PHY_1388;
+	volatile u32 DENALI_PHY_1389;
+	volatile u32 DENALI_PHY_1390;
+	volatile u32 DENALI_PHY_1391;
+	volatile u32 DENALI_PHY_1392;
+	volatile u32 DENALI_PHY_1393;
+	volatile u32 DENALI_PHY_1394;
+	volatile u32 DENALI_PHY_1395;
+	volatile u32 DENALI_PHY_1396;
+	volatile u32 DENALI_PHY_1397;
+	volatile u32 DENALI_PHY_1398;
+	volatile u32 DENALI_PHY_1399;
+	volatile u32 DENALI_PHY_1400;
+	volatile u32 DENALI_PHY_1401;
+	volatile u32 DENALI_PHY_1402;
+	volatile u32 DENALI_PHY_1403;
+	volatile u32 DENALI_PHY_1404;
+	volatile u32 DENALI_PHY_1405;
+} lpddr4_ctlregs;
+
+#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
new file mode 100644
index 0000000000..d46b77b23f
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_RW_MASKS_H_
+#define LPDDR4_RW_MASKS_H_
+
+#include <stdint.h>
+
+extern u32 g_lpddr4_ddr_controller_rw_mask[423];
+extern u32 g_lpddr4_pi_rw_mask[345];
+extern u32 g_lpddr4_data_slice_0_rw_mask[126];
+extern u32 g_lpddr4_data_slice_1_rw_mask[126];
+extern u32 g_lpddr4_address_slice_0_rw_mask[43];
+extern u32 g_lpddr4_address_slice_1_rw_mask[43];
+extern u32 g_lpddr4_address_slice_2_rw_mask[43];
+extern u32 g_lpddr4_phy_core_rw_mask[126];
+
+#endif /* LPDDR4_RW_MASKS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
new file mode 100644
index 0000000000..d3bf24e677
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
@@ -0,0 +1,2036 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_0_READ_MASK                               0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK                              0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_MASK    0x00000007U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_WIDTH            3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_MASK  0x00007F00U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_WIDTH          7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK   0x07FF0000U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1_READ_MASK                               0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK                              0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK  0x0000000FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH          4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH       10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK   0x07000000U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH           3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_2_READ_MASK                               0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK                              0x010303FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT       0U
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK     0x00030000U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH             2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET                 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_3_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5_READ_MASK                               0x1F030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK                              0x1F030F3FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK               0x0000003FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH                       6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK              0x00000F00U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH                      4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH           2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH              5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_6_READ_MASK                               0x030F0F1FU
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK                              0x030F0F1FU
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH                4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT      16U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH       4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT       24U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH        2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_7_READ_MASK                               0x01FF031FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK                              0x01FF031FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK   0x0000001FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH           5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_MASK                0x00000300U
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_WIDTH                        2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_WIDTH                        9U
+#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_8_READ_MASK                               0x00000101U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK                              0x00000101U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET                 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOSET             0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__FLD LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_9_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK  0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH         32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_10_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK     0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH            28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_11_READ_MASK                              0x7F0101FFU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_MASK                    0x000001FFU
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_SHIFT                            0U
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_WIDTH                            9U
+#define LPDDR4__PHY_DQ_IDLE_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_DQ_IDLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_MASK                0x00010000U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOSET                        0U
+#define LPDDR4__PHY_PDA_MODE_EN_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PDA_MODE_EN_0__FLD LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK         0x7F000000U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH                 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_12_READ_MASK                              0x010101FFU
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_MASK          0x000001FFU
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_WIDTH                  9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET            0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT      24U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH       1U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR       0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET       0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_13_READ_MASK                              0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH              6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_MASK             0x00007F00U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_WIDTH                     7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_14_READ_MASK                              0x01FF000FU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0
+
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_MASK           0x00000100U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOSET                   0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_14
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_15_READ_MASK                              0x01FF0701U
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_MASK                      0x00000001U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_SHIFT                              0U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WIDTH                              1U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOCLR                              0U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOSET                              0U
+#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_15__PHY_LPDDR_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_MASK                  0x00000700U
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_WIDTH                          3U
+#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_16_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_MASK          0x00000003U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_WIDTH                  2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_16
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0
+
+#define LPDDR4__DENALI_PHY_17_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_17
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0
+
+#define LPDDR4__DENALI_PHY_18_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_WIDTH                      2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_18
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0
+
+#define LPDDR4__DENALI_PHY_19_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_WIDTH                       32U
+#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0
+
+#define LPDDR4__DENALI_PHY_20_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_WIDTH                       32U
+#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_20
+#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0
+
+#define LPDDR4__DENALI_PHY_21_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_21
+#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0
+
+#define LPDDR4__DENALI_PHY_22_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_22
+#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0
+
+#define LPDDR4__DENALI_PHY_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_23
+#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0
+
+#define LPDDR4__DENALI_PHY_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_24
+#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0
+
+#define LPDDR4__DENALI_PHY_25_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_25
+#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0
+
+#define LPDDR4__DENALI_PHY_26_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0
+
+#define LPDDR4__DENALI_PHY_27_READ_MASK                              0x070F0107U
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK      0x00000007U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH              3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK    0x00000100U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET            0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH         4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_MASK        0x07000000U
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH                3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_MASK          0x00000F00U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_WIDTH                  4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH                4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH                4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29_READ_MASK                              0x3F030001U
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOSET                     0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOSET                  0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_29
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_MASK                 0x00030000U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_WIDTH                         2U
+#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_30_READ_MASK                              0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_WIDTH                            8U
+#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK          0x003F0000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31_READ_MASK                              0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK          0x0000003FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK              0x00030000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH                      2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK  0x1F000000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH          5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_32_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH                    8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_MASK         0x03FFFF00U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_WIDTH                18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0
+
+#define LPDDR4__DENALI_PHY_33_READ_MASK                              0x00073FFFU
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_WIDTH                   6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH                        3U
+#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0
+
+#define LPDDR4__DENALI_PHY_34_READ_MASK                              0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT    0U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH   11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK     0x0F000000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH             4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_35_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH         8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_WIDTH                8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_MASK         0x000F0000U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_WIDTH                 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH         1U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR         0U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET         0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_35
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
+
+#define LPDDR4__DENALI_PHY_36_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_WIDTH                 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0
+
+#define LPDDR4__DENALI_PHY_37_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_37
+#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0
+
+#define LPDDR4__DENALI_PHY_38_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_38
+#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0
+
+#define LPDDR4__DENALI_PHY_39_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_39
+#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0
+
+#define LPDDR4__DENALI_PHY_40_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_40
+#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0
+
+#define LPDDR4__DENALI_PHY_41_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_WIDTH                        16U
+#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0
+
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_MASK             0x00010000U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOSET                     0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0
+
+#define LPDDR4__DENALI_PHY_42_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_MASK        0x000003FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_WIDTH               10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_MASK       0x03FF0000U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH              10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_43_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0
+
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK   0x03FF0000U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0
+
+#define LPDDR4__DENALI_PHY_44_READ_MASK                              0x00FF0001U
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET           0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0
+
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_WIDTH                    6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_44
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_MASK               0x00FF0000U
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_WIDTH                       8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0
+
+#define LPDDR4__DENALI_PHY_45_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_WIDTH                   32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_46_READ_MASK                              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_MASK       0x0000FFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH              16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_MASK        0x07FF0000U
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_47_READ_MASK                              0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK       0x0000007FU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH               7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_MASK        0x00FF0000U
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH                8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48_READ_MASK                              0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH        11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49_READ_MASK                              0x0007FFFFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK  0x000000FFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH          8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH           8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_WIDTH                       3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_50_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK      0x000003FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_51_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_WIDTH                  21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_52_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_53_READ_MASK                              0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK                             0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK      0x00003FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK      0x3FFF0000U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_54_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH                  18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_55_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_56_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH     2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
+
+#define LPDDR4__DENALI_PHY_57_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH                  32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_58_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_59_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_59
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_60_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH               32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0
+
+#define LPDDR4__DENALI_PHY_61_READ_MASK                              0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_MASK                   0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_WIDTH                          31U
+#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_61
+#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_62_READ_MASK                              0x0000003FU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_WIDTH                           6U
+#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_62
+#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_63_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_WIDTH                      32U
+#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_63
+#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_64_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH             32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_64
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_65_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH            8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOSET                 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0
+
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0
+
+#define LPDDR4__DENALI_PHY_66_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0
+
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0
+
+#define LPDDR4__DENALI_PHY_67_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0
+
+#define LPDDR4__DENALI_PHY_68_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0
+
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0
+
+#define LPDDR4__DENALI_PHY_69_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0
+
+#define LPDDR4__DENALI_PHY_70_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_MASK                  0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_WIDTH                         18U
+#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0
+
+#define LPDDR4__DENALI_PHY_71_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0
+
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0
+
+#define LPDDR4__DENALI_PHY_72_READ_MASK                              0x071F07FFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK                             0x071F07FFU
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_WIDTH                    11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0
+
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_MASK         0x001F0000U
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_WIDTH                 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_MASK              0x07000000U
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_WIDTH                      3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_73_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET          0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WIDTH                1U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOCLR                0U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOSET                0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET        0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET              0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_74_READ_MASK                              0x07FFFF07U
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_MASK             0x00000007U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_WIDTH                     3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_MASK             0x00FFFF00U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_WIDTH                    16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_MASK            0x07000000U
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_WIDTH                    3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_75_READ_MASK                              0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_WIDTH                   16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_WIDTH                   2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_MASK   0x7F000000U
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0
+
+#define LPDDR4__DENALI_PHY_76_READ_MASK                              0xFF01037FU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_MASK    0x0000007FU
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH            7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_MASK         0x00000300U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_WIDTH                 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOSET                       0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_MASK          0xFF000000U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH                  8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0
+
+#define LPDDR4__DENALI_PHY_77_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_MASK              0x000007FFU
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_MASK               0x07FF0000U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_WIDTH                      11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0
+
+#define LPDDR4__DENALI_PHY_78_READ_MASK                              0x0103FFFFU
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_MASK             0x000000FFU
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_WIDTH                     8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_MASK             0x0003FF00U
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_WIDTH                    10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET               0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_79_READ_MASK                              0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_MASK    0x0000003FU
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH            6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_MASK                0x00000F00U
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_WIDTH                        4U
+#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_MASK                 0x001F0000U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_WIDTH                         5U
+#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0
+
+#define LPDDR4__DENALI_PHY_80_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0
+
+#define LPDDR4__DENALI_PHY_81_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_WIDTH                      5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82_READ_MASK                              0x007F1F1FU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_WIDTH                    5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_MASK          0x007F0000U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_WIDTH                  7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_83_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_84_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_85_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_86_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_87_READ_MASK                              0x1F0703FFU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_WIDTH                  10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_MASK            0x00070000U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_WIDTH                    3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_WIDTH                     5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0
+
+#define LPDDR4__DENALI_PHY_88_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_MASK               0x000000FFU
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_WIDTH                       8U
+#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_MASK          0x0000FF00U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_WIDTH                  8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_WIDTH                  8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_MASK              0xFF000000U
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_WIDTH                      8U
+#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89_READ_MASK                              0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_WIDTH                4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_WIDTH                 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_MASK           0x00FF0000U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_WIDTH                   8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_WIDTH                 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_90_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_WIDTH                 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_MASK           0x0FFF0000U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_WIDTH                  12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0
+
+#define LPDDR4__DENALI_PHY_91_READ_MASK                              0x0303FFFFU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK                             0x0303FFFFU
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_MASK               0x000000FFU
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_WIDTH                       8U
+#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_WIDTH                      8U
+#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_WIDTH                   2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_MASK                    0x03000000U
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_SHIFT                           24U
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_WIDTH                            2U
+#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_92_READ_MASK                              0x1F1F0103U
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_WIDTH                           2U
+#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_MASK               0x00000100U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOSET                       0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_WIDTH               5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_MASK  0x1F000000U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_WIDTH          5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93_READ_MASK                              0x000F1F1FU
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK                             0x000F1F1FU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_MASK         0x0000001FU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH                 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_WIDTH                   5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_MASK             0x000F0000U
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_WIDTH                     4U
+#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_94_READ_MASK                              0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_WIDTH                11U
+#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_MASK          0x003F0000U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_WIDTH                  6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_MASK          0xFF000000U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_WIDTH                  8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_95_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK  0x000000FFU
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH          8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_MASK                0x00000F00U
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_WIDTH                        4U
+#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_WIDTH                     8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH                4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0
+
+#define LPDDR4__DENALI_PHY_96_READ_MASK                              0x001F0F3FU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_MASK        0x0000003FU
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH                6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_WIDTH                     4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH                5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_97_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_WIDTH                   10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_MASK           0x03FF0000U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0
+
+#define LPDDR4__DENALI_PHY_98_READ_MASK                              0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_WIDTH                    8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH                4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_WIDTH             9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0
+
+#define LPDDR4__DENALI_PHY_99_READ_MASK                              0x00000F01U
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOSET                 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_WIDTH                     4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_100_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0
+
+#define LPDDR4__DENALI_PHY_101_READ_MASK                             0x7F7F0703U
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK                            0x7F7F0703U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_MASK             0x007F0000U
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_MASK      0x7F000000U
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_102_READ_MASK                             0x0000001FU
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK                            0x0000001FU
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_103_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_104_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_105_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_106_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_107_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_110_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_111_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_112_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT      16U
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_121_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0
+
+#define LPDDR4__DENALI_PHY_122_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0
+
+#define LPDDR4__DENALI_PHY_123_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0
+
+#define LPDDR4__DENALI_PHY_124_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_125_READ_MASK                             0x003FFFFFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK                            0x003FFFFFU
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
+
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
+
+#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
new file mode 100644
index 0000000000..d60bb6afe8
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
@@ -0,0 +1,2036 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_256_READ_MASK                             0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK                            0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_WIDTH        7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_257_READ_MASK                             0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK                            0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT      8U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_258_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK                            0x010303FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_259_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK                            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH                     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH                    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK    0x1F000000U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_262_READ_MASK                             0x030F0F1FU
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK                            0x030F0F1FU
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT       0U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK      0x00000F00U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT    16U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT     24U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_263_READ_MASK                             0x01FF031FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK                            0x01FF031FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_MASK              0x00000300U
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_WIDTH                      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_MASK              0x01FF0000U
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_WIDTH                      9U
+#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_264_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOSET           0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__FLD LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_265_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_266_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_267_READ_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK                            0x7F0101FFU
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_WIDTH                           9U
+#define LPDDR4__PHY_DQ_IDLE_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_DQ_IDLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOSET                       0U
+#define LPDDR4__PHY_PDA_MODE_EN_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PDA_MODE_EN_1__FLD LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK        0x7F000000U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT               24U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH                7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_268_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_WIDTH                 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT     24U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH      1U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR      0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_269_READ_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK                            0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_MASK            0x00007F00U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_WIDTH                    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_270_READ_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK                            0x01FF000FU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1
+
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOSET                  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_270
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_271_READ_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK                            0x01FF0701U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_MASK                     0x00000001U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_SHIFT                             0U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOSET                             0U
+#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_271__PHY_LPDDR_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_MASK                 0x00000700U
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_WIDTH                         3U
+#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_272_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_WIDTH                 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_272
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1
+
+#define LPDDR4__DENALI_PHY_273_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_WIDTH                32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_273
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1
+
+#define LPDDR4__DENALI_PHY_274_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_MASK             0x00000003U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_WIDTH                     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_274
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1
+
+#define LPDDR4__DENALI_PHY_275_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1
+
+#define LPDDR4__DENALI_PHY_276_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_276
+#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1
+
+#define LPDDR4__DENALI_PHY_277_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_277
+#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1
+
+#define LPDDR4__DENALI_PHY_278_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_278
+#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1
+
+#define LPDDR4__DENALI_PHY_279_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_279
+#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1
+
+#define LPDDR4__DENALI_PHY_280_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_280
+#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1
+
+#define LPDDR4__DENALI_PHY_281_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_281
+#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1
+
+#define LPDDR4__DENALI_PHY_282_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1
+
+#define LPDDR4__DENALI_PHY_283_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK                            0x070F0107U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_WIDTH                 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285_READ_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK                            0x3F030001U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOSET                    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOSET                 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_285
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_WIDTH                        2U
+#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_286_READ_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK                            0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_SHIFT                           8U
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_WIDTH                           8U
+#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK                            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH                     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_288_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH                   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_MASK        0x03FFFF00U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_WIDTH               18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1
+
+#define LPDDR4__DENALI_PHY_289_READ_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK                            0x00073FFFU
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT       0U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_MASK          0x00003F00U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_WIDTH                  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH                       3U
+#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1
+
+#define LPDDR4__DENALI_PHY_290_READ_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK                            0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT   0U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK      0x000F0000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK    0x0F000000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_291_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_WIDTH               8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_WIDTH                4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH        1U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR        0U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_291
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
+
+#define LPDDR4__DENALI_PHY_292_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_WIDTH                9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1
+
+#define LPDDR4__DENALI_PHY_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_293
+#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1
+
+#define LPDDR4__DENALI_PHY_294_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_294
+#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1
+
+#define LPDDR4__DENALI_PHY_295_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_295
+#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1
+
+#define LPDDR4__DENALI_PHY_296_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_296
+#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1
+
+#define LPDDR4__DENALI_PHY_297_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_WIDTH                       16U
+#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1
+
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOSET                    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1
+
+#define LPDDR4__DENALI_PHY_298_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_299_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1
+
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1
+
+#define LPDDR4__DENALI_PHY_300_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK                            0x00FF0001U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1
+
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_WIDTH                   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_300
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_WIDTH                      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1
+
+#define LPDDR4__DENALI_PHY_301_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_WIDTH                  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_302_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_303_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK                            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK                            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_WIDTH                      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_306_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_307_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_MASK          0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_WIDTH                 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_308_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_309_READ_MASK                             0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK                            0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_310_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH                 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_311_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_312_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT    0U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
+
+#define LPDDR4__DENALI_PHY_313_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH                 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_314_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_315_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_WIDTH                32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_315
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_316_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1
+
+#define LPDDR4__DENALI_PHY_317_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_WIDTH                         31U
+#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_317
+#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_318_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_WIDTH                          6U
+#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_318
+#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_319_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_WIDTH                     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_319
+#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_320_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_320
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_321_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOSET                0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1
+
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1
+
+#define LPDDR4__DENALI_PHY_322_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1
+
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1
+
+#define LPDDR4__DENALI_PHY_323_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1
+
+#define LPDDR4__DENALI_PHY_324_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1
+
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1
+
+#define LPDDR4__DENALI_PHY_325_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1
+
+#define LPDDR4__DENALI_PHY_326_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_WIDTH                        18U
+#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1
+
+#define LPDDR4__DENALI_PHY_327_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1
+
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_WIDTH                       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1
+
+#define LPDDR4__DENALI_PHY_328_READ_MASK                             0x071F07FFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK                            0x071F07FFU
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_WIDTH                   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1
+
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_WIDTH                5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_MASK             0x07000000U
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_WIDTH                     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_329_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH         1U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR         0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_MASK       0x00000100U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH       1U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR       0U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_330_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK                            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_WIDTH                    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_WIDTH                   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_WIDTH                   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_331_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK                            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_WIDTH                  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_WIDTH                  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_SHIFT         24U
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1
+
+#define LPDDR4__DENALI_PHY_332_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK                            0xFF01037FU
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_WIDTH                2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOSET                      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH                 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1
+
+#define LPDDR4__DENALI_PHY_333_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_WIDTH                    11U
+#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1
+
+#define LPDDR4__DENALI_PHY_334_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_WIDTH                    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_WIDTH                   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_335_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK                            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_WIDTH                       4U
+#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_WIDTH                        5U
+#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1
+
+#define LPDDR4__DENALI_PHY_336_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1
+
+#define LPDDR4__DENALI_PHY_337_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338_READ_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK                            0x007F1F1FU
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_WIDTH                    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_WIDTH                   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_MASK         0x007F0000U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_WIDTH                 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_339_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_340_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_341_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_342_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_343_READ_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK                            0x1F0703FFU
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_WIDTH                 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_MASK           0x00070000U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_WIDTH                   3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_WIDTH                    5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1
+
+#define LPDDR4__DENALI_PHY_344_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_WIDTH                      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_WIDTH                     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK                            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_WIDTH                  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_SHIFT               24U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_346_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_WIDTH                16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_WIDTH                 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1
+
+#define LPDDR4__DENALI_PHY_347_READ_MASK                             0x0303FFFFU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK                            0x0303FFFFU
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_WIDTH                      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_MASK             0x0000FF00U
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_WIDTH                     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_WIDTH                  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_MASK                   0x03000000U
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_SHIFT                          24U
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_WIDTH                           2U
+#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_348_READ_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK                            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_MASK                  0x00000003U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_WIDTH                          2U
+#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_MASK              0x00000100U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOSET                      0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_WIDTH              5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_WIDTH         5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349_READ_MASK                             0x000F1F1FU
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK                            0x000F1F1FU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_MASK        0x0000001FU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH                5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_MASK          0x00001F00U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_WIDTH                  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_WIDTH                    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_350_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_WIDTH                 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_WIDTH                 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_351_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_WIDTH                       4U
+#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_MASK            0x00FF0000U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_WIDTH                    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1
+
+#define LPDDR4__DENALI_PHY_352_READ_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK                            0x001F0F3FU
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_MASK       0x0000003FU
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_WIDTH                    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_353_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_WIDTH                 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1
+
+#define LPDDR4__DENALI_PHY_354_READ_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK                            0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_WIDTH                   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_WIDTH            9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1
+
+#define LPDDR4__DENALI_PHY_355_READ_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK                            0x00000F01U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOSET                0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_WIDTH                    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_356_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1
+
+#define LPDDR4__DENALI_PHY_357_READ_MASK                             0x7F7F0703U
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK                            0x7F7F0703U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_MASK             0x007F0000U
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_MASK      0x7F000000U
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_358_READ_MASK                             0x0000001FU
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK                            0x0000001FU
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_359_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_360_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_361_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_362_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_363_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_366_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_367_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_368_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_377_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH            1U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR            0U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1
+
+#define LPDDR4__DENALI_PHY_378_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1
+
+#define LPDDR4__DENALI_PHY_379_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1
+
+#define LPDDR4__DENALI_PHY_380_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_381_READ_MASK                             0x003FFFFFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK                            0x003FFFFFU
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
+
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
+
+#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
new file mode 100644
index 0000000000..3df803e9ef
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,6436 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK                               0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK                              0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH                                     1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET                                     0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH                                4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK                     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH                            16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK                               0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK                              0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH                               5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK                       0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH                               4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH                                2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK              0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH                      8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK          0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH                  8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK             0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH                     8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK         0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT                16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH                 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH                   16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK        0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT               16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH                8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH                          8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH                   8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK            0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH                    8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK          0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH                  8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK   0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT          24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH           8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK                          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH                                 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH                                24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH                                24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH                               24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH                                24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH                               24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH                               24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH                               24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH                                24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH                               24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH                               24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH                               24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET                         0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK                              0x03030301U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK                             0x03030301U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET                         0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F0__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F0__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_MASK                0x00030000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F1__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F1__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F2__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F2__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK                              0x01030101U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK                             0x01030101U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOSET                            0U
+#define LPDDR4__DFI_CMD_RATIO__REG DENALI_CTL_20
+#define LPDDR4__DFI_CMD_RATIO__FLD LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO
+
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOSET                              0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_20
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_20__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_WIDTH                                2U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_20
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_20__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK             0x01000000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET                     0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK                              0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK                             0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_MASK                    0x0000003FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_WIDTH                            6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_21
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_MASK              0x00000100U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOSET                      0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_21
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK                              0x0303031FU
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK                             0x0303031FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_22
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH                              32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK                     0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH                            32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_WIDTH                                 16U
+#define LPDDR4__TDLL_F0__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F0__FLD LPDDR4__DENALI_CTL_25__TDLL_F0
+
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_WIDTH                                 16U
+#define LPDDR4__TDLL_F1__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F1__FLD LPDDR4__DENALI_CTL_25__TDLL_F1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_WIDTH                                 16U
+#define LPDDR4__TDLL_F2__REG DENALI_CTL_26
+#define LPDDR4__TDLL_F2__FLD LPDDR4__DENALI_CTL_26__TDLL_F2
+
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOSET 0U
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__REG DENALI_CTL_26
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__FLD LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_SHIFT      24U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_WIDTH       2U
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOSET                              0U
+#define LPDDR4__DQS_OSC_TST__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_TST__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_TST
+
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_MASK                  0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_WIDTH                         24U
+#define LPDDR4__DQS_OSC_MPC_CMD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_MPC_CMD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_WIDTH                              8U
+#define LPDDR4__MRR_LSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_LSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_LSB_REG
+
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_WIDTH                              8U
+#define LPDDR4__MRR_MSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_MSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_MSB_REG
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOSET                           0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK                              0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK                             0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_MASK                   0x00007FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_WIDTH                          15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_WIDTH                        4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_29
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_WIDTH                  32U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_WIDTH                  32U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_31
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_WIDTH                         32U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_32
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_SHIFT                0U
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_WIDTH               32U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_33
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK                              0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK                             0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_MASK               0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_WIDTH                      16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_34
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOSET                          0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_34
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_WIDTH                                 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_34
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_34__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_WIDTH                                 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_35__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_MASK                         0x0000FF00U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_WIDTH                                 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_35__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_35
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_WIDTH                           4U
+#define LPDDR4__DQS_OSC_STATUS__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_MASK       0x01000000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_SHIFT              24U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WIDTH               1U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOCLR               0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOSET               0U
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_38
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_WIDTH                                 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_38
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_38__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F0__REG DENALI_CTL_38
+#define LPDDR4__ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F0__REG DENALI_CTL_38
+#define LPDDR4__CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F0__REG DENALI_CTL_39
+#define LPDDR4__TMOD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F0__REG DENALI_CTL_39
+#define LPDDR4__TMRD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__REG DENALI_CTL_39
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__REG DENALI_CTL_39
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_40
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_WIDTH                                 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_40
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_40__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F1__REG DENALI_CTL_40
+#define LPDDR4__ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F1__REG DENALI_CTL_40
+#define LPDDR4__CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F1__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F1__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_42
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_WIDTH                                 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_42
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_42__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F2__REG DENALI_CTL_42
+#define LPDDR4__ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F2__REG DENALI_CTL_42
+#define LPDDR4__CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F2__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F2__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK                              0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK                             0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_WIDTH                        3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_44
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_44__TCCD_MASK                             0x00001F00U
+#define LPDDR4__DENALI_CTL_44__TCCD_SHIFT                                     8U
+#define LPDDR4__DENALI_CTL_44__TCCD_WIDTH                                     5U
+#define LPDDR4__TCCD__REG DENALI_CTL_44
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_44__TCCD
+
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_MASK                        0x001F0000U
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_WIDTH                                5U
+#define LPDDR4__TCCD_L_F0__REG DENALI_CTL_44
+#define LPDDR4__TCCD_L_F0__FLD LPDDR4__DENALI_CTL_44__TCCD_L_F0
+
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_WIDTH                                  8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_44
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_44__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_WIDTH                                8U
+#define LPDDR4__TRRD_L_F0__REG DENALI_CTL_45
+#define LPDDR4__TRRD_L_F0__FLD LPDDR4__DENALI_CTL_45__TRRD_L_F0
+
+#define LPDDR4__DENALI_CTL_45__TRC_F0_MASK                           0x0001FF00U
+#define LPDDR4__DENALI_CTL_45__TRC_F0_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_45__TRC_F0_WIDTH                                   9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_45
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_45__TRC_F0
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_46
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_46__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_WIDTH                                  6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_46
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_WIDTH                                6U
+#define LPDDR4__TWTR_L_F0__REG DENALI_CTL_46
+#define LPDDR4__TWTR_L_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_L_F0
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_47__TRP_F0_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TRP_F0_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_47__TRP_F0_WIDTH                                   8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_47
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_47__TRP_F0
+
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_WIDTH                                  9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_47
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_47__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_WIDTH                                5U
+#define LPDDR4__TCCD_L_F1__REG DENALI_CTL_47
+#define LPDDR4__TCCD_L_F1__FLD LPDDR4__DENALI_CTL_47__TCCD_L_F1
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_WIDTH                                  8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_48
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_WIDTH                                8U
+#define LPDDR4__TRRD_L_F1__REG DENALI_CTL_48
+#define LPDDR4__TRRD_L_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_L_F1
+
+#define LPDDR4__DENALI_CTL_48__TRC_F1_MASK                           0x01FF0000U
+#define LPDDR4__DENALI_CTL_48__TRC_F1_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_48__TRC_F1_WIDTH                                   9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_48
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_48__TRC_F1
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_49
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_49__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_WIDTH                                  6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_49
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_WIDTH                                6U
+#define LPDDR4__TWTR_L_F1__REG DENALI_CTL_49
+#define LPDDR4__TWTR_L_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_L_F1
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_50__TRP_F1_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_50__TRP_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_50__TRP_F1_WIDTH                                   8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_50
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_50__TRP_F1
+
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_WIDTH                                  9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_50
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_50__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_WIDTH                                5U
+#define LPDDR4__TCCD_L_F2__REG DENALI_CTL_50
+#define LPDDR4__TCCD_L_F2__FLD LPDDR4__DENALI_CTL_50__TCCD_L_F2
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_WIDTH                                  8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_51
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_WIDTH                                8U
+#define LPDDR4__TRRD_L_F2__REG DENALI_CTL_51
+#define LPDDR4__TRRD_L_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_L_F2
+
+#define LPDDR4__DENALI_CTL_51__TRC_F2_MASK                           0x01FF0000U
+#define LPDDR4__DENALI_CTL_51__TRC_F2_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_51__TRC_F2_WIDTH                                   9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_51
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_51__TRC_F2
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_52
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_52__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_WIDTH                                  6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_52
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_WIDTH                                6U
+#define LPDDR4__TWTR_L_F2__REG DENALI_CTL_52
+#define LPDDR4__TWTR_L_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_L_F2
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_53__TRP_F2_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_53__TRP_F2_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_53__TRP_F2_WIDTH                                   8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_53
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_53__TRP_F2
+
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_WIDTH                                  9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_53
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_53__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_WIDTH                                  8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_53
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_53__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F0__REG DENALI_CTL_54
+#define LPDDR4__TRTP_AP_F0__FLD LPDDR4__DENALI_CTL_54__TRTP_AP_F0
+
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_WIDTH                                  8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_54
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_54__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_WIDTH                                  8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_54
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_54__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_55
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_55__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_WIDTH                                  5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_55
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_55__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK                              0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK                             0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_WIDTH                                8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_56
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_56__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_WIDTH                                6U
+#define LPDDR4__TCCDMW_F0__REG DENALI_CTL_56
+#define LPDDR4__TCCDMW_F0__FLD LPDDR4__DENALI_CTL_56__TCCDMW_F0
+
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_WIDTH                                  8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_56
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_MASK                       0xFF000000U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F1__REG DENALI_CTL_56
+#define LPDDR4__TRTP_AP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_AP_F1
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_WIDTH                                  8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_57
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_57__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_WIDTH                                  8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_57
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_57__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_58
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_58__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_WIDTH                                  5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_58
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_58__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK                              0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK                             0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_WIDTH                                8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_59
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_59__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_WIDTH                                6U
+#define LPDDR4__TCCDMW_F1__REG DENALI_CTL_59
+#define LPDDR4__TCCDMW_F1__FLD LPDDR4__DENALI_CTL_59__TCCDMW_F1
+
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_WIDTH                                  8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_59
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F2__REG DENALI_CTL_59
+#define LPDDR4__TRTP_AP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_AP_F2
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_WIDTH                                  8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_60
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_60__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_WIDTH                                  8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_60
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_60__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_61
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_61__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_WIDTH                                  5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_61
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_61__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK                              0x07073FFFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK                             0x07073FFFU
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_WIDTH                                8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_62
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_62__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_WIDTH                                6U
+#define LPDDR4__TCCDMW_F2__REG DENALI_CTL_62
+#define LPDDR4__TCCDMW_F2__FLD LPDDR4__DENALI_CTL_62__TCCDMW_F2
+
+#define LPDDR4__DENALI_CTL_62__TPPD_MASK                             0x00070000U
+#define LPDDR4__DENALI_CTL_62__TPPD_SHIFT                                    16U
+#define LPDDR4__DENALI_CTL_62__TPPD_WIDTH                                     3U
+#define LPDDR4__TPPD__REG DENALI_CTL_62
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_62__TPPD
+
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_WIDTH                             3U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_62
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_62__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK                              0xFFFF0107U
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK                             0xFFFF0107U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_WIDTH                             3U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_63
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_63__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOSET                              0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_63
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_63__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_WIDTH                                  8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_63
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_63__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_63__TWR_F0_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_63__TWR_F0_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_63__TWR_F0_WIDTH                                   8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_63
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_63__TWR_F0
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_WIDTH                                  8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_64
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_64__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_64__TWR_F1_MASK                           0x0000FF00U
+#define LPDDR4__DENALI_CTL_64__TWR_F1_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_64__TWR_F1_WIDTH                                   8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_64
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_64__TWR_F1
+
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_WIDTH                                  8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_64
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_64__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_64__TWR_F2_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_64__TWR_F2_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_64__TWR_F2_WIDTH                                   8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_64
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_64__TWR_F2
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK                              0x0101010FU
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK                             0x0101010FU
+#define LPDDR4__DENALI_CTL_65__TMRR_MASK                             0x0000000FU
+#define LPDDR4__DENALI_CTL_65__TMRR_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_65__TMRR_WIDTH                                     4U
+#define LPDDR4__TMRR__REG DENALI_CTL_65
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_65__TMRR
+
+#define LPDDR4__DENALI_CTL_65__AP_MASK                               0x00000100U
+#define LPDDR4__DENALI_CTL_65__AP_SHIFT                                       8U
+#define LPDDR4__DENALI_CTL_65__AP_WIDTH                                       1U
+#define LPDDR4__DENALI_CTL_65__AP_WOCLR                                       0U
+#define LPDDR4__DENALI_CTL_65__AP_WOSET                                       0U
+#define LPDDR4__AP__REG DENALI_CTL_65
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_65__AP
+
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOSET                             0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_65
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_65__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOSET                             0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_65
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_WIDTH                                  8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_66__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_WIDTH                                  8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_66__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_WIDTH                                  8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_66__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_66__BSTLEN_MASK                           0x3F000000U
+#define LPDDR4__DENALI_CTL_66__BSTLEN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_66__BSTLEN_WIDTH                                   6U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_66
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_66__BSTLEN
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_68
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_68
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOSET                          0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_68
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_WIDTH                        2U
+#define LPDDR4__ADDRESS_MIRRORING__REG DENALI_CTL_68
+#define LPDDR4__ADDRESS_MIRRORING__FLD LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK                              0x00010101U
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOSET                         0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_69
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOSET                             0U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_69
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_69__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOSET                             0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_69
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_69__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_MASK           0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_WIDTH                  26U
+#define LPDDR4__CA_PARITY_ERROR_INJECT__REG DENALI_CTL_70
+#define LPDDR4__CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK                              0x01010001U
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK                             0x01010001U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOSET                          0U
+#define LPDDR4__CA_PARITY_ERROR__REG DENALI_CTL_71
+#define LPDDR4__CA_PARITY_ERROR__FLD LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR
+
+#define LPDDR4__DENALI_CTL_71__AREFRESH_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WOSET                                 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_71
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_71__AREFRESH
+
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOSET                              0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_71
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_71__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOSET                              0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_71
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_71__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK                              0x03FF3F07U
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK                             0x03FF3F07U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_MASK               0x00000007U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_WIDTH                       3U
+#define LPDDR4__TRFC_OPT_THRESHOLD__REG DENALI_CTL_72
+#define LPDDR4__TRFC_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK  0x00003F00U
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT          8U
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH          6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_72
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_MASK                          0x03FF0000U
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_WIDTH                                 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_72
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_72__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73__TREF_F0_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73__TREF_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_73__TREF_F0_WIDTH                                 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_73
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_73__TREF_F0
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_WIDTH                                 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_74
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_74__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F1_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_75__TREF_F1_WIDTH                                 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_75
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_75__TREF_F1
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_WIDTH                                 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_76
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_76__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F2_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_77__TREF_F2_WIDTH                                 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_77
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_77__TREF_F2
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_MASK                    0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_WIDTH                           20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_78
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_78__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_79
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_79__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_80
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_80__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_81
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_81__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_82
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_82__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_83
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_83__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_84
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_84__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_84__PBR_EN_MASK                           0x01000000U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WIDTH                                   1U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WOCLR                                   0U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WOSET                                   0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_84
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_84__PBR_EN
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK                              0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK                             0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOSET                        0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_85
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_MASK                0x00FFFF00U
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_WIDTH                       16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_85
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_MASK            0x0F000000U
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_WIDTH                    4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_85
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK                              0x001F1F01U
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK                             0x001F1F01U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOSET                          0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_86
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_MASK       0x00001F00U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_SHIFT               8U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_WIDTH               5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_86
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_MASK      0x001F0000U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT             16U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH              5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_86
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_WIDTH                                16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_87
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_87__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_WIDTH                                16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_87
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_87__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_WIDTH                                16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_88
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_88__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_WIDTH                        32U
+#define LPDDR4__CTL_UNUSED_REG_0__REG DENALI_CTL_89
+#define LPDDR4__CTL_UNUSED_REG_0__FLD LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK                              0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK                             0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_WIDTH                                 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_90__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_MASK                         0x0000FF00U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_WIDTH                                 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_90__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_MASK                         0x00FF0000U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_WIDTH                                 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_90__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_WIDTH                               5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_90
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_90__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK                              0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK                             0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_91
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_91
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_91__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_MASK                        0x000F0000U
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_WIDTH                                4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_91
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_91__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_WIDTH                               5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_91
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_91__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK                              0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK                             0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_92
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_92
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_92__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_MASK                        0x000F0000U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_WIDTH                                4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_92
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_92__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_WIDTH                               5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_92
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_92__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK                              0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK                             0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_93
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_93
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_93__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_MASK                        0x000F0000U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_WIDTH                                4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_93
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_93__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_WIDTH                                5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_93
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_93__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK                              0x1F011F01U
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK                             0x1F011F01U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_WIDTH                                5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_WIDTH                                5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK                              0x00FFFF01U
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK                             0x00FFFF01U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_95
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_MASK                          0x00FFFF00U
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_WIDTH                                 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_95
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_95__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_WIDTH                                16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_96
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_96__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_WIDTH                                 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_96
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_96__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_WIDTH                                16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_97
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_97__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_WIDTH                                 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_97
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_97__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_WIDTH                                16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_98
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_98__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_WIDTH                                 16U
+#define LPDDR4__TXPR_F0__REG DENALI_CTL_98
+#define LPDDR4__TXPR_F0__FLD LPDDR4__DENALI_CTL_98__TXPR_F0
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_WIDTH                                 16U
+#define LPDDR4__TXPR_F1__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F1__FLD LPDDR4__DENALI_CTL_99__TXPR_F1
+
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_WIDTH                                 16U
+#define LPDDR4__TXPR_F2__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F2__FLD LPDDR4__DENALI_CTL_99__TXPR_F2
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK                             0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK                            0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_100__TSR_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_100__TSR_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_100__TSR_F0_WIDTH                                  8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_100
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_100__TSR_F0
+
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_MASK                       0x00000700U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_WIDTH                               3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_100
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_100__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_100
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_100__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_MASK                     0x1F000000U
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_100
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_100__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK                            0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_MASK                     0x0000001FU
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_101__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_WIDTH                              5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_101__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_101__TSR_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_101__TSR_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_101__TSR_F1_WIDTH                                  8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_101
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_101__TSR_F1
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK                            0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_MASK                       0x00000007U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_WIDTH                               3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_102
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_102__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_102
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_102__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_MASK                     0x001F0000U
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_102
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_MASK                     0x1F000000U
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_102
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK                             0x07FF1F1FU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK                            0x07FF1F1FU
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_103__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_WIDTH                              5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_103__TSR_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_103__TSR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_103__TSR_F2_WIDTH                                  8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_103
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_103__TSR_F2
+
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_MASK                       0x07000000U
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_WIDTH                               3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_103
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_103__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_104
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_104__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_MASK                     0x00001F00U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_MASK                     0x001F0000U
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_104__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_WIDTH                              5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_105__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK                             0x07010101U
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK                            0x07010101U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOSET                     0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_106
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_MASK        0x00000100U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_SHIFT                8U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WIDTH                1U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOCLR                0U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOSET                0U
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__REG DENALI_CTL_106
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOSET                   0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_106
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_MASK                       0x07000000U
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_WIDTH                               3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_106
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_106__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK                             0x00017F00U
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK                            0x00017F00U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_MASK                         0x0000001FU
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_WIDTH                                 5U
+#define LPDDR4__DFS_CMD__REG DENALI_CTL_107
+#define LPDDR4__DFS_CMD__FLD LPDDR4__DENALI_CTL_107__DFS_CMD
+
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_MASK                      0x00007F00U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_WIDTH                              7U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_107
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_107__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOSET                               0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_107
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_107__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK                             0x0707FFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_109
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_WIDTH                           3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_109
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_MASK                    0x07000000U
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_WIDTH                            3U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_109
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_109__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK                             0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK                            0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_WIDTH                            3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_WIDTH                            8U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_WIDTH                            8U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_WIDTH                            8U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT    16U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT     0U
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_113
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT     0U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT    16U
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT    16U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT     0U
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_121
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_123
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT       0U
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_125
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_126
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_127
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_128
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_129
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_130
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT       0U
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_131
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_132
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_133
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_134
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_135
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_136
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_137
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT       0U
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_138
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_139
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOSET                         0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_139
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK                             0x00010103U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK                            0x00010103U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_MASK            0x00000003U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_MASK       0x00000100U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_SHIFT               8U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WIDTH               1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOCLR               0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOSET               0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT      16U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH       1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR       0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET       0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_141
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_142
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_143
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_145
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_146
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_147
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_148
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_149
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOSET                             0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_149
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_149__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK                             0x0000FF00U
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK                            0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_WIDTH                             3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_MASK          0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_WIDTH                  8U
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_MASK            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_WIDTH                   17U
+#define LPDDR4__PPR_COMMAND_MRW_DATA__REG DENALI_CTL_151
+#define LPDDR4__PPR_COMMAND_MRW_DATA__FLD LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK                             0x0F01FFFFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK                            0x0F01FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_WIDTH                        17U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_WIDTH                        4U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOSET                          0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_153
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_WIDTH                             32U
+#define LPDDR4__PPR_DATA_0__REG DENALI_CTL_154
+#define LPDDR4__PPR_DATA_0__FLD LPDDR4__DENALI_CTL_154__PPR_DATA_0
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_WIDTH                             32U
+#define LPDDR4__PPR_DATA_1__REG DENALI_CTL_155
+#define LPDDR4__PPR_DATA_1__FLD LPDDR4__DENALI_CTL_155__PPR_DATA_1
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK                             0xFFFF0103U
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK                            0xFFFF0103U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_MASK                      0x00000003U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_WIDTH                              2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_156
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_156__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_MASK               0x00000100U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOSET                       0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_156
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_WIDTH                                8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_156
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_156__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_WIDTH                                8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_156
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_156__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_WIDTH                                8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_157
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_157__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_WIDTH                                8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_157
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_157__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_WIDTH                                8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_157
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_157__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_WIDTH                                8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_157
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_157__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK                             0x0F0F0003U
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK                            0x0F0F0003U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_MASK         0x00000003U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_WIDTH                 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_158
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_158__LP_CMD_MASK                          0x00007F00U
+#define LPDDR4__DENALI_CTL_158__LP_CMD_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_158__LP_CMD_WIDTH                                  7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_158
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_158__LP_CMD
+
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__REG DENALI_CTL_158
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_MASK          0x0F000000U
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_158
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_MASK           0x0000000FU
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT        8U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_MASK        0x0F000000U
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT               24U
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_MASK         0x0000000FU
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT      8U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_MASK             0x000F0000U
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__REG DENALI_CTL_160
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT       16U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_MASK        0x0000000FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_MASK         0x00000F00U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT     16U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_MASK             0x0F000000U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_MASK          0x00000F00U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_MASK           0x000F0000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT       24U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_MASK                0x0000000FU
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_MASK        0x00000F00U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT                8U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_MASK         0x000F0000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT     24U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK                             0x00013F0FU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK                            0x00013F0FU
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_WIDTH                           6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_165
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOSET                         0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_165
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_MASK                 0x00000FFFU
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_WIDTH                        12U
+#define LPDDR4__LPI_TIMER_COUNT__REG DENALI_CTL_166
+#define LPDDR4__LPI_TIMER_COUNT__FLD LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT
+
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_MASK              0x0FFF0000U
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_WIDTH                     12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_166
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK                             0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK                            0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_WIDTH                            3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_167
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_167__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_167__LP_STATE_MASK                        0x00007F00U
+#define LPDDR4__DENALI_CTL_167__LP_STATE_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_167__LP_STATE_WIDTH                                7U
+#define LPDDR4__LP_STATE__REG DENALI_CTL_167
+#define LPDDR4__LP_STATE__FLD LPDDR4__DENALI_CTL_167__LP_STATE
+
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_WIDTH                        4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_167
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_WIDTH                         4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_167
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK                             0x000FFF07U
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK                            0x000FFF07U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_MASK             0x00000007U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_WIDTH                     3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_168
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_MASK                 0x000FFF00U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_WIDTH                        12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_168
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK                             0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK                            0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_MASK           0x00000FFFU
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_WIDTH                  12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_MASK            0x00FF0000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_WIDTH                    8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK    0xFF000000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT           24U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH            8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_170
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_170
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_171
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_171
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_172
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_MASK                0x00000100U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOSET                        0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_MASK               0x00010000U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_MASK              0x01000000U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOSET                      0U
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK                             0x0101FF01U
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK                            0x0101FF01U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOSET                            0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_174
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_MASK               0x0001FF00U
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_WIDTH                       9U
+#define LPDDR4__PWRDN_SHIFT_DELAY__REG DENALI_CTL_174
+#define LPDDR4__PWRDN_SHIFT_DELAY__FLD LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY
+
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOSET                              0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_174
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_174__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK                             0x00000107U
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK                            0x00000107U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_WIDTH                             3U
+#define LPDDR4__DFS_DLL_OFF__REG DENALI_CTL_175
+#define LPDDR4__DFS_DLL_OFF__FLD LPDDR4__DENALI_CTL_175__DFS_DLL_OFF
+
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOSET                    0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_175
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_WIDTH                 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_176
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK                             0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK                            0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_WIDTH                  4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_MASK          0x00FFFF00U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_WIDTH                 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_WIDTH                        2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_177
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK                             0x00000303U
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK                            0x00000303U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_MASK                       0x00000003U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_WIDTH                               2U
+#define LPDDR4__INIT_FREQ__REG DENALI_CTL_178
+#define LPDDR4__INIT_FREQ__FLD LPDDR4__DENALI_CTL_178__INIT_FREQ
+
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_WIDTH                        2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_178
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_179
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_180
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_181
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_182
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_183
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_184
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_185
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_186
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_187
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_MASK                   0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_WIDTH                          27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_188
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_188__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_WIDTH                              8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_189
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_189__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_MASK                    0x01FFFF00U
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_WIDTH                           17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_189
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_189__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_MASK             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_WIDTH                    24U
+#define LPDDR4__PERIPHERAL_MRR_DATA__REG DENALI_CTL_190
+#define LPDDR4__PERIPHERAL_MRR_DATA__FLD LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA
+
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_MASK              0xFF000000U
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_WIDTH                      8U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_190
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK                             0x000301FFU
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK                            0x000301FFU
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_WIDTH                      8U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_191
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOSET                    0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_191
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_WIDTH                      2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_191
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_192
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_192
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_193__TFC_F0_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_193__TFC_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_193__TFC_F0_WIDTH                                 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_193
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_193__TFC_F0
+
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_193
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_193
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_194
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_194__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_196__TFC_F1_WIDTH                                 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_196
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_196__TFC_F1
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_197
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_197__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_199__TFC_F2_WIDTH                                 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_199
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_199__TFC_F2
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_200
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_200__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_201
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_201
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_202
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_202
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_203
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_203
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK                             0x01FFFF01U
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK                            0x01FFFF01U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOSET                             0U
+#define LPDDR4__MR4_DLL_RST__REG DENALI_CTL_204
+#define LPDDR4__MR4_DLL_RST__FLD LPDDR4__DENALI_CTL_204__MR4_DLL_RST
+
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_MASK                   0x01FFFF00U
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F0_0__REG DENALI_CTL_204
+#define LPDDR4__MR0_DATA_F0_0__FLD LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_205
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_206
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_207_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F1_0__REG DENALI_CTL_207
+#define LPDDR4__MR0_DATA_F1_0__FLD LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_208_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_208
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_209_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_209
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_210_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F2_0__REG DENALI_CTL_210
+#define LPDDR4__MR0_DATA_F2_0__FLD LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_211_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_211
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_212_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_212
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_213_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F0_1__REG DENALI_CTL_213
+#define LPDDR4__MR0_DATA_F0_1__FLD LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_214_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_214
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_215_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_215
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_216_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F1_1__REG DENALI_CTL_216
+#define LPDDR4__MR0_DATA_F1_1__FLD LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_217_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_217
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_218_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_218
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_219_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F2_1__REG DENALI_CTL_219
+#define LPDDR4__MR0_DATA_F2_1__FLD LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_220_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_220
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_221_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_221
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_222_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_WIDTH                        17U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_222
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_223_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_WIDTH                        17U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_223
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_224_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_224
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_225_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_225
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_226_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_226
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_227_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_227
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_228_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_228
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_229_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_229
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_230_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_230
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_231_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_231
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_232_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_232
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_233_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_233
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_234_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_234
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_235_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_235
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_236_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F0_0__REG DENALI_CTL_236
+#define LPDDR4__MR5_DATA_F0_0__FLD LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_237_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F1_0__REG DENALI_CTL_237
+#define LPDDR4__MR5_DATA_F1_0__FLD LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_238_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F2_0__REG DENALI_CTL_238
+#define LPDDR4__MR5_DATA_F2_0__FLD LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_239_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F0_1__REG DENALI_CTL_239
+#define LPDDR4__MR5_DATA_F0_1__FLD LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_240_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F1_1__REG DENALI_CTL_240
+#define LPDDR4__MR5_DATA_F1_1__FLD LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_241_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F2_1__REG DENALI_CTL_241
+#define LPDDR4__MR5_DATA_F2_1__FLD LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_242_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F0_0__REG DENALI_CTL_242
+#define LPDDR4__MR6_DATA_F0_0__FLD LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_243_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F1_0__REG DENALI_CTL_243
+#define LPDDR4__MR6_DATA_F1_0__FLD LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_244_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F2_0__REG DENALI_CTL_244
+#define LPDDR4__MR6_DATA_F2_0__FLD LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_245_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F0_1__REG DENALI_CTL_245
+#define LPDDR4__MR6_DATA_F0_1__FLD LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_246_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F1_1__REG DENALI_CTL_246
+#define LPDDR4__MR6_DATA_F1_1__FLD LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_247_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F2_1__REG DENALI_CTL_247
+#define LPDDR4__MR6_DATA_F2_1__FLD LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_WIDTH                              8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_247
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_247__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_248_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_WIDTH                              8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_248
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_248__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F0_0__REG DENALI_CTL_248
+#define LPDDR4__MR10_DATA_F0_0__FLD LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_249_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F1_0__REG DENALI_CTL_249
+#define LPDDR4__MR10_DATA_F1_0__FLD LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_250_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F2_0__REG DENALI_CTL_250
+#define LPDDR4__MR10_DATA_F2_0__FLD LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_251_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F0_1__REG DENALI_CTL_251
+#define LPDDR4__MR10_DATA_F0_1__FLD LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_252_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F1_1__REG DENALI_CTL_252
+#define LPDDR4__MR10_DATA_F1_1__FLD LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_253_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F2_1__REG DENALI_CTL_253
+#define LPDDR4__MR10_DATA_F2_1__FLD LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_253
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_254_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_255_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_255
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_255
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_256_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_256
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_257_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_257
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_258_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_258
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_259_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_259
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_260_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_260
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_261_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_MASK                     0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_WIDTH                            17U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_261
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_261__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_262_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_MASK                     0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_WIDTH                            17U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_262
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_262__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_263_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_263
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_264_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_264
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_265_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_265
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_266_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_266
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_267_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_267
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_268_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_268
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_WIDTH                             8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_268
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_268__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_269_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_WIDTH                             8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_269
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_WIDTH                             8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_269
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_WIDTH                             8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_269
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_WIDTH                             8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_269
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_270_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_WIDTH                             8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_270
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_270__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_270
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_271_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_271
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_272_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_272
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_273_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_273
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_274_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_274
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_275_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_275
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_276_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_MASK                       0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_WIDTH                              17U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_276
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_276__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_MASK            0x01000000U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_276
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_277_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_277
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_277
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOSET                   0U
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__REG DENALI_CTL_277
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE
+
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_SHIFT                24U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOSET                 0U
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__REG DENALI_CTL_277
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE
+
+#define LPDDR4__DENALI_CTL_278_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_MASK              0x00000001U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOSET                      0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_278
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOSET                    0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_278
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOSET                              0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_278
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_278__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_278
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_279_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK                            0x03010101U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_279
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_279
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_279
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_MASK                        0x03000000U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_WIDTH                                2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_279
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_280_READ_MASK                             0x3F030003U
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK                            0x3F030003U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_MASK                        0x00000003U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_WIDTH                                2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_280
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_280__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_280__BIST_GO_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WOSET                                 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_280
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_280__BIST_GO
+
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_MASK                     0x00030000U
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_WIDTH                             2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_280
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_280__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_MASK                      0x3F000000U
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_WIDTH                              6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_280
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_280__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_281_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOSET                         0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_281
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_MASK                 0x00000100U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOSET                         0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_281
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_282_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_WIDTH                   32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_282
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_283_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOSET                    0U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_283
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_284_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_WIDTH                         32U
+#define LPDDR4__BIST_DATA_MASK__REG DENALI_CTL_284
+#define LPDDR4__BIST_DATA_MASK__FLD LPDDR4__DENALI_CTL_284__BIST_DATA_MASK
+
+#define LPDDR4__DENALI_CTL_285_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_MASK                  0x00000007U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_WIDTH                          3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_285
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_285__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_286_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_286
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_287_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_287
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_288_READ_MASK                             0x000FFF01U
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK                            0x000FFF01U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOSET                          0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_288
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_288__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_MASK                   0x000FFF00U
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_WIDTH                          12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_288
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_288__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_289_READ_MASK                             0x1F000FFFU
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK                            0x1F000FFFU
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_MASK                  0x00000FFFU
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_WIDTH                         12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_289
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_MASK             0x00010000U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOSET                     0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_289
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_MASK                 0x1F000000U
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_WIDTH                         5U
+#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_289
+#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_CTL_290_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_MASK             0x0000001FU
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_290
+#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_MASK             0x00001F00U
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_290
+#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_MASK                0x001F0000U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_WIDTH                        5U
+#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_290
+#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT
+
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_MASK                 0x1F000000U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_WIDTH                         5U
+#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_290
+#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT
+
+#define LPDDR4__DENALI_CTL_291_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_WIDTH                  4U
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_291
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI
+
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_WIDTH                      3U
+#define LPDDR4__ZQCS_OPT_THRESHOLD__REG DENALI_CTL_291
+#define LPDDR4__ZQCS_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_291
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_292_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_292
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_292
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_293
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_293
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_294_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_294
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_294
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_295_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_295
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_295
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_296_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_296_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_296
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_296
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_297_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_298_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_299_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_300_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_300
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_300
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_301_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_302_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_303_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_304_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_304
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_304
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_305_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_MASK               0x000000FFU
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_WIDTH                       8U
+#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_305
+#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG
+
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_WIDTH                              12U
+#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_305
+#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_305__ZQINIT_F0
+
+#define LPDDR4__DENALI_CTL_306_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_WIDTH                                12U
+#define LPDDR4__ZQCL_F0__REG DENALI_CTL_306
+#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_306__ZQCL_F0
+
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_WIDTH                                12U
+#define LPDDR4__ZQCS_F0__REG DENALI_CTL_306
+#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_306__ZQCS_F0
+
+#define LPDDR4__DENALI_CTL_307_READ_MASK                             0x007F0FFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK                            0x007F0FFFU
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_WIDTH                              12U
+#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_307
+#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_307__TZQCAL_F0
+
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_WIDTH                               7U
+#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_307
+#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_307__TZQLAT_F0
+
+#define LPDDR4__DENALI_CTL_308_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_WIDTH                              12U
+#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_308
+#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_308__ZQINIT_F1
+
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_WIDTH                                12U
+#define LPDDR4__ZQCL_F1__REG DENALI_CTL_308
+#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_308__ZQCL_F1
+
+#define LPDDR4__DENALI_CTL_309_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_WIDTH                                12U
+#define LPDDR4__ZQCS_F1__REG DENALI_CTL_309
+#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_309__ZQCS_F1
+
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_MASK                       0x0FFF0000U
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_WIDTH                              12U
+#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_309
+#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_309__TZQCAL_F1
+
+#define LPDDR4__DENALI_CTL_310_READ_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK                            0x000FFF7FU
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_MASK                       0x0000007FU
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_WIDTH                               7U
+#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_310
+#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_310__TZQLAT_F1
+
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_WIDTH                              12U
+#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_310
+#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_310__ZQINIT_F2
+
+#define LPDDR4__DENALI_CTL_311_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_WIDTH                                12U
+#define LPDDR4__ZQCL_F2__REG DENALI_CTL_311
+#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_311__ZQCL_F2
+
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_WIDTH                                12U
+#define LPDDR4__ZQCS_F2__REG DENALI_CTL_311
+#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_311__ZQCS_F2
+
+#define LPDDR4__DENALI_CTL_312_READ_MASK                             0x037F0FFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK                            0x037F0FFFU
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_WIDTH                              12U
+#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_312
+#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_312__TZQCAL_F2
+
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_WIDTH                               7U
+#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_312
+#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_312__TZQLAT_F2
+
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_MASK       0x03000000U
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_SHIFT              24U
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_WIDTH               2U
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_312
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP
+
+#define LPDDR4__DENALI_CTL_313_READ_MASK                             0x0FFF0100U
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK                            0x0FFF0100U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_MASK                          0x0000000FU
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_WIDTH                                  4U
+#define LPDDR4__ZQ_REQ__REG DENALI_CTL_313
+#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ
+
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOSET                          0U
+#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_313
+#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_WIDTH                             12U
+#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_313
+#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_313__ZQRESET_F0
+
+#define LPDDR4__DENALI_CTL_314_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_MASK                      0x00000FFFU
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_WIDTH                             12U
+#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_314
+#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F1
+
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_WIDTH                             12U
+#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_314
+#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F2
+
+#define LPDDR4__DENALI_CTL_315_READ_MASK                             0x03030101U
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK                            0x03030101U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOSET                              0U
+#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_315
+#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_315__NO_ZQ_INIT
+
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOSET                             0U
+#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_315
+#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_315__ZQCS_ROTATE
+
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_315
+#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_315
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_CTL_316_READ_MASK                             0x03030303U
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK                            0x03030303U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_316
+#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_316
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_MASK                     0x00030000U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_316
+#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_0
+
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_MASK                     0x03000000U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_316
+#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_1
+
+#define LPDDR4__DENALI_CTL_317_READ_MASK                             0x0F0F0707U
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK                            0x0F0F0707U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_MASK                      0x00000007U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_317
+#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_0
+
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_MASK                      0x00000700U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_317
+#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_1
+
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_MASK                      0x000F0000U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_WIDTH                              4U
+#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_317
+#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_0
+
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_MASK                      0x0F000000U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_WIDTH                              4U
+#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_317
+#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_1
+
+#define LPDDR4__DENALI_CTL_318_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_318
+#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0
+
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_318
+#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0
+
+#define LPDDR4__DENALI_CTL_319_READ_MASK                             0x00FFFF03U
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK                            0x00FFFF03U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_WIDTH                         2U
+#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_319
+#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_319__ROW_START_VAL_0
+
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_MASK                        0x00FFFF00U
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_WIDTH                               16U
+#define LPDDR4__CS_MSK_0__REG DENALI_CTL_319
+#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_319__CS_MSK_0
+
+#define LPDDR4__DENALI_CTL_320_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_320
+#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1
+
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_320
+#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1
+
+#define LPDDR4__DENALI_CTL_321_READ_MASK                             0x03FFFF03U
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK                            0x03FFFF03U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_WIDTH                         2U
+#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_321
+#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_321__ROW_START_VAL_1
+
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_MASK                        0x00FFFF00U
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_WIDTH                               16U
+#define LPDDR4__CS_MSK_1__REG DENALI_CTL_321
+#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_321__CS_MSK_1
+
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_MASK                 0x03000000U
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_WIDTH                         2U
+#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_321
+#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2
+
+#define LPDDR4__DENALI_CTL_322_READ_MASK                             0x1F011F01U
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK                            0x1F011F01U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOSET                        0U
+#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_322
+#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN
+
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_MASK                    0x00001F00U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_WIDTH                            5U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_322
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOSET                            0U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_322
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_322__APREBIT_MASK                         0x1F000000U
+#define LPDDR4__DENALI_CTL_322__APREBIT_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_322__APREBIT_WIDTH                                 5U
+#define LPDDR4__APREBIT__REG DENALI_CTL_322
+#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_322__APREBIT
+
+#define LPDDR4__DENALI_CTL_323_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_WIDTH                               8U
+#define LPDDR4__AGE_COUNT__REG DENALI_CTL_323
+#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_WIDTH                       8U
+#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_323
+#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOSET                             0U
+#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_323
+#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_323__ADDR_CMP_EN
+
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_MASK          0x01000000U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOSET                  0U
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_323
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS
+
+#define LPDDR4__DENALI_CTL_324_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOSET                           0U
+#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_324
+#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOSET                            0U
+#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_324
+#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_324__PLACEMENT_EN
+
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOSET                             0U
+#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_324
+#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_324__PRIORITY_EN
+
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOSET                              0U
+#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_324
+#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_324__RW_SAME_EN
+
+#define LPDDR4__DENALI_CTL_325_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK                            0x03010101U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOSET                         0U
+#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_325
+#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN
+
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOSET                              0U
+#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_325
+#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_325__CS_SAME_EN
+
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOSET                            0U
+#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_325
+#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT        24U
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH         2U
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_325
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT
+
+#define LPDDR4__DENALI_CTL_326_READ_MASK                             0x0301011FU
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK                            0x0301011FU
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_MASK       0x0000001FU
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT               0U
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH               5U
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_326
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE
+
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOSET                                 0U
+#define LPDDR4__SWAP_EN__REG DENALI_CTL_326
+#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_326__SWAP_EN
+
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOSET                   0U
+#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_326
+#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE
+
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_WIDTH                        2U
+#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_326
+#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD
+
+#define LPDDR4__DENALI_CTL_327_READ_MASK                             0x07010F03U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK                            0x07010F03U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_MASK                          0x00000003U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_WIDTH                                  2U
+#define LPDDR4__CS_MAP__REG DENALI_CTL_327
+#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_327__CS_MAP
+
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_WIDTH                        4U
+#define LPDDR4__BURST_ON_FLY_BIT__REG DENALI_CTL_327
+#define LPDDR4__BURST_ON_FLY_BIT__FLD LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT
+
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOSET                        0U
+#define LPDDR4__MEM_DP_REDUCTION__REG DENALI_CTL_327
+#define LPDDR4__MEM_DP_REDUCTION__FLD LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION
+
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_MASK                 0x07000000U
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_327
+#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_CTL_328_READ_MASK                             0x03030307U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK                            0x03030307U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_328
+#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_MASK               0x00000300U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_WIDTH                       2U
+#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_328
+#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_MASK               0x00030000U
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_WIDTH                       2U
+#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_328
+#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_MASK               0x03000000U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_WIDTH                       2U
+#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_328
+#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_329_READ_MASK                             0x03011F03U
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK                            0x03011F03U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_MASK               0x00000003U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_WIDTH                       2U
+#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_329
+#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_WIDTH                              5U
+#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_329
+#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_329__Q_FULLNESS
+
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOSET                         0U
+#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_329
+#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT
+
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_MASK                    0x03000000U
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_WIDTH                            2U
+#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_329
+#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_329__WR_ORDER_REQ
+
+#define LPDDR4__DENALI_CTL_330_READ_MASK                             0x01010001U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK                            0x01010001U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOSET                         0U
+#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_330
+#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOSET                             0U
+#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_MASK         0x00010000U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_SHIFT                16U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOSET                 0U
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_MASK          0x01000000U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOSET                  0U
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE
+
+#define LPDDR4__DENALI_CTL_331_READ_MASK                             0x01030303U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK                            0x01030303U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_MASK             0x00000003U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_MASK             0x00000300U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_SHIFT                24U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOSET                 0U
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_331
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_CTL_332_READ_MASK                             0x00070101U
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK                            0x00070101U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOSET                               0U
+#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_332
+#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_332__WR_DBI_EN
+
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOSET                               0U
+#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_332
+#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_332__RD_DBI_EN
+
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_MASK                       0x00070000U
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_WIDTH                               3U
+#define LPDDR4__DFI_ERROR__REG DENALI_CTL_332
+#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_332__DFI_ERROR
+
+#define LPDDR4__DENALI_CTL_333_READ_MASK                             0x00010FFFU
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK                            0x00010FFFU
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_MASK                  0x00000FFFU
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_WIDTH                         12U
+#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_333
+#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOSET                            0U
+#define LPDDR4__BG_ROTATE_EN__REG DENALI_CTL_333
+#define LPDDR4__BG_ROTATE_EN__FLD LPDDR4__DENALI_CTL_333__BG_ROTATE_EN
+
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOSET                           0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_333
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_333__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_334_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_WIDTH                      32U
+#define LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL_334
+#define LPDDR4__INT_STATUS_MASTER__FLD LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER
+
+#define LPDDR4__DENALI_CTL_335_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_WIDTH                        32U
+#define LPDDR4__INT_MASK_MASTER__REG DENALI_CTL_335
+#define LPDDR4__INT_MASK_MASTER__FLD LPDDR4__DENALI_CTL_335__INT_MASK_MASTER
+
+#define LPDDR4__DENALI_CTL_336_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_WIDTH                     32U
+#define LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL_336
+#define LPDDR4__INT_STATUS_TIMEOUT__FLD LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_337_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_WIDTH                          16U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_337
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_337__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_WIDTH                    16U
+#define LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL_337
+#define LPDDR4__INT_STATUS_LOWPOWER__FLD LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_338_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_WIDTH                          16U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_338
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_WIDTH                          16U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_338
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_339_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_WIDTH                    32U
+#define LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL_339
+#define LPDDR4__INT_STATUS_TRAINING__FLD LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING
+
+#define LPDDR4__DENALI_CTL_340_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_WIDTH                      32U
+#define LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL_340
+#define LPDDR4__INT_STATUS_USERIF__FLD LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF
+
+#define LPDDR4__DENALI_CTL_341_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_341_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_WIDTH                        16U
+#define LPDDR4__INT_STATUS_MISC__REG DENALI_CTL_341
+#define LPDDR4__INT_STATUS_MISC__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_MISC
+
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_WIDTH                         8U
+#define LPDDR4__INT_STATUS_BIST__REG DENALI_CTL_341
+#define LPDDR4__INT_STATUS_BIST__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_BIST
+
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_WIDTH                           8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_341
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_341__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_342_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_WIDTH                          8U
+#define LPDDR4__INT_STATUS_DFI__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_DFI__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_DFI
+
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_WIDTH                           8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_342
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_WIDTH                         8U
+#define LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_FREQ__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ
+
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_MASK                 0xFF000000U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_WIDTH                         8U
+#define LPDDR4__INT_STATUS_INIT__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_INIT__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_INIT
+
+#define LPDDR4__DENALI_CTL_343_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_WIDTH                         8U
+#define LPDDR4__INT_STATUS_MODE__REG DENALI_CTL_343
+#define LPDDR4__INT_STATUS_MODE__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_MODE
+
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_WIDTH                       8U
+#define LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL_343
+#define LPDDR4__INT_STATUS_PARITY__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY
+
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_WIDTH                        32U
+#define LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL_344
+#define LPDDR4__INT_ACK_TIMEOUT__FLD LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_WIDTH                          16U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_345
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_345__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_WIDTH                       16U
+#define LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL_345
+#define LPDDR4__INT_ACK_LOWPOWER__FLD LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_WIDTH                          16U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_WIDTH                          16U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_WIDTH                       32U
+#define LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL_347
+#define LPDDR4__INT_ACK_TRAINING__FLD LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING
+
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_WIDTH                         32U
+#define LPDDR4__INT_ACK_USERIF__REG DENALI_CTL_348
+#define LPDDR4__INT_ACK_USERIF__FLD LPDDR4__DENALI_CTL_348__INT_ACK_USERIF
+
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_MASK                    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_WIDTH                           16U
+#define LPDDR4__INT_ACK_MISC__REG DENALI_CTL_349
+#define LPDDR4__INT_ACK_MISC__FLD LPDDR4__DENALI_CTL_349__INT_ACK_MISC
+
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_WIDTH                            8U
+#define LPDDR4__INT_ACK_BIST__REG DENALI_CTL_349
+#define LPDDR4__INT_ACK_BIST__FLD LPDDR4__DENALI_CTL_349__INT_ACK_BIST
+
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_WIDTH                           8U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_349
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_349__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_WIDTH                             8U
+#define LPDDR4__INT_ACK_DFI__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_DFI__FLD LPDDR4__DENALI_CTL_350__INT_ACK_DFI
+
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_WIDTH                           8U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_350
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_350__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_WIDTH                            8U
+#define LPDDR4__INT_ACK_FREQ__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_FREQ__FLD LPDDR4__DENALI_CTL_350__INT_ACK_FREQ
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_WIDTH                            8U
+#define LPDDR4__INT_ACK_INIT__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_INIT__FLD LPDDR4__DENALI_CTL_350__INT_ACK_INIT
+
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_MASK                    0x000000FFU
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_WIDTH                            8U
+#define LPDDR4__INT_ACK_MODE__REG DENALI_CTL_351
+#define LPDDR4__INT_ACK_MODE__FLD LPDDR4__DENALI_CTL_351__INT_ACK_MODE
+
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_WIDTH                          8U
+#define LPDDR4__INT_ACK_PARITY__REG DENALI_CTL_351
+#define LPDDR4__INT_ACK_PARITY__FLD LPDDR4__DENALI_CTL_351__INT_ACK_PARITY
+
+#define LPDDR4__DENALI_CTL_352_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_WIDTH                       32U
+#define LPDDR4__INT_MASK_TIMEOUT__REG DENALI_CTL_352
+#define LPDDR4__INT_MASK_TIMEOUT__FLD LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_353_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_WIDTH                          16U
+#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_353
+#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_353__MC_RESERVED21
+
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_MASK               0xFFFF0000U
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_WIDTH                      16U
+#define LPDDR4__INT_MASK_LOWPOWER__REG DENALI_CTL_353
+#define LPDDR4__INT_MASK_LOWPOWER__FLD LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_354_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_WIDTH                          16U
+#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED22
+
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_WIDTH                          16U
+#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED23
+
+#define LPDDR4__DENALI_CTL_355_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_WIDTH                      32U
+#define LPDDR4__INT_MASK_TRAINING__REG DENALI_CTL_355
+#define LPDDR4__INT_MASK_TRAINING__FLD LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING
+
+#define LPDDR4__DENALI_CTL_356_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_WIDTH                        32U
+#define LPDDR4__INT_MASK_USERIF__REG DENALI_CTL_356
+#define LPDDR4__INT_MASK_USERIF__FLD LPDDR4__DENALI_CTL_356__INT_MASK_USERIF
+
+#define LPDDR4__DENALI_CTL_357_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_WIDTH                          16U
+#define LPDDR4__INT_MASK_MISC__REG DENALI_CTL_357
+#define LPDDR4__INT_MASK_MISC__FLD LPDDR4__DENALI_CTL_357__INT_MASK_MISC
+
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_WIDTH                           8U
+#define LPDDR4__INT_MASK_BIST__REG DENALI_CTL_357
+#define LPDDR4__INT_MASK_BIST__FLD LPDDR4__DENALI_CTL_357__INT_MASK_BIST
+
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_WIDTH                           8U
+#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_357
+#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_357__MC_RESERVED24
+
+#define LPDDR4__DENALI_CTL_358_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_MASK                    0x000000FFU
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_WIDTH                            8U
+#define LPDDR4__INT_MASK_DFI__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_DFI__FLD LPDDR4__DENALI_CTL_358__INT_MASK_DFI
+
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_WIDTH                           8U
+#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_358
+#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_358__MC_RESERVED25
+
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_WIDTH                           8U
+#define LPDDR4__INT_MASK_FREQ__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_FREQ__FLD LPDDR4__DENALI_CTL_358__INT_MASK_FREQ
+
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_WIDTH                           8U
+#define LPDDR4__INT_MASK_INIT__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_INIT__FLD LPDDR4__DENALI_CTL_358__INT_MASK_INIT
+
+#define LPDDR4__DENALI_CTL_359_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_359_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_WIDTH                           8U
+#define LPDDR4__INT_MASK_MODE__REG DENALI_CTL_359
+#define LPDDR4__INT_MASK_MODE__FLD LPDDR4__DENALI_CTL_359__INT_MASK_MODE
+
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_WIDTH                         8U
+#define LPDDR4__INT_MASK_PARITY__REG DENALI_CTL_359
+#define LPDDR4__INT_MASK_PARITY__FLD LPDDR4__DENALI_CTL_359__INT_MASK_PARITY
+
+#define LPDDR4__DENALI_CTL_360_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_WIDTH                    32U
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_360
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0
+
+#define LPDDR4__DENALI_CTL_361_READ_MASK                             0x7F07FF01U
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK                            0x7F07FF01U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOSET                     0U
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1
+
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_MASK             0x0007FF00U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_WIDTH                    11U
+#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH
+
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_MASK               0x7F000000U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_WIDTH                       7U
+#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE
+
+#define LPDDR4__DENALI_CTL_362_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_MASK          0x0000003FU
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_WIDTH                  6U
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_362
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID
+
+#define LPDDR4__DENALI_CTL_363_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_363
+#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_CTL_364_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_364
+#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_CTL_365_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_365
+#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_CTL_366_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_366
+#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_CTL_367_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_367
+#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_CTL_368_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOSET                        0U
+#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_368
+#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_CTL_369_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_WIDTH                  32U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_369
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0
+
+#define LPDDR4__DENALI_CTL_370_READ_MASK                             0xFF033F01U
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK                            0xFF033F01U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_MASK           0x00000001U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOSET                   0U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1
+
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_MASK               0x00003F00U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_WIDTH                       6U
+#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID
+
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_WIDTH                     2U
+#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_370
+#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_CTL_371_READ_MASK                             0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK                            0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_371
+#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F0
+
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_MASK                     0x00000F00U
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_371
+#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_RD_F0
+
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_371
+#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_371
+#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F1
+
+#define LPDDR4__DENALI_CTL_372_READ_MASK                             0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK                            0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_372
+#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F1
+
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_WR_F2
+
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F2
+
+#define LPDDR4__DENALI_CTL_373_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOSET                               0U
+#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F0
+
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOSET                               0U
+#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F1
+
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOSET                               0U
+#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F2
+
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_SHIFT                24U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOSET                 0U
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_373
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD
+
+#define LPDDR4__DENALI_CTL_374_READ_MASK                             0x033F3F3FU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK                            0x033F3F3FU
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_MASK                  0x03000000U
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_374
+#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_375_READ_MASK                             0x3F030303U
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK                            0x3F030303U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_MASK                  0x00000003U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_375
+#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_MASK                  0x00000300U
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_375
+#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_MASK                  0x00030000U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_375
+#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_MASK                   0x3F000000U
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_375
+#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_376_READ_MASK                             0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK                            0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_376
+#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_376
+#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_376
+#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0
+
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_376
+#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1
+
+#define LPDDR4__DENALI_CTL_377_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_377
+#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2
+
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_378_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_378
+#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_379_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_379
+#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_380_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_380
+#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_381_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK                            0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_MASK                  0x0000001FU
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_MASK                  0x00001F00U
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_MASK                  0x001F0000U
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_381
+#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_CTL_382_READ_MASK                             0x0F070F07U
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK                            0x0F070F07U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_CTL_383_READ_MASK                             0x07010107U
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK                            0x07010107U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_383
+#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2
+
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_MASK    0x00000100U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_SHIFT            8U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WIDTH            1U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOCLR            0U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOSET            0U
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_383
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE
+
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT        16U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH         1U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR         0U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET         0U
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_383
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE
+
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_MASK                 0x07000000U
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_383
+#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY
+
+#define LPDDR4__DENALI_CTL_384_READ_MASK                             0xFF010307U
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK                            0xFF010307U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_384
+#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY
+
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_MASK                      0x00000300U
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_WIDTH                              2U
+#define LPDDR4__CKE_STATUS__REG DENALI_CTL_384
+#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_384__CKE_STATUS
+
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOSET                           0U
+#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_384
+#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_384__MEM_RST_VALID
+
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_384
+#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0
+
+#define LPDDR4__DENALI_CTL_385_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_385
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_CTL_386_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_386
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_387_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_388_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_388
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_389_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_389
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_390_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_390
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0
+
+#define LPDDR4__DENALI_CTL_391_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_391
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_CTL_392_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_RDDATA_EN_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0
+
+#define LPDDR4__DENALI_CTL_393_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHY_WRLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1
+
+#define LPDDR4__DENALI_CTL_394_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_394
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_CTL_395_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_395
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_396_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_396
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_397_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_397
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_398_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_398
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_399_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_399
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1
+
+#define LPDDR4__DENALI_CTL_400_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_400
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_CTL_401_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_RDDATA_EN_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1
+
+#define LPDDR4__DENALI_CTL_402_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHY_WRLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2
+
+#define LPDDR4__DENALI_CTL_403_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_403
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_CTL_404_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_404
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_405_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_405
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_406_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_406
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_407_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_407
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_408_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_408
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2
+
+#define LPDDR4__DENALI_CTL_409_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_409
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_CTL_410_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_RDDATA_EN_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2
+
+#define LPDDR4__DENALI_CTL_411_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_PHY_WRLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_WIDTH                          16U
+#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_411
+#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_411__DLL_RST_DELAY
+
+#define LPDDR4__DENALI_CTL_412_READ_MASK                             0x00037FFFU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK                            0x00037FFFU
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_WIDTH                         8U
+#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_412
+#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_MASK             0x00007F00U
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_WIDTH                     7U
+#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_412
+#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_MASK                0x00030000U
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_WIDTH                        2U
+#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_412
+#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413_READ_MASK                             0x0F0FFFFFU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK                            0x0F0FFFFFU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_WIDTH                       16U
+#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_413
+#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK           0x000F0000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH                   4U
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK            0x0F000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH                    4U
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
+
+#define LPDDR4__DENALI_CTL_414_READ_MASK                             0x0701FF07U
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK                            0x0701FF07U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_MASK                  0x00000007U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_WIDTH                          3U
+#define LPDDR4__TDFI_PARIN_LAT__REG DENALI_CTL_414
+#define LPDDR4__TDFI_PARIN_LAT__FLD LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_WIDTH                       8U
+#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_414
+#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY
+
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_MASK     0x00010000U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_SHIFT            16U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WIDTH             1U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOCLR             0U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOSET             0U
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_414
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE
+
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_MASK            0x07000000U
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_WIDTH                    3U
+#define LPDDR4__STRATEGY_2TICK_COUNT__REG DENALI_CTL_414
+#define LPDDR4__STRATEGY_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415_READ_MASK                             0x07070707U
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK                            0x07070707U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_MASK       0x00000007U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_SHIFT               0U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_WIDTH               3U
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_MASK                 0x00000700U
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_WIDTH                         3U
+#define LPDDR4__PRE_2TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__PRE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_MASK            0x00070000U
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_WIDTH                    3U
+#define LPDDR4__STRATEGY_4TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__STRATEGY_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_MASK       0x07000000U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_SHIFT              24U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_WIDTH               3U
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_416_READ_MASK                             0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK                            0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_WIDTH                         3U
+#define LPDDR4__PRE_4TICK_COUNT__REG DENALI_CTL_416
+#define LPDDR4__PRE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_MASK           0x0F000000U
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__ODT_TICK_PLUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__ODT_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__ODT_TICK_MINUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__ODT_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_WIDTH                     4U
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__TRP_TICK_PLUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRP_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRP_TICK_MINUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRP_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__TWR_TICK_PLUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TWR_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__TWR_TICK_MINUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TWR_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_WIDTH                     4U
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_WIDTH                        4U
+#define LPDDR4__RL_TICK_PLUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__RL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_WIDTH                       4U
+#define LPDDR4__RL_TICK_MINUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__RL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_WIDTH                        4U
+#define LPDDR4__WL_TICK_PLUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__WL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_421_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK                            0xFFFFFF0FU
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_MASK               0x0000000FU
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_WIDTH                       4U
+#define LPDDR4__WL_TICK_MINUS_ADJ__REG DENALI_CTL_421
+#define LPDDR4__WL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_421__NWR_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_421__NWR_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_421__NWR_F0_WIDTH                                  8U
+#define LPDDR4__NWR_F0__REG DENALI_CTL_421
+#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_421__NWR_F0
+
+#define LPDDR4__DENALI_CTL_421__NWR_F1_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_421__NWR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_421__NWR_F1_WIDTH                                  8U
+#define LPDDR4__NWR_F1__REG DENALI_CTL_421
+#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_421__NWR_F1
+
+#define LPDDR4__DENALI_CTL_421__NWR_F2_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_421__NWR_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_421__NWR_F2_WIDTH                                  8U
+#define LPDDR4__NWR_F2__REG DENALI_CTL_421
+#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_421__NWR_F2
+
+#define LPDDR4__DENALI_CTL_422_READ_MASK                             0x007F7F7FU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK                            0x007F7F7FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_MASK            0x0000007FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_MASK            0x00007F00U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_MASK            0x007F0000U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2
+
+#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
new file mode 100644
index 0000000000..dcfd7d9e86
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
@@ -0,0 +1,1838 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
+#define REG_LPDDR4_PHY_CORE_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1280_READ_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_1280_WRITE_MASK                           0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH                           2U
+#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280
+#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1281_READ_MASK                            0x1F030101U
+#define LPDDR4__DENALI_PHY_1281_WRITE_MASK                           0x1F030101U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET                0U
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_MASK      0x00000100U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_SHIFT              8U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOSET              0U
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN
+
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH                     2U
+#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX
+
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1283_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1284_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285_READ_MASK                            0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1285_WRITE_MASK                           0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1286_READ_MASK                            0x011F07FFU
+#define LPDDR4__DENALI_PHY_1286_WRITE_MASK                           0x011F07FFU
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH            11U
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1286
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY
+
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_WIDTH                5U
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1286
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT
+
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOSET                0U
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1286
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1287_READ_MASK                            0x07FF0100U
+#define LPDDR4__DENALI_PHY_1287_WRITE_MASK                           0x07FF0100U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_MASK           0x00000001U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOSET                   0U
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1287
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH        1U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR        0U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET        0U
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1287
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
+
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_MASK                0x07FF0000U
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_WIDTH                       11U
+#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1287
+#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START
+
+#define LPDDR4__DENALI_PHY_1288_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1288_WRITE_MASK                           0x000107FFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_WIDTH                  11U
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1288
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY
+
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_MASK           0x00010000U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOSET                   0U
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1288
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE
+
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOSET                0U
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1288
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT
+
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOSET                 0U
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1289
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR
+
+#define LPDDR4__DENALI_PHY_1290_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1290
+#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0
+
+#define LPDDR4__DENALI_PHY_1291_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1291
+#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1
+
+#define LPDDR4__DENALI_PHY_1292_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1292
+#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2
+
+#define LPDDR4__DENALI_PHY_1293_READ_MASK                            0x0101FF01U
+#define LPDDR4__DENALI_PHY_1293_WRITE_MASK                           0x0101FF01U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_MASK               0x00000001U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOSET                       0U
+#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1293
+#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE
+
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH        9U
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1293
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET
+
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOSET                   0U
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1293
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE
+
+#define LPDDR4__DENALI_PHY_1294_READ_MASK                            0x0007FF03U
+#define LPDDR4__DENALI_PHY_1294_WRITE_MASK                           0x0007FF03U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_MASK               0x00000003U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_WIDTH                       2U
+#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1294
+#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP
+
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_MASK                  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_WIDTH                         11U
+#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1294
+#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR
+
+#define LPDDR4__DENALI_PHY_1295_READ_MASK                            0x070F07FFU
+#define LPDDR4__DENALI_PHY_1295_WRITE_MASK                           0x070F07FFU
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_WIDTH                  11U
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1295
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK
+
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH           4U
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1295
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT      24U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH       3U
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE
+
+#define LPDDR4__DENALI_PHY_1296_READ_MASK                            0x01010300U
+#define LPDDR4__DENALI_PHY_1296_WRITE_MASK                           0x01010300U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOSET               0U
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS
+
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_MASK            0x00000300U
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_WIDTH                    2U
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1296
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE
+
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOSET                       0U
+#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR
+
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_MASK                 0x01000000U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOSET                         0U
+#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1296
+#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE
+
+#define LPDDR4__DENALI_PHY_1297_READ_MASK                            0x0F010001U
+#define LPDDR4__DENALI_PHY_1297_WRITE_MASK                           0x0F010001U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_MASK                  0x00000001U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOSET                          0U
+#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1297
+#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS
+
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET           0U
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1297
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES
+
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET          0U
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1297
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_MASK             0x0F000000U
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1297
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1298_READ_MASK                            0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1298_WRITE_MASK                           0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK             0x0000000FU
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_MASK             0x000F0000U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOSET                0U
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1298
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL
+
+#define LPDDR4__DENALI_PHY_1299_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1299_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK     0x00000F00U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_MASK     0x000F0000U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_MASK     0x0F000000U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1300_READ_MASK                            0x00010101U
+#define LPDDR4__DENALI_PHY_1300_WRITE_MASK                           0x00010101U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET               0U
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1300
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL
+
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOSET             0U
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT   16U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET    0U
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1301_READ_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_PHY_1301_WRITE_MASK                           0x010FFFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_WIDTH                16U
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1301
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL
+
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK  0x000F0000U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH          4U
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET          0U
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1302_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1302_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOSET                0U
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1302
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1303_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_WIDTH                    32U
+#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1303
+#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS
+
+#define LPDDR4__DENALI_PHY_1304_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_WIDTH                          16U
+#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1304
+#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT
+
+#define LPDDR4__DENALI_PHY_1305_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1305_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_MASK              0x00000001U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOSET                      0U
+#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1305
+#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1306_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_2__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_2__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_3__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_3__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3
+
+#define LPDDR4__DENALI_PHY_1307_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1307_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0
+
+#define LPDDR4__DENALI_PHY_1308_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1308_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1
+
+#define LPDDR4__DENALI_PHY_1309_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1309_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2
+
+#define LPDDR4__DENALI_PHY_1310_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1310_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3
+
+#define LPDDR4__DENALI_PHY_1311_READ_MASK                            0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1311_WRITE_MASK                           0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_MASK          0x00001FFFU
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_WIDTH                 13U
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1311
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_WIDTH                 16U
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1311
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1312_READ_MASK                            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1312_WRITE_MASK                           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOSET               0U
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1312
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK
+
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_WIDTH                   8U
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1312
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL
+
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK    0x00030000U
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH            2U
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1312
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS
+
+#define LPDDR4__DENALI_PHY_1313_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_WIDTH                         16U
+#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1313
+#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1314_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_WIDTH                 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1314
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1315_READ_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1315_WRITE_MASK                           0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_MASK          0x00000FFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_WIDTH                 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_WIDTH        12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1316_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_WIDTH                         16U
+#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1316
+#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1317_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_WIDTH                 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1318_READ_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1318_WRITE_MASK                           0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_MASK          0x00000FFFU
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_WIDTH                 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_WIDTH        12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1319_READ_MASK                            0xFF0F0101U
+#define LPDDR4__DENALI_PHY_1319_WRITE_MASK                           0xFF0F0101U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOSET                     0U
+#define LPDDR4__PHY_PLL_REFOUT_SEL__REG DENALI_PHY_1319
+#define LPDDR4__PHY_PLL_REFOUT_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL
+
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK      0x00000100U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT              8U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET              0U
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1319
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_MASK                0x000F0000U
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_WIDTH                        4U
+#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1319
+#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT
+
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_MASK                  0xFF000000U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_WIDTH                          8U
+#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1319
+#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP
+
+#define LPDDR4__DENALI_PHY_1320_READ_MASK                            0x0003FF01U
+#define LPDDR4__DENALI_PHY_1320_WRITE_MASK                           0x0003FF01U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOSET                         0U
+#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1320
+#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN
+
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_MASK        0x0003FF00U
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH               10U
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1320
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG
+
+#define LPDDR4__DENALI_PHY_1321_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1321_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_WIDTH                      17U
+#define LPDDR4__PHY_DS_EXIT_CTRL__REG DENALI_PHY_1321
+#define LPDDR4__PHY_DS_EXIT_CTRL__FLD LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL
+
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOSET                   0U
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1321
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY
+
+#define LPDDR4__DENALI_PHY_1322_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_MASK              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_WIDTH                     18U
+#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1322
+#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM
+
+#define LPDDR4__DENALI_PHY_1323_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_MASK              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_WIDTH                     17U
+#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1323
+#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM
+
+#define LPDDR4__DENALI_PHY_1324_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_WIDTH                      17U
+#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1324
+#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM
+
+#define LPDDR4__DENALI_PHY_1325_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_MASK              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_WIDTH                     18U
+#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1325
+#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM
+
+#define LPDDR4__DENALI_PHY_1326_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1326
+#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM
+
+#define LPDDR4__DENALI_PHY_1327_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_ERR_TERM__REG DENALI_PHY_1327
+#define LPDDR4__PHY_PAD_ERR_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM
+
+#define LPDDR4__DENALI_PHY_1328_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1328
+#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM
+
+#define LPDDR4__DENALI_PHY_1329_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1329
+#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM
+
+#define LPDDR4__DENALI_PHY_1330_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_MASK                0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_WIDTH                       18U
+#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1330
+#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM
+
+#define LPDDR4__DENALI_PHY_1331_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1331
+#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM
+
+#define LPDDR4__DENALI_PHY_1332_READ_MASK                            0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1332_WRITE_MASK                           0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_MASK              0x000003FFU
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_WIDTH                     10U
+#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1332
+#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_MASK          0x1FFF0000U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_WIDTH                 13U
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1332
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1333_READ_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333_WRITE_MASK                           0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_MASK                 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_WIDTH                        13U
+#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0
+
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_MASK                0x00010000U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOSET                        0U
+#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_SHIFT                       24U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOSET                        0U
+#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_1334_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_WIDTH              32U
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1334
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0
+
+#define LPDDR4__DENALI_PHY_1335_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1335_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1335
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK  0x00000700U
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1335
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1336_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_WIDTH                  24U
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1336
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1337_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1337
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0
+
+#define LPDDR4__DENALI_PHY_1338_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1338
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0
+
+#define LPDDR4__DENALI_PHY_1339_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1339
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0
+
+#define LPDDR4__DENALI_PHY_1340_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1340
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0
+
+#define LPDDR4__DENALI_PHY_1341_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1341_WRITE_MASK                           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1341
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0
+
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_MASK             0x7F000000U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_WIDTH                     7U
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1341
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0
+
+#define LPDDR4__DENALI_PHY_1342_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1342_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_MASK          0x0000FF00U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_WIDTH                 8U
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOSET                      0U
+#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0
+
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_MASK          0x00000001U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOSET                  0U
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1343
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0
+
+#define LPDDR4__DENALI_PHY_1344_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1344
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0
+
+#define LPDDR4__DENALI_PHY_1345_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1345_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_WIDTH                   8U
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1345
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0
+
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_MASK            0x0FFFFF00U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_WIDTH                   20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1345
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1346_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK      0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH             20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1346
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0
+
+#define LPDDR4__DENALI_PHY_1347_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_MASK         0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_WIDTH                25U
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1347
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0
+
+#define LPDDR4__DENALI_PHY_1348_READ_MASK                            0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1348_WRITE_MASK                           0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_MASK           0x007FFFFFU
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_WIDTH                  23U
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1348
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0
+
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1348
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349_READ_MASK                            0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1349_WRITE_MASK                           0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350_READ_MASK                            0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1350_WRITE_MASK                           0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351_READ_MASK                            0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1351_WRITE_MASK                           0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1352_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_MASK               0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_WIDTH                      16U
+#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1352
+#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL
+
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOSET               0U
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1352
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOSET                  0U
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1352
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR
+
+#define LPDDR4__DENALI_PHY_1353_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1353_WRITE_MASK                           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_WIDTH                 2U
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_WIDTH                     4U
+#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_MASK            0x01FF0000U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_WIDTH                    9U
+#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1354_READ_MASK                            0x00000F7FU
+#define LPDDR4__DENALI_PHY_1354_WRITE_MASK                           0x00000F7FU
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_WIDTH              7U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1354
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START
+
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_WIDTH               4U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1354
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK
+
+#define LPDDR4__DENALI_PHY_1355_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_WIDTH                32U
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1355
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1356_READ_MASK                            0x003F0101U
+#define LPDDR4__DENALI_PHY_1356_WRITE_MASK                           0x003F0101U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET             0U
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOSET                 0U
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_MASK        0x003F0000U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_WIDTH                6U
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1357_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1357_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_MASK     0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH            16U
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1357
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_MASK         0x00010000U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOSET                 0U
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1357
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOSET                0U
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1357
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1358_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1358_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT       0U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH       1U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR       0U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET       0U
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1358
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
+
+#define LPDDR4__DENALI_PHY_1359_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_WIDTH               32U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1359
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL
+
+#define LPDDR4__DENALI_PHY_1360_READ_MASK                            0x03071FFFU
+#define LPDDR4__DENALI_PHY_1360_WRITE_MASK                           0x03071FFFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH           8U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1360
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH
+
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_WIDTH                   5U
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1360
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP
+
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_WIDTH                        3U
+#define LPDDR4__PHY_ADR_DISABLE__REG DENALI_PHY_1360
+#define LPDDR4__PHY_ADR_DISABLE__FLD LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE
+
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK  0x03000000U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1360
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
+
+#define LPDDR4__DENALI_PHY_1361_READ_MASK                            0x00030303U
+#define LPDDR4__DENALI_PHY_1361_WRITE_MASK                           0x00030303U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK  0x00000003U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
+
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_MASK  0x00000300U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2
+
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_MASK  0x00030000U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3
+
+#define LPDDR4__DENALI_PHY_1362_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_WIDTH                     32U
+#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1362
+#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE
+
+#define LPDDR4__DENALI_PHY_1363_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_MASK                0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_WIDTH                       26U
+#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1363
+#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE
+
+#define LPDDR4__DENALI_PHY_1364_READ_MASK                            0x00FF073FU
+#define LPDDR4__DENALI_PHY_1364_WRITE_MASK                           0x00FF073FU
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_MASK                0x0000003FU
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_WIDTH                        6U
+#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1364
+#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK
+
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_MASK         0x00000700U
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_WIDTH                 3U
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1364
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG
+
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH         8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1364
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC
+
+#define LPDDR4__DENALI_PHY_1365_READ_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1365_WRITE_MASK                           0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_WIDTH           16U
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__REG DENALI_PHY_1365
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__FLD LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN
+
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_WIDTH                        3U
+#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1365
+#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN
+
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_MASK                 0x07000000U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_WIDTH                         3U
+#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1365
+#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS
+
+#define LPDDR4__DENALI_PHY_1366_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1366
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1367_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1367
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1368_READ_MASK                            0x030FFF03U
+#define LPDDR4__DENALI_PHY_1368_WRITE_MASK                           0x030FFF03U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_MASK                 0x00000003U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_WIDTH                         2U
+#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1368
+#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN
+
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_MASK       0x000FFF00U
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_WIDTH              12U
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1368
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_MASK       0x03000000U
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_SHIFT              24U
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_WIDTH               2U
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1368
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1369_READ_MASK                            0x0F1F0101U
+#define LPDDR4__DENALI_PHY_1369_WRITE_MASK                           0x0F1F0101U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_MASK                0x00000001U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOSET                        0U
+#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1369
+#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK
+
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_MASK                     0x00000100U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_SHIFT                             8U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOSET                             0U
+#define LPDDR4__PHY_ERR_IE__REG DENALI_PHY_1369
+#define LPDDR4__PHY_ERR_IE__FLD LPDDR4__DENALI_PHY_1369__PHY_ERR_IE
+
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH         5U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1369
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_SHIFT              24U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_WIDTH               4U
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1369
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1370_READ_MASK                            0x000707FFU
+#define LPDDR4__DENALI_PHY_1370_WRITE_MASK                           0x000707FFU
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH               11U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1370
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS
+
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_WIDTH                      3U
+#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1370
+#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS
+
+#define LPDDR4__DENALI_PHY_1371_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_MASK           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_WIDTH                  18U
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1371
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_1372_READ_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1372_WRITE_MASK                           0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_WIDTH                    16U
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1372
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG
+
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_MASK    0x00070000U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_WIDTH            3U
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__REG DENALI_PHY_1372
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL
+
+#define LPDDR4__DENALI_PHY_1373_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1373_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOSET                         0U
+#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1373
+#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1374_READ_MASK                            0x00011FFFU
+#define LPDDR4__DENALI_PHY_1374_WRITE_MASK                           0x00011FFFU
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_MASK                   0x00001FFFU
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_WIDTH                          13U
+#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1374
+#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOSET                       0U
+#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1374
+#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1375_READ_MASK                            0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1375_WRITE_MASK                           0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_MASK           0x00000FFFU
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_WIDTH                  12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1375
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC
+
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_MASK          0x000F0000U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_WIDTH                  4U
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1375
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_MASK             0x0F000000U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_WIDTH                     4U
+#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1375
+#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP
+
+#define LPDDR4__DENALI_PHY_1376_READ_MASK                            0x010103FFU
+#define LPDDR4__DENALI_PHY_1376_WRITE_MASK                           0x010103FFU
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_WIDTH                  10U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1376
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN
+
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOSET                0U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1376
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN
+
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET           0U
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1376
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE
+
+#define LPDDR4__DENALI_PHY_1377_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1377_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1377
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1377
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1378_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1378_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1378
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1378
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1379_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1379_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1379
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1379
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1380_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1380_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1380
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1380
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1381_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1381_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__REG DENALI_PHY_1381
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__REG DENALI_PHY_1381
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1382_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1382_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__REG DENALI_PHY_1382
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__REG DENALI_PHY_1382
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1383_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1383_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__REG DENALI_PHY_1383
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1384_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1384_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__REG DENALI_PHY_1384
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1385_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1385_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__REG DENALI_PHY_1385
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1386_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1386_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__REG DENALI_PHY_1386
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1387_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_WIDTH                    30U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1387
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1388_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_MASK            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_WIDTH                   18U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1388
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1389_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389_WRITE_MASK                           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_MASK             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_WIDTH                    31U
+#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1389
+#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE
+
+#define LPDDR4__DENALI_PHY_1390_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_WIDTH                     32U
+#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1390
+#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1391_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_WIDTH                    30U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1391
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1392_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_MASK            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_WIDTH                   28U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1392
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1393_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_WIDTH                     32U
+#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1393
+#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1394_READ_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394_WRITE_MASK                           0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_MASK             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_WIDTH                    19U
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1394
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1395_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_ERR_DRIVE__REG DENALI_PHY_1395
+#define LPDDR4__PHY_PAD_ERR_DRIVE__FLD LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1396_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__REG DENALI_PHY_1396
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__FLD LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1397_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1397
+#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE
+
+#define LPDDR4__DENALI_PHY_1398_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1398
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1399_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1399
+#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE
+
+#define LPDDR4__DENALI_PHY_1400_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1400
+#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1401_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_MASK               0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_WIDTH                      30U
+#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1401
+#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1402_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_MASK              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_WIDTH                     28U
+#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1402
+#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1403_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1403
+#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE
+
+#define LPDDR4__DENALI_PHY_1404_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1404
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1405_READ_MASK                            0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1405_WRITE_MASK                           0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_MASK           0x00000007U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_WIDTH                   3U
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_MASK    0x00FFFF00U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH           16U
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0
+
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_MASK         0x7F000000U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_WIDTH                 7U
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0
+
+#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
new file mode 100644
index 0000000000..9aa281af21
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
@@ -0,0 +1,5784 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PI_MACROS_H_
+#define REG_LPDDR4_PI_MACROS_H_
+
+#define LPDDR4__DENALI_PI_0_READ_MASK                                0x00000F01U
+#define LPDDR4__DENALI_PI_0_WRITE_MASK                               0x00000F01U
+#define LPDDR4__DENALI_PI_0__PI_START_MASK                           0x00000001U
+#define LPDDR4__DENALI_PI_0__PI_START_SHIFT                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WIDTH                                   1U
+#define LPDDR4__DENALI_PI_0__PI_START_WOCLR                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WOSET                                   0U
+#define LPDDR4__PI_START__REG DENALI_PI_0
+#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
+
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT                              8U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH                              4U
+#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
+#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
+
+#define LPDDR4__DENALI_PI_1_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH                              32U
+#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
+#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
+
+#define LPDDR4__DENALI_PI_2_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH                              32U
+#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
+#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
+
+#define LPDDR4__DENALI_PI_3_READ_MASK                                0x0101FFFFU
+#define LPDDR4__DENALI_PI_3_WRITE_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT                                      0U
+#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH                                     16U
+#define LPDDR4__PI_ID__REG DENALI_PI_3
+#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
+
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT                            16U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH                             1U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR                             0U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET                             0U
+#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3
+#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI
+
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT                         24U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH                          1U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR                          0U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET                          0U
+#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3
+#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ
+
+#define LPDDR4__DENALI_PI_4_READ_MASK                                0xFFFF0301U
+#define LPDDR4__DENALI_PI_4_WRITE_MASK                               0xFFFF0301U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT                             0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET                             0U
+#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4
+#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN
+
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT                          8U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH                          2U
+#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4
+#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD
+
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK                        0xFFFF0000U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT                               16U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH                               16U
+#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4
+#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP
+
+#define LPDDR4__DENALI_PI_5_READ_MASK                                0x030100FFU
+#define LPDDR4__DENALI_PI_5_WRITE_MASK                               0x030100FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH                               8U
+#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5
+#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0
+
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT                      8U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH                      1U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR                      0U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET                      0U
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT                            16U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH                             1U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR                             0U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET                             0U
+#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT                       24U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH                        2U
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_6_READ_MASK                                0x00000101U
+#define LPDDR4__DENALI_PI_6_WRITE_MASK                               0x00000101U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK          0x00000001U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT                  0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH                  1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR                  0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET                  0U
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R
+
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK         0x00000100U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT                 8U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH                 1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR                 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET                 0U
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R
+
+#define LPDDR4__DENALI_PI_7_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX
+
+#define LPDDR4__DENALI_PI_8_READ_MASK                                0x000FFFFFU
+#define LPDDR4__DENALI_PI_8_WRITE_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK               0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH                      20U
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP
+
+#define LPDDR4__DENALI_PI_9_READ_MASK                                0x000FFFFFU
+#define LPDDR4__DENALI_PI_9_WRITE_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK                0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH                       20U
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP
+
+#define LPDDR4__DENALI_PI_10_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX
+
+#define LPDDR4__DENALI_PI_11_READ_MASK                               0x0000011FU
+#define LPDDR4__DENALI_PI_11_WRITE_MASK                              0x0000011FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK                 0x0000001FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT                         0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH                         5U
+#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ
+
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK            0x00000100U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT                    8U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET                    0U
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY
+
+#define LPDDR4__DENALI_PI_12_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT                               0U
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH                              32U
+#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
+#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
+
+#define LPDDR4__DENALI_PI_13_READ_MASK                               0x01030101U
+#define LPDDR4__DENALI_PI_13_WRITE_MASK                              0x01030101U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT                               0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH                               1U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR                               0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET                               0U
+#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
+#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
+
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK                      0x00000100U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT                              8U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH                              1U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR                              0U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET                              0U
+#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
+#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
+
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK                         0x00030000U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT                                16U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH                                 2U
+#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13
+#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP
+
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT                          24U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH                           1U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR                           0U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET                           0U
+#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13
+#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL
+
+#define LPDDR4__DENALI_PI_14_READ_MASK                               0x0F011F03U
+#define LPDDR4__DENALI_PI_14_WRITE_MASK                              0x0F011F03U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK                        0x00000003U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT                                0U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH                                2U
+#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14
+#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK
+
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK               0x00001F00U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT                       8U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH                       5U
+#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
+#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
+
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK           0x00010000U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT                  16U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH                   1U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR                   0U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET                   0U
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
+
+#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK                           0x0F000000U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT                                  24U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH                                   4U
+#define LPDDR4__PI_TMRR__REG DENALI_PI_14
+#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
+
+#define LPDDR4__DENALI_PI_15_READ_MASK                               0x0101070FU
+#define LPDDR4__DENALI_PI_15_WRITE_MASK                              0x0101070FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK                          0x0000000FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT                                  0U
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH                                  4U
+#define LPDDR4__PI_TMPRR__REG DENALI_PI_15
+#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR
+
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK                        0x00000700U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT                                8U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH                                3U
+#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15
+#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN
+
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT                   16U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET                    0U
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
+
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT                             24U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH                              1U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR                              0U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET                              0U
+#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
+#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
+
+#define LPDDR4__DENALI_PI_16_READ_MASK                               0x010FFFFFU
+#define LPDDR4__DENALI_PI_16_WRITE_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT                          0U
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH                         20U
+#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
+#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
+
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT                             24U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH                              1U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR                              0U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET                              0U
+#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
+#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
+
+#define LPDDR4__DENALI_PI_17_READ_MASK                               0x01010001U
+#define LPDDR4__DENALI_PI_17_WRITE_MASK                              0x01010001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH                         1U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET                         0U
+#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
+#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT                             8U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH                             1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR                             0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET                             0U
+#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK                  0x00010000U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT                         16U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH                          1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR                          0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET                          0U
+#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH                        1U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR                        0U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
+#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18_READ_MASK                               0x03030301U
+#define LPDDR4__DENALI_PI_18_WRITE_MASK                              0x03030301U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK                0x00000300U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0
+
+#define LPDDR4__DENALI_PI_19_READ_MASK                               0x00000007U
+#define LPDDR4__DENALI_PI_19_WRITE_MASK                              0x00000007U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_MASK               0x00000007U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_SHIFT                       0U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_WIDTH                       3U
+#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_19
+#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_SHIFT                            8U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WIDTH                            1U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOCLR                            0U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOSET                            0U
+#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_19
+#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_START
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_SHIFT                            16U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WIDTH                             1U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOCLR                             0U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOSET                             0U
+#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_19
+#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_SHIFT                      24U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_19
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0
+
+#define LPDDR4__DENALI_PI_20_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_20_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT              8U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH              1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR              0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0
+
+#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_20
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1
+
+#define LPDDR4__DENALI_PI_21_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_21_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT              8U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH              1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR              0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1
+
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_SHIFT                      16U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_21
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_SHIFT                       24U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WIDTH                        1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOCLR                        0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOSET                        0U
+#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START
+
+#define LPDDR4__DENALI_PI_22_READ_MASK                               0x01000000U
+#define LPDDR4__DENALI_PI_22_WRITE_MASK                              0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_MASK                   0x00000001U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_SHIFT                           0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WIDTH                           1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOCLR                           0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOSET                           0U
+#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_MASK                   0x00000100U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_SHIFT                           8U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WIDTH                           1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOCLR                           0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOSET                           0U
+#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD
+
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_SHIFT                    16U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WIDTH                     1U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOCLR                     0U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOSET                     0U
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_22
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ
+
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_SHIFT                         24U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_22
+#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_23_READ_MASK                               0x00010101U
+#define LPDDR4__DENALI_PI_23_WRITE_MASK                              0x00010101U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_SHIFT                          0U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_23
+#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_23
+#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_MASK                 0x00010000U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_SHIFT                        16U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WIDTH                         1U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOCLR                         0U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOSET                         0U
+#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_23
+#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY
+
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_SHIFT                             24U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOSET                              0U
+#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_23
+#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_23__PI_WRLVL_REQ
+
+#define LPDDR4__DENALI_PI_24_READ_MASK                               0x3F3F0103U
+#define LPDDR4__DENALI_PI_24_WRITE_MASK                              0x3F3F0103U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_MASK                    0x00000003U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_SHIFT                            0U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_WIDTH                            2U
+#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_24
+#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_MASK                       0x00000100U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SHIFT                               8U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WIDTH                               1U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOCLR                               0U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOSET                               0U
+#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_24
+#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS
+
+#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_MASK                        0x003F0000U
+#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_SHIFT                               16U
+#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_WIDTH                                6U
+#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_24
+#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_24__PI_WLDQSEN
+
+#define LPDDR4__DENALI_PI_24__PI_WLMRD_MASK                          0x3F000000U
+#define LPDDR4__DENALI_PI_24__PI_WLMRD_SHIFT                                 24U
+#define LPDDR4__DENALI_PI_24__PI_WLMRD_WIDTH                                  6U
+#define LPDDR4__PI_WLMRD__REG DENALI_PI_24
+#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_24__PI_WLMRD
+
+#define LPDDR4__DENALI_PI_25_READ_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_25_WRITE_MASK                              0x0101FFFFU
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_SHIFT                         0U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_25
+#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_SHIFT                    16U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_25
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_MASK              0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_SHIFT                     24U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_25
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_26_READ_MASK                               0x01030103U
+#define LPDDR4__DENALI_PI_26_WRITE_MASK                              0x01030103U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_MASK                0x00000003U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_WIDTH                        2U
+#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_MASK                   0x00000100U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_SHIFT                           8U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_SHIFT                          16U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_MASK              0x01000000U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_SHIFT                     24U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOSET                      0U
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_27_READ_MASK                               0x0000FF01U
+#define LPDDR4__DENALI_PI_27_WRITE_MASK                              0x0000FF01U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_SHIFT                     0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOSET                     0U
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_27
+#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_PI_28_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_28_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_28
+#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_PI_29_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_29_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_29
+#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_PI_30_READ_MASK                               0x030F0F1FU
+#define LPDDR4__DENALI_PI_30_WRITE_MASK                              0x030F0F1FU
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_MASK               0x0000001FU
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_SHIFT                       0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_MASK                       0x00000F00U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_SHIFT                               8U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_WIDTH                               4U
+#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_30
+#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_30__PI_TODTH_WR
+
+#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_MASK                       0x000F0000U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_SHIFT                              16U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_WIDTH                               4U
+#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_30
+#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_30__PI_TODTH_RD
+
+#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_MASK                      0x03000000U
+#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_SHIFT                             24U
+#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_WIDTH                              2U
+#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_30
+#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_30__PI_ODT_VALUE
+
+#define LPDDR4__DENALI_PI_31_READ_MASK                               0x00000003U
+#define LPDDR4__DENALI_PI_31_WRITE_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_MASK              0x00000003U
+#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_SHIFT                      0U
+#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_WIDTH                      2U
+#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_31
+#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_PI_32_READ_MASK                               0x03FFFFFFU
+#define LPDDR4__DENALI_PI_32_WRITE_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_MASK         0x03FFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_SHIFT                 0U
+#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_WIDTH                26U
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_32
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_PI_33_READ_MASK                               0x00000F07U
+#define LPDDR4__DENALI_PI_33_WRITE_MASK                              0x00000F07U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED3_MASK                      0x00000007U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED3_SHIFT                              0U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED3_WIDTH                              3U
+#define LPDDR4__PI_RESERVED3__REG DENALI_PI_33
+#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_33__PI_RESERVED3
+
+#define LPDDR4__DENALI_PI_33__PI_RESERVED4_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED4_SHIFT                              8U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED4_WIDTH                              4U
+#define LPDDR4__PI_RESERVED4__REG DENALI_PI_33
+#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_33__PI_RESERVED4
+
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_SHIFT                             16U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOSET                              0U
+#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_33
+#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_REQ
+
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_MASK                 0x01000000U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_SHIFT                        24U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WIDTH                         1U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOCLR                         0U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOSET                         0U
+#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_33
+#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_PI_34_READ_MASK                               0x00000103U
+#define LPDDR4__DENALI_PI_34_WRITE_MASK                              0x00000103U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_MASK                    0x00000003U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_SHIFT                            0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_WIDTH                            2U
+#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK                       0x00000100U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT                               8U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH                               1U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOCLR                               0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOSET                               0U
+#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS
+
+#define LPDDR4__DENALI_PI_35_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35
+#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0
+
+#define LPDDR4__DENALI_PI_36_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT                            0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1
+
+#define LPDDR4__DENALI_PI_37_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2
+
+#define LPDDR4__DENALI_PI_38_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT                            0U
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38
+#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3
+
+#define LPDDR4__DENALI_PI_39_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT                            0U
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39
+#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4
+
+#define LPDDR4__DENALI_PI_40_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT                            0U
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40
+#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5
+
+#define LPDDR4__DENALI_PI_41_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT                            0U
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41
+#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6
+
+#define LPDDR4__DENALI_PI_42_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT                            0U
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42
+#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7
+
+#define LPDDR4__DENALI_PI_43_READ_MASK                               0x0101010FU
+#define LPDDR4__DENALI_PI_43_WRITE_MASK                              0x0101010FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK                   0x0000000FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT                           0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH                           4U
+#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT                     8U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK              0x00010000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT                     16U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_MASK        0x01000000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT               24U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH                1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR                0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET                0U
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_44_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_44_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK         0x00000001U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT                 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH                 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR                 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET                 0U
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_SHIFT                      8U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOSET                      0U
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_MASK         0x00010000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT                16U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH                 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR                 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET                 0U
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT                          24U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_45_READ_MASK                               0x00030301U
+#define LPDDR4__DENALI_PI_45_WRITE_MASK                              0x00030301U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT                      0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH                      1U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR                      0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET                      0U
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK                   0x00000300U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT                           8U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK              0x00030000U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT                     16U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_PI_46_READ_MASK                               0x000003FFU
+#define LPDDR4__DENALI_PI_46_WRITE_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK                  0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT                          0U
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH                         10U
+#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46
+#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_PI_47_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47
+#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_PI_48_READ_MASK                               0x0000FF03U
+#define LPDDR4__DENALI_PI_48_WRITE_MASK                              0x0000FF03U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK                0x00000003U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH                        2U
+#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48
+#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_PI_49_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49
+#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_PI_50_READ_MASK                               0x00FFFF01U
+#define LPDDR4__DENALI_PI_50_WRITE_MASK                              0x00FFFF01U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT                     0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET                     0U
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK                 0x00FFFF00U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT                         8U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_51_READ_MASK                               0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51_WRITE_MASK                              0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT                    0U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH                   16U
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK            0x000F0000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT                   16U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH                    4U
+#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK              0x0F000000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT                     24U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH                      4U
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM
+
+#define LPDDR4__DENALI_PI_52_READ_MASK                               0x01011F1FU
+#define LPDDR4__DENALI_PI_52_WRITE_MASK                              0x01011F1FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK               0x0000001FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT                       0U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK          0x00001F00U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT                  8U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH                  5U
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK        0x00010000U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT               16U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH                1U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR                0U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET                0U
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT                       24U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH                        1U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR                        0U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET                        0U
+#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52
+#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_PI_53_READ_MASK                               0x0300FFFFU
+#define LPDDR4__DENALI_PI_53_WRITE_MASK                              0x0300FFFFU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH                         8U
+#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT                         8U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH                         8U
+#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT                             16U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET                              0U
+#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_MASK                    0x03000000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_SHIFT                           24U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_WIDTH                            2U
+#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW
+
+#define LPDDR4__DENALI_PI_54_READ_MASK                               0x030F0101U
+#define LPDDR4__DENALI_PI_54_WRITE_MASK                              0x030F0101U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_SHIFT                               0U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WIDTH                               1U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOCLR                               0U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOSET                               0U
+#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_54__PI_CALVL_CS
+
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_MASK                      0x00000100U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_SHIFT                              8U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WIDTH                              1U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOCLR                              0U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOSET                              0U
+#define LPDDR4__PI_RESERVED5__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_54__PI_RESERVED5
+
+#define LPDDR4__DENALI_PI_54__PI_RESERVED6_MASK                      0x000F0000U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED6_SHIFT                             16U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED6_WIDTH                              4U
+#define LPDDR4__PI_RESERVED6__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_54__PI_RESERVED6
+
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK                   0x03000000U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT                          24U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH                           2U
+#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_55_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_55_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_SHIFT                         0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOSET                         0U
+#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT                     8U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK              0x00010000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT                     16U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT                          24U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE
+
+#define LPDDR4__DENALI_PI_56_READ_MASK                               0x0000FF03U
+#define LPDDR4__DENALI_PI_56_WRITE_MASK                              0x0000FF03U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_SHIFT                           0U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_WIDTH                           2U
+#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_56
+#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_PI_57_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57
+#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_PI_58_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58
+#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_PI_59_READ_MASK                               0xFFFF0301U
+#define LPDDR4__DENALI_PI_59_WRITE_MASK                              0xFFFF0301U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH                        1U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR                        0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET                        0U
+#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK             0x00000300U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT                     8U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH                     2U
+#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK                 0xFFFF0000U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT                        16U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_60_READ_MASK                               0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60_WRITE_MASK                              0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK                        0x0000001FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT                                0U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH                                5U
+#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL
+
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK                         0x00003F00U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT                                 8U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH                                 6U
+#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60
+#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD
+
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT                               16U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH                                5U
+#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH
+
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK                         0x1F000000U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT                                24U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH                                 5U
+#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60
+#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT
+
+#define LPDDR4__DENALI_PI_61_READ_MASK                               0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61_WRITE_MASK                              0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT                       0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH                       1U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR                       0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET                       0U
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK    0x00000F00U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT            8U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH            4U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK     0x000F0000U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT            16U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH             4U
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK            0xFF000000U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT                   24U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH                    8U
+#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61
+#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN
+
+#define LPDDR4__DENALI_PI_62_READ_MASK                               0x017F1FFFU
+#define LPDDR4__DENALI_PI_62_WRITE_MASK                              0x017F1FFFU
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT                                0U
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH                                8U
+#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62
+#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK               0x00001F00U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT                       8U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK               0x007F0000U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT                      16U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH                       7U
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF
+
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT       24U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH        1U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR        0U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET        0U
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_62
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
+
+#define LPDDR4__DENALI_PI_63_READ_MASK                               0xFF01FFFFU
+#define LPDDR4__DENALI_PI_63_WRITE_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK        0x000000FFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT                0U
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH                8U
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START
+
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT      8U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH      8U
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
+
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK  0x00010000U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT         16U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH          1U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR          0U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET          0U
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
+
+#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_MASK         0xFF000000U
+#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_SHIFT                24U
+#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_WIDTH                 8U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_63
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN
+
+#define LPDDR4__DENALI_PI_64_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_64_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_MASK                        0x00000001U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_SHIFT                                0U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WIDTH                                1U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOCLR                                0U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOSET                                0U
+#define LPDDR4__PI_VREF_CS__REG DENALI_PI_64
+#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_64__PI_VREF_CS
+
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_SHIFT                            8U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WIDTH                            1U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOCLR                            0U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOSET                            0U
+#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_64
+#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN
+
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_SHIFT                   16U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WIDTH                    1U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOCLR                    0U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOSET                    0U
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_64
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK      0x01000000U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT             24U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH              1U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR              0U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET              0U
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE
+
+#define LPDDR4__DENALI_PI_65_READ_MASK                               0x030701FFU
+#define LPDDR4__DENALI_PI_65_WRITE_MASK                              0x030701FFU
+#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT        0U
+#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH        8U
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_65
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT
+
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_MASK                 0x00000100U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_SHIFT                         8U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WIDTH                         1U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOCLR                         0U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOSET                         0U
+#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_65
+#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN
+
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_MASK                 0x00070000U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_SHIFT                        16U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_WIDTH                         3U
+#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_65
+#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM
+
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_MASK               0x03000000U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_SHIFT                      24U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_WIDTH                       2U
+#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_65
+#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_66_READ_MASK                               0x1F1F0301U
+#define LPDDR4__DENALI_PI_66_WRITE_MASK                              0x1F1F0301U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH                          1U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR                          0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_SHIFT                          8U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK   0x001F0000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT          16U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH           5U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK    0x1F000000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT           24U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH            5U
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_67_READ_MASK                               0x01030001U
+#define LPDDR4__DENALI_PI_67_WRITE_MASK                              0x01030001U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT                        0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH                        1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR                        0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET                        0U
+#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_SHIFT                             8U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOSET                             0U
+#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_SHIFT                          16U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_WIDTH                           2U
+#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SHIFT                             24U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WIDTH                              1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOCLR                              0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOSET                              0U
+#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS
+
+#define LPDDR4__DENALI_PI_68_READ_MASK                               0x000000FFU
+#define LPDDR4__DENALI_PI_68_WRITE_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH                         8U
+#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68
+#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_69_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH                      32U
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP
+
+#define LPDDR4__DENALI_PI_70_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX
+
+#define LPDDR4__DENALI_PI_71_READ_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_71_WRITE_MASK                              0x0101FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH                       16U
+#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT                   16U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH                    1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR                    0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET                    0U
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_SHIFT                    24U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_72_READ_MASK                               0x00030301U
+#define LPDDR4__DENALI_PI_72_WRITE_MASK                              0x00030301U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_SHIFT                     0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK            0x00000300U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT                    8U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_MASK       0x00030000U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT              16U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH               2U
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE
+
+#define LPDDR4__DENALI_PI_73_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK   0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT           0U
+#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH          32U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_73
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0
+
+#define LPDDR4__DENALI_PI_74_READ_MASK                               0x00010101U
+#define LPDDR4__DENALI_PI_74_WRITE_MASK                              0x00010101U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK   0x00000001U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT           0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH           1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOCLR           0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOSET           0U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1
+
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_SHIFT                     8U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WIDTH                     1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOCLR                     0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN
+
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_MASK                   0x00010000U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_SHIFT                          16U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WIDTH                           1U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOCLR                           0U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOSET                           0U
+#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_74
+#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM
+
+#define LPDDR4__DENALI_PI_75_READ_MASK                               0x010003FFU
+#define LPDDR4__DENALI_PI_75_WRITE_MASK                              0x010003FFU
+#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_MASK                 0x000003FFU
+#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_SHIFT                         0U
+#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_WIDTH                        10U
+#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_75
+#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW
+
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_MASK      0x00010000U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT             16U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH              1U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR              0U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET              0U
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_75
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START
+
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_SHIFT                    24U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WIDTH                     1U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOCLR                     0U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE
+
+#define LPDDR4__DENALI_PI_76_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_76_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_SHIFT                          0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN
+
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_SHIFT                      8U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WIDTH                      1U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOCLR                      0U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOSET                      0U
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_76
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_MASK                  0x00010000U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_SHIFT                         16U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN
+
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_MASK          0x01000000U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT                 24U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH                  1U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR                  0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOSET                  0U
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN
+
+#define LPDDR4__DENALI_PI_77_READ_MASK                               0x1F070303U
+#define LPDDR4__DENALI_PI_77_WRITE_MASK                              0x1F070303U
+#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_SHIFT                       0U
+#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_WIDTH                       2U
+#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_77
+#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_MASK                      0x00000300U
+#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_SHIFT                              8U
+#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_WIDTH                              2U
+#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_77
+#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_77__PI_BANK_DIFF
+
+#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_MASK                       0x00070000U
+#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_SHIFT                              16U
+#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_WIDTH                               3U
+#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_77
+#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_77__PI_ROW_DIFF
+
+#define LPDDR4__DENALI_PI_77__PI_TCCD_MASK                           0x1F000000U
+#define LPDDR4__DENALI_PI_77__PI_TCCD_SHIFT                                  24U
+#define LPDDR4__DENALI_PI_77__PI_TCCD_WIDTH                                   5U
+#define LPDDR4__PI_TCCD__REG DENALI_PI_77
+#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_77__PI_TCCD
+
+#define LPDDR4__DENALI_PI_78_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_78_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED7_MASK                      0x0000000FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED7_SHIFT                              0U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED7_WIDTH                              4U
+#define LPDDR4__PI_RESERVED7__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_78__PI_RESERVED7
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED8_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED8_SHIFT                              8U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED8_WIDTH                              4U
+#define LPDDR4__PI_RESERVED8__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_78__PI_RESERVED8
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED9_MASK                      0x000F0000U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED9_SHIFT                             16U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED9_WIDTH                              4U
+#define LPDDR4__PI_RESERVED9__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_78__PI_RESERVED9
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED10_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED10_SHIFT                            24U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED10_WIDTH                             4U
+#define LPDDR4__PI_RESERVED10__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_78__PI_RESERVED10
+
+#define LPDDR4__DENALI_PI_79_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_79_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_79__PI_RESERVED11_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_79__PI_RESERVED11_SHIFT                             0U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED11_WIDTH                             4U
+#define LPDDR4__PI_RESERVED11__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_79__PI_RESERVED11
+
+#define LPDDR4__DENALI_PI_79__PI_RESERVED12_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED12_SHIFT                             8U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED12_WIDTH                             4U
+#define LPDDR4__PI_RESERVED12__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_79__PI_RESERVED12
+
+#define LPDDR4__DENALI_PI_79__PI_RESERVED13_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED13_SHIFT                            16U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED13_WIDTH                             4U
+#define LPDDR4__PI_RESERVED13__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_79__PI_RESERVED13
+
+#define LPDDR4__DENALI_PI_79__PI_RESERVED14_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED14_SHIFT                            24U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED14_WIDTH                             4U
+#define LPDDR4__PI_RESERVED14__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_79__PI_RESERVED14
+
+#define LPDDR4__DENALI_PI_80_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_80_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_80__PI_RESERVED15_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_80__PI_RESERVED15_SHIFT                             0U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED15_WIDTH                             4U
+#define LPDDR4__PI_RESERVED15__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_80__PI_RESERVED15
+
+#define LPDDR4__DENALI_PI_80__PI_RESERVED16_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED16_SHIFT                             8U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED16_WIDTH                             4U
+#define LPDDR4__PI_RESERVED16__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_80__PI_RESERVED16
+
+#define LPDDR4__DENALI_PI_80__PI_RESERVED17_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED17_SHIFT                            16U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED17_WIDTH                             4U
+#define LPDDR4__PI_RESERVED17__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_80__PI_RESERVED17
+
+#define LPDDR4__DENALI_PI_80__PI_RESERVED18_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED18_SHIFT                            24U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED18_WIDTH                             4U
+#define LPDDR4__PI_RESERVED18__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_80__PI_RESERVED18
+
+#define LPDDR4__DENALI_PI_81_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_81_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_81__PI_RESERVED19_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_81__PI_RESERVED19_SHIFT                             0U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED19_WIDTH                             4U
+#define LPDDR4__PI_RESERVED19__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_81__PI_RESERVED19
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED20_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED20_SHIFT                             8U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED20_WIDTH                             4U
+#define LPDDR4__PI_RESERVED20__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_81__PI_RESERVED20
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED21_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED21_SHIFT                            16U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED21_WIDTH                             4U
+#define LPDDR4__PI_RESERVED21__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_81__PI_RESERVED21
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED22_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED22_SHIFT                            24U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED22_WIDTH                             4U
+#define LPDDR4__PI_RESERVED22__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_81__PI_RESERVED22
+
+#define LPDDR4__DENALI_PI_82_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED23_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED23_SHIFT                             0U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED23_WIDTH                             4U
+#define LPDDR4__PI_RESERVED23__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_82__PI_RESERVED23
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED24_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED24_SHIFT                             8U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED24_WIDTH                             4U
+#define LPDDR4__PI_RESERVED24__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_82__PI_RESERVED24
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED25_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED25_SHIFT                            16U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED25_WIDTH                             4U
+#define LPDDR4__PI_RESERVED25__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_82__PI_RESERVED25
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED26_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED26_SHIFT                            24U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED26_WIDTH                             4U
+#define LPDDR4__PI_RESERVED26__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_82__PI_RESERVED26
+
+#define LPDDR4__DENALI_PI_83_READ_MASK                               0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_83_WRITE_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_MASK                     0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_SHIFT                             0U
+#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_WIDTH                            30U
+#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_83
+#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_83__PI_INT_STATUS
+
+#define LPDDR4__DENALI_PI_84__PI_INT_ACK_MASK                        0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_84__PI_INT_ACK_SHIFT                                0U
+#define LPDDR4__DENALI_PI_84__PI_INT_ACK_WIDTH                               29U
+#define LPDDR4__PI_INT_ACK__REG DENALI_PI_84
+#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_84__PI_INT_ACK
+
+#define LPDDR4__DENALI_PI_85_READ_MASK                               0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_85_WRITE_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_INT_MASK_MASK                       0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_INT_MASK_SHIFT                               0U
+#define LPDDR4__DENALI_PI_85__PI_INT_MASK_WIDTH                              30U
+#define LPDDR4__PI_INT_MASK__REG DENALI_PI_85
+#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_85__PI_INT_MASK
+
+#define LPDDR4__DENALI_PI_86_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_86
+#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_PI_87_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_87
+#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_PI_88_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_88
+#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_PI_89_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_89
+#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_PI_90_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_PI_91_READ_MASK                               0x011F3F01U
+#define LPDDR4__DENALI_PI_91_WRITE_MASK                              0x011F3F01U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH                       1U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOCLR                       0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOSET                       0U
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK                         0x00003F00U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT                                 8U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH                                 6U
+#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91
+#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN
+
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT                       16U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH                        5U
+#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91
+#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT                           24U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH                            1U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR                            0U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET                            0U
+#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91
+#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN
+
+#define LPDDR4__DENALI_PI_92_READ_MASK                               0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_92_WRITE_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_MASK                  0x0000001FU
+#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_SHIFT                          0U
+#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_WIDTH                          5U
+#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_92
+#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX
+
+#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_MASK                      0x00001F00U
+#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_SHIFT                              8U
+#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_WIDTH                              5U
+#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_92
+#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_92__PI_ACT_N_MUX
+
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_SHIFT                              16U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_WIDTH                               5U
+#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_92
+#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_0
+
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_MASK                       0x1F000000U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_SHIFT                              24U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_WIDTH                               5U
+#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_92
+#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_1
+
+#define LPDDR4__DENALI_PI_93_READ_MASK                               0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_93_WRITE_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_MASK                      0x0000001FU
+#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_SHIFT                              0U
+#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_WIDTH                              5U
+#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_93
+#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_RAS_N_MUX
+
+#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_MASK                      0x00001F00U
+#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_SHIFT                              8U
+#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_WIDTH                              5U
+#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_93
+#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_CAS_N_MUX
+
+#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_SHIFT                              16U
+#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_WIDTH                               5U
+#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_93
+#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_WE_N_MUX
+
+#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_MASK                     0x1F000000U
+#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_SHIFT                            24U
+#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_WIDTH                             5U
+#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_93
+#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_93__PI_BANK_MUX_0
+
+#define LPDDR4__DENALI_PI_94_READ_MASK                               0x0101011FU
+#define LPDDR4__DENALI_PI_94_WRITE_MASK                              0x0101011FU
+#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_MASK                     0x0000001FU
+#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_WIDTH                             5U
+#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_94
+#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_94__PI_BANK_MUX_1
+
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_SHIFT                      8U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WIDTH                      1U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOCLR                      0U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOSET                      0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_94
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN
+
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_MASK          0x00010000U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_SHIFT                 16U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WIDTH                  1U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOCLR                  0U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOSET                  0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_94
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0
+
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_MASK          0x01000000U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_SHIFT                 24U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WIDTH                  1U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOCLR                  0U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOSET                  0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_94
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1
+
+#define LPDDR4__DENALI_PI_95_READ_MASK                               0x03FFFF01U
+#define LPDDR4__DENALI_PI_95_WRITE_MASK                              0x03FFFF01U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_MASK        0x00000001U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT                0U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH                1U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR                0U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET                0U
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_95
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_MASK               0x00FFFF00U
+#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_SHIFT                       8U
+#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_WIDTH                      16U
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_95
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_MASK            0x03000000U
+#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_SHIFT                   24U
+#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_95
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_96_READ_MASK                               0x01030107U
+#define LPDDR4__DENALI_PI_96_WRITE_MASK                              0x01030107U
+#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_MASK                 0x00000007U
+#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_SHIFT                         0U
+#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_WIDTH                         3U
+#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_96
+#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_MASK                        0x00000100U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_SHIFT                                8U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WIDTH                                1U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOCLR                                0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOSET                                0U
+#define LPDDR4__PI_BIST_GO__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_96__PI_BIST_GO
+
+#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_MASK                    0x00030000U
+#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_SHIFT                           16U
+#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_WIDTH                            2U
+#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_96__PI_BIST_RESULT
+
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_MASK         0x01000000U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_SHIFT                24U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WIDTH                 1U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOCLR                 0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOSET                 0U
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE
+
+#define LPDDR4__DENALI_PI_97_READ_MASK                               0x000101FFU
+#define LPDDR4__DENALI_PI_97_WRITE_MASK                              0x000101FFU
+#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_SHIFT                             0U
+#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_WIDTH                             8U
+#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_97
+#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_97__PI_ADDR_SPACE
+
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_MASK                0x00000100U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_SHIFT                        8U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WIDTH                        1U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOCLR                        0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOSET                        0U
+#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_SHIFT                       16U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WIDTH                        1U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOCLR                        0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOSET                        0U
+#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_PI_98_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_WIDTH                  32U
+#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_98
+#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_PI_99_READ_MASK                               0x0000FF01U
+#define LPDDR4__DENALI_PI_99_WRITE_MASK                              0x0000FF01U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_MASK           0x00000001U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WIDTH                   1U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOCLR                   0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOSET                   0U
+#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_99
+#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_MASK             0x0000FF00U
+#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_SHIFT                     8U
+#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_WIDTH                     8U
+#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_99
+#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN
+
+#define LPDDR4__DENALI_PI_100_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_100_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_WIDTH                       32U
+#define LPDDR4__PI_BIST_DATA_MASK__REG DENALI_PI_100
+#define LPDDR4__PI_BIST_DATA_MASK__FLD LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK
+
+#define LPDDR4__DENALI_PI_101_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_101_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_MASK                0x00000FFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_SHIFT                        0U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_WIDTH                       12U
+#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_101
+#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_MASK                 0x0FFF0000U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_SHIFT                        16U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_WIDTH                        12U
+#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_101
+#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP
+
+#define LPDDR4__DENALI_PI_102_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_102_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_102
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0
+
+#define LPDDR4__DENALI_PI_103_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_103_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_103
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1
+
+#define LPDDR4__DENALI_PI_104_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_104_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_104
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0
+
+#define LPDDR4__DENALI_PI_105_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_105_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1
+
+#define LPDDR4__DENALI_PI_106_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_106_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0
+
+#define LPDDR4__DENALI_PI_107_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_107_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_107
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1
+
+#define LPDDR4__DENALI_PI_108_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_108_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_108
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0
+
+#define LPDDR4__DENALI_PI_109_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_109_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_109
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1
+
+#define LPDDR4__DENALI_PI_110_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_110
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0
+
+#define LPDDR4__DENALI_PI_111_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_111_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1
+
+#define LPDDR4__DENALI_PI_112_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_112
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0
+
+#define LPDDR4__DENALI_PI_113_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_113_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_113
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1
+
+#define LPDDR4__DENALI_PI_114_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_114
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0
+
+#define LPDDR4__DENALI_PI_115_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_115_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_115
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1
+
+#define LPDDR4__DENALI_PI_116_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_116
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0
+
+#define LPDDR4__DENALI_PI_117_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_117_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_117
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1
+
+#define LPDDR4__DENALI_PI_118_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_118
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0
+
+#define LPDDR4__DENALI_PI_119_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PI_119_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_119
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1
+
+#define LPDDR4__DENALI_PI_120_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0
+
+#define LPDDR4__DENALI_PI_121_READ_MASK                              0x03030703U
+#define LPDDR4__DENALI_PI_121_WRITE_MASK                             0x03030703U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_WIDTH                    2U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1
+
+#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_MASK                     0x00000700U
+#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_SHIFT                             8U
+#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_WIDTH                             3U
+#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_MODE
+
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_SHIFT                       16U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_WIDTH                        2U
+#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE
+
+#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_MASK                 0x03000000U
+#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_SHIFT                        24U
+#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_WIDTH                         2U
+#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE
+
+#define LPDDR4__DENALI_PI_122_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_122
+#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0
+
+#define LPDDR4__DENALI_PI_123_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_123
+#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1
+
+#define LPDDR4__DENALI_PI_124_READ_MASK                              0x0000003FU
+#define LPDDR4__DENALI_PI_124_WRITE_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_SHIFT                          0U
+#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_WIDTH                          6U
+#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_124
+#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM
+
+#define LPDDR4__DENALI_PI_125_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_125_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_SHIFT                          0U
+#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_125
+#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0
+
+#define LPDDR4__DENALI_PI_126_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_126
+#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1
+
+#define LPDDR4__DENALI_PI_127_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_127
+#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2
+
+#define LPDDR4__DENALI_PI_128_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_SHIFT                          0U
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_128
+#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3
+
+#define LPDDR4__DENALI_PI_129_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_SHIFT                          0U
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_129
+#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4
+
+#define LPDDR4__DENALI_PI_130_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_SHIFT                          0U
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_130
+#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5
+
+#define LPDDR4__DENALI_PI_131_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_SHIFT                          0U
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6
+
+#define LPDDR4__DENALI_PI_132_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_SHIFT                          0U
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_132
+#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7
+
+#define LPDDR4__DENALI_PI_133_READ_MASK                              0x0101010FU
+#define LPDDR4__DENALI_PI_133_WRITE_MASK                             0x0101010FU
+#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_MASK                      0x0000000FU
+#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_SHIFT                              0U
+#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_WIDTH                              4U
+#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_133
+#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_133__PI_COL_DIFF
+
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOSET                          0U
+#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_133
+#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN
+
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_SHIFT                             16U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WIDTH                              1U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOCLR                              0U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOSET                              0U
+#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_133
+#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_133__PI_CRC_CALC
+
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_SHIFT                      24U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WIDTH                       1U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOCLR                       0U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOSET                       0U
+#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_133
+#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN
+
+#define LPDDR4__DENALI_PI_134_READ_MASK                              0x00010101U
+#define LPDDR4__DENALI_PI_134_WRITE_MASK                             0x00010101U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_MASK        0x00000001U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT                0U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH                1U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR                0U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOSET                0U
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK           0x00000100U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT                   8U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH                   1U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR                   0U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET                   0U
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK      0x00010000U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT             16U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH              1U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR              0U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET              0U
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_SHIFT                       24U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WIDTH                        1U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOCLR                        0U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOSET                        0U
+#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_134
+#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ
+
+#define LPDDR4__DENALI_PI_135_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_135_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT                        0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH                        1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR                        0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET                        0U
+#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK                   0x00000100U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT                           8U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH                           1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR                           0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET                           0U
+#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK         0x00010000U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT                16U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH                 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR                 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET                 0U
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_MASK              0x01000000U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_SHIFT                     24U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WIDTH                      1U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOCLR                      0U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOSET                      0U
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_PI_136_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_136_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_SHIFT                            0U
+#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_WIDTH                           32U
+#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_136
+#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_136__PI_TRST_PWRON
+
+#define LPDDR4__DENALI_PI_137_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_WIDTH                         32U
+#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_137
+#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE
+
+#define LPDDR4__DENALI_PI_138_READ_MASK                              0xFFFF0101U
+#define LPDDR4__DENALI_PI_138_WRITE_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_SHIFT                               0U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WIDTH                               1U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOCLR                               0U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOSET                               0U
+#define LPDDR4__PI_DLL_RST__REG DENALI_PI_138
+#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST
+
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOSET                          0U
+#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_138
+#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN
+
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_MASK                 0xFFFF0000U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_SHIFT                        16U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_WIDTH                        16U
+#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_138
+#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY
+
+#define LPDDR4__DENALI_PI_139_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_139_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_MASK               0x000000FFU
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_SHIFT                       0U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_WIDTH                       8U
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_139
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_PI_140_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_140_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_MASK                 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_SHIFT                         0U
+#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_WIDTH                        26U
+#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_140
+#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG
+
+#define LPDDR4__DENALI_PI_141_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PI_141_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_MASK                    0x000000FFU
+#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_SHIFT                            0U
+#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_WIDTH                            8U
+#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_141
+#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_141__PI_MRW_STATUS
+
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_SHIFT                            8U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WIDTH                            1U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOCLR                            0U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOSET                            0U
+#define LPDDR4__PI_RESERVED27__REG DENALI_PI_141
+#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_141__PI_RESERVED27
+
+#define LPDDR4__DENALI_PI_142_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_142_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT                          0U
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH                         17U
+#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142
+#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG
+
+#define LPDDR4__DENALI_PI_143_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT                 0U
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH                24U
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT                           24U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH                            1U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR                            0U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET                            0U
+#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143
+#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT
+
+#define LPDDR4__DENALI_PI_144_READ_MASK                              0x01010003U
+#define LPDDR4__DENALI_PI_144_WRITE_MASK                             0x01010003U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED28_MASK                    0x00000003U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED28_SHIFT                            0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED28_WIDTH                            2U
+#define LPDDR4__PI_RESERVED28__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_144__PI_RESERVED28
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED29_MASK                    0x00000F00U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED29_SHIFT                            8U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED29_WIDTH                            4U
+#define LPDDR4__PI_RESERVED29__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_144__PI_RESERVED29
+
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT                       16U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH                        1U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR                        0U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET                        0U
+#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144
+#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_SHIFT                           24U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WIDTH                            1U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOCLR                            0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOSET                            0U
+#define LPDDR4__PI_RESERVED30__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_144__PI_RESERVED30
+
+#define LPDDR4__DENALI_PI_145_READ_MASK                              0xFF010F07U
+#define LPDDR4__DENALI_PI_145_WRITE_MASK                             0xFF010F07U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED31_MASK                    0x00000007U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED31_SHIFT                            0U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED31_WIDTH                            3U
+#define LPDDR4__PI_RESERVED31__REG DENALI_PI_145
+#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_145__PI_RESERVED31
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK             0x00000F00U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT                     8U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT                    16U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH                     1U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR                     0U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT                            24U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0
+
+#define LPDDR4__DENALI_PI_146_READ_MASK                              0x0FFF010FU
+#define LPDDR4__DENALI_PI_146_WRITE_MASK                             0x0FFF010FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK             0x0000000FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT                     8U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH                     1U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR                     0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK             0x0F000000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT                    24U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2
+
+#define LPDDR4__DENALI_PI_147_READ_MASK                              0x010FFF01U
+#define LPDDR4__DENALI_PI_147_WRITE_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH                     1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR                     0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK             0x000F0000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT                    16U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT                    24U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH                     1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR                     0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3
+
+#define LPDDR4__DENALI_PI_148_READ_MASK                              0xFF010FFFU
+#define LPDDR4__DENALI_PI_148_WRITE_MASK                             0xFF010FFFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT                             0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK             0x00000F00U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT                     8U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT                    16U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH                     1U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR                     0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT                            24U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4
+
+#define LPDDR4__DENALI_PI_149_READ_MASK                              0x0FFF010FU
+#define LPDDR4__DENALI_PI_149_WRITE_MASK                             0x0FFF010FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK             0x0000000FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT                     0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT                     8U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH                     1U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR                     0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT                            16U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK             0x0F000000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT                    24U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6
+
+#define LPDDR4__DENALI_PI_150_READ_MASK                              0x010FFF01U
+#define LPDDR4__DENALI_PI_150_WRITE_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT                     0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH                     1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR                     0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT                             8U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK             0x000F0000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT                    16U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT                    24U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH                     1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR                     0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7
+
+#define LPDDR4__DENALI_PI_151_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_151_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT                             0U
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151
+#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7
+
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT                        0U
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH                        8U
+#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152
+#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE
+
+#define LPDDR4__DENALI_PI_153_READ_MASK                              0x011F1F01U
+#define LPDDR4__DENALI_PI_153_WRITE_MASK                             0x011F1F01U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK                      0x00000001U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT                              0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH                              1U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR                              0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET                              0U
+#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153
+#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK            0x00001F00U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT                    8U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH                    5U
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK            0x001F0000U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT                   16U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH                    5U
+#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM
+
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_SHIFT                           24U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WIDTH                            1U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOCLR                            0U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOSET                            0U
+#define LPDDR4__PI_RESERVED32__REG DENALI_PI_153
+#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_153__PI_RESERVED32
+
+#define LPDDR4__DENALI_PI_154_READ_MASK                              0x01010103U
+#define LPDDR4__DENALI_PI_154_WRITE_MASK                             0x01010103U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK                  0x00000003U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH                          2U
+#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154
+#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_SHIFT                            8U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WIDTH                            1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOCLR                            0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOSET                            0U
+#define LPDDR4__PI_RESERVED33__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_154__PI_RESERVED33
+
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT                       16U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH                        1U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR                        0U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET                        0U
+#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154
+#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_SHIFT                           24U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WIDTH                            1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOCLR                            0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOSET                            0U
+#define LPDDR4__PI_RESERVED34__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_154__PI_RESERVED34
+
+#define LPDDR4__DENALI_PI_155_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_155_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET                            0U
+#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_SHIFT                            8U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOSET                            0U
+#define LPDDR4__PI_RESERVED36__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_155__PI_RESERVED36
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_SHIFT                           16U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOSET                            0U
+#define LPDDR4__PI_RESERVED37__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_155__PI_RESERVED37
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_SHIFT                           24U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOSET                            0U
+#define LPDDR4__PI_RESERVED38__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_155__PI_RESERVED38
+
+#define LPDDR4__DENALI_PI_156_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_156_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET                            0U
+#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_SHIFT                            8U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOSET                            0U
+#define LPDDR4__PI_RESERVED40__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_156__PI_RESERVED40
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_SHIFT                           16U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOSET                            0U
+#define LPDDR4__PI_RESERVED41__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_156__PI_RESERVED41
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_SHIFT                           24U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOSET                            0U
+#define LPDDR4__PI_RESERVED42__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_156__PI_RESERVED42
+
+#define LPDDR4__DENALI_PI_157_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_157_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET                            0U
+#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_SHIFT                            8U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOSET                            0U
+#define LPDDR4__PI_RESERVED44__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_157__PI_RESERVED44
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_SHIFT                           16U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOSET                            0U
+#define LPDDR4__PI_RESERVED45__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_157__PI_RESERVED45
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_SHIFT                           24U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOSET                            0U
+#define LPDDR4__PI_RESERVED46__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_157__PI_RESERVED46
+
+#define LPDDR4__DENALI_PI_158_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_158_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET                            0U
+#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_SHIFT                            8U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOSET                            0U
+#define LPDDR4__PI_RESERVED48__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_158__PI_RESERVED48
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_SHIFT                           16U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOSET                            0U
+#define LPDDR4__PI_RESERVED49__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_158__PI_RESERVED49
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_SHIFT                           24U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOSET                            0U
+#define LPDDR4__PI_RESERVED50__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_158__PI_RESERVED50
+
+#define LPDDR4__DENALI_PI_159_READ_MASK                              0x00FF0101U
+#define LPDDR4__DENALI_PI_159_WRITE_MASK                             0x00FF0101U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_SHIFT                            0U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WIDTH                            1U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOCLR                            0U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOSET                            0U
+#define LPDDR4__PI_RESERVED51__REG DENALI_PI_159
+#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_159__PI_RESERVED51
+
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_SHIFT                            8U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WIDTH                            1U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOCLR                            0U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOSET                            0U
+#define LPDDR4__PI_RESERVED52__REG DENALI_PI_159
+#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_159__PI_RESERVED52
+
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT                16U
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH                 8U
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND
+
+#define LPDDR4__DENALI_PI_160_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PI_160_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_MASK                    0x000001FFU
+#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_SHIFT                            0U
+#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_WIDTH                            9U
+#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_160
+#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_160__PI_TREFBW_THR
+
+#define LPDDR4__DENALI_PI_161_READ_MASK                              0x0000001FU
+#define LPDDR4__DENALI_PI_161_WRITE_MASK                             0x0000001FU
+#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_MASK          0x0000001FU
+#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_SHIFT                  0U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_WIDTH                  5U
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_161
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY
+
+#define LPDDR4__DENALI_PI_162_READ_MASK                              0x01031F01U
+#define LPDDR4__DENALI_PI_162_WRITE_MASK                             0x01031F01U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_MASK           0x00000001U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_SHIFT                   0U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WIDTH                   1U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOCLR                   0U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOSET                   0U
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_162
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PI_162__PI_RESERVED53_MASK                    0x00001F00U
+#define LPDDR4__DENALI_PI_162__PI_RESERVED53_SHIFT                            8U
+#define LPDDR4__DENALI_PI_162__PI_RESERVED53_WIDTH                            5U
+#define LPDDR4__PI_RESERVED53__REG DENALI_PI_162
+#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_162__PI_RESERVED53
+
+#define LPDDR4__DENALI_PI_162__PI_CATR_MASK                          0x00030000U
+#define LPDDR4__DENALI_PI_162__PI_CATR_SHIFT                                 16U
+#define LPDDR4__DENALI_PI_162__PI_CATR_WIDTH                                  2U
+#define LPDDR4__PI_CATR__REG DENALI_PI_162
+#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_162__PI_CATR
+
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT                         24U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH                          1U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR                          0U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET                          0U
+#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162
+#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ
+
+#define LPDDR4__DENALI_PI_163_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_163_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_MASK            0x00000001U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_SHIFT                    0U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WIDTH                    1U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOCLR                    0U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOSET                    0U
+#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_163
+#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE
+
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_MASK                 0x00000100U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_SHIFT                         8U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOSET                         0U
+#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_163
+#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC
+
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_MASK           0x00010000U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_SHIFT                  16U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WIDTH                   1U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOCLR                   0U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOSET                   0U
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_163
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ
+
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_MASK         0x01000000U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_SHIFT                24U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WIDTH                 1U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOCLR                 0U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOSET                 0U
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_163
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START
+
+#define LPDDR4__DENALI_PI_164_READ_MASK                              0x00FFFF07U
+#define LPDDR4__DENALI_PI_164_WRITE_MASK                             0x00FFFF07U
+#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK    0x00000007U
+#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT            0U
+#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH            3U
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_164
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY
+
+#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_MASK                      0x00FFFF00U
+#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_SHIFT                              8U
+#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_WIDTH                             16U
+#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_164
+#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_164__PI_TVREF_F0
+
+#define LPDDR4__DENALI_PI_165_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_165_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_WIDTH                             16U
+#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_165
+#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F1
+
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_MASK                      0xFFFF0000U
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_SHIFT                             16U
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_WIDTH                             16U
+#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_165
+#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F2
+
+#define LPDDR4__DENALI_PI_166_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_166_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_166
+#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F0
+
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_SHIFT                               8U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_166
+#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F1
+
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_166
+#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F2
+
+#define LPDDR4__DENALI_PI_167_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_167_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT             0U
+#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_167
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0
+
+#define LPDDR4__DENALI_PI_168_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_168_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT             0U
+#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_168
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1
+
+#define LPDDR4__DENALI_PI_169_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_169_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT             0U
+#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_169
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2
+
+#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_MASK                     0x000FFF00U
+#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_169
+#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_169__PI_ZQINIT_F0
+
+#define LPDDR4__DENALI_PI_170_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_170_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_MASK                     0x00000FFFU
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_170
+#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F1
+
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_170
+#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F2
+
+#define LPDDR4__DENALI_PI_171_READ_MASK                              0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_171_WRITE_MASK                             0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_MASK                      0x0000007FU
+#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_171__PI_WRLAT_F0
+
+#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_MASK               0x00003F00U
+#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_SHIFT                       8U
+#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_WIDTH                       6U
+#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_MASK              0x000F0000U
+#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_SHIFT                     16U
+#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_WIDTH                      4U
+#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK  0xFF000000U
+#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT         24U
+#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH          8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0
+
+#define LPDDR4__DENALI_PI_172_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_172_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_MASK                 0x0000007FU
+#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_172
+#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_MASK                      0x00007F00U
+#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_SHIFT                              8U
+#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_172
+#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_172__PI_WRLAT_F1
+
+#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_MASK               0x003F0000U
+#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_SHIFT                      16U
+#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_WIDTH                       6U
+#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_172
+#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_MASK              0x0F000000U
+#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_SHIFT                     24U
+#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_WIDTH                      4U
+#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_172
+#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_PI_173_READ_MASK                              0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_173_WRITE_MASK                             0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK  0x000000FFU
+#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT          0U
+#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH          8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_173
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1
+
+#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_MASK                 0x00007F00U
+#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_173
+#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_MASK                      0x007F0000U
+#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_SHIFT                             16U
+#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_173
+#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_173__PI_WRLAT_F2
+
+#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_MASK               0x3F000000U
+#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_SHIFT                      24U
+#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_WIDTH                       6U
+#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_173
+#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_PI_174_READ_MASK                              0x007FFF0FU
+#define LPDDR4__DENALI_PI_174_WRITE_MASK                             0x007FFF0FU
+#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_SHIFT                      0U
+#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_WIDTH                      4U
+#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_174
+#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT          8U
+#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH          8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_174
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2
+
+#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_MASK                 0x007F0000U
+#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_174
+#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_PI_175_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_175_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_175
+#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_175__PI_TRFC_F0
+
+#define LPDDR4__DENALI_PI_176_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_176_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_176__PI_TREF_F0_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_176__PI_TREF_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_176__PI_TREF_F0_WIDTH                              20U
+#define LPDDR4__PI_TREF_F0__REG DENALI_PI_176
+#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TREF_F0
+
+#define LPDDR4__DENALI_PI_177_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_177_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_177
+#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_177__PI_TRFC_F1
+
+#define LPDDR4__DENALI_PI_178_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_178_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_178__PI_TREF_F1_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_178__PI_TREF_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_178__PI_TREF_F1_WIDTH                              20U
+#define LPDDR4__PI_TREF_F1__REG DENALI_PI_178
+#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_178__PI_TREF_F1
+
+#define LPDDR4__DENALI_PI_179_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_179_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_179
+#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_179__PI_TRFC_F2
+
+#define LPDDR4__DENALI_PI_180_READ_MASK                              0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_180_WRITE_MASK                             0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_180__PI_TREF_F2_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_180__PI_TREF_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_180__PI_TREF_F2_WIDTH                              20U
+#define LPDDR4__PI_TREF_F2__REG DENALI_PI_180
+#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_180__PI_TREF_F2
+
+#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_MASK            0x0F000000U
+#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_SHIFT                   24U
+#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_180
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_PI_181_READ_MASK                              0x03030F0FU
+#define LPDDR4__DENALI_PI_181_WRITE_MASK                             0x03030F0FU
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_181
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_MASK            0x00000F00U
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_SHIFT                    8U
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_181
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_181
+#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_MASK                   0x03000000U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_181
+#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_182_READ_MASK                              0x0003FF03U
+#define LPDDR4__DENALI_PI_182_WRITE_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_182
+#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_MASK              0x0003FF00U
+#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_SHIFT                      8U
+#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_182
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0
+
+#define LPDDR4__DENALI_PI_183_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_183_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_SHIFT                      0U
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_183
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1
+
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_MASK              0x03FF0000U
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_SHIFT                     16U
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_183
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2
+
+#define LPDDR4__DENALI_PI_184_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PI_184_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_184
+#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WIDTH                             1U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOCLR                             0U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_184
+#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F0
+
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_184
+#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_MASK                     0x01000000U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WIDTH                             1U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOCLR                             0U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_184
+#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F1
+
+#define LPDDR4__DENALI_PI_185_READ_MASK                              0x0F0F01FFU
+#define LPDDR4__DENALI_PI_185_WRITE_MASK                             0x0F0F01FFU
+#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_185
+#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WIDTH                             1U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOCLR                             0U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_185
+#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_ODT_EN_F2
+
+#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_185
+#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_185__PI_ODTLON_F0
+
+#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_MASK                 0x0F000000U
+#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_185
+#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0
+
+#define LPDDR4__DENALI_PI_186_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_186_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_186
+#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F1
+
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_MASK                 0x00000F00U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_186
+#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1
+
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_186
+#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F2
+
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_MASK                 0x0F000000U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_SHIFT                        24U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_186
+#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2
+
+#define LPDDR4__DENALI_PI_187_READ_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_187_WRITE_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_MASK                 0x0000003FU
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_WIDTH                         6U
+#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_187
+#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_MASK                 0x00003F00U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_WIDTH                         6U
+#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_187
+#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_MASK                 0x003F0000U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_WIDTH                         6U
+#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_187
+#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_MASK                 0x3F000000U
+#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_WIDTH                         6U
+#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_187
+#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_188_READ_MASK                              0x03033F3FU
+#define LPDDR4__DENALI_PI_188_WRITE_MASK                             0x03033F3FU
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_MASK                 0x0000003FU
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_WIDTH                         6U
+#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_188
+#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_MASK                 0x00003F00U
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_SHIFT                         8U
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_WIDTH                         6U
+#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_188
+#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_188
+#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_SHIFT                     24U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_188
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0
+
+#define LPDDR4__DENALI_PI_189_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_189_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_MASK              0x00000300U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_SHIFT                      8U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1
+
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_SHIFT                     24U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2
+
+#define LPDDR4__DENALI_PI_190_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_190_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_MASK                    0x000000FFU
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_WIDTH                            8U
+#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_190
+#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0
+
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_SHIFT                            8U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_WIDTH                            8U
+#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_190
+#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1
+
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_SHIFT                           16U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_WIDTH                            8U
+#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_190
+#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2
+
+#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_SHIFT                     24U
+#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_190
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0
+
+#define LPDDR4__DENALI_PI_191_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_191_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_MASK             0x00000003U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_SHIFT                     0U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_SHIFT                       8U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_MASK             0x00030000U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_SHIFT                    16U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_SHIFT                     24U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1
+
+#define LPDDR4__DENALI_PI_192_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_192_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_MASK             0x00000003U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1
+
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_SHIFT                       8U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1
+
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_MASK             0x00030000U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_SHIFT                    16U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1
+
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_SHIFT                     24U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2
+
+#define LPDDR4__DENALI_PI_193_READ_MASK                              0xFF030303U
+#define LPDDR4__DENALI_PI_193_WRITE_MASK                             0xFF030303U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_MASK             0x00000003U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_193
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2
+
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_SHIFT                       8U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_193
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2
+
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_MASK             0x00030000U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_SHIFT                    16U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_193
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2
+
+#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_SHIFT                         24U
+#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_WIDTH                          8U
+#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_193
+#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_194_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_194_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_SHIFT                          0U
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_WIDTH                          8U
+#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_194
+#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_SHIFT                          8U
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_WIDTH                          8U
+#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_194
+#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_WIDTH                          8U
+#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_194
+#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_WIDTH                          8U
+#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_194
+#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_195_READ_MASK                              0x070707FFU
+#define LPDDR4__DENALI_PI_195_WRITE_MASK                             0x070707FFU
+#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_MASK                  0x000000FFU
+#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_WIDTH                          8U
+#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_195
+#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_MASK            0x00000700U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_SHIFT                    8U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_MASK            0x00070000U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_SHIFT                   16U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_MASK            0x07000000U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_SHIFT                   24U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_PI_196_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_196_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_SHIFT                      0U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_SHIFT                16U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_PI_197_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_197_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_SHIFT                      0U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_SHIFT                16U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_PI_198_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_198_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_SHIFT                      0U
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_SHIFT                16U
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_PI_199_READ_MASK                              0x1F030303U
+#define LPDDR4__DENALI_PI_199_WRITE_MASK                             0x1F030303U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_MASK                   0x00000300U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2
+
+#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_199
+#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_199__PI_TMRZ_F0
+
+#define LPDDR4__DENALI_PI_200_READ_MASK                              0x001F3FFFU
+#define LPDDR4__DENALI_PI_200_WRITE_MASK                             0x001F3FFFU
+#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_200
+#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_200__PI_TCAENT_F0
+
+#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_200
+#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_200__PI_TMRZ_F1
+
+#define LPDDR4__DENALI_PI_201_READ_MASK                              0x001F3FFFU
+#define LPDDR4__DENALI_PI_201_WRITE_MASK                             0x001F3FFFU
+#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_201
+#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_201__PI_TCAENT_F1
+
+#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_201
+#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_201__PI_TMRZ_F2
+
+#define LPDDR4__DENALI_PI_202_READ_MASK                              0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_202_WRITE_MASK                             0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_202
+#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_202__PI_TCAENT_F2
+
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0
+
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0
+
+#define LPDDR4__DENALI_PI_203_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_203_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_MASK                0x000003FFU
+#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_203
+#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0
+
+#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_203
+#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0
+
+#define LPDDR4__DENALI_PI_204_READ_MASK                              0x03FF1F1FU
+#define LPDDR4__DENALI_PI_204_WRITE_MASK                             0x03FF1F1FU
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_MASK                0x0000001FU
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_204
+#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1
+
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_MASK                 0x00001F00U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_204
+#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1
+
+#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_204
+#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1
+
+#define LPDDR4__DENALI_PI_205_READ_MASK                              0x1F1F03FFU
+#define LPDDR4__DENALI_PI_205_WRITE_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_205
+#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1
+
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2
+
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_SHIFT                        24U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2
+
+#define LPDDR4__DENALI_PI_206_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_206_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_MASK                0x000003FFU
+#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_206
+#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2
+
+#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_206
+#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2
+
+#define LPDDR4__DENALI_PI_207_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_207_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT     0U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT      8U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT    16U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT     24U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_208_READ_MASK                              0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_208_WRITE_MASK                             0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT     0U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT      8U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_MASK           0x000F0000U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_SHIFT                  16U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_MASK           0x0F000000U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_SHIFT                  24U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_209_READ_MASK                              0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_209_WRITE_MASK                             0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_MASK           0x0000000FU
+#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_209
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_SHIFT                  8U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_209
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0
+
+#define LPDDR4__DENALI_PI_209__PI_TXP_F0_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_209__PI_TXP_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_209__PI_TXP_F0_WIDTH                                5U
+#define LPDDR4__PI_TXP_F0__REG DENALI_PI_209
+#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_209__PI_TXP_F0
+
+#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_209
+#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0
+
+#define LPDDR4__DENALI_PI_210_READ_MASK                              0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_210_WRITE_MASK                             0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_210
+#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_210__PI_TCKELCK_F0
+
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_SHIFT                  8U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1
+
+#define LPDDR4__DENALI_PI_210__PI_TXP_F1_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_210__PI_TXP_F1_SHIFT                               16U
+#define LPDDR4__DENALI_PI_210__PI_TXP_F1_WIDTH                                5U
+#define LPDDR4__PI_TXP_F1__REG DENALI_PI_210
+#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_210__PI_TXP_F1
+
+#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_210
+#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1
+
+#define LPDDR4__DENALI_PI_211_READ_MASK                              0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_211_WRITE_MASK                             0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_SHIFT                            0U
+#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_211
+#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_211__PI_TCKELCK_F1
+
+#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_SHIFT                  8U
+#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_211
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2
+
+#define LPDDR4__DENALI_PI_211__PI_TXP_F2_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_211__PI_TXP_F2_SHIFT                               16U
+#define LPDDR4__DENALI_PI_211__PI_TXP_F2_WIDTH                                5U
+#define LPDDR4__PI_TXP_F2__REG DENALI_PI_211
+#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_211__PI_TXP_F2
+
+#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_211
+#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2
+
+#define LPDDR4__DENALI_PI_212_READ_MASK                              0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_212_WRITE_MASK                             0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_212
+#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_212__PI_TCKELCK_F2
+
+#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_MASK            0xFFFFFF00U
+#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_SHIFT                    8U
+#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_WIDTH                   24U
+#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_212
+#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_PI_213_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_213_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_SHIFT                 0U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_WIDTH                24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_213
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_PI_214_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_214_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_MASK            0x00FFFFFFU
+#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_WIDTH                   24U
+#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_214
+#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_PI_215_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_215_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_SHIFT                 0U
+#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_WIDTH                24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_215
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_PI_216_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_216_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_MASK            0x00FFFFFFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_SHIFT                    0U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_WIDTH                   24U
+#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_PI_217_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_217_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_SHIFT                 0U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_WIDTH                24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_217
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_MASK                   0x3F000000U
+#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_217
+#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0
+
+#define LPDDR4__DENALI_PI_218_READ_MASK                              0x003F03FFU
+#define LPDDR4__DENALI_PI_218_WRITE_MASK                             0x003F03FFU
+#define LPDDR4__DENALI_PI_218__PI_TFC_F0_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_218__PI_TFC_F0_SHIFT                                0U
+#define LPDDR4__DENALI_PI_218__PI_TFC_F0_WIDTH                               10U
+#define LPDDR4__PI_TFC_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_218__PI_TFC_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_MASK                   0x003F0000U
+#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_218
+#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1
+
+#define LPDDR4__DENALI_PI_219_READ_MASK                              0x003F03FFU
+#define LPDDR4__DENALI_PI_219_WRITE_MASK                             0x003F03FFU
+#define LPDDR4__DENALI_PI_219__PI_TFC_F1_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_219__PI_TFC_F1_SHIFT                                0U
+#define LPDDR4__DENALI_PI_219__PI_TFC_F1_WIDTH                               10U
+#define LPDDR4__PI_TFC_F1__REG DENALI_PI_219
+#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_219__PI_TFC_F1
+
+#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_219
+#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2
+
+#define LPDDR4__DENALI_PI_220_READ_MASK                              0x030303FFU
+#define LPDDR4__DENALI_PI_220_WRITE_MASK                             0x030303FFU
+#define LPDDR4__DENALI_PI_220__PI_TFC_F2_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_220__PI_TFC_F2_SHIFT                                0U
+#define LPDDR4__DENALI_PI_220__PI_TFC_F2_WIDTH                               10U
+#define LPDDR4__PI_TFC_F2__REG DENALI_PI_220
+#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_220__PI_TFC_F2
+
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_MASK                    0x00030000U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_SHIFT                           16U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_WIDTH                            2U
+#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_220
+#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F0
+
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_MASK                    0x03000000U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_SHIFT                           24U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_WIDTH                            2U
+#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_220
+#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F1
+
+#define LPDDR4__DENALI_PI_221_READ_MASK                              0x0003FF03U
+#define LPDDR4__DENALI_PI_221_WRITE_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_MASK                    0x00000003U
+#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_WIDTH                            2U
+#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_221
+#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_221__PI_VREF_EN_F2
+
+#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_MASK             0x0003FF00U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_SHIFT                     8U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0
+
+#define LPDDR4__DENALI_PI_222_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_222_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_SHIFT                     0U
+#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_222
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0
+
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT   16U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_222
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT    24U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_222
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_223_READ_MASK                              0x1F03030FU
+#define LPDDR4__DENALI_PI_223_WRITE_MASK                             0x1F03030FU
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_SHIFT                  0U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_223
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_SHIFT                          8U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_223
+#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_223
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0
+
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_MASK                  0x1F000000U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_SHIFT                         24U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_WIDTH                          5U
+#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_223
+#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0
+
+#define LPDDR4__DENALI_PI_224_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_224_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT                   0U
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_224
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT                   8U
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_224
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_MASK             0x03FF0000U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_SHIFT                    16U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1
+
+#define LPDDR4__DENALI_PI_225_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_225_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_225
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1
+
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT   16U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_225
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT    24U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_225
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_226_READ_MASK                              0x1F03030FU
+#define LPDDR4__DENALI_PI_226_WRITE_MASK                             0x1F03030FU
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_SHIFT                  0U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_226
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_SHIFT                          8U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_226
+#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_SHIFT                      16U
+#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_226
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1
+
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_MASK                  0x1F000000U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_WIDTH                          5U
+#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_226
+#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1
+
+#define LPDDR4__DENALI_PI_227_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_227_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_227
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT                   8U
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_227
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_MASK             0x03FF0000U
+#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_SHIFT                    16U
+#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_227
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2
+
+#define LPDDR4__DENALI_PI_228_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_228_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2
+
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT   16U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_228
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT    24U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_228
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_229_READ_MASK                              0x1F03030FU
+#define LPDDR4__DENALI_PI_229_WRITE_MASK                             0x1F03030FU
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_SHIFT                  0U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_229
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_SHIFT                          8U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_229
+#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_SHIFT                      16U
+#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_229
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2
+
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_MASK                  0x1F000000U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_SHIFT                         24U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_WIDTH                          5U
+#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_229
+#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2
+
+#define LPDDR4__DENALI_PI_230_READ_MASK                              0x0303FFFFU
+#define LPDDR4__DENALI_PI_230_WRITE_MASK                             0x0303FFFFU
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_MASK           0x000000FFU
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_230
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT                   8U
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH                   8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_230
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_MASK            0x00030000U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_SHIFT                   16U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_WIDTH                    2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_230
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0
+
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_MASK            0x03000000U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_SHIFT                   24U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_WIDTH                    2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_230
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1
+
+#define LPDDR4__DENALI_PI_231_READ_MASK                              0xFFFFFF03U
+#define LPDDR4__DENALI_PI_231_WRITE_MASK                             0xFFFFFF03U
+#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_SHIFT                    0U
+#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_WIDTH                    2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_231
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2
+
+#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_231
+#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRTP_F0
+
+#define LPDDR4__DENALI_PI_231__PI_TRP_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_231__PI_TRP_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_231__PI_TRP_F0_WIDTH                                8U
+#define LPDDR4__PI_TRP_F0__REG DENALI_PI_231
+#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRP_F0
+
+#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_231
+#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_231__PI_TRCD_F0
+
+#define LPDDR4__DENALI_PI_232_READ_MASK                              0x00FF3F1FU
+#define LPDDR4__DENALI_PI_232_WRITE_MASK                             0x00FF3F1FU
+#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_MASK                     0x0000001FU
+#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_WIDTH                             5U
+#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_232
+#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_232__PI_TCCD_L_F0
+
+#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_MASK                       0x00003F00U
+#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_232
+#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWTR_F0
+
+#define LPDDR4__DENALI_PI_232__PI_TWR_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_232__PI_TWR_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_232__PI_TWR_F0_WIDTH                                8U
+#define LPDDR4__PI_TWR_F0__REG DENALI_PI_232
+#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWR_F0
+
+#define LPDDR4__DENALI_PI_233_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_233_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_WIDTH                          20U
+#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_233
+#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0
+
+#define LPDDR4__DENALI_PI_234_READ_MASK                              0x3F0F01FFU
+#define LPDDR4__DENALI_PI_234_WRITE_MASK                             0x3F0F01FFU
+#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_WIDTH                           9U
+#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0
+
+#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_MASK                 0x000F0000U
+#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_SHIFT                            24U
+#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_234__PI_TCCDMW_F0
+
+#define LPDDR4__DENALI_PI_235_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235__PI_TSR_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_235__PI_TSR_F0_SHIFT                                0U
+#define LPDDR4__DENALI_PI_235__PI_TSR_F0_WIDTH                                8U
+#define LPDDR4__PI_TSR_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TSR_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRD_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_SHIFT                              16U
+#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRW_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_WIDTH                               8U
+#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMOD_F0
+
+#define LPDDR4__DENALI_PI_236_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_236_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_WIDTH                           8U
+#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_236
+#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_SHIFT                           8U
+#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_WIDTH                           8U
+#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_236
+#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRTP_F1
+
+#define LPDDR4__DENALI_PI_236__PI_TRP_F1_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_236__PI_TRP_F1_SHIFT                               24U
+#define LPDDR4__DENALI_PI_236__PI_TRP_F1_WIDTH                                8U
+#define LPDDR4__PI_TRP_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRP_F1
+
+#define LPDDR4__DENALI_PI_237_READ_MASK                              0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_237_WRITE_MASK                             0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_237__PI_TRCD_F1
+
+#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_SHIFT                             8U
+#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_WIDTH                             5U
+#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_237__PI_TCCD_L_F1
+
+#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_MASK                       0x003F0000U
+#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWTR_F1
+
+#define LPDDR4__DENALI_PI_237__PI_TWR_F1_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_237__PI_TWR_F1_SHIFT                               24U
+#define LPDDR4__DENALI_PI_237__PI_TWR_F1_WIDTH                                8U
+#define LPDDR4__PI_TWR_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWR_F1
+
+#define LPDDR4__DENALI_PI_238_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_238_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_WIDTH                          20U
+#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_238
+#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1
+
+#define LPDDR4__DENALI_PI_239_READ_MASK                              0x3F0F01FFU
+#define LPDDR4__DENALI_PI_239_WRITE_MASK                             0x3F0F01FFU
+#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_WIDTH                           9U
+#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_239
+#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1
+
+#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_MASK                 0x000F0000U
+#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_239
+#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_239
+#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_239__PI_TCCDMW_F1
+
+#define LPDDR4__DENALI_PI_240_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_240_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_240__PI_TSR_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_240__PI_TSR_F1_SHIFT                                0U
+#define LPDDR4__DENALI_PI_240__PI_TSR_F1_WIDTH                                8U
+#define LPDDR4__PI_TSR_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_240__PI_TSR_F1
+
+#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_SHIFT                               8U
+#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRD_F1
+
+#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRW_F1
+
+#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_SHIFT                              24U
+#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_WIDTH                               8U
+#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMOD_F1
+
+#define LPDDR4__DENALI_PI_241_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_241_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_WIDTH                           8U
+#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_241
+#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1
+
+#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_WIDTH                           8U
+#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_241
+#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1
+
+#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_241
+#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRTP_F2
+
+#define LPDDR4__DENALI_PI_241__PI_TRP_F2_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_241__PI_TRP_F2_SHIFT                               24U
+#define LPDDR4__DENALI_PI_241__PI_TRP_F2_WIDTH                                8U
+#define LPDDR4__PI_TRP_F2__REG DENALI_PI_241
+#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRP_F2
+
+#define LPDDR4__DENALI_PI_242_READ_MASK                              0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_242_WRITE_MASK                             0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_242__PI_TRCD_F2
+
+#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_WIDTH                             5U
+#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_242__PI_TCCD_L_F2
+
+#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_MASK                       0x003F0000U
+#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWTR_F2
+
+#define LPDDR4__DENALI_PI_242__PI_TWR_F2_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_242__PI_TWR_F2_SHIFT                               24U
+#define LPDDR4__DENALI_PI_242__PI_TWR_F2_WIDTH                                8U
+#define LPDDR4__PI_TWR_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWR_F2
+
+#define LPDDR4__DENALI_PI_243_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_243_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_WIDTH                          20U
+#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_243
+#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2
+
+#define LPDDR4__DENALI_PI_244_READ_MASK                              0x3F0F01FFU
+#define LPDDR4__DENALI_PI_244_WRITE_MASK                             0x3F0F01FFU
+#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_WIDTH                           9U
+#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_244
+#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2
+
+#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_MASK                 0x000F0000U
+#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_244
+#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_SHIFT                            24U
+#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_244
+#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_244__PI_TCCDMW_F2
+
+#define LPDDR4__DENALI_PI_245_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_245_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TSR_F2_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_245__PI_TSR_F2_SHIFT                                0U
+#define LPDDR4__DENALI_PI_245__PI_TSR_F2_WIDTH                                8U
+#define LPDDR4__PI_TSR_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_245__PI_TSR_F2
+
+#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_SHIFT                               8U
+#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRD_F2
+
+#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRW_F2
+
+#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_SHIFT                              24U
+#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_WIDTH                               8U
+#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMOD_F2
+
+#define LPDDR4__DENALI_PI_246_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_246_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_WIDTH                           8U
+#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_246
+#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2
+
+#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_SHIFT                           8U
+#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_WIDTH                           8U
+#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_246
+#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2
+
+#define LPDDR4__DENALI_PI_247_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_247_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_SHIFT                   0U
+#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_PI_248_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT              0U
+#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_248
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_PI_249_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_249_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_PI_250_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_250_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT              0U
+#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_250
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_PI_251_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_251_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_251
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_PI_252_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT              0U
+#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_252
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_PI_253_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_253
+#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F0
+
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_MASK                       0xFFFF0000U
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_253
+#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F1
+
+#define LPDDR4__DENALI_PI_254_READ_MASK                              0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_254_WRITE_MASK                             0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_254__PI_TXSR_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_MASK                     0x003F0000U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_254
+#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F0
+
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_254
+#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F1
+
+#define LPDDR4__DENALI_PI_255_READ_MASK                              0x00FFFF3FU
+#define LPDDR4__DENALI_PI_255_WRITE_MASK                             0x00FFFF3FU
+#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_MASK                     0x0000003FU
+#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_255
+#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_255__PI_TEXCKE_F2
+
+#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_MASK                       0x00FFFF00U
+#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_WIDTH                              16U
+#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_255
+#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_255__PI_TDLL_F0
+
+#define LPDDR4__DENALI_PI_256_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_256_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_WIDTH                              16U
+#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_256
+#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F1
+
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_MASK                       0xFFFF0000U
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_WIDTH                              16U
+#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F2
+
+#define LPDDR4__DENALI_PI_257_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_WIDTH                             8U
+#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F0
+
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_WIDTH                             8U
+#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F0
+
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_WIDTH                             8U
+#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F1
+
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_WIDTH                             8U
+#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F1
+
+#define LPDDR4__DENALI_PI_258_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_258_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_WIDTH                             8U
+#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRX_F2
+
+#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_WIDTH                             8U
+#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRE_F2
+
+#define LPDDR4__DENALI_PI_259_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_259_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_259
+#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_259__PI_TINIT_F0
+
+#define LPDDR4__DENALI_PI_260_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_260_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_260
+#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_260__PI_TINIT3_F0
+
+#define LPDDR4__DENALI_PI_261_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_261_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_261
+#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_261__PI_TINIT4_F0
+
+#define LPDDR4__DENALI_PI_262_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_262_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_262
+#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_262__PI_TINIT5_F0
+
+#define LPDDR4__DENALI_PI_263_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_263_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_263
+#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_263__PI_TXSNR_F0
+
+#define LPDDR4__DENALI_PI_264_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_264_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_264
+#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_264__PI_TINIT_F1
+
+#define LPDDR4__DENALI_PI_265_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_265_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_265
+#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_265__PI_TINIT3_F1
+
+#define LPDDR4__DENALI_PI_266_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_266_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_266
+#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_266__PI_TINIT4_F1
+
+#define LPDDR4__DENALI_PI_267_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_267_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_267
+#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_267__PI_TINIT5_F1
+
+#define LPDDR4__DENALI_PI_268_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_268_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_268
+#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_268__PI_TXSNR_F1
+
+#define LPDDR4__DENALI_PI_269_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_269_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_SHIFT                              0U
+#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_269
+#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_269__PI_TINIT_F2
+
+#define LPDDR4__DENALI_PI_270_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_270_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_270
+#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_270__PI_TINIT3_F2
+
+#define LPDDR4__DENALI_PI_271_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_271
+#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_271__PI_TINIT4_F2
+
+#define LPDDR4__DENALI_PI_272_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_272
+#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_272__PI_TINIT5_F2
+
+#define LPDDR4__DENALI_PI_273_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_273_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_SHIFT                              0U
+#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_273
+#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_273__PI_TXSNR_F2
+
+#define LPDDR4__DENALI_PI_273__PI_RESERVED54_MASK                    0x0FFF0000U
+#define LPDDR4__DENALI_PI_273__PI_RESERVED54_SHIFT                           16U
+#define LPDDR4__DENALI_PI_273__PI_RESERVED54_WIDTH                           12U
+#define LPDDR4__PI_RESERVED54__REG DENALI_PI_273
+#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_273__PI_RESERVED54
+
+#define LPDDR4__DENALI_PI_274_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_274_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_274__PI_RESERVED55_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_274__PI_RESERVED55_SHIFT                            0U
+#define LPDDR4__DENALI_PI_274__PI_RESERVED55_WIDTH                           12U
+#define LPDDR4__PI_RESERVED55__REG DENALI_PI_274
+#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_274__PI_RESERVED55
+
+#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_274
+#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_274__PI_TZQCAL_F0
+
+#define LPDDR4__DENALI_PI_275_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_275_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_275
+#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_275__PI_TZQLAT_F0
+
+#define LPDDR4__DENALI_PI_275__PI_RESERVED56_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_275__PI_RESERVED56_SHIFT                            8U
+#define LPDDR4__DENALI_PI_275__PI_RESERVED56_WIDTH                           12U
+#define LPDDR4__PI_RESERVED56__REG DENALI_PI_275
+#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_275__PI_RESERVED56
+
+#define LPDDR4__DENALI_PI_276_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_276_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_276__PI_RESERVED57_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_276__PI_RESERVED57_SHIFT                            0U
+#define LPDDR4__DENALI_PI_276__PI_RESERVED57_WIDTH                           12U
+#define LPDDR4__PI_RESERVED57__REG DENALI_PI_276
+#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_276__PI_RESERVED57
+
+#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_276
+#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_276__PI_TZQCAL_F1
+
+#define LPDDR4__DENALI_PI_277_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_277_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_277
+#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_277__PI_TZQLAT_F1
+
+#define LPDDR4__DENALI_PI_277__PI_RESERVED58_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_277__PI_RESERVED58_SHIFT                            8U
+#define LPDDR4__DENALI_PI_277__PI_RESERVED58_WIDTH                           12U
+#define LPDDR4__PI_RESERVED58__REG DENALI_PI_277
+#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_277__PI_RESERVED58
+
+#define LPDDR4__DENALI_PI_278_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_278_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_278__PI_RESERVED59_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_278__PI_RESERVED59_SHIFT                            0U
+#define LPDDR4__DENALI_PI_278__PI_RESERVED59_WIDTH                           12U
+#define LPDDR4__PI_RESERVED59__REG DENALI_PI_278
+#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_278__PI_RESERVED59
+
+#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_278
+#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_278__PI_TZQCAL_F2
+
+#define LPDDR4__DENALI_PI_279_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_279_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_279
+#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_279__PI_TZQLAT_F2
+
+#define LPDDR4__DENALI_PI_279__PI_RESERVED60_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_279__PI_RESERVED60_SHIFT                            8U
+#define LPDDR4__DENALI_PI_279__PI_RESERVED60_WIDTH                           12U
+#define LPDDR4__PI_RESERVED60__REG DENALI_PI_279
+#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_279__PI_RESERVED60
+
+#define LPDDR4__DENALI_PI_280_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_280_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_280__PI_RESERVED61_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_280__PI_RESERVED61_SHIFT                            0U
+#define LPDDR4__DENALI_PI_280__PI_RESERVED61_WIDTH                           12U
+#define LPDDR4__PI_RESERVED61__REG DENALI_PI_280
+#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_280__PI_RESERVED61
+
+#define LPDDR4__DENALI_PI_280__PI_RESERVED62_MASK                    0x0FFF0000U
+#define LPDDR4__DENALI_PI_280__PI_RESERVED62_SHIFT                           16U
+#define LPDDR4__DENALI_PI_280__PI_RESERVED62_WIDTH                           12U
+#define LPDDR4__PI_RESERVED62__REG DENALI_PI_280
+#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_280__PI_RESERVED62
+
+#define LPDDR4__DENALI_PI_281_READ_MASK                              0x030F0F0FU
+#define LPDDR4__DENALI_PI_281_WRITE_MASK                             0x030F0F0FU
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT                0U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_281
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0
+
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_MASK        0x00000F00U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT                8U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_281
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1
+
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_MASK        0x000F0000U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT               16U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_281
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2
+
+#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_MASK           0x03000000U
+#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_SHIFT                  24U
+#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_WIDTH                   2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_281
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_PI_282_READ_MASK                              0x07070303U
+#define LPDDR4__DENALI_PI_282_WRITE_MASK                             0x07070303U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_MASK           0x00000003U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_WIDTH                   2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_282
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_MASK           0x00000300U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_SHIFT                   8U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_WIDTH                   2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_282
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_MASK               0x00070000U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_WIDTH                       3U
+#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_282
+#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_MASK               0x07000000U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_WIDTH                       3U
+#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_282
+#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_PI_283_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_283_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_MASK                0x00000003U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_WIDTH                        2U
+#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_MASK                0x00000300U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_WIDTH                        2U
+#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_WIDTH                        2U
+#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_WIDTH                        2U
+#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_PI_284_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_284_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_MASK               0x0000007FU
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0
+
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_MASK               0x00007F00U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_SHIFT                       8U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1
+
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_MASK               0x007F0000U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0
+
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_MASK               0x7F000000U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_WIDTH                       7U
+#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1
+
+#define LPDDR4__DENALI_PI_285_READ_MASK                              0x3F3F0303U
+#define LPDDR4__DENALI_PI_285_WRITE_MASK                             0x3F3F0303U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_WIDTH                       2U
+#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_285
+#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0
+
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_MASK               0x00000300U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_SHIFT                       8U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_WIDTH                       2U
+#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_285
+#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_285
+#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0
+
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_MASK                  0x3F000000U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1
+
+#define LPDDR4__DENALI_PI_286_READ_MASK                              0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_286_WRITE_MASK                             0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_SHIFT                          0U
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_286
+#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0
+
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_MASK                  0x00003F00U
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_SHIFT                          8U
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_WIDTH                          6U
+#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_286
+#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR13_DATA_0
+
+#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_286
+#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR15_DATA_0
+
+#define LPDDR4__DENALI_PI_287_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_287_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_287
+#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR16_DATA_0
+
+#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_SHIFT                           8U
+#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_287
+#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR17_DATA_0
+
+#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_287
+#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR20_DATA_0
+
+#define LPDDR4__DENALI_PI_288_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_288_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_WIDTH                          17U
+#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_288
+#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR32_DATA_0
+
+#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_288
+#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR40_DATA_0
+
+#define LPDDR4__DENALI_PI_289_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR13_DATA_1
+
+#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR15_DATA_1
+
+#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR16_DATA_1
+
+#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR17_DATA_1
+
+#define LPDDR4__DENALI_PI_290_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_PI_290_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_290
+#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR20_DATA_1
+
+#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_MASK                   0x01FFFF00U
+#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_WIDTH                          17U
+#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_290
+#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR32_DATA_1
+
+#define LPDDR4__DENALI_PI_291_READ_MASK                              0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_291_WRITE_MASK                             0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_291
+#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_291__PI_MR40_DATA_1
+
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_WIDTH                             5U
+#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_291
+#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_0
+
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_MASK                     0x001F0000U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_WIDTH                             5U
+#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_291
+#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_1
+
+#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_MASK                      0x1F000000U
+#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_SHIFT                             24U
+#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_WIDTH                              5U
+#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_291
+#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CS_MUX_0
+
+#define LPDDR4__DENALI_PI_292_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_292_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_MASK                      0x0000001FU
+#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_WIDTH                              5U
+#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_292
+#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_CS_MUX_1
+
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_MASK                     0x00001F00U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_WIDTH                             5U
+#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_292
+#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_0
+
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_MASK                     0x001F0000U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_WIDTH                             5U
+#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_292
+#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_1
+
+#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_WIDTH                         5U
+#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_292
+#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0
+
+#define LPDDR4__DENALI_PI_293_READ_MASK                              0x01FFFF1FU
+#define LPDDR4__DENALI_PI_293_WRITE_MASK                             0x01FFFF1FU
+#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_MASK                 0x0000001FU
+#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_WIDTH                         5U
+#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_293
+#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1
+
+#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_MASK               0x01FFFF00U
+#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_SHIFT                       8U
+#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_WIDTH                      17U
+#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_293
+#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_PI_294_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_PI_294_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_WIDTH                      17U
+#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_294
+#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_MASK            0x03000000U
+#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_SHIFT                   24U
+#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_WIDTH                    2U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_294
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_PI_295_READ_MASK                              0x00030303U
+#define LPDDR4__DENALI_PI_295_WRITE_MASK                             0x00030303U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_WIDTH                    2U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_295
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_MASK            0x00000300U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_WIDTH                    2U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_295
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_MASK            0x00030000U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_SHIFT                   16U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_WIDTH                    2U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_295
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_PI_296_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT                0U
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_296
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0
+
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT               16U
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_296
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1
+
+#define LPDDR4__DENALI_PI_297_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_297_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_297
+#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_298_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_298_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_298
+#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_299_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_299_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_299
+#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_300_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_300_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_300
+#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_301_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_301_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_301
+#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_302_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_302_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_302
+#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_303_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_303_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_303
+#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_304_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_305_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_305_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_305
+#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_306_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_306_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_306
+#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_307_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_307_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_308_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_308_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_308
+#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_309_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_309_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_309
+#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_310_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_310_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_310
+#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_311_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_311_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_311
+#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_311
+#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_312_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_313_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_313_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_313
+#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_314_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_314_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_314
+#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_315_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_315_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_315
+#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_316_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_316_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_316
+#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_317_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_317_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_317
+#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_318_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_318_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_318
+#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_319_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_319_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_319
+#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_319
+#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_320_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_321_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_321_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_321
+#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_322_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_322_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_322
+#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_323_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_323_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_323
+#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_324_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_324_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_324
+#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_325_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_325_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_325
+#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_326_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_326_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_326
+#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_327_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_327_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_327
+#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_327
+#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_328_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_329_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_329_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_329
+#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_330_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_330_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_330
+#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_331_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_331_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_331
+#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_332_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_332_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_332
+#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_333_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_333_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_333
+#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_334_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_334_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_334
+#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_335_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_335_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_335
+#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_335
+#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_336_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_337_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_337_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_337
+#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_338_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_338_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_338
+#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_339_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_339_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_339
+#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_340_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_340_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_340
+#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_341_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_341_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_341
+#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_342_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_342_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_342
+#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_343_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_343_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_WIDTH                        17U
+#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_343
+#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_343
+#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_344_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1
+
+#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
new file mode 100644
index 0000000000..f14ca245ee
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_IF_H
+#define LPDDR4_32BIT_IF_H
+
+#include <linux/types.h>
+
+#define LPDDR4_INTR_MAX_CS (2U)
+
+#define LPDDR4_INTR_CTL_REG_COUNT (459U)
+
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (300U)
+
+#define LPDDR4_INTR_PHY_REG_COUNT (1423U)
+
+typedef enum {
+	LPDDR4_INTR_RESET_DONE			= 0U,
+	LPDDR4_INTR_BUS_ACCESS_ERROR		= 1U,
+	LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR	= 2U,
+	LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR	= 3U,
+	LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR	= 4U,
+	LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR	= 5U,
+	LPDDR4_INTR_ECC_SCRUB_DONE		= 6U,
+	LPDDR4_INTR_ECC_SCRUB_ERROR		= 7U,
+	LPDDR4_INTR_PORT_COMMAND_ERROR		= 8U,
+	LPDDR4_INTR_MC_INIT_DONE		= 9U,
+	LPDDR4_INTR_LP_DONE			= 10U,
+	LPDDR4_INTR_BIST_DONE			= 11U,
+	LPDDR4_INTR_WRAP_ERROR			= 12U,
+	LPDDR4_INTR_INVALID_BURST_ERROR		= 13U,
+	LPDDR4_INTR_RDLVL_ERROR			= 14U,
+	LPDDR4_INTR_RDLVL_GATE_ERROR		= 15U,
+	LPDDR4_INTR_WRLVL_ERROR			= 16U,
+	LPDDR4_INTR_CA_TRAINING_ERROR		= 17U,
+	LPDDR4_INTR_DFI_UPDATE_ERROR		= 18U,
+	LPDDR4_INTR_MRR_ERROR			= 19U,
+	LPDDR4_INTR_PHY_MASTER_ERROR		= 20U,
+	LPDDR4_INTR_WRLVL_REQ			= 21U,
+	LPDDR4_INTR_RDLVL_REQ			= 22U,
+	LPDDR4_INTR_RDLVL_GATE_REQ		= 23U,
+	LPDDR4_INTR_CA_TRAINING_REQ		= 24U,
+	LPDDR4_INTR_LEVELING_DONE		= 25U,
+	LPDDR4_INTR_PHY_ERROR			= 26U,
+	LPDDR4_INTR_MR_READ_DONE		= 27U,
+	LPDDR4_INTR_TEMP_CHANGE			= 28U,
+	LPDDR4_INTR_TEMP_ALERT			= 29U,
+	LPDDR4_INTR_SW_DQS_COMPLETE		= 30U,
+	LPDDR4_INTR_DQS_OSC_BV_UPDATED		= 31U,
+	LPDDR4_INTR_DQS_OSC_OVERFLOW		= 32U,
+	LPDDR4_INTR_DQS_OSC_VAR_OUT		= 33U,
+	LPDDR4_INTR_MR_WRITE_DONE		= 34U,
+	LPDDR4_INTR_INHIBIT_DRAM_DONE		= 35U,
+	LPDDR4_INTR_DFI_INIT_STATE		= 36U,
+	LPDDR4_INTR_DLL_RESYNC_DONE		= 37U,
+	LPDDR4_INTR_TDFI_TO			= 38U,
+	LPDDR4_INTR_DFS_DONE			= 39U,
+	LPDDR4_INTR_DFS_STATUS			= 40U,
+	LPDDR4_INTR_REFRESH_STATUS		= 41U,
+	LPDDR4_INTR_ZQ_STATUS			= 42U,
+	LPDDR4_INTR_SW_REQ_MODE			= 43U,
+	LPDDR4_INTR_LOR_BITS			= 44U
+} lpddr4_intr_ctlinterrupt;
+
+typedef enum {
+	LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT		= 0U,
+	LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT		= 1U,
+	LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT		= 2U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT		= 3U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT		= 4U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT		= 5U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT		= 6U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT		= 7U,
+	LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT		= 8U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT		= 9U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT	= 10U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT		= 11U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT		= 12U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT		= 13U,
+	LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT		= 14U,
+	LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT		= 15U,
+	LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT	= 16U,
+	LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
+} lpddr4_intr_phyindepinterrupt;
+
+#endif  /* LPDDR4_32BIT_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
new file mode 100644
index 0000000000..7fee54f00d
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_OBJ_IF_H
+#define LPDDR4_32BIT_OBJ_IF_H
+
+#include "lpddr4_32bit_if.h"
+
+#endif  /* LPDDR4_32BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
new file mode 100644
index 0000000000..69b2a47ab3
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_STRUCTS_IF_H
+#define LPDDR4_32BIT_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_32bit_if.h"
+
+#endif  /* LPDDR4_32BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
index bc8059efd1..58ba340e78 100644
--- a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
@@ -1,17 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
  *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
 #define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
 
-#define LPDDR4__DENALI_PHY_1024_READ_MASK				            0x000107FFU
-#define LPDDR4__DENALI_PHY_1024_WRITE_MASK				           0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_WRITE_MASK                           0x000107FFU
 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT    0U
 #define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH   11U
@@ -32,16 +31,16 @@
 #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
 #define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
 
-#define LPDDR4__DENALI_PHY_1025_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1025_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK      0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH             32U
 #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
 #define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
 
-#define LPDDR4__DENALI_PHY_1026_READ_MASK				            0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_1026_WRITE_MASK				           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_WRITE_MASK                           0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT         0U
 #define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH        16U
@@ -60,8 +59,8 @@
 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
 #define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
 
-#define LPDDR4__DENALI_PHY_1027_READ_MASK				            0xFF7F07FFU
-#define LPDDR4__DENALI_PHY_1027_WRITE_MASK				           0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_READ_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_WRITE_MASK                           0xFF7F07FFU
 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK  0x000007FFU
 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH         11U
@@ -80,8 +79,8 @@
 #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
 #define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
 
-#define LPDDR4__DENALI_PHY_1028_READ_MASK				            0x01000707U
-#define LPDDR4__DENALI_PHY_1028_WRITE_MASK				           0x01000707U
+#define LPDDR4__DENALI_PHY_1028_READ_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_1028_WRITE_MASK                           0x01000707U
 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH        3U
@@ -103,18 +102,18 @@
 #define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
 
 #define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK          0x01000000U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET				  0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET                  0U
 #define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
 #define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
 
-#define LPDDR4__DENALI_PHY_1029_READ_MASK				            0x011F7F7FU
-#define LPDDR4__DENALI_PHY_1029_WRITE_MASK				           0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_READ_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_WRITE_MASK                           0x011F7F7FU
 #define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK         0x0000007FU
-#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH				 7U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH                 7U
 #define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
 #define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
 
@@ -138,8 +137,8 @@
 #define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
 #define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
 
-#define LPDDR4__DENALI_PHY_1030_READ_MASK				            0x01070301U
-#define LPDDR4__DENALI_PHY_1030_WRITE_MASK				           0x01070301U
+#define LPDDR4__DENALI_PHY_1030_READ_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_1030_WRITE_MASK                           0x01070301U
 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT    0U
 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH    1U
@@ -148,9 +147,9 @@
 #define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
 #define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
 
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK				 0x00000300U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT				         8U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH				         2U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK                 0x00000300U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH                         2U
 #define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
 #define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
 
@@ -161,50 +160,50 @@
 #define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
 
 #define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK              0x01000000U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH				      1U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR				      0U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET				      0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET                      0U
 #define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
 #define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
 
-#define LPDDR4__DENALI_PHY_1031_READ_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1031_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_WRITE_MASK                           0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK             0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH				    27U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH                    27U
 #define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
 #define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
 
-#define LPDDR4__DENALI_PHY_1032_READ_MASK				            0x0000003FU
-#define LPDDR4__DENALI_PHY_1032_WRITE_MASK				           0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_READ_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_WRITE_MASK                           0x0000003FU
 #define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK             0x0000003FU
-#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH				     6U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH                     6U
 #define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
 #define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
 
-#define LPDDR4__DENALI_PHY_1033_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1033_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH				32U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH                32U
 #define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
 #define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
 
-#define LPDDR4__DENALI_PHY_1034_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1034_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH       32U
 #define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
 #define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
 
-#define LPDDR4__DENALI_PHY_1035_READ_MASK				            0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1035_WRITE_MASK				           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_WRITE_MASK                           0x07FF07FFU
 #define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK          0x000007FFU
-#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH				 11U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH                 11U
 #define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
 #define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
 
@@ -214,24 +213,24 @@
 #define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
 #define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
 
-#define LPDDR4__DENALI_PHY_1036_READ_MASK				            0x000007FFU
-#define LPDDR4__DENALI_PHY_1036_WRITE_MASK				           0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_WRITE_MASK                           0x000007FFU
 #define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK            0x000007FFU
-#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH				   11U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH                   11U
 #define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
 #define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
 
-#define LPDDR4__DENALI_PHY_1037_READ_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1037_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_WRITE_MASK                           0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK       0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH              24U
 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
 #define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
 
-#define LPDDR4__DENALI_PHY_1038_READ_MASK				            0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1038_WRITE_MASK				           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_WRITE_MASK                           0x03FFFFFFU
 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK       0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH              24U
@@ -244,8 +243,8 @@
 #define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
 #define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
 
-#define LPDDR4__DENALI_PHY_1039_READ_MASK				            0x01FF0F03U
-#define LPDDR4__DENALI_PHY_1039_WRITE_MASK				           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_WRITE_MASK                           0x01FF0F03U
 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK   0x00000003U
 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH           2U
@@ -264,8 +263,8 @@
 #define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
 #define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
 
-#define LPDDR4__DENALI_PHY_1040_READ_MASK				            0x07000001U
-#define LPDDR4__DENALI_PHY_1040_WRITE_MASK				           0x07000001U
+#define LPDDR4__DENALI_PHY_1040_READ_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_1040_WRITE_MASK                           0x07000001U
 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK     0x00000001U
 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH             1U
@@ -296,112 +295,112 @@
 #define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
 #define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
 
-#define LPDDR4__DENALI_PHY_1041_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1041_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH              32U
 #define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
 #define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
 
-#define LPDDR4__DENALI_PHY_1042_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1042_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH              32U
 #define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
 #define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
 
-#define LPDDR4__DENALI_PHY_1043_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1043_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH				  32U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH                  32U
 #define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
 #define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
 
-#define LPDDR4__DENALI_PHY_1044_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1044_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH				  32U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH                  32U
 #define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
 #define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
 
-#define LPDDR4__DENALI_PHY_1045_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1045_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
 #define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
 
-#define LPDDR4__DENALI_PHY_1046_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1046_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
 #define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
 
-#define LPDDR4__DENALI_PHY_1047_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1047_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
 #define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
 
-#define LPDDR4__DENALI_PHY_1048_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1048_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
 #define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
 
-#define LPDDR4__DENALI_PHY_1049_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1049_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
 #define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
 
-#define LPDDR4__DENALI_PHY_1050_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1050_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
 #define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
 
-#define LPDDR4__DENALI_PHY_1051_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1051_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
 #define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
 
-#define LPDDR4__DENALI_PHY_1052_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1052_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK           0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH				  20U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH                  20U
 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
 #define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
 
-#define LPDDR4__DENALI_PHY_1053_READ_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1053_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK                           0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK             0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH				    24U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH                    24U
 #define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
 #define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
 
-#define LPDDR4__DENALI_PHY_1054_READ_MASK				            0x3F3F03FFU
-#define LPDDR4__DENALI_PHY_1054_WRITE_MASK				           0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054_READ_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054_WRITE_MASK                           0x3F3F03FFU
 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK   0x000003FFU
 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH          10U
@@ -409,19 +408,19 @@
 #define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
 
 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK             0x003F0000U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH				     6U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH                     6U
 #define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
 #define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
 
 #define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK             0x3F000000U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH				     6U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH                     6U
 #define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
 #define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
 
-#define LPDDR4__DENALI_PHY_1055_READ_MASK				            0x3F0F3F3FU
-#define LPDDR4__DENALI_PHY_1055_WRITE_MASK				           0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055_READ_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055_WRITE_MASK                           0x3F0F3F3FU
 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK     0x0000003FU
 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH             6U
@@ -441,13 +440,13 @@
 #define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
 
 #define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK         0x3F000000U
-#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT				24U
-#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH                 6U
 #define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
 #define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
 
-#define LPDDR4__DENALI_PHY_1056_READ_MASK				            0xFFFFFF03U
-#define LPDDR4__DENALI_PHY_1056_WRITE_MASK				           0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056_READ_MASK                            0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056_WRITE_MASK                           0xFFFFFF03U
 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK      0x00000003U
 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH              2U
@@ -472,8 +471,8 @@
 #define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
 #define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
 
-#define LPDDR4__DENALI_PHY_1057_READ_MASK				            0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1057_WRITE_MASK				           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057_WRITE_MASK                           0x01FFFFFFU
 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK   0x000000FFU
 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH           8U
@@ -500,8 +499,8 @@
 #define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
 #define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
 
-#define LPDDR4__DENALI_PHY_1058_READ_MASK				            0x3F03FFFFU
-#define LPDDR4__DENALI_PHY_1058_WRITE_MASK				           0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058_READ_MASK                            0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058_WRITE_MASK                           0x3F03FFFFU
 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK   0x000000FFU
 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH           8U
@@ -515,8 +514,8 @@
 #define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
 
 #define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK            0x00030000U
-#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH				    2U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH                    2U
 #define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
 #define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
 
@@ -526,8 +525,8 @@
 #define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
 #define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
 
-#define LPDDR4__DENALI_PHY_1059_READ_MASK				            0x0101FFFFU
-#define LPDDR4__DENALI_PHY_1059_WRITE_MASK				           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059_WRITE_MASK                           0x0101FFFFU
 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT         0U
 #define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH         8U
@@ -556,19 +555,19 @@
 #define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
 #define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
 
-#define LPDDR4__DENALI_PHY_1060_READ_MASK				            0x07FF3F01U
-#define LPDDR4__DENALI_PHY_1060_WRITE_MASK				           0x07FF3F01U
+#define LPDDR4__DENALI_PHY_1060_READ_MASK                            0x07FF3F01U
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK                           0x07FF3F01U
 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK         0x00000001U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET				 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET                 0U
 #define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
 #define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
 
 #define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK        0x00003F00U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT				8U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH				6U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH                6U
 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
 #define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
 
@@ -578,11 +577,11 @@
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
 
-#define LPDDR4__DENALI_PHY_1061_READ_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_1061_WRITE_MASK				           0x01FF01FFU
+#define LPDDR4__DENALI_PHY_1061_READ_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK                           0x01FF01FFU
 #define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK        0x000001FFU
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT				0U
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH				9U
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH                9U
 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
 
@@ -592,8 +591,8 @@
 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
 #define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
 
-#define LPDDR4__DENALI_PHY_1062_READ_MASK				            0x01010000U
-#define LPDDR4__DENALI_PHY_1062_WRITE_MASK				           0x01010000U
+#define LPDDR4__DENALI_PHY_1062_READ_MASK                            0x01010000U
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK                           0x01010000U
 #define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
 #define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT       0U
 #define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH       9U
@@ -624,11 +623,11 @@
 #define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
 #define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
 
-#define LPDDR4__DENALI_PHY_1064_READ_MASK				            0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1064_WRITE_MASK				           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1064_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK                           0x07FF07FFU
 #define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK          0x000000FFU
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH                  8U
 #define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
 #define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
 
@@ -639,13 +638,13 @@
 #define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
 
 #define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK           0x07FF0000U
-#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH				  11U
+#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH                  11U
 #define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
 #define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
 
-#define LPDDR4__DENALI_PHY_1065_READ_MASK				            0x1F07FF1FU
-#define LPDDR4__DENALI_PHY_1065_WRITE_MASK				           0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1065_READ_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK                           0x1F07FF1FU
 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK     0x0000001FU
 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH             5U
@@ -664,8 +663,8 @@
 #define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
 #define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1066_READ_MASK				            0x001F07FFU
-#define LPDDR4__DENALI_PHY_1066_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066_WRITE_MASK                           0x001F07FFU
 #define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
 #define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
@@ -678,8 +677,8 @@
 #define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
 #define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1067_READ_MASK				            0x001F07FFU
-#define LPDDR4__DENALI_PHY_1067_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1067_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1067_WRITE_MASK                           0x001F07FFU
 #define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
 #define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
@@ -692,8 +691,8 @@
 #define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
 #define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1068_READ_MASK				            0x001F07FFU
-#define LPDDR4__DENALI_PHY_1068_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1068_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1068_WRITE_MASK                           0x001F07FFU
 #define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
 #define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
@@ -706,8 +705,8 @@
 #define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
 #define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1069_READ_MASK				            0x001F07FFU
-#define LPDDR4__DENALI_PHY_1069_WRITE_MASK				           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1069_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1069_WRITE_MASK                           0x001F07FFU
 #define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
 #define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
@@ -720,8 +719,8 @@
 #define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
 #define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1070_READ_MASK				            0x000F07FFU
-#define LPDDR4__DENALI_PHY_1070_WRITE_MASK				           0x000F07FFU
+#define LPDDR4__DENALI_PHY_1070_READ_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_1070_WRITE_MASK                           0x000F07FFU
 #define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK  0x000007FFU
 #define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH         11U
@@ -734,8 +733,8 @@
 #define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
 #define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
 
-#define LPDDR4__DENALI_PHY_1071_READ_MASK				            0xFF3F07FFU
-#define LPDDR4__DENALI_PHY_1071_WRITE_MASK				           0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1071_READ_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1071_WRITE_MASK                           0xFF3F07FFU
 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK   0x000007FFU
 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH          11U
@@ -754,8 +753,8 @@
 #define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
 #define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
 
-#define LPDDR4__DENALI_PHY_1072_READ_MASK				            0x0103FFFFU
-#define LPDDR4__DENALI_PHY_1072_WRITE_MASK				           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1072_READ_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1072_WRITE_MASK                           0x0103FFFFU
 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT    0U
 #define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH    8U
@@ -776,16 +775,16 @@
 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
 #define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
 
-#define LPDDR4__DENALI_PHY_1073_READ_MASK				            0x0000000FU
-#define LPDDR4__DENALI_PHY_1073_WRITE_MASK				           0x0000000FU
+#define LPDDR4__DENALI_PHY_1073_READ_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_1073_WRITE_MASK                           0x0000000FU
 #define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH               4U
 #define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
 #define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
 
-#define LPDDR4__DENALI_PHY_1074_READ_MASK				            0x03FF010FU
-#define LPDDR4__DENALI_PHY_1074_WRITE_MASK				           0x03FF010FU
+#define LPDDR4__DENALI_PHY_1074_READ_MASK                            0x03FF010FU
+#define LPDDR4__DENALI_PHY_1074_WRITE_MASK                           0x03FF010FU
 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK    0x0000000FU
 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH            4U
@@ -806,8 +805,8 @@
 #define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
 #define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1075_READ_MASK				            0x0000FF01U
-#define LPDDR4__DENALI_PHY_1075_WRITE_MASK				           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1075_READ_MASK                            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1075_WRITE_MASK                           0x0000FF01U
 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH              1U
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
new file mode 100644
index 0000000000..4113608434
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
@@ -0,0 +1,1545 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_CTL_REGS_H_
+#define REG_LPDDR4_CTL_REGS_H_
+
+#include "lpddr4_ddr_controller_macros.h"
+#include "lpddr4_pi_macros.h"
+#include "lpddr4_data_slice_0_macros.h"
+#include "lpddr4_data_slice_1_macros.h"
+#include "lpddr4_data_slice_2_macros.h"
+#include "lpddr4_data_slice_3_macros.h"
+#include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_phy_core_macros.h"
+
+typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
+	volatile u32 DENALI_CTL_0;
+	volatile u32 DENALI_CTL_1;
+	volatile u32 DENALI_CTL_2;
+	volatile u32 DENALI_CTL_3;
+	volatile u32 DENALI_CTL_4;
+	volatile u32 DENALI_CTL_5;
+	volatile u32 DENALI_CTL_6;
+	volatile u32 DENALI_CTL_7;
+	volatile u32 DENALI_CTL_8;
+	volatile u32 DENALI_CTL_9;
+	volatile u32 DENALI_CTL_10;
+	volatile u32 DENALI_CTL_11;
+	volatile u32 DENALI_CTL_12;
+	volatile u32 DENALI_CTL_13;
+	volatile u32 DENALI_CTL_14;
+	volatile u32 DENALI_CTL_15;
+	volatile u32 DENALI_CTL_16;
+	volatile u32 DENALI_CTL_17;
+	volatile u32 DENALI_CTL_18;
+	volatile u32 DENALI_CTL_19;
+	volatile u32 DENALI_CTL_20;
+	volatile u32 DENALI_CTL_21;
+	volatile u32 DENALI_CTL_22;
+	volatile u32 DENALI_CTL_23;
+	volatile u32 DENALI_CTL_24;
+	volatile u32 DENALI_CTL_25;
+	volatile u32 DENALI_CTL_26;
+	volatile u32 DENALI_CTL_27;
+	volatile u32 DENALI_CTL_28;
+	volatile u32 DENALI_CTL_29;
+	volatile u32 DENALI_CTL_30;
+	volatile u32 DENALI_CTL_31;
+	volatile u32 DENALI_CTL_32;
+	volatile u32 DENALI_CTL_33;
+	volatile u32 DENALI_CTL_34;
+	volatile u32 DENALI_CTL_35;
+	volatile u32 DENALI_CTL_36;
+	volatile u32 DENALI_CTL_37;
+	volatile u32 DENALI_CTL_38;
+	volatile u32 DENALI_CTL_39;
+	volatile u32 DENALI_CTL_40;
+	volatile u32 DENALI_CTL_41;
+	volatile u32 DENALI_CTL_42;
+	volatile u32 DENALI_CTL_43;
+	volatile u32 DENALI_CTL_44;
+	volatile u32 DENALI_CTL_45;
+	volatile u32 DENALI_CTL_46;
+	volatile u32 DENALI_CTL_47;
+	volatile u32 DENALI_CTL_48;
+	volatile u32 DENALI_CTL_49;
+	volatile u32 DENALI_CTL_50;
+	volatile u32 DENALI_CTL_51;
+	volatile u32 DENALI_CTL_52;
+	volatile u32 DENALI_CTL_53;
+	volatile u32 DENALI_CTL_54;
+	volatile u32 DENALI_CTL_55;
+	volatile u32 DENALI_CTL_56;
+	volatile u32 DENALI_CTL_57;
+	volatile u32 DENALI_CTL_58;
+	volatile u32 DENALI_CTL_59;
+	volatile u32 DENALI_CTL_60;
+	volatile u32 DENALI_CTL_61;
+	volatile u32 DENALI_CTL_62;
+	volatile u32 DENALI_CTL_63;
+	volatile u32 DENALI_CTL_64;
+	volatile u32 DENALI_CTL_65;
+	volatile u32 DENALI_CTL_66;
+	volatile u32 DENALI_CTL_67;
+	volatile u32 DENALI_CTL_68;
+	volatile u32 DENALI_CTL_69;
+	volatile u32 DENALI_CTL_70;
+	volatile u32 DENALI_CTL_71;
+	volatile u32 DENALI_CTL_72;
+	volatile u32 DENALI_CTL_73;
+	volatile u32 DENALI_CTL_74;
+	volatile u32 DENALI_CTL_75;
+	volatile u32 DENALI_CTL_76;
+	volatile u32 DENALI_CTL_77;
+	volatile u32 DENALI_CTL_78;
+	volatile u32 DENALI_CTL_79;
+	volatile u32 DENALI_CTL_80;
+	volatile u32 DENALI_CTL_81;
+	volatile u32 DENALI_CTL_82;
+	volatile u32 DENALI_CTL_83;
+	volatile u32 DENALI_CTL_84;
+	volatile u32 DENALI_CTL_85;
+	volatile u32 DENALI_CTL_86;
+	volatile u32 DENALI_CTL_87;
+	volatile u32 DENALI_CTL_88;
+	volatile u32 DENALI_CTL_89;
+	volatile u32 DENALI_CTL_90;
+	volatile u32 DENALI_CTL_91;
+	volatile u32 DENALI_CTL_92;
+	volatile u32 DENALI_CTL_93;
+	volatile u32 DENALI_CTL_94;
+	volatile u32 DENALI_CTL_95;
+	volatile u32 DENALI_CTL_96;
+	volatile u32 DENALI_CTL_97;
+	volatile u32 DENALI_CTL_98;
+	volatile u32 DENALI_CTL_99;
+	volatile u32 DENALI_CTL_100;
+	volatile u32 DENALI_CTL_101;
+	volatile u32 DENALI_CTL_102;
+	volatile u32 DENALI_CTL_103;
+	volatile u32 DENALI_CTL_104;
+	volatile u32 DENALI_CTL_105;
+	volatile u32 DENALI_CTL_106;
+	volatile u32 DENALI_CTL_107;
+	volatile u32 DENALI_CTL_108;
+	volatile u32 DENALI_CTL_109;
+	volatile u32 DENALI_CTL_110;
+	volatile u32 DENALI_CTL_111;
+	volatile u32 DENALI_CTL_112;
+	volatile u32 DENALI_CTL_113;
+	volatile u32 DENALI_CTL_114;
+	volatile u32 DENALI_CTL_115;
+	volatile u32 DENALI_CTL_116;
+	volatile u32 DENALI_CTL_117;
+	volatile u32 DENALI_CTL_118;
+	volatile u32 DENALI_CTL_119;
+	volatile u32 DENALI_CTL_120;
+	volatile u32 DENALI_CTL_121;
+	volatile u32 DENALI_CTL_122;
+	volatile u32 DENALI_CTL_123;
+	volatile u32 DENALI_CTL_124;
+	volatile u32 DENALI_CTL_125;
+	volatile u32 DENALI_CTL_126;
+	volatile u32 DENALI_CTL_127;
+	volatile u32 DENALI_CTL_128;
+	volatile u32 DENALI_CTL_129;
+	volatile u32 DENALI_CTL_130;
+	volatile u32 DENALI_CTL_131;
+	volatile u32 DENALI_CTL_132;
+	volatile u32 DENALI_CTL_133;
+	volatile u32 DENALI_CTL_134;
+	volatile u32 DENALI_CTL_135;
+	volatile u32 DENALI_CTL_136;
+	volatile u32 DENALI_CTL_137;
+	volatile u32 DENALI_CTL_138;
+	volatile u32 DENALI_CTL_139;
+	volatile u32 DENALI_CTL_140;
+	volatile u32 DENALI_CTL_141;
+	volatile u32 DENALI_CTL_142;
+	volatile u32 DENALI_CTL_143;
+	volatile u32 DENALI_CTL_144;
+	volatile u32 DENALI_CTL_145;
+	volatile u32 DENALI_CTL_146;
+	volatile u32 DENALI_CTL_147;
+	volatile u32 DENALI_CTL_148;
+	volatile u32 DENALI_CTL_149;
+	volatile u32 DENALI_CTL_150;
+	volatile u32 DENALI_CTL_151;
+	volatile u32 DENALI_CTL_152;
+	volatile u32 DENALI_CTL_153;
+	volatile u32 DENALI_CTL_154;
+	volatile u32 DENALI_CTL_155;
+	volatile u32 DENALI_CTL_156;
+	volatile u32 DENALI_CTL_157;
+	volatile u32 DENALI_CTL_158;
+	volatile u32 DENALI_CTL_159;
+	volatile u32 DENALI_CTL_160;
+	volatile u32 DENALI_CTL_161;
+	volatile u32 DENALI_CTL_162;
+	volatile u32 DENALI_CTL_163;
+	volatile u32 DENALI_CTL_164;
+	volatile u32 DENALI_CTL_165;
+	volatile u32 DENALI_CTL_166;
+	volatile u32 DENALI_CTL_167;
+	volatile u32 DENALI_CTL_168;
+	volatile u32 DENALI_CTL_169;
+	volatile u32 DENALI_CTL_170;
+	volatile u32 DENALI_CTL_171;
+	volatile u32 DENALI_CTL_172;
+	volatile u32 DENALI_CTL_173;
+	volatile u32 DENALI_CTL_174;
+	volatile u32 DENALI_CTL_175;
+	volatile u32 DENALI_CTL_176;
+	volatile u32 DENALI_CTL_177;
+	volatile u32 DENALI_CTL_178;
+	volatile u32 DENALI_CTL_179;
+	volatile u32 DENALI_CTL_180;
+	volatile u32 DENALI_CTL_181;
+	volatile u32 DENALI_CTL_182;
+	volatile u32 DENALI_CTL_183;
+	volatile u32 DENALI_CTL_184;
+	volatile u32 DENALI_CTL_185;
+	volatile u32 DENALI_CTL_186;
+	volatile u32 DENALI_CTL_187;
+	volatile u32 DENALI_CTL_188;
+	volatile u32 DENALI_CTL_189;
+	volatile u32 DENALI_CTL_190;
+	volatile u32 DENALI_CTL_191;
+	volatile u32 DENALI_CTL_192;
+	volatile u32 DENALI_CTL_193;
+	volatile u32 DENALI_CTL_194;
+	volatile u32 DENALI_CTL_195;
+	volatile u32 DENALI_CTL_196;
+	volatile u32 DENALI_CTL_197;
+	volatile u32 DENALI_CTL_198;
+	volatile u32 DENALI_CTL_199;
+	volatile u32 DENALI_CTL_200;
+	volatile u32 DENALI_CTL_201;
+	volatile u32 DENALI_CTL_202;
+	volatile u32 DENALI_CTL_203;
+	volatile u32 DENALI_CTL_204;
+	volatile u32 DENALI_CTL_205;
+	volatile u32 DENALI_CTL_206;
+	volatile u32 DENALI_CTL_207;
+	volatile u32 DENALI_CTL_208;
+	volatile u32 DENALI_CTL_209;
+	volatile u32 DENALI_CTL_210;
+	volatile u32 DENALI_CTL_211;
+	volatile u32 DENALI_CTL_212;
+	volatile u32 DENALI_CTL_213;
+	volatile u32 DENALI_CTL_214;
+	volatile u32 DENALI_CTL_215;
+	volatile u32 DENALI_CTL_216;
+	volatile u32 DENALI_CTL_217;
+	volatile u32 DENALI_CTL_218;
+	volatile u32 DENALI_CTL_219;
+	volatile u32 DENALI_CTL_220;
+	volatile u32 DENALI_CTL_221;
+	volatile u32 DENALI_CTL_222;
+	volatile u32 DENALI_CTL_223;
+	volatile u32 DENALI_CTL_224;
+	volatile u32 DENALI_CTL_225;
+	volatile u32 DENALI_CTL_226;
+	volatile u32 DENALI_CTL_227;
+	volatile u32 DENALI_CTL_228;
+	volatile u32 DENALI_CTL_229;
+	volatile u32 DENALI_CTL_230;
+	volatile u32 DENALI_CTL_231;
+	volatile u32 DENALI_CTL_232;
+	volatile u32 DENALI_CTL_233;
+	volatile u32 DENALI_CTL_234;
+	volatile u32 DENALI_CTL_235;
+	volatile u32 DENALI_CTL_236;
+	volatile u32 DENALI_CTL_237;
+	volatile u32 DENALI_CTL_238;
+	volatile u32 DENALI_CTL_239;
+	volatile u32 DENALI_CTL_240;
+	volatile u32 DENALI_CTL_241;
+	volatile u32 DENALI_CTL_242;
+	volatile u32 DENALI_CTL_243;
+	volatile u32 DENALI_CTL_244;
+	volatile u32 DENALI_CTL_245;
+	volatile u32 DENALI_CTL_246;
+	volatile u32 DENALI_CTL_247;
+	volatile u32 DENALI_CTL_248;
+	volatile u32 DENALI_CTL_249;
+	volatile u32 DENALI_CTL_250;
+	volatile u32 DENALI_CTL_251;
+	volatile u32 DENALI_CTL_252;
+	volatile u32 DENALI_CTL_253;
+	volatile u32 DENALI_CTL_254;
+	volatile u32 DENALI_CTL_255;
+	volatile u32 DENALI_CTL_256;
+	volatile u32 DENALI_CTL_257;
+	volatile u32 DENALI_CTL_258;
+	volatile u32 DENALI_CTL_259;
+	volatile u32 DENALI_CTL_260;
+	volatile u32 DENALI_CTL_261;
+	volatile u32 DENALI_CTL_262;
+	volatile u32 DENALI_CTL_263;
+	volatile u32 DENALI_CTL_264;
+	volatile u32 DENALI_CTL_265;
+	volatile u32 DENALI_CTL_266;
+	volatile u32 DENALI_CTL_267;
+	volatile u32 DENALI_CTL_268;
+	volatile u32 DENALI_CTL_269;
+	volatile u32 DENALI_CTL_270;
+	volatile u32 DENALI_CTL_271;
+	volatile u32 DENALI_CTL_272;
+	volatile u32 DENALI_CTL_273;
+	volatile u32 DENALI_CTL_274;
+	volatile u32 DENALI_CTL_275;
+	volatile u32 DENALI_CTL_276;
+	volatile u32 DENALI_CTL_277;
+	volatile u32 DENALI_CTL_278;
+	volatile u32 DENALI_CTL_279;
+	volatile u32 DENALI_CTL_280;
+	volatile u32 DENALI_CTL_281;
+	volatile u32 DENALI_CTL_282;
+	volatile u32 DENALI_CTL_283;
+	volatile u32 DENALI_CTL_284;
+	volatile u32 DENALI_CTL_285;
+	volatile u32 DENALI_CTL_286;
+	volatile u32 DENALI_CTL_287;
+	volatile u32 DENALI_CTL_288;
+	volatile u32 DENALI_CTL_289;
+	volatile u32 DENALI_CTL_290;
+	volatile u32 DENALI_CTL_291;
+	volatile u32 DENALI_CTL_292;
+	volatile u32 DENALI_CTL_293;
+	volatile u32 DENALI_CTL_294;
+	volatile u32 DENALI_CTL_295;
+	volatile u32 DENALI_CTL_296;
+	volatile u32 DENALI_CTL_297;
+	volatile u32 DENALI_CTL_298;
+	volatile u32 DENALI_CTL_299;
+	volatile u32 DENALI_CTL_300;
+	volatile u32 DENALI_CTL_301;
+	volatile u32 DENALI_CTL_302;
+	volatile u32 DENALI_CTL_303;
+	volatile u32 DENALI_CTL_304;
+	volatile u32 DENALI_CTL_305;
+	volatile u32 DENALI_CTL_306;
+	volatile u32 DENALI_CTL_307;
+	volatile u32 DENALI_CTL_308;
+	volatile u32 DENALI_CTL_309;
+	volatile u32 DENALI_CTL_310;
+	volatile u32 DENALI_CTL_311;
+	volatile u32 DENALI_CTL_312;
+	volatile u32 DENALI_CTL_313;
+	volatile u32 DENALI_CTL_314;
+	volatile u32 DENALI_CTL_315;
+	volatile u32 DENALI_CTL_316;
+	volatile u32 DENALI_CTL_317;
+	volatile u32 DENALI_CTL_318;
+	volatile u32 DENALI_CTL_319;
+	volatile u32 DENALI_CTL_320;
+	volatile u32 DENALI_CTL_321;
+	volatile u32 DENALI_CTL_322;
+	volatile u32 DENALI_CTL_323;
+	volatile u32 DENALI_CTL_324;
+	volatile u32 DENALI_CTL_325;
+	volatile u32 DENALI_CTL_326;
+	volatile u32 DENALI_CTL_327;
+	volatile u32 DENALI_CTL_328;
+	volatile u32 DENALI_CTL_329;
+	volatile u32 DENALI_CTL_330;
+	volatile u32 DENALI_CTL_331;
+	volatile u32 DENALI_CTL_332;
+	volatile u32 DENALI_CTL_333;
+	volatile u32 DENALI_CTL_334;
+	volatile u32 DENALI_CTL_335;
+	volatile u32 DENALI_CTL_336;
+	volatile u32 DENALI_CTL_337;
+	volatile u32 DENALI_CTL_338;
+	volatile u32 DENALI_CTL_339;
+	volatile u32 DENALI_CTL_340;
+	volatile u32 DENALI_CTL_341;
+	volatile u32 DENALI_CTL_342;
+	volatile u32 DENALI_CTL_343;
+	volatile u32 DENALI_CTL_344;
+	volatile u32 DENALI_CTL_345;
+	volatile u32 DENALI_CTL_346;
+	volatile u32 DENALI_CTL_347;
+	volatile u32 DENALI_CTL_348;
+	volatile u32 DENALI_CTL_349;
+	volatile u32 DENALI_CTL_350;
+	volatile u32 DENALI_CTL_351;
+	volatile u32 DENALI_CTL_352;
+	volatile u32 DENALI_CTL_353;
+	volatile u32 DENALI_CTL_354;
+	volatile u32 DENALI_CTL_355;
+	volatile u32 DENALI_CTL_356;
+	volatile u32 DENALI_CTL_357;
+	volatile u32 DENALI_CTL_358;
+	volatile u32 DENALI_CTL_359;
+	volatile u32 DENALI_CTL_360;
+	volatile u32 DENALI_CTL_361;
+	volatile u32 DENALI_CTL_362;
+	volatile u32 DENALI_CTL_363;
+	volatile u32 DENALI_CTL_364;
+	volatile u32 DENALI_CTL_365;
+	volatile u32 DENALI_CTL_366;
+	volatile u32 DENALI_CTL_367;
+	volatile u32 DENALI_CTL_368;
+	volatile u32 DENALI_CTL_369;
+	volatile u32 DENALI_CTL_370;
+	volatile u32 DENALI_CTL_371;
+	volatile u32 DENALI_CTL_372;
+	volatile u32 DENALI_CTL_373;
+	volatile u32 DENALI_CTL_374;
+	volatile u32 DENALI_CTL_375;
+	volatile u32 DENALI_CTL_376;
+	volatile u32 DENALI_CTL_377;
+	volatile u32 DENALI_CTL_378;
+	volatile u32 DENALI_CTL_379;
+	volatile u32 DENALI_CTL_380;
+	volatile u32 DENALI_CTL_381;
+	volatile u32 DENALI_CTL_382;
+	volatile u32 DENALI_CTL_383;
+	volatile u32 DENALI_CTL_384;
+	volatile u32 DENALI_CTL_385;
+	volatile u32 DENALI_CTL_386;
+	volatile u32 DENALI_CTL_387;
+	volatile u32 DENALI_CTL_388;
+	volatile u32 DENALI_CTL_389;
+	volatile u32 DENALI_CTL_390;
+	volatile u32 DENALI_CTL_391;
+	volatile u32 DENALI_CTL_392;
+	volatile u32 DENALI_CTL_393;
+	volatile u32 DENALI_CTL_394;
+	volatile u32 DENALI_CTL_395;
+	volatile u32 DENALI_CTL_396;
+	volatile u32 DENALI_CTL_397;
+	volatile u32 DENALI_CTL_398;
+	volatile u32 DENALI_CTL_399;
+	volatile u32 DENALI_CTL_400;
+	volatile u32 DENALI_CTL_401;
+	volatile u32 DENALI_CTL_402;
+	volatile u32 DENALI_CTL_403;
+	volatile u32 DENALI_CTL_404;
+	volatile u32 DENALI_CTL_405;
+	volatile u32 DENALI_CTL_406;
+	volatile u32 DENALI_CTL_407;
+	volatile u32 DENALI_CTL_408;
+	volatile u32 DENALI_CTL_409;
+	volatile u32 DENALI_CTL_410;
+	volatile u32 DENALI_CTL_411;
+	volatile u32 DENALI_CTL_412;
+	volatile u32 DENALI_CTL_413;
+	volatile u32 DENALI_CTL_414;
+	volatile u32 DENALI_CTL_415;
+	volatile u32 DENALI_CTL_416;
+	volatile u32 DENALI_CTL_417;
+	volatile u32 DENALI_CTL_418;
+	volatile u32 DENALI_CTL_419;
+	volatile u32 DENALI_CTL_420;
+	volatile u32 DENALI_CTL_421;
+	volatile u32 DENALI_CTL_422;
+	volatile u32 DENALI_CTL_423;
+	volatile u32 DENALI_CTL_424;
+	volatile u32 DENALI_CTL_425;
+	volatile u32 DENALI_CTL_426;
+	volatile u32 DENALI_CTL_427;
+	volatile u32 DENALI_CTL_428;
+	volatile u32 DENALI_CTL_429;
+	volatile u32 DENALI_CTL_430;
+	volatile u32 DENALI_CTL_431;
+	volatile u32 DENALI_CTL_432;
+	volatile u32 DENALI_CTL_433;
+	volatile u32 DENALI_CTL_434;
+	volatile u32 DENALI_CTL_435;
+	volatile u32 DENALI_CTL_436;
+	volatile u32 DENALI_CTL_437;
+	volatile u32 DENALI_CTL_438;
+	volatile u32 DENALI_CTL_439;
+	volatile u32 DENALI_CTL_440;
+	volatile u32 DENALI_CTL_441;
+	volatile u32 DENALI_CTL_442;
+	volatile u32 DENALI_CTL_443;
+	volatile u32 DENALI_CTL_444;
+	volatile u32 DENALI_CTL_445;
+	volatile u32 DENALI_CTL_446;
+	volatile u32 DENALI_CTL_447;
+	volatile u32 DENALI_CTL_448;
+	volatile u32 DENALI_CTL_449;
+	volatile u32 DENALI_CTL_450;
+	volatile u32 DENALI_CTL_451;
+	volatile u32 DENALI_CTL_452;
+	volatile u32 DENALI_CTL_453;
+	volatile u32 DENALI_CTL_454;
+	volatile u32 DENALI_CTL_455;
+	volatile u32 DENALI_CTL_456;
+	volatile u32 DENALI_CTL_457;
+	volatile u32 DENALI_CTL_458;
+	volatile char pad__0[0x18D4U];
+	volatile u32 DENALI_PI_0;
+	volatile u32 DENALI_PI_1;
+	volatile u32 DENALI_PI_2;
+	volatile u32 DENALI_PI_3;
+	volatile u32 DENALI_PI_4;
+	volatile u32 DENALI_PI_5;
+	volatile u32 DENALI_PI_6;
+	volatile u32 DENALI_PI_7;
+	volatile u32 DENALI_PI_8;
+	volatile u32 DENALI_PI_9;
+	volatile u32 DENALI_PI_10;
+	volatile u32 DENALI_PI_11;
+	volatile u32 DENALI_PI_12;
+	volatile u32 DENALI_PI_13;
+	volatile u32 DENALI_PI_14;
+	volatile u32 DENALI_PI_15;
+	volatile u32 DENALI_PI_16;
+	volatile u32 DENALI_PI_17;
+	volatile u32 DENALI_PI_18;
+	volatile u32 DENALI_PI_19;
+	volatile u32 DENALI_PI_20;
+	volatile u32 DENALI_PI_21;
+	volatile u32 DENALI_PI_22;
+	volatile u32 DENALI_PI_23;
+	volatile u32 DENALI_PI_24;
+	volatile u32 DENALI_PI_25;
+	volatile u32 DENALI_PI_26;
+	volatile u32 DENALI_PI_27;
+	volatile u32 DENALI_PI_28;
+	volatile u32 DENALI_PI_29;
+	volatile u32 DENALI_PI_30;
+	volatile u32 DENALI_PI_31;
+	volatile u32 DENALI_PI_32;
+	volatile u32 DENALI_PI_33;
+	volatile u32 DENALI_PI_34;
+	volatile u32 DENALI_PI_35;
+	volatile u32 DENALI_PI_36;
+	volatile u32 DENALI_PI_37;
+	volatile u32 DENALI_PI_38;
+	volatile u32 DENALI_PI_39;
+	volatile u32 DENALI_PI_40;
+	volatile u32 DENALI_PI_41;
+	volatile u32 DENALI_PI_42;
+	volatile u32 DENALI_PI_43;
+	volatile u32 DENALI_PI_44;
+	volatile u32 DENALI_PI_45;
+	volatile u32 DENALI_PI_46;
+	volatile u32 DENALI_PI_47;
+	volatile u32 DENALI_PI_48;
+	volatile u32 DENALI_PI_49;
+	volatile u32 DENALI_PI_50;
+	volatile u32 DENALI_PI_51;
+	volatile u32 DENALI_PI_52;
+	volatile u32 DENALI_PI_53;
+	volatile u32 DENALI_PI_54;
+	volatile u32 DENALI_PI_55;
+	volatile u32 DENALI_PI_56;
+	volatile u32 DENALI_PI_57;
+	volatile u32 DENALI_PI_58;
+	volatile u32 DENALI_PI_59;
+	volatile u32 DENALI_PI_60;
+	volatile u32 DENALI_PI_61;
+	volatile u32 DENALI_PI_62;
+	volatile u32 DENALI_PI_63;
+	volatile u32 DENALI_PI_64;
+	volatile u32 DENALI_PI_65;
+	volatile u32 DENALI_PI_66;
+	volatile u32 DENALI_PI_67;
+	volatile u32 DENALI_PI_68;
+	volatile u32 DENALI_PI_69;
+	volatile u32 DENALI_PI_70;
+	volatile u32 DENALI_PI_71;
+	volatile u32 DENALI_PI_72;
+	volatile u32 DENALI_PI_73;
+	volatile u32 DENALI_PI_74;
+	volatile u32 DENALI_PI_75;
+	volatile u32 DENALI_PI_76;
+	volatile u32 DENALI_PI_77;
+	volatile u32 DENALI_PI_78;
+	volatile u32 DENALI_PI_79;
+	volatile u32 DENALI_PI_80;
+	volatile u32 DENALI_PI_81;
+	volatile u32 DENALI_PI_82;
+	volatile u32 DENALI_PI_83;
+	volatile u32 DENALI_PI_84;
+	volatile u32 DENALI_PI_85;
+	volatile u32 DENALI_PI_86;
+	volatile u32 DENALI_PI_87;
+	volatile u32 DENALI_PI_88;
+	volatile u32 DENALI_PI_89;
+	volatile u32 DENALI_PI_90;
+	volatile u32 DENALI_PI_91;
+	volatile u32 DENALI_PI_92;
+	volatile u32 DENALI_PI_93;
+	volatile u32 DENALI_PI_94;
+	volatile u32 DENALI_PI_95;
+	volatile u32 DENALI_PI_96;
+	volatile u32 DENALI_PI_97;
+	volatile u32 DENALI_PI_98;
+	volatile u32 DENALI_PI_99;
+	volatile u32 DENALI_PI_100;
+	volatile u32 DENALI_PI_101;
+	volatile u32 DENALI_PI_102;
+	volatile u32 DENALI_PI_103;
+	volatile u32 DENALI_PI_104;
+	volatile u32 DENALI_PI_105;
+	volatile u32 DENALI_PI_106;
+	volatile u32 DENALI_PI_107;
+	volatile u32 DENALI_PI_108;
+	volatile u32 DENALI_PI_109;
+	volatile u32 DENALI_PI_110;
+	volatile u32 DENALI_PI_111;
+	volatile u32 DENALI_PI_112;
+	volatile u32 DENALI_PI_113;
+	volatile u32 DENALI_PI_114;
+	volatile u32 DENALI_PI_115;
+	volatile u32 DENALI_PI_116;
+	volatile u32 DENALI_PI_117;
+	volatile u32 DENALI_PI_118;
+	volatile u32 DENALI_PI_119;
+	volatile u32 DENALI_PI_120;
+	volatile u32 DENALI_PI_121;
+	volatile u32 DENALI_PI_122;
+	volatile u32 DENALI_PI_123;
+	volatile u32 DENALI_PI_124;
+	volatile u32 DENALI_PI_125;
+	volatile u32 DENALI_PI_126;
+	volatile u32 DENALI_PI_127;
+	volatile u32 DENALI_PI_128;
+	volatile u32 DENALI_PI_129;
+	volatile u32 DENALI_PI_130;
+	volatile u32 DENALI_PI_131;
+	volatile u32 DENALI_PI_132;
+	volatile u32 DENALI_PI_133;
+	volatile u32 DENALI_PI_134;
+	volatile u32 DENALI_PI_135;
+	volatile u32 DENALI_PI_136;
+	volatile u32 DENALI_PI_137;
+	volatile u32 DENALI_PI_138;
+	volatile u32 DENALI_PI_139;
+	volatile u32 DENALI_PI_140;
+	volatile u32 DENALI_PI_141;
+	volatile u32 DENALI_PI_142;
+	volatile u32 DENALI_PI_143;
+	volatile u32 DENALI_PI_144;
+	volatile u32 DENALI_PI_145;
+	volatile u32 DENALI_PI_146;
+	volatile u32 DENALI_PI_147;
+	volatile u32 DENALI_PI_148;
+	volatile u32 DENALI_PI_149;
+	volatile u32 DENALI_PI_150;
+	volatile u32 DENALI_PI_151;
+	volatile u32 DENALI_PI_152;
+	volatile u32 DENALI_PI_153;
+	volatile u32 DENALI_PI_154;
+	volatile u32 DENALI_PI_155;
+	volatile u32 DENALI_PI_156;
+	volatile u32 DENALI_PI_157;
+	volatile u32 DENALI_PI_158;
+	volatile u32 DENALI_PI_159;
+	volatile u32 DENALI_PI_160;
+	volatile u32 DENALI_PI_161;
+	volatile u32 DENALI_PI_162;
+	volatile u32 DENALI_PI_163;
+	volatile u32 DENALI_PI_164;
+	volatile u32 DENALI_PI_165;
+	volatile u32 DENALI_PI_166;
+	volatile u32 DENALI_PI_167;
+	volatile u32 DENALI_PI_168;
+	volatile u32 DENALI_PI_169;
+	volatile u32 DENALI_PI_170;
+	volatile u32 DENALI_PI_171;
+	volatile u32 DENALI_PI_172;
+	volatile u32 DENALI_PI_173;
+	volatile u32 DENALI_PI_174;
+	volatile u32 DENALI_PI_175;
+	volatile u32 DENALI_PI_176;
+	volatile u32 DENALI_PI_177;
+	volatile u32 DENALI_PI_178;
+	volatile u32 DENALI_PI_179;
+	volatile u32 DENALI_PI_180;
+	volatile u32 DENALI_PI_181;
+	volatile u32 DENALI_PI_182;
+	volatile u32 DENALI_PI_183;
+	volatile u32 DENALI_PI_184;
+	volatile u32 DENALI_PI_185;
+	volatile u32 DENALI_PI_186;
+	volatile u32 DENALI_PI_187;
+	volatile u32 DENALI_PI_188;
+	volatile u32 DENALI_PI_189;
+	volatile u32 DENALI_PI_190;
+	volatile u32 DENALI_PI_191;
+	volatile u32 DENALI_PI_192;
+	volatile u32 DENALI_PI_193;
+	volatile u32 DENALI_PI_194;
+	volatile u32 DENALI_PI_195;
+	volatile u32 DENALI_PI_196;
+	volatile u32 DENALI_PI_197;
+	volatile u32 DENALI_PI_198;
+	volatile u32 DENALI_PI_199;
+	volatile u32 DENALI_PI_200;
+	volatile u32 DENALI_PI_201;
+	volatile u32 DENALI_PI_202;
+	volatile u32 DENALI_PI_203;
+	volatile u32 DENALI_PI_204;
+	volatile u32 DENALI_PI_205;
+	volatile u32 DENALI_PI_206;
+	volatile u32 DENALI_PI_207;
+	volatile u32 DENALI_PI_208;
+	volatile u32 DENALI_PI_209;
+	volatile u32 DENALI_PI_210;
+	volatile u32 DENALI_PI_211;
+	volatile u32 DENALI_PI_212;
+	volatile u32 DENALI_PI_213;
+	volatile u32 DENALI_PI_214;
+	volatile u32 DENALI_PI_215;
+	volatile u32 DENALI_PI_216;
+	volatile u32 DENALI_PI_217;
+	volatile u32 DENALI_PI_218;
+	volatile u32 DENALI_PI_219;
+	volatile u32 DENALI_PI_220;
+	volatile u32 DENALI_PI_221;
+	volatile u32 DENALI_PI_222;
+	volatile u32 DENALI_PI_223;
+	volatile u32 DENALI_PI_224;
+	volatile u32 DENALI_PI_225;
+	volatile u32 DENALI_PI_226;
+	volatile u32 DENALI_PI_227;
+	volatile u32 DENALI_PI_228;
+	volatile u32 DENALI_PI_229;
+	volatile u32 DENALI_PI_230;
+	volatile u32 DENALI_PI_231;
+	volatile u32 DENALI_PI_232;
+	volatile u32 DENALI_PI_233;
+	volatile u32 DENALI_PI_234;
+	volatile u32 DENALI_PI_235;
+	volatile u32 DENALI_PI_236;
+	volatile u32 DENALI_PI_237;
+	volatile u32 DENALI_PI_238;
+	volatile u32 DENALI_PI_239;
+	volatile u32 DENALI_PI_240;
+	volatile u32 DENALI_PI_241;
+	volatile u32 DENALI_PI_242;
+	volatile u32 DENALI_PI_243;
+	volatile u32 DENALI_PI_244;
+	volatile u32 DENALI_PI_245;
+	volatile u32 DENALI_PI_246;
+	volatile u32 DENALI_PI_247;
+	volatile u32 DENALI_PI_248;
+	volatile u32 DENALI_PI_249;
+	volatile u32 DENALI_PI_250;
+	volatile u32 DENALI_PI_251;
+	volatile u32 DENALI_PI_252;
+	volatile u32 DENALI_PI_253;
+	volatile u32 DENALI_PI_254;
+	volatile u32 DENALI_PI_255;
+	volatile u32 DENALI_PI_256;
+	volatile u32 DENALI_PI_257;
+	volatile u32 DENALI_PI_258;
+	volatile u32 DENALI_PI_259;
+	volatile u32 DENALI_PI_260;
+	volatile u32 DENALI_PI_261;
+	volatile u32 DENALI_PI_262;
+	volatile u32 DENALI_PI_263;
+	volatile u32 DENALI_PI_264;
+	volatile u32 DENALI_PI_265;
+	volatile u32 DENALI_PI_266;
+	volatile u32 DENALI_PI_267;
+	volatile u32 DENALI_PI_268;
+	volatile u32 DENALI_PI_269;
+	volatile u32 DENALI_PI_270;
+	volatile u32 DENALI_PI_271;
+	volatile u32 DENALI_PI_272;
+	volatile u32 DENALI_PI_273;
+	volatile u32 DENALI_PI_274;
+	volatile u32 DENALI_PI_275;
+	volatile u32 DENALI_PI_276;
+	volatile u32 DENALI_PI_277;
+	volatile u32 DENALI_PI_278;
+	volatile u32 DENALI_PI_279;
+	volatile u32 DENALI_PI_280;
+	volatile u32 DENALI_PI_281;
+	volatile u32 DENALI_PI_282;
+	volatile u32 DENALI_PI_283;
+	volatile u32 DENALI_PI_284;
+	volatile u32 DENALI_PI_285;
+	volatile u32 DENALI_PI_286;
+	volatile u32 DENALI_PI_287;
+	volatile u32 DENALI_PI_288;
+	volatile u32 DENALI_PI_289;
+	volatile u32 DENALI_PI_290;
+	volatile u32 DENALI_PI_291;
+	volatile u32 DENALI_PI_292;
+	volatile u32 DENALI_PI_293;
+	volatile u32 DENALI_PI_294;
+	volatile u32 DENALI_PI_295;
+	volatile u32 DENALI_PI_296;
+	volatile u32 DENALI_PI_297;
+	volatile u32 DENALI_PI_298;
+	volatile u32 DENALI_PI_299;
+	volatile char pad__1[0x1B50U];
+	volatile u32 DENALI_PHY_0;
+	volatile u32 DENALI_PHY_1;
+	volatile u32 DENALI_PHY_2;
+	volatile u32 DENALI_PHY_3;
+	volatile u32 DENALI_PHY_4;
+	volatile u32 DENALI_PHY_5;
+	volatile u32 DENALI_PHY_6;
+	volatile u32 DENALI_PHY_7;
+	volatile u32 DENALI_PHY_8;
+	volatile u32 DENALI_PHY_9;
+	volatile u32 DENALI_PHY_10;
+	volatile u32 DENALI_PHY_11;
+	volatile u32 DENALI_PHY_12;
+	volatile u32 DENALI_PHY_13;
+	volatile u32 DENALI_PHY_14;
+	volatile u32 DENALI_PHY_15;
+	volatile u32 DENALI_PHY_16;
+	volatile u32 DENALI_PHY_17;
+	volatile u32 DENALI_PHY_18;
+	volatile u32 DENALI_PHY_19;
+	volatile u32 DENALI_PHY_20;
+	volatile u32 DENALI_PHY_21;
+	volatile u32 DENALI_PHY_22;
+	volatile u32 DENALI_PHY_23;
+	volatile u32 DENALI_PHY_24;
+	volatile u32 DENALI_PHY_25;
+	volatile u32 DENALI_PHY_26;
+	volatile u32 DENALI_PHY_27;
+	volatile u32 DENALI_PHY_28;
+	volatile u32 DENALI_PHY_29;
+	volatile u32 DENALI_PHY_30;
+	volatile u32 DENALI_PHY_31;
+	volatile u32 DENALI_PHY_32;
+	volatile u32 DENALI_PHY_33;
+	volatile u32 DENALI_PHY_34;
+	volatile u32 DENALI_PHY_35;
+	volatile u32 DENALI_PHY_36;
+	volatile u32 DENALI_PHY_37;
+	volatile u32 DENALI_PHY_38;
+	volatile u32 DENALI_PHY_39;
+	volatile u32 DENALI_PHY_40;
+	volatile u32 DENALI_PHY_41;
+	volatile u32 DENALI_PHY_42;
+	volatile u32 DENALI_PHY_43;
+	volatile u32 DENALI_PHY_44;
+	volatile u32 DENALI_PHY_45;
+	volatile u32 DENALI_PHY_46;
+	volatile u32 DENALI_PHY_47;
+	volatile u32 DENALI_PHY_48;
+	volatile u32 DENALI_PHY_49;
+	volatile u32 DENALI_PHY_50;
+	volatile u32 DENALI_PHY_51;
+	volatile u32 DENALI_PHY_52;
+	volatile u32 DENALI_PHY_53;
+	volatile u32 DENALI_PHY_54;
+	volatile u32 DENALI_PHY_55;
+	volatile u32 DENALI_PHY_56;
+	volatile u32 DENALI_PHY_57;
+	volatile u32 DENALI_PHY_58;
+	volatile u32 DENALI_PHY_59;
+	volatile u32 DENALI_PHY_60;
+	volatile u32 DENALI_PHY_61;
+	volatile u32 DENALI_PHY_62;
+	volatile u32 DENALI_PHY_63;
+	volatile u32 DENALI_PHY_64;
+	volatile u32 DENALI_PHY_65;
+	volatile u32 DENALI_PHY_66;
+	volatile u32 DENALI_PHY_67;
+	volatile u32 DENALI_PHY_68;
+	volatile u32 DENALI_PHY_69;
+	volatile u32 DENALI_PHY_70;
+	volatile u32 DENALI_PHY_71;
+	volatile u32 DENALI_PHY_72;
+	volatile u32 DENALI_PHY_73;
+	volatile u32 DENALI_PHY_74;
+	volatile u32 DENALI_PHY_75;
+	volatile u32 DENALI_PHY_76;
+	volatile u32 DENALI_PHY_77;
+	volatile u32 DENALI_PHY_78;
+	volatile u32 DENALI_PHY_79;
+	volatile u32 DENALI_PHY_80;
+	volatile u32 DENALI_PHY_81;
+	volatile u32 DENALI_PHY_82;
+	volatile u32 DENALI_PHY_83;
+	volatile u32 DENALI_PHY_84;
+	volatile u32 DENALI_PHY_85;
+	volatile u32 DENALI_PHY_86;
+	volatile u32 DENALI_PHY_87;
+	volatile u32 DENALI_PHY_88;
+	volatile u32 DENALI_PHY_89;
+	volatile u32 DENALI_PHY_90;
+	volatile u32 DENALI_PHY_91;
+	volatile u32 DENALI_PHY_92;
+	volatile u32 DENALI_PHY_93;
+	volatile u32 DENALI_PHY_94;
+	volatile u32 DENALI_PHY_95;
+	volatile u32 DENALI_PHY_96;
+	volatile u32 DENALI_PHY_97;
+	volatile u32 DENALI_PHY_98;
+	volatile u32 DENALI_PHY_99;
+	volatile u32 DENALI_PHY_100;
+	volatile u32 DENALI_PHY_101;
+	volatile u32 DENALI_PHY_102;
+	volatile u32 DENALI_PHY_103;
+	volatile u32 DENALI_PHY_104;
+	volatile u32 DENALI_PHY_105;
+	volatile u32 DENALI_PHY_106;
+	volatile u32 DENALI_PHY_107;
+	volatile u32 DENALI_PHY_108;
+	volatile u32 DENALI_PHY_109;
+	volatile u32 DENALI_PHY_110;
+	volatile u32 DENALI_PHY_111;
+	volatile u32 DENALI_PHY_112;
+	volatile u32 DENALI_PHY_113;
+	volatile u32 DENALI_PHY_114;
+	volatile u32 DENALI_PHY_115;
+	volatile u32 DENALI_PHY_116;
+	volatile u32 DENALI_PHY_117;
+	volatile u32 DENALI_PHY_118;
+	volatile u32 DENALI_PHY_119;
+	volatile u32 DENALI_PHY_120;
+	volatile u32 DENALI_PHY_121;
+	volatile u32 DENALI_PHY_122;
+	volatile u32 DENALI_PHY_123;
+	volatile u32 DENALI_PHY_124;
+	volatile u32 DENALI_PHY_125;
+	volatile u32 DENALI_PHY_126;
+	volatile u32 DENALI_PHY_127;
+	volatile u32 DENALI_PHY_128;
+	volatile u32 DENALI_PHY_129;
+	volatile u32 DENALI_PHY_130;
+	volatile u32 DENALI_PHY_131;
+	volatile u32 DENALI_PHY_132;
+	volatile u32 DENALI_PHY_133;
+	volatile u32 DENALI_PHY_134;
+	volatile u32 DENALI_PHY_135;
+	volatile u32 DENALI_PHY_136;
+	volatile u32 DENALI_PHY_137;
+	volatile u32 DENALI_PHY_138;
+	volatile u32 DENALI_PHY_139;
+	volatile char pad__2[0x1D0U];
+	volatile u32 DENALI_PHY_256;
+	volatile u32 DENALI_PHY_257;
+	volatile u32 DENALI_PHY_258;
+	volatile u32 DENALI_PHY_259;
+	volatile u32 DENALI_PHY_260;
+	volatile u32 DENALI_PHY_261;
+	volatile u32 DENALI_PHY_262;
+	volatile u32 DENALI_PHY_263;
+	volatile u32 DENALI_PHY_264;
+	volatile u32 DENALI_PHY_265;
+	volatile u32 DENALI_PHY_266;
+	volatile u32 DENALI_PHY_267;
+	volatile u32 DENALI_PHY_268;
+	volatile u32 DENALI_PHY_269;
+	volatile u32 DENALI_PHY_270;
+	volatile u32 DENALI_PHY_271;
+	volatile u32 DENALI_PHY_272;
+	volatile u32 DENALI_PHY_273;
+	volatile u32 DENALI_PHY_274;
+	volatile u32 DENALI_PHY_275;
+	volatile u32 DENALI_PHY_276;
+	volatile u32 DENALI_PHY_277;
+	volatile u32 DENALI_PHY_278;
+	volatile u32 DENALI_PHY_279;
+	volatile u32 DENALI_PHY_280;
+	volatile u32 DENALI_PHY_281;
+	volatile u32 DENALI_PHY_282;
+	volatile u32 DENALI_PHY_283;
+	volatile u32 DENALI_PHY_284;
+	volatile u32 DENALI_PHY_285;
+	volatile u32 DENALI_PHY_286;
+	volatile u32 DENALI_PHY_287;
+	volatile u32 DENALI_PHY_288;
+	volatile u32 DENALI_PHY_289;
+	volatile u32 DENALI_PHY_290;
+	volatile u32 DENALI_PHY_291;
+	volatile u32 DENALI_PHY_292;
+	volatile u32 DENALI_PHY_293;
+	volatile u32 DENALI_PHY_294;
+	volatile u32 DENALI_PHY_295;
+	volatile u32 DENALI_PHY_296;
+	volatile u32 DENALI_PHY_297;
+	volatile u32 DENALI_PHY_298;
+	volatile u32 DENALI_PHY_299;
+	volatile u32 DENALI_PHY_300;
+	volatile u32 DENALI_PHY_301;
+	volatile u32 DENALI_PHY_302;
+	volatile u32 DENALI_PHY_303;
+	volatile u32 DENALI_PHY_304;
+	volatile u32 DENALI_PHY_305;
+	volatile u32 DENALI_PHY_306;
+	volatile u32 DENALI_PHY_307;
+	volatile u32 DENALI_PHY_308;
+	volatile u32 DENALI_PHY_309;
+	volatile u32 DENALI_PHY_310;
+	volatile u32 DENALI_PHY_311;
+	volatile u32 DENALI_PHY_312;
+	volatile u32 DENALI_PHY_313;
+	volatile u32 DENALI_PHY_314;
+	volatile u32 DENALI_PHY_315;
+	volatile u32 DENALI_PHY_316;
+	volatile u32 DENALI_PHY_317;
+	volatile u32 DENALI_PHY_318;
+	volatile u32 DENALI_PHY_319;
+	volatile u32 DENALI_PHY_320;
+	volatile u32 DENALI_PHY_321;
+	volatile u32 DENALI_PHY_322;
+	volatile u32 DENALI_PHY_323;
+	volatile u32 DENALI_PHY_324;
+	volatile u32 DENALI_PHY_325;
+	volatile u32 DENALI_PHY_326;
+	volatile u32 DENALI_PHY_327;
+	volatile u32 DENALI_PHY_328;
+	volatile u32 DENALI_PHY_329;
+	volatile u32 DENALI_PHY_330;
+	volatile u32 DENALI_PHY_331;
+	volatile u32 DENALI_PHY_332;
+	volatile u32 DENALI_PHY_333;
+	volatile u32 DENALI_PHY_334;
+	volatile u32 DENALI_PHY_335;
+	volatile u32 DENALI_PHY_336;
+	volatile u32 DENALI_PHY_337;
+	volatile u32 DENALI_PHY_338;
+	volatile u32 DENALI_PHY_339;
+	volatile u32 DENALI_PHY_340;
+	volatile u32 DENALI_PHY_341;
+	volatile u32 DENALI_PHY_342;
+	volatile u32 DENALI_PHY_343;
+	volatile u32 DENALI_PHY_344;
+	volatile u32 DENALI_PHY_345;
+	volatile u32 DENALI_PHY_346;
+	volatile u32 DENALI_PHY_347;
+	volatile u32 DENALI_PHY_348;
+	volatile u32 DENALI_PHY_349;
+	volatile u32 DENALI_PHY_350;
+	volatile u32 DENALI_PHY_351;
+	volatile u32 DENALI_PHY_352;
+	volatile u32 DENALI_PHY_353;
+	volatile u32 DENALI_PHY_354;
+	volatile u32 DENALI_PHY_355;
+	volatile u32 DENALI_PHY_356;
+	volatile u32 DENALI_PHY_357;
+	volatile u32 DENALI_PHY_358;
+	volatile u32 DENALI_PHY_359;
+	volatile u32 DENALI_PHY_360;
+	volatile u32 DENALI_PHY_361;
+	volatile u32 DENALI_PHY_362;
+	volatile u32 DENALI_PHY_363;
+	volatile u32 DENALI_PHY_364;
+	volatile u32 DENALI_PHY_365;
+	volatile u32 DENALI_PHY_366;
+	volatile u32 DENALI_PHY_367;
+	volatile u32 DENALI_PHY_368;
+	volatile u32 DENALI_PHY_369;
+	volatile u32 DENALI_PHY_370;
+	volatile u32 DENALI_PHY_371;
+	volatile u32 DENALI_PHY_372;
+	volatile u32 DENALI_PHY_373;
+	volatile u32 DENALI_PHY_374;
+	volatile u32 DENALI_PHY_375;
+	volatile u32 DENALI_PHY_376;
+	volatile u32 DENALI_PHY_377;
+	volatile u32 DENALI_PHY_378;
+	volatile u32 DENALI_PHY_379;
+	volatile u32 DENALI_PHY_380;
+	volatile u32 DENALI_PHY_381;
+	volatile u32 DENALI_PHY_382;
+	volatile u32 DENALI_PHY_383;
+	volatile u32 DENALI_PHY_384;
+	volatile u32 DENALI_PHY_385;
+	volatile u32 DENALI_PHY_386;
+	volatile u32 DENALI_PHY_387;
+	volatile u32 DENALI_PHY_388;
+	volatile u32 DENALI_PHY_389;
+	volatile u32 DENALI_PHY_390;
+	volatile u32 DENALI_PHY_391;
+	volatile u32 DENALI_PHY_392;
+	volatile u32 DENALI_PHY_393;
+	volatile u32 DENALI_PHY_394;
+	volatile u32 DENALI_PHY_395;
+	volatile char pad__3[0x1D0U];
+	volatile u32 DENALI_PHY_512;
+	volatile u32 DENALI_PHY_513;
+	volatile u32 DENALI_PHY_514;
+	volatile u32 DENALI_PHY_515;
+	volatile u32 DENALI_PHY_516;
+	volatile u32 DENALI_PHY_517;
+	volatile u32 DENALI_PHY_518;
+	volatile u32 DENALI_PHY_519;
+	volatile u32 DENALI_PHY_520;
+	volatile u32 DENALI_PHY_521;
+	volatile u32 DENALI_PHY_522;
+	volatile u32 DENALI_PHY_523;
+	volatile u32 DENALI_PHY_524;
+	volatile u32 DENALI_PHY_525;
+	volatile u32 DENALI_PHY_526;
+	volatile u32 DENALI_PHY_527;
+	volatile u32 DENALI_PHY_528;
+	volatile u32 DENALI_PHY_529;
+	volatile u32 DENALI_PHY_530;
+	volatile u32 DENALI_PHY_531;
+	volatile u32 DENALI_PHY_532;
+	volatile u32 DENALI_PHY_533;
+	volatile u32 DENALI_PHY_534;
+	volatile u32 DENALI_PHY_535;
+	volatile u32 DENALI_PHY_536;
+	volatile u32 DENALI_PHY_537;
+	volatile u32 DENALI_PHY_538;
+	volatile u32 DENALI_PHY_539;
+	volatile u32 DENALI_PHY_540;
+	volatile u32 DENALI_PHY_541;
+	volatile u32 DENALI_PHY_542;
+	volatile u32 DENALI_PHY_543;
+	volatile u32 DENALI_PHY_544;
+	volatile u32 DENALI_PHY_545;
+	volatile u32 DENALI_PHY_546;
+	volatile u32 DENALI_PHY_547;
+	volatile u32 DENALI_PHY_548;
+	volatile u32 DENALI_PHY_549;
+	volatile u32 DENALI_PHY_550;
+	volatile u32 DENALI_PHY_551;
+	volatile u32 DENALI_PHY_552;
+	volatile u32 DENALI_PHY_553;
+	volatile u32 DENALI_PHY_554;
+	volatile u32 DENALI_PHY_555;
+	volatile u32 DENALI_PHY_556;
+	volatile u32 DENALI_PHY_557;
+	volatile u32 DENALI_PHY_558;
+	volatile u32 DENALI_PHY_559;
+	volatile u32 DENALI_PHY_560;
+	volatile u32 DENALI_PHY_561;
+	volatile u32 DENALI_PHY_562;
+	volatile u32 DENALI_PHY_563;
+	volatile u32 DENALI_PHY_564;
+	volatile u32 DENALI_PHY_565;
+	volatile u32 DENALI_PHY_566;
+	volatile u32 DENALI_PHY_567;
+	volatile u32 DENALI_PHY_568;
+	volatile u32 DENALI_PHY_569;
+	volatile u32 DENALI_PHY_570;
+	volatile u32 DENALI_PHY_571;
+	volatile u32 DENALI_PHY_572;
+	volatile u32 DENALI_PHY_573;
+	volatile u32 DENALI_PHY_574;
+	volatile u32 DENALI_PHY_575;
+	volatile u32 DENALI_PHY_576;
+	volatile u32 DENALI_PHY_577;
+	volatile u32 DENALI_PHY_578;
+	volatile u32 DENALI_PHY_579;
+	volatile u32 DENALI_PHY_580;
+	volatile u32 DENALI_PHY_581;
+	volatile u32 DENALI_PHY_582;
+	volatile u32 DENALI_PHY_583;
+	volatile u32 DENALI_PHY_584;
+	volatile u32 DENALI_PHY_585;
+	volatile u32 DENALI_PHY_586;
+	volatile u32 DENALI_PHY_587;
+	volatile u32 DENALI_PHY_588;
+	volatile u32 DENALI_PHY_589;
+	volatile u32 DENALI_PHY_590;
+	volatile u32 DENALI_PHY_591;
+	volatile u32 DENALI_PHY_592;
+	volatile u32 DENALI_PHY_593;
+	volatile u32 DENALI_PHY_594;
+	volatile u32 DENALI_PHY_595;
+	volatile u32 DENALI_PHY_596;
+	volatile u32 DENALI_PHY_597;
+	volatile u32 DENALI_PHY_598;
+	volatile u32 DENALI_PHY_599;
+	volatile u32 DENALI_PHY_600;
+	volatile u32 DENALI_PHY_601;
+	volatile u32 DENALI_PHY_602;
+	volatile u32 DENALI_PHY_603;
+	volatile u32 DENALI_PHY_604;
+	volatile u32 DENALI_PHY_605;
+	volatile u32 DENALI_PHY_606;
+	volatile u32 DENALI_PHY_607;
+	volatile u32 DENALI_PHY_608;
+	volatile u32 DENALI_PHY_609;
+	volatile u32 DENALI_PHY_610;
+	volatile u32 DENALI_PHY_611;
+	volatile u32 DENALI_PHY_612;
+	volatile u32 DENALI_PHY_613;
+	volatile u32 DENALI_PHY_614;
+	volatile u32 DENALI_PHY_615;
+	volatile u32 DENALI_PHY_616;
+	volatile u32 DENALI_PHY_617;
+	volatile u32 DENALI_PHY_618;
+	volatile u32 DENALI_PHY_619;
+	volatile u32 DENALI_PHY_620;
+	volatile u32 DENALI_PHY_621;
+	volatile u32 DENALI_PHY_622;
+	volatile u32 DENALI_PHY_623;
+	volatile u32 DENALI_PHY_624;
+	volatile u32 DENALI_PHY_625;
+	volatile u32 DENALI_PHY_626;
+	volatile u32 DENALI_PHY_627;
+	volatile u32 DENALI_PHY_628;
+	volatile u32 DENALI_PHY_629;
+	volatile u32 DENALI_PHY_630;
+	volatile u32 DENALI_PHY_631;
+	volatile u32 DENALI_PHY_632;
+	volatile u32 DENALI_PHY_633;
+	volatile u32 DENALI_PHY_634;
+	volatile u32 DENALI_PHY_635;
+	volatile u32 DENALI_PHY_636;
+	volatile u32 DENALI_PHY_637;
+	volatile u32 DENALI_PHY_638;
+	volatile u32 DENALI_PHY_639;
+	volatile u32 DENALI_PHY_640;
+	volatile u32 DENALI_PHY_641;
+	volatile u32 DENALI_PHY_642;
+	volatile u32 DENALI_PHY_643;
+	volatile u32 DENALI_PHY_644;
+	volatile u32 DENALI_PHY_645;
+	volatile u32 DENALI_PHY_646;
+	volatile u32 DENALI_PHY_647;
+	volatile u32 DENALI_PHY_648;
+	volatile u32 DENALI_PHY_649;
+	volatile u32 DENALI_PHY_650;
+	volatile u32 DENALI_PHY_651;
+	volatile char pad__4[0x1D0U];
+	volatile u32 DENALI_PHY_768;
+	volatile u32 DENALI_PHY_769;
+	volatile u32 DENALI_PHY_770;
+	volatile u32 DENALI_PHY_771;
+	volatile u32 DENALI_PHY_772;
+	volatile u32 DENALI_PHY_773;
+	volatile u32 DENALI_PHY_774;
+	volatile u32 DENALI_PHY_775;
+	volatile u32 DENALI_PHY_776;
+	volatile u32 DENALI_PHY_777;
+	volatile u32 DENALI_PHY_778;
+	volatile u32 DENALI_PHY_779;
+	volatile u32 DENALI_PHY_780;
+	volatile u32 DENALI_PHY_781;
+	volatile u32 DENALI_PHY_782;
+	volatile u32 DENALI_PHY_783;
+	volatile u32 DENALI_PHY_784;
+	volatile u32 DENALI_PHY_785;
+	volatile u32 DENALI_PHY_786;
+	volatile u32 DENALI_PHY_787;
+	volatile u32 DENALI_PHY_788;
+	volatile u32 DENALI_PHY_789;
+	volatile u32 DENALI_PHY_790;
+	volatile u32 DENALI_PHY_791;
+	volatile u32 DENALI_PHY_792;
+	volatile u32 DENALI_PHY_793;
+	volatile u32 DENALI_PHY_794;
+	volatile u32 DENALI_PHY_795;
+	volatile u32 DENALI_PHY_796;
+	volatile u32 DENALI_PHY_797;
+	volatile u32 DENALI_PHY_798;
+	volatile u32 DENALI_PHY_799;
+	volatile u32 DENALI_PHY_800;
+	volatile u32 DENALI_PHY_801;
+	volatile u32 DENALI_PHY_802;
+	volatile u32 DENALI_PHY_803;
+	volatile u32 DENALI_PHY_804;
+	volatile u32 DENALI_PHY_805;
+	volatile u32 DENALI_PHY_806;
+	volatile u32 DENALI_PHY_807;
+	volatile u32 DENALI_PHY_808;
+	volatile u32 DENALI_PHY_809;
+	volatile u32 DENALI_PHY_810;
+	volatile u32 DENALI_PHY_811;
+	volatile u32 DENALI_PHY_812;
+	volatile u32 DENALI_PHY_813;
+	volatile u32 DENALI_PHY_814;
+	volatile u32 DENALI_PHY_815;
+	volatile u32 DENALI_PHY_816;
+	volatile u32 DENALI_PHY_817;
+	volatile u32 DENALI_PHY_818;
+	volatile u32 DENALI_PHY_819;
+	volatile u32 DENALI_PHY_820;
+	volatile u32 DENALI_PHY_821;
+	volatile u32 DENALI_PHY_822;
+	volatile u32 DENALI_PHY_823;
+	volatile u32 DENALI_PHY_824;
+	volatile u32 DENALI_PHY_825;
+	volatile u32 DENALI_PHY_826;
+	volatile u32 DENALI_PHY_827;
+	volatile u32 DENALI_PHY_828;
+	volatile u32 DENALI_PHY_829;
+	volatile u32 DENALI_PHY_830;
+	volatile u32 DENALI_PHY_831;
+	volatile u32 DENALI_PHY_832;
+	volatile u32 DENALI_PHY_833;
+	volatile u32 DENALI_PHY_834;
+	volatile u32 DENALI_PHY_835;
+	volatile u32 DENALI_PHY_836;
+	volatile u32 DENALI_PHY_837;
+	volatile u32 DENALI_PHY_838;
+	volatile u32 DENALI_PHY_839;
+	volatile u32 DENALI_PHY_840;
+	volatile u32 DENALI_PHY_841;
+	volatile u32 DENALI_PHY_842;
+	volatile u32 DENALI_PHY_843;
+	volatile u32 DENALI_PHY_844;
+	volatile u32 DENALI_PHY_845;
+	volatile u32 DENALI_PHY_846;
+	volatile u32 DENALI_PHY_847;
+	volatile u32 DENALI_PHY_848;
+	volatile u32 DENALI_PHY_849;
+	volatile u32 DENALI_PHY_850;
+	volatile u32 DENALI_PHY_851;
+	volatile u32 DENALI_PHY_852;
+	volatile u32 DENALI_PHY_853;
+	volatile u32 DENALI_PHY_854;
+	volatile u32 DENALI_PHY_855;
+	volatile u32 DENALI_PHY_856;
+	volatile u32 DENALI_PHY_857;
+	volatile u32 DENALI_PHY_858;
+	volatile u32 DENALI_PHY_859;
+	volatile u32 DENALI_PHY_860;
+	volatile u32 DENALI_PHY_861;
+	volatile u32 DENALI_PHY_862;
+	volatile u32 DENALI_PHY_863;
+	volatile u32 DENALI_PHY_864;
+	volatile u32 DENALI_PHY_865;
+	volatile u32 DENALI_PHY_866;
+	volatile u32 DENALI_PHY_867;
+	volatile u32 DENALI_PHY_868;
+	volatile u32 DENALI_PHY_869;
+	volatile u32 DENALI_PHY_870;
+	volatile u32 DENALI_PHY_871;
+	volatile u32 DENALI_PHY_872;
+	volatile u32 DENALI_PHY_873;
+	volatile u32 DENALI_PHY_874;
+	volatile u32 DENALI_PHY_875;
+	volatile u32 DENALI_PHY_876;
+	volatile u32 DENALI_PHY_877;
+	volatile u32 DENALI_PHY_878;
+	volatile u32 DENALI_PHY_879;
+	volatile u32 DENALI_PHY_880;
+	volatile u32 DENALI_PHY_881;
+	volatile u32 DENALI_PHY_882;
+	volatile u32 DENALI_PHY_883;
+	volatile u32 DENALI_PHY_884;
+	volatile u32 DENALI_PHY_885;
+	volatile u32 DENALI_PHY_886;
+	volatile u32 DENALI_PHY_887;
+	volatile u32 DENALI_PHY_888;
+	volatile u32 DENALI_PHY_889;
+	volatile u32 DENALI_PHY_890;
+	volatile u32 DENALI_PHY_891;
+	volatile u32 DENALI_PHY_892;
+	volatile u32 DENALI_PHY_893;
+	volatile u32 DENALI_PHY_894;
+	volatile u32 DENALI_PHY_895;
+	volatile u32 DENALI_PHY_896;
+	volatile u32 DENALI_PHY_897;
+	volatile u32 DENALI_PHY_898;
+	volatile u32 DENALI_PHY_899;
+	volatile u32 DENALI_PHY_900;
+	volatile u32 DENALI_PHY_901;
+	volatile u32 DENALI_PHY_902;
+	volatile u32 DENALI_PHY_903;
+	volatile u32 DENALI_PHY_904;
+	volatile u32 DENALI_PHY_905;
+	volatile u32 DENALI_PHY_906;
+	volatile u32 DENALI_PHY_907;
+	volatile char pad__5[0x1D0U];
+	volatile u32 DENALI_PHY_1024;
+	volatile u32 DENALI_PHY_1025;
+	volatile u32 DENALI_PHY_1026;
+	volatile u32 DENALI_PHY_1027;
+	volatile u32 DENALI_PHY_1028;
+	volatile u32 DENALI_PHY_1029;
+	volatile u32 DENALI_PHY_1030;
+	volatile u32 DENALI_PHY_1031;
+	volatile u32 DENALI_PHY_1032;
+	volatile u32 DENALI_PHY_1033;
+	volatile u32 DENALI_PHY_1034;
+	volatile u32 DENALI_PHY_1035;
+	volatile u32 DENALI_PHY_1036;
+	volatile u32 DENALI_PHY_1037;
+	volatile u32 DENALI_PHY_1038;
+	volatile u32 DENALI_PHY_1039;
+	volatile u32 DENALI_PHY_1040;
+	volatile u32 DENALI_PHY_1041;
+	volatile u32 DENALI_PHY_1042;
+	volatile u32 DENALI_PHY_1043;
+	volatile u32 DENALI_PHY_1044;
+	volatile u32 DENALI_PHY_1045;
+	volatile u32 DENALI_PHY_1046;
+	volatile u32 DENALI_PHY_1047;
+	volatile u32 DENALI_PHY_1048;
+	volatile u32 DENALI_PHY_1049;
+	volatile u32 DENALI_PHY_1050;
+	volatile u32 DENALI_PHY_1051;
+	volatile u32 DENALI_PHY_1052;
+	volatile u32 DENALI_PHY_1053;
+	volatile u32 DENALI_PHY_1054;
+	volatile u32 DENALI_PHY_1055;
+	volatile u32 DENALI_PHY_1056;
+	volatile u32 DENALI_PHY_1057;
+	volatile u32 DENALI_PHY_1058;
+	volatile u32 DENALI_PHY_1059;
+	volatile u32 DENALI_PHY_1060;
+	volatile u32 DENALI_PHY_1061;
+	volatile u32 DENALI_PHY_1062;
+	volatile u32 DENALI_PHY_1063;
+	volatile u32 DENALI_PHY_1064;
+	volatile u32 DENALI_PHY_1065;
+	volatile u32 DENALI_PHY_1066;
+	volatile u32 DENALI_PHY_1067;
+	volatile u32 DENALI_PHY_1068;
+	volatile u32 DENALI_PHY_1069;
+	volatile u32 DENALI_PHY_1070;
+	volatile u32 DENALI_PHY_1071;
+	volatile u32 DENALI_PHY_1072;
+	volatile u32 DENALI_PHY_1073;
+	volatile u32 DENALI_PHY_1074;
+	volatile u32 DENALI_PHY_1075;
+	volatile char pad__6[0x330U];
+	volatile u32 DENALI_PHY_1280;
+	volatile u32 DENALI_PHY_1281;
+	volatile u32 DENALI_PHY_1282;
+	volatile u32 DENALI_PHY_1283;
+	volatile u32 DENALI_PHY_1284;
+	volatile u32 DENALI_PHY_1285;
+	volatile u32 DENALI_PHY_1286;
+	volatile u32 DENALI_PHY_1287;
+	volatile u32 DENALI_PHY_1288;
+	volatile u32 DENALI_PHY_1289;
+	volatile u32 DENALI_PHY_1290;
+	volatile u32 DENALI_PHY_1291;
+	volatile u32 DENALI_PHY_1292;
+	volatile u32 DENALI_PHY_1293;
+	volatile u32 DENALI_PHY_1294;
+	volatile u32 DENALI_PHY_1295;
+	volatile u32 DENALI_PHY_1296;
+	volatile u32 DENALI_PHY_1297;
+	volatile u32 DENALI_PHY_1298;
+	volatile u32 DENALI_PHY_1299;
+	volatile u32 DENALI_PHY_1300;
+	volatile u32 DENALI_PHY_1301;
+	volatile u32 DENALI_PHY_1302;
+	volatile u32 DENALI_PHY_1303;
+	volatile u32 DENALI_PHY_1304;
+	volatile u32 DENALI_PHY_1305;
+	volatile u32 DENALI_PHY_1306;
+	volatile u32 DENALI_PHY_1307;
+	volatile u32 DENALI_PHY_1308;
+	volatile u32 DENALI_PHY_1309;
+	volatile u32 DENALI_PHY_1310;
+	volatile u32 DENALI_PHY_1311;
+	volatile u32 DENALI_PHY_1312;
+	volatile u32 DENALI_PHY_1313;
+	volatile u32 DENALI_PHY_1314;
+	volatile u32 DENALI_PHY_1315;
+	volatile u32 DENALI_PHY_1316;
+	volatile u32 DENALI_PHY_1317;
+	volatile u32 DENALI_PHY_1318;
+	volatile u32 DENALI_PHY_1319;
+	volatile u32 DENALI_PHY_1320;
+	volatile u32 DENALI_PHY_1321;
+	volatile u32 DENALI_PHY_1322;
+	volatile u32 DENALI_PHY_1323;
+	volatile u32 DENALI_PHY_1324;
+	volatile u32 DENALI_PHY_1325;
+	volatile u32 DENALI_PHY_1326;
+	volatile u32 DENALI_PHY_1327;
+	volatile u32 DENALI_PHY_1328;
+	volatile u32 DENALI_PHY_1329;
+	volatile u32 DENALI_PHY_1330;
+	volatile u32 DENALI_PHY_1331;
+	volatile u32 DENALI_PHY_1332;
+	volatile u32 DENALI_PHY_1333;
+	volatile u32 DENALI_PHY_1334;
+	volatile u32 DENALI_PHY_1335;
+	volatile u32 DENALI_PHY_1336;
+	volatile u32 DENALI_PHY_1337;
+	volatile u32 DENALI_PHY_1338;
+	volatile u32 DENALI_PHY_1339;
+	volatile u32 DENALI_PHY_1340;
+	volatile u32 DENALI_PHY_1341;
+	volatile u32 DENALI_PHY_1342;
+	volatile u32 DENALI_PHY_1343;
+	volatile u32 DENALI_PHY_1344;
+	volatile u32 DENALI_PHY_1345;
+	volatile u32 DENALI_PHY_1346;
+	volatile u32 DENALI_PHY_1347;
+	volatile u32 DENALI_PHY_1348;
+	volatile u32 DENALI_PHY_1349;
+	volatile u32 DENALI_PHY_1350;
+	volatile u32 DENALI_PHY_1351;
+	volatile u32 DENALI_PHY_1352;
+	volatile u32 DENALI_PHY_1353;
+	volatile u32 DENALI_PHY_1354;
+	volatile u32 DENALI_PHY_1355;
+	volatile u32 DENALI_PHY_1356;
+	volatile u32 DENALI_PHY_1357;
+	volatile u32 DENALI_PHY_1358;
+	volatile u32 DENALI_PHY_1359;
+	volatile u32 DENALI_PHY_1360;
+	volatile u32 DENALI_PHY_1361;
+	volatile u32 DENALI_PHY_1362;
+	volatile u32 DENALI_PHY_1363;
+	volatile u32 DENALI_PHY_1364;
+	volatile u32 DENALI_PHY_1365;
+	volatile u32 DENALI_PHY_1366;
+	volatile u32 DENALI_PHY_1367;
+	volatile u32 DENALI_PHY_1368;
+	volatile u32 DENALI_PHY_1369;
+	volatile u32 DENALI_PHY_1370;
+	volatile u32 DENALI_PHY_1371;
+	volatile u32 DENALI_PHY_1372;
+	volatile u32 DENALI_PHY_1373;
+	volatile u32 DENALI_PHY_1374;
+	volatile u32 DENALI_PHY_1375;
+	volatile u32 DENALI_PHY_1376;
+	volatile u32 DENALI_PHY_1377;
+	volatile u32 DENALI_PHY_1378;
+	volatile u32 DENALI_PHY_1379;
+	volatile u32 DENALI_PHY_1380;
+	volatile u32 DENALI_PHY_1381;
+	volatile u32 DENALI_PHY_1382;
+	volatile u32 DENALI_PHY_1383;
+	volatile u32 DENALI_PHY_1384;
+	volatile u32 DENALI_PHY_1385;
+	volatile u32 DENALI_PHY_1386;
+	volatile u32 DENALI_PHY_1387;
+	volatile u32 DENALI_PHY_1388;
+	volatile u32 DENALI_PHY_1389;
+	volatile u32 DENALI_PHY_1390;
+	volatile u32 DENALI_PHY_1391;
+	volatile u32 DENALI_PHY_1392;
+	volatile u32 DENALI_PHY_1393;
+	volatile u32 DENALI_PHY_1394;
+	volatile u32 DENALI_PHY_1395;
+	volatile u32 DENALI_PHY_1396;
+	volatile u32 DENALI_PHY_1397;
+	volatile u32 DENALI_PHY_1398;
+	volatile u32 DENALI_PHY_1399;
+	volatile u32 DENALI_PHY_1400;
+	volatile u32 DENALI_PHY_1401;
+	volatile u32 DENALI_PHY_1402;
+	volatile u32 DENALI_PHY_1403;
+	volatile u32 DENALI_PHY_1404;
+	volatile u32 DENALI_PHY_1405;
+	volatile u32 DENALI_PHY_1406;
+	volatile u32 DENALI_PHY_1407;
+	volatile u32 DENALI_PHY_1408;
+	volatile u32 DENALI_PHY_1409;
+	volatile u32 DENALI_PHY_1410;
+	volatile u32 DENALI_PHY_1411;
+	volatile u32 DENALI_PHY_1412;
+	volatile u32 DENALI_PHY_1413;
+	volatile u32 DENALI_PHY_1414;
+	volatile u32 DENALI_PHY_1415;
+	volatile u32 DENALI_PHY_1416;
+	volatile u32 DENALI_PHY_1417;
+	volatile u32 DENALI_PHY_1418;
+	volatile u32 DENALI_PHY_1419;
+	volatile u32 DENALI_PHY_1420;
+	volatile u32 DENALI_PHY_1421;
+	volatile u32 DENALI_PHY_1422;
+} lpddr4_ctlregs;
+
+#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
new file mode 100644
index 0000000000..71122946b4
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_RW_MASKS_H_
+#define LPDDR4_RW_MASKS_H_
+
+#include <stdint.h>
+
+extern u32 g_lpddr4_ddr_controller_rw_mask[459];
+extern u32 g_lpddr4_pi_rw_mask[300];
+extern u32 g_lpddr4_data_slice_0_rw_mask[140];
+extern u32 g_lpddr4_data_slice_1_rw_mask[140];
+extern u32 g_lpddr4_data_slice_2_rw_mask[140];
+extern u32 g_lpddr4_data_slice_3_rw_mask[140];
+extern u32 g_lpddr4_address_slice_0_rw_mask[52];
+extern u32 g_lpddr4_phy_core_rw_mask[143];
+
+#endif /* LPDDR4_RW_MASKS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
index 3208b1cf9d..ad45dd98d7 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
@@ -1,17 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
  *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
 #define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
 
-#define LPDDR4__DENALI_PHY_0_READ_MASK				               0x000F07FFU
-#define LPDDR4__DENALI_PHY_0_WRITE_MASK				              0x000F07FFU
+#define LPDDR4__DENALI_PHY_0_READ_MASK                               0x000F07FFU
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK                              0x000F07FFU
 #define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK   0x000007FFU
 #define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH          11U
@@ -24,8 +23,8 @@
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_0
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
 
-#define LPDDR4__DENALI_PHY_1_READ_MASK				               0x000703FFU
-#define LPDDR4__DENALI_PHY_1_WRITE_MASK				              0x000703FFU
+#define LPDDR4__DENALI_PHY_1_READ_MASK                               0x000703FFU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK                              0x000703FFU
 #define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH       10U
@@ -38,8 +37,8 @@
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
 
-#define LPDDR4__DENALI_PHY_2_READ_MASK				               0x010303FFU
-#define LPDDR4__DENALI_PHY_2_WRITE_MASK				              0x010303FFU
+#define LPDDR4__DENALI_PHY_2_READ_MASK                               0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK                              0x010303FFU
 #define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT       0U
 #define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH      10U
@@ -53,82 +52,82 @@
 #define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
 
 #define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK         0x01000000U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT				24U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET				 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET                 0U
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
 
-#define LPDDR4__DENALI_PHY_3_READ_MASK				               0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_3_WRITE_MASK				              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK                              0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK              0x0000003FU
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK              0x00003F00U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK              0x003F0000U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK              0x3F000000U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_4_READ_MASK				               0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_4_WRITE_MASK				              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK                              0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK              0x0000003FU
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK              0x00003F00U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK              0x003F0000U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK              0x3F000000U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH				      6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH                      6U
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_5_READ_MASK				               0x01030F3FU
-#define LPDDR4__DENALI_PHY_5_WRITE_MASK				              0x01030F3FU
+#define LPDDR4__DENALI_PHY_5_READ_MASK                               0x01030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK                              0x01030F3FU
 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK               0x0000003FU
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH				       6U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH                       6U
 #define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
 #define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK              0x00000F00U
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH				      4U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH                      4U
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK             0x00030000U
-#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH                     2U
 #define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5
 #define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0
 
@@ -140,8 +139,8 @@
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0
 
-#define LPDDR4__DENALI_PHY_6_READ_MASK				               0x1F1F0301U
-#define LPDDR4__DENALI_PHY_6_WRITE_MASK				              0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6_READ_MASK                               0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK                              0x1F1F0301U
 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK       0x00000001U
 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH               1U
@@ -168,11 +167,11 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
 
-#define LPDDR4__DENALI_PHY_7_READ_MASK				               0x1F030F0FU
-#define LPDDR4__DENALI_PHY_7_WRITE_MASK				              0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7_READ_MASK                               0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK                              0x1F030F0FU
 #define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK        0x0000000FU
-#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT				0U
-#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH				4U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH                4U
 #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7
 #define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0
 
@@ -194,55 +193,55 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
 
-#define LPDDR4__DENALI_PHY_8_READ_MASK				               0x0101FF03U
-#define LPDDR4__DENALI_PHY_8_WRITE_MASK				              0x0101FF03U
-#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK				0x00000003U
-#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH				        2U
+#define LPDDR4__DENALI_PHY_8_READ_MASK                               0x0101FF03U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK                              0x0101FF03U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK                0x00000003U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH                        2U
 #define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8
 #define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0
 
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK				0x0001FF00U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT				        8U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK                0x0001FF00U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH                        9U
 #define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8
 #define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0
 
 #define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK         0x01000000U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT				24U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET				 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET                 0U
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
 
-#define LPDDR4__DENALI_PHY_9_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_9_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK                              0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK  0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH         32U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0
 
-#define LPDDR4__DENALI_PHY_10_READ_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_10_WRITE_MASK				             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK                             0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK     0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH            28U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0
 
-#define LPDDR4__DENALI_PHY_11_READ_MASK				              0x0101FF7FU
-#define LPDDR4__DENALI_PHY_11_WRITE_MASK				             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_11_READ_MASK                              0x0101FF7FU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK                             0x0101FF7FU
 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK         0x0000007FU
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH				 7U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH                 7U
 #define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11
 #define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0
 
 #define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_MASK          0x0001FF00U
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH				  9U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH                  9U
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_11
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0
 
@@ -254,8 +253,8 @@
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_11
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0
 
-#define LPDDR4__DENALI_PHY_12_READ_MASK				              0x007F3F01U
-#define LPDDR4__DENALI_PHY_12_WRITE_MASK				             0x007F3F01U
+#define LPDDR4__DENALI_PHY_12_READ_MASK                              0x007F3F01U
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK                             0x007F3F01U
 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT       0U
 #define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH       1U
@@ -271,13 +270,13 @@
 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0
 
 #define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_MASK             0x007F0000U
-#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH				     7U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH                     7U
 #define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_12
 #define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0
 
-#define LPDDR4__DENALI_PHY_13_READ_MASK				              0x000F03FFU
-#define LPDDR4__DENALI_PHY_13_WRITE_MASK				             0x000F03FFU
+#define LPDDR4__DENALI_PHY_13_READ_MASK                              0x000F03FFU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK                             0x000F03FFU
 #define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH       10U
@@ -291,37 +290,37 @@
 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0
 
 #define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET				   0U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET                   0U
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_13
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0
 
-#define LPDDR4__DENALI_PHY_14_READ_MASK				              0x070101FFU
-#define LPDDR4__DENALI_PHY_14_WRITE_MASK				             0x070101FFU
+#define LPDDR4__DENALI_PHY_14_READ_MASK                              0x070101FFU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK                             0x070101FFU
 #define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK     0x000001FFU
 #define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH             9U
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK				      0x00010000U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT				             16U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH				              1U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR				              0U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET				              0U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK                      0x00010000U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT                             16U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH                              1U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR                              0U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET                              0U
 #define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_14
 #define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_14__PHY_LPDDR_0
 
-#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK				  0x07000000U
-#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT				         24U
-#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH				          3U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK                  0x07000000U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH                          3U
 #define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_14
 #define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0
 
-#define LPDDR4__DENALI_PHY_15_READ_MASK				              0x000301FFU
-#define LPDDR4__DENALI_PHY_15_WRITE_MASK				             0x000301FFU
+#define LPDDR4__DENALI_PHY_15_READ_MASK                              0x000301FFU
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK                             0x000301FFU
 #define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK     0x000001FFU
 #define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH             9U
@@ -329,101 +328,101 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_MASK          0x00030000U
-#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH                  2U
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_15
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0
 
-#define LPDDR4__DENALI_PHY_16_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_16_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_16_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH				 32U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH                 32U
 #define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_16
 #define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0
 
-#define LPDDR4__DENALI_PHY_17_READ_MASK				              0x00000301U
-#define LPDDR4__DENALI_PHY_17_WRITE_MASK				             0x00000301U
+#define LPDDR4__DENALI_PHY_17_READ_MASK                              0x00000301U
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK                             0x00000301U
 #define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_MASK             0x00000001U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH				     1U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR				     0U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET				     0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET                     0U
 #define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_17
 #define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0
 
 #define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_MASK              0x00000300U
-#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH				      2U
+#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH                      2U
 #define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_17
 #define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0
 
-#define LPDDR4__DENALI_PHY_18_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_18_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_18_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH                       32U
 #define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_18
 #define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0
 
-#define LPDDR4__DENALI_PHY_19_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_19_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_19_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH                       32U
 #define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_19
 #define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0
 
-#define LPDDR4__DENALI_PHY_20_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_20_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_20
 #define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0
 
-#define LPDDR4__DENALI_PHY_21_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_21_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_21
 #define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0
 
-#define LPDDR4__DENALI_PHY_22_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_22_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_22
 #define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0
 
-#define LPDDR4__DENALI_PHY_23_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_23_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_23
 #define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0
 
-#define LPDDR4__DENALI_PHY_24_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_24_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_24
 #define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0
 
-#define LPDDR4__DENALI_PHY_25_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_25_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_25
 #define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0
 
-#define LPDDR4__DENALI_PHY_26_READ_MASK				              0x070F0107U
-#define LPDDR4__DENALI_PHY_26_WRITE_MASK				             0x070F0107U
+#define LPDDR4__DENALI_PHY_26_READ_MASK                              0x070F0107U
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK                             0x070F0107U
 #define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK      0x00000007U
 #define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH              3U
@@ -446,12 +445,12 @@
 
 #define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_MASK        0x07000000U
 #define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT               24U
-#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH				3U
+#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH                3U
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_26
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0
 
-#define LPDDR4__DENALI_PHY_27_READ_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_27_WRITE_MASK				             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_27_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK                             0x0F0F0F0FU
 #define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK    0x0000000FU
 #define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH            4U
@@ -459,110 +458,110 @@
 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
 
 #define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_MASK          0x00000F00U
-#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH				  4U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH                  4U
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_27
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0
 
 #define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_MASK        0x000F0000U
 #define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT               16U
-#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH				4U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH                4U
 #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_27
 #define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0
 
 #define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_MASK        0x0F000000U
 #define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT               24U
-#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH				4U
+#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH                4U
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_27
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0
 
-#define LPDDR4__DENALI_PHY_28_READ_MASK				              0xFF030001U
-#define LPDDR4__DENALI_PHY_28_WRITE_MASK				             0xFF030001U
+#define LPDDR4__DENALI_PHY_28_READ_MASK                              0xFF030001U
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK                             0xFF030001U
 #define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_MASK             0x00000001U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH				     1U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR				     0U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET				     0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET                     0U
 #define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_28
 #define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0
 
 #define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_MASK          0x00000100U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET				  0U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET                  0U
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_28
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0
 
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK				 0x00030000U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT				        16U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH				         2U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK                 0x00030000U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH                         2U
 #define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_28
 #define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0
 
 #define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_MASK            0xFF000000U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH                    8U
 #define LPDDR4__PHY_WRLVL_PER_START_0__REG DENALI_PHY_28
 #define LPDDR4__PHY_WRLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0
 
-#define LPDDR4__DENALI_PHY_29_READ_MASK				              0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_29_WRITE_MASK				             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_29_READ_MASK                              0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK                             0x00FF0F3FU
 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK          0x0000003FU
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH                  6U
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0
 
 #define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK        0x00000F00U
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT				8U
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH				4U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH                4U
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_29
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0
 
-#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK				    0x00FF0000U
-#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT				           16U
-#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH				            8U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT                           16U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH                            8U
 #define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_29
 #define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0
 
-#define LPDDR4__DENALI_PHY_30_READ_MASK				              0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_30_WRITE_MASK				             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_30_READ_MASK                              0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK                             0x0F3F03FFU
 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_MASK            0x000003FFU
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH                   10U
 #define LPDDR4__PHY_GTLVL_PER_START_0__REG DENALI_PHY_30
 #define LPDDR4__PHY_GTLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0
 
 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK          0x003F0000U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH                  6U
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0
 
 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK        0x0F000000U
 #define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT               24U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH				4U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH                4U
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0
 
-#define LPDDR4__DENALI_PHY_31_READ_MASK				              0x1F030F3FU
-#define LPDDR4__DENALI_PHY_31_WRITE_MASK				             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_READ_MASK                              0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK                             0x1F030F3FU
 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK          0x0000003FU
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH                  6U
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0
 
 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK        0x00000F00U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT				8U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH				4U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH                4U
 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0
 
 #define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK              0x00030000U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH				      2U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH                      2U
 #define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31
 #define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0
 
@@ -572,8 +571,8 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
 
-#define LPDDR4__DENALI_PHY_32_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_32_WRITE_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_32_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK                             0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_MASK  0x000000FFU
 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_WIDTH          8U
@@ -581,8 +580,8 @@
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0
 
 #define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK            0x0000FF00U
-#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH                    8U
 #define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32
 #define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0
 
@@ -593,16 +592,16 @@
 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
 
 #define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_MASK           0x3F000000U
-#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH				   6U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH                   6U
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_32
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0
 
-#define LPDDR4__DENALI_PHY_33_READ_MASK				              0x0F07FF07U
-#define LPDDR4__DENALI_PHY_33_WRITE_MASK				             0x0F07FF07U
-#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK				0x00000007U
-#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH				        3U
+#define LPDDR4__DENALI_PHY_33_READ_MASK                              0x0F07FF07U
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK                             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK                0x00000007U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH                        3U
 #define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33
 #define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0
 
@@ -618,8 +617,8 @@
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_33
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0
 
-#define LPDDR4__DENALI_PHY_34_READ_MASK				              0x0000FF0FU
-#define LPDDR4__DENALI_PHY_34_WRITE_MASK				             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_34_READ_MASK                              0x0000FF0FU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK                             0x0000FF0FU
 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK     0x0000000FU
 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH             4U
@@ -640,66 +639,66 @@
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_34
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
 
-#define LPDDR4__DENALI_PHY_35_READ_MASK				              0x000001FFU
-#define LPDDR4__DENALI_PHY_35_WRITE_MASK				             0x000001FFU
+#define LPDDR4__DENALI_PHY_35_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK                             0x000001FFU
 #define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_MASK         0x000001FFU
-#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH				 9U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH                 9U
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_35
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0
 
-#define LPDDR4__DENALI_PHY_36_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_36_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH				        32U
+#define LPDDR4__DENALI_PHY_36_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH                        32U
 #define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_36
 #define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0
 
-#define LPDDR4__DENALI_PHY_37_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_37_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH				        32U
+#define LPDDR4__DENALI_PHY_37_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH                        32U
 #define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_37
 #define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0
 
-#define LPDDR4__DENALI_PHY_38_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_38_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH				        32U
+#define LPDDR4__DENALI_PHY_38_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH                        32U
 #define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_38
 #define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0
 
-#define LPDDR4__DENALI_PHY_39_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_39_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH				        32U
+#define LPDDR4__DENALI_PHY_39_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH                        32U
 #define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_39
 #define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0
 
-#define LPDDR4__DENALI_PHY_40_READ_MASK				              0x0001FFFFU
-#define LPDDR4__DENALI_PHY_40_WRITE_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK				 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH				        16U
+#define LPDDR4__DENALI_PHY_40_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH                        16U
 #define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_40
 #define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0
 
 #define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_MASK             0x00010000U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH				     1U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR				     0U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET				     0U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET                     0U
 #define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_40
 #define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0
 
-#define LPDDR4__DENALI_PHY_41_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_41_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_41_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_MASK        0x000003FFU
-#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT                0U
 #define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_WIDTH               10U
 #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_41
 #define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0
@@ -710,8 +709,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_41
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0
 
-#define LPDDR4__DENALI_PHY_42_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_42_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK   0x000003FFU
 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH          10U
@@ -724,8 +723,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_42
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0
 
-#define LPDDR4__DENALI_PHY_43_READ_MASK				              0x00FF0001U
-#define LPDDR4__DENALI_PHY_43_WRITE_MASK				             0x00FF0001U
+#define LPDDR4__DENALI_PHY_43_READ_MASK                              0x00FF0001U
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK                             0x00FF0001U
 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK   0x00000001U
 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH           1U
@@ -735,27 +734,27 @@
 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0
 
 #define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_MASK            0x00003F00U
-#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH                    6U
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_43
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0
 
 #define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_MASK               0x00FF0000U
-#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH				       8U
+#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH                       8U
 #define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_43
 #define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0
 
-#define LPDDR4__DENALI_PHY_44_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_44_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_44_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH				   32U
+#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH                   32U
 #define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_44
 #define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0
 
-#define LPDDR4__DENALI_PHY_45_READ_MASK				              0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_45_WRITE_MASK				             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_45_READ_MASK                              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK                             0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_MASK       0x0000FFFFU
 #define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH              16U
@@ -768,8 +767,8 @@
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_45
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0
 
-#define LPDDR4__DENALI_PHY_46_READ_MASK				              0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_46_WRITE_MASK				             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_46_READ_MASK                              0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK                             0xFFFF7F7FU
 #define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK       0x0000007FU
 #define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH               7U
@@ -784,7 +783,7 @@
 
 #define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_MASK        0x00FF0000U
 #define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT               16U
-#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH				8U
+#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH                8U
 #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_46
 #define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0
 
@@ -794,8 +793,8 @@
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
 
-#define LPDDR4__DENALI_PHY_47_READ_MASK				              0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_47_WRITE_MASK				             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_47_READ_MASK                              0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK                             0x7F07FFFFU
 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
 #define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
@@ -814,8 +813,8 @@
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
 
-#define LPDDR4__DENALI_PHY_48_READ_MASK				              0x0007FFFFU
-#define LPDDR4__DENALI_PHY_48_WRITE_MASK				             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_48_READ_MASK                              0x0007FFFFU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK                             0x0007FFFFU
 #define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK  0x000000FFU
 #define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH          8U
@@ -829,13 +828,13 @@
 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
 
 #define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_MASK               0x00070000U
-#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH				       3U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH                       3U
 #define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_48
 #define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0
 
-#define LPDDR4__DENALI_PHY_49_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_49_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_49_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK      0x000003FFU
 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH             10U
@@ -848,16 +847,16 @@
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_49
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0
 
-#define LPDDR4__DENALI_PHY_50_READ_MASK				              0x0001FFFFU
-#define LPDDR4__DENALI_PHY_50_WRITE_MASK				             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_50_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK                             0x0001FFFFU
 #define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_MASK           0x0001FFFFU
-#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH				  17U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH                  17U
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_50
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0
 
-#define LPDDR4__DENALI_PHY_51_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_51_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT         0U
 #define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH        10U
@@ -870,11 +869,11 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
 
-#define LPDDR4__DENALI_PHY_52_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_52_WRITE_MASK				             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_52_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK                             0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_MASK            0x0000FFFFU
-#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH				   16U
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH                   16U
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_52
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0
 
@@ -884,24 +883,24 @@
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_52
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0
 
-#define LPDDR4__DENALI_PHY_53_READ_MASK				              0x00003FFFU
-#define LPDDR4__DENALI_PHY_53_WRITE_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_53_READ_MASK                              0x00003FFFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK                             0x00003FFFU
 #define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK      0x00003FFFU
 #define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH             14U
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0
 
-#define LPDDR4__DENALI_PHY_54_READ_MASK				              0x0003FFFFU
-#define LPDDR4__DENALI_PHY_54_WRITE_MASK				             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK                             0x0003FFFFU
 #define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK           0x0003FFFFU
-#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH				  18U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH                  18U
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0
 
-#define LPDDR4__DENALI_PHY_55_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_55_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK  0x000003FFU
 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH         10U
@@ -914,32 +913,32 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
 
-#define LPDDR4__DENALI_PHY_56_READ_MASK				              0x00000003U
-#define LPDDR4__DENALI_PHY_56_WRITE_MASK				             0x00000003U
+#define LPDDR4__DENALI_PHY_56_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK                             0x00000003U
 #define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
 #define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT     0U
 #define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH     2U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
 
-#define LPDDR4__DENALI_PHY_57_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_57_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH				  32U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH                  32U
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0
 
-#define LPDDR4__DENALI_PHY_58_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_58_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_58_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH				32U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH                32U
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__REG DENALI_PHY_58
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0
 
-#define LPDDR4__DENALI_PHY_59_READ_MASK				              0x07FF07FFU
-#define LPDDR4__DENALI_PHY_59_WRITE_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_59_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK                             0x07FF07FFU
 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH            11U
@@ -952,56 +951,56 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_59
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
 
-#define LPDDR4__DENALI_PHY_60_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_60_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH				 32U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH                 32U
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_60
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0
 
-#define LPDDR4__DENALI_PHY_61_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_61_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT				0U
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT                0U
 #define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH               32U
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_61
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0
 
-#define LPDDR4__DENALI_PHY_62_READ_MASK				              0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_62_WRITE_MASK				             0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK				   0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH				          31U
+#define LPDDR4__DENALI_PHY_62_READ_MASK                              0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK                   0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH                          31U
 #define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_62
 #define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0
 
-#define LPDDR4__DENALI_PHY_63_READ_MASK				              0x0000003FU
-#define LPDDR4__DENALI_PHY_63_WRITE_MASK				             0x0000003FU
-#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK				   0x0000003FU
-#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH				           6U
+#define LPDDR4__DENALI_PHY_63_READ_MASK                              0x0000003FU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH                           6U
 #define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_63
 #define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0
 
-#define LPDDR4__DENALI_PHY_64_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_64_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH                      32U
 #define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_64
 #define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0
 
-#define LPDDR4__DENALI_PHY_65_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_65_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK      0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH             32U
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_65
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0
 
-#define LPDDR4__DENALI_PHY_66_READ_MASK				              0x010001FFU
-#define LPDDR4__DENALI_PHY_66_WRITE_MASK				             0x010001FFU
+#define LPDDR4__DENALI_PHY_66_READ_MASK                              0x010001FFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK                             0x010001FFU
 #define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH            8U
@@ -1009,34 +1008,34 @@
 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0
 
 #define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET				 0U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET                 0U
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_66
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0
 
 #define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_MASK            0x00010000U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET				    0U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET                    0U
 #define LPDDR4__SC_PHY_RX_CAL_START_0__REG DENALI_PHY_66
 #define LPDDR4__SC_PHY_RX_CAL_START_0__FLD LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0
 
 #define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_MASK            0x01000000U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET				    0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET                    0U
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_0__REG DENALI_PHY_66
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0
 
-#define LPDDR4__DENALI_PHY_67_READ_MASK				              0x01FF01FFU
-#define LPDDR4__DENALI_PHY_67_WRITE_MASK				             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK                             0x01FF01FFU
 #define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_MASK         0x000000FFU
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH                 8U
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_67
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0
 
@@ -1048,147 +1047,147 @@
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__REG DENALI_PHY_67
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__FLD LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0
 
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK				 0x01FF0000U
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT				        16U
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67
 #define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0
 
-#define LPDDR4__DENALI_PHY_68_READ_MASK				              0x01FF01FFU
-#define LPDDR4__DENALI_PHY_68_WRITE_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK				 0x000001FFU
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_68_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68
 #define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0
 
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK				 0x01FF0000U
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT				        16U
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68
 #define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0
 
-#define LPDDR4__DENALI_PHY_69_READ_MASK				              0x01FF01FFU
-#define LPDDR4__DENALI_PHY_69_WRITE_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK				 0x000001FFU
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_69_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69
 #define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0
 
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK				 0x01FF0000U
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT				        16U
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69
 #define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0
 
-#define LPDDR4__DENALI_PHY_70_READ_MASK				              0x01FF01FFU
-#define LPDDR4__DENALI_PHY_70_WRITE_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK				 0x000001FFU
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_70_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70
 #define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0
 
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK				 0x01FF0000U
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT				        16U
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70
 #define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0
 
-#define LPDDR4__DENALI_PHY_71_READ_MASK				              0x000001FFU
-#define LPDDR4__DENALI_PHY_71_WRITE_MASK				             0x000001FFU
-#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK				 0x000001FFU
-#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_71_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71
 #define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0
 
-#define LPDDR4__DENALI_PHY_72_READ_MASK				              0x0003FFFFU
-#define LPDDR4__DENALI_PHY_72_WRITE_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK				  0x0003FFFFU
-#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH				         18U
+#define LPDDR4__DENALI_PHY_72_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK                  0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH                         18U
 #define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72
 #define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0
 
-#define LPDDR4__DENALI_PHY_73_READ_MASK				              0x01FF01FFU
-#define LPDDR4__DENALI_PHY_73_WRITE_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK				 0x000001FFU
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH				         9U
+#define LPDDR4__DENALI_PHY_73_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH                         9U
 #define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73
 #define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0
 
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73
 #define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0
 
-#define LPDDR4__DENALI_PHY_74_READ_MASK				              0x01FF07FFU
-#define LPDDR4__DENALI_PHY_74_WRITE_MASK				             0x01FF07FFU
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK				 0x000007FFU
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH				        11U
+#define LPDDR4__DENALI_PHY_74_READ_MASK                              0x01FF07FFU
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK                             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK                 0x000007FFU
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH                        11U
 #define LPDDR4__PHY_RX_CAL_OBS_0__REG DENALI_PHY_74
 #define LPDDR4__PHY_RX_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0
 
 #define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_MASK            0x01FF0000U
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH				    9U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH                    9U
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG DENALI_PHY_74
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0
 
-#define LPDDR4__DENALI_PHY_75_READ_MASK				              0x017F7F01U
-#define LPDDR4__DENALI_PHY_75_WRITE_MASK				             0x017F7F01U
+#define LPDDR4__DENALI_PHY_75_READ_MASK                              0x017F7F01U
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK                             0x017F7F01U
 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_MASK             0x00000001U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH				     1U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR				     0U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET				     0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET                     0U
 #define LPDDR4__PHY_RX_CAL_DISABLE_0__REG DENALI_PHY_75
 #define LPDDR4__PHY_RX_CAL_DISABLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0
 
 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_MASK           0x00007F00U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH				   7U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH                   7U
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__REG DENALI_PHY_75
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0
 
 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_MASK         0x007F0000U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT				16U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH				 7U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH                 7U
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__REG DENALI_PHY_75
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0
 
 #define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_MASK            0x01000000U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET				    0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET                    0U
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_0__REG DENALI_PHY_75
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0
 
-#define LPDDR4__DENALI_PHY_76_READ_MASK				              0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_76_WRITE_MASK				             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_76_READ_MASK                              0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK                             0x07FF0FFFU
 #define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_MASK          0x00000FFFU
-#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH				 12U
+#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH                 12U
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__REG DENALI_PHY_76
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__FLD LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0
 
 #define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_MASK             0x07FF0000U
-#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH				    11U
+#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH                    11U
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_76
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0
 
-#define LPDDR4__DENALI_PHY_77_READ_MASK				              0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_77_WRITE_MASK				             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_77_READ_MASK                              0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK                             0x03FFFF1FU
 #define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_MASK         0x0000001FU
-#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH				 5U
+#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH                 5U
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_77
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0
 
@@ -1200,18 +1199,18 @@
 
 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_MASK        0x00FF0000U
 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT               16U
-#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH				8U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH                8U
 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_77
 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0
 
 #define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_MASK             0x03000000U
-#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH                     2U
 #define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_77
 #define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0
 
-#define LPDDR4__DENALI_PHY_78_READ_MASK				              0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_78_WRITE_MASK				             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_78_READ_MASK                              0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK                             0x01FFFF3FU
 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_MASK       0x0000003FU
 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_WIDTH               6U
@@ -1238,8 +1237,8 @@
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_78
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0
 
-#define LPDDR4__DENALI_PHY_79_READ_MASK				              0x07030101U
-#define LPDDR4__DENALI_PHY_79_WRITE_MASK				             0x07030101U
+#define LPDDR4__DENALI_PHY_79_READ_MASK                              0x07030101U
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK                             0x07030101U
 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_MASK       0x00000001U
 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WIDTH               1U
@@ -1249,27 +1248,27 @@
 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0
 
 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_MASK          0x00000100U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET				  0U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET                  0U
 #define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_79
 #define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0
 
 #define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_MASK            0x00030000U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH				    2U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH                    2U
 #define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_79
 #define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0
 
 #define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_MASK              0x07000000U
-#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH				      3U
+#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH                      3U
 #define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_79
 #define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0
 
-#define LPDDR4__DENALI_PHY_80_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_PHY_80_WRITE_MASK				             0x01010101U
+#define LPDDR4__DENALI_PHY_80_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK                             0x01010101U
 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK  0x00000001U
 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH          1U
@@ -1279,10 +1278,10 @@
 #define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
 
 #define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_MASK        0x00000100U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT				8U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH				1U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR				0U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET				0U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH                1U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR                0U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET                0U
 #define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_80
 #define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0
 
@@ -1302,22 +1301,22 @@
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_80
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0
 
-#define LPDDR4__DENALI_PHY_81_READ_MASK				              0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_81_WRITE_MASK				             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_81_READ_MASK                              0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK                             0x3FFF07FFU
 #define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_MASK         0x000007FFU
-#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH				11U
+#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH                11U
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_0__REG DENALI_PHY_81
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_0__FLD LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0
 
 #define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_MASK          0x3FFF0000U
-#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH				 14U
+#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH                 14U
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__REG DENALI_PHY_81
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0
 
-#define LPDDR4__DENALI_PHY_82_READ_MASK				              0x00003FFFU
-#define LPDDR4__DENALI_PHY_82_WRITE_MASK				             0x00003FFFU
+#define LPDDR4__DENALI_PHY_82_READ_MASK                              0x00003FFFU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK                             0x00003FFFU
 #define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_MASK     0x00003FFFU
 #define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_WIDTH            14U
@@ -1330,8 +1329,8 @@
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_82
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0
 
-#define LPDDR4__DENALI_PHY_83_READ_MASK				              0x00001F1FU
-#define LPDDR4__DENALI_PHY_83_WRITE_MASK				             0x00001F1FU
+#define LPDDR4__DENALI_PHY_83_READ_MASK                              0x00001F1FU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK                             0x00001F1FU
 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_MASK  0x0000001FU
 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_SHIFT          0U
 #define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_WIDTH          5U
@@ -1350,37 +1349,37 @@
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_83
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
 
-#define LPDDR4__DENALI_PHY_84_READ_MASK				              0x07FFFF07U
-#define LPDDR4__DENALI_PHY_84_WRITE_MASK				             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_84_READ_MASK                              0x07FFFF07U
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK                             0x07FFFF07U
 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_MASK             0x00000007U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH				     3U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH                     3U
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_84
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0
 
 #define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_MASK             0x00FFFF00U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT				     8U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH				    16U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH                    16U
 #define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_84
 #define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0
 
 #define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_MASK            0x07000000U
-#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH				    3U
+#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH                    3U
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_84
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0
 
-#define LPDDR4__DENALI_PHY_85_READ_MASK				              0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_85_WRITE_MASK				             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_85_READ_MASK                              0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK                             0x7F03FFFFU
 #define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_MASK            0x0000FFFFU
-#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH				   16U
+#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH                   16U
 #define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_85
 #define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0
 
 #define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_MASK           0x00030000U
-#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH				   2U
+#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH                   2U
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_85
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0
 
@@ -1390,8 +1389,8 @@
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_85
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0
 
-#define LPDDR4__DENALI_PHY_86_READ_MASK				              0xFF01037FU
-#define LPDDR4__DENALI_PHY_86_WRITE_MASK				             0xFF01037FU
+#define LPDDR4__DENALI_PHY_86_READ_MASK                              0xFF01037FU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK                             0xFF01037FU
 #define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_MASK    0x0000007FU
 #define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH            7U
@@ -1399,50 +1398,50 @@
 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0
 
 #define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_MASK         0x00000300U
-#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH				 2U
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH                 2U
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_86
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0
 
 #define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_MASK               0x00010000U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH				       1U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR				       0U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET				       0U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET                       0U
 #define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_86
 #define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0
 
 #define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_MASK          0xFF000000U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH                  8U
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_86
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0
 
-#define LPDDR4__DENALI_PHY_87_READ_MASK				              0x07FF07FFU
-#define LPDDR4__DENALI_PHY_87_WRITE_MASK				             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_87_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK                             0x07FF07FFU
 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_MASK              0x000007FFU
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH				     11U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH                     11U
 #define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_87
 #define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0
 
 #define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_MASK               0x07FF0000U
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH				      11U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH                      11U
 #define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_87
 #define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0
 
-#define LPDDR4__DENALI_PHY_88_READ_MASK				              0x0103FFFFU
-#define LPDDR4__DENALI_PHY_88_WRITE_MASK				             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_88_READ_MASK                              0x0103FFFFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK                             0x0103FFFFU
 #define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_MASK             0x000000FFU
-#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH                     8U
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_88
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0
 
 #define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_MASK             0x0003FF00U
-#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT				     8U
-#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH				    10U
+#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH                    10U
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_88
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0
 
@@ -1454,321 +1453,321 @@
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_88
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0
 
-#define LPDDR4__DENALI_PHY_89_READ_MASK				              0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_89_WRITE_MASK				             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_89_READ_MASK                              0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK                             0x1F1F0F3FU
 #define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_MASK    0x0000003FU
 #define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH            6U
 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_89
 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0
 
-#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK				0x00000F00U
-#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT				        8U
-#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH				        4U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK                0x00000F00U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH                        4U
 #define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_89
 #define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0
 
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK				 0x001F0000U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT				        16U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH				         5U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK                 0x001F0000U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH                         5U
 #define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_89
 #define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0
 
 #define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_MASK               0x1F000000U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT				      24U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_89
 #define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0
 
-#define LPDDR4__DENALI_PHY_90_READ_MASK				              0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_90_WRITE_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_90_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK                             0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_MASK               0x0000001FU
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_90
 #define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0
 
 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_MASK               0x00001F00U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT				       8U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_90
 #define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0
 
 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_MASK               0x001F0000U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_90
 #define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0
 
 #define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_MASK               0x1F000000U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT				      24U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_90
 #define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0
 
-#define LPDDR4__DENALI_PHY_91_READ_MASK				              0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_91_WRITE_MASK				             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_91_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK                             0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_MASK               0x0000001FU
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_91
 #define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0
 
 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_MASK               0x00001F00U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT				       8U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_91
 #define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0
 
 #define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_MASK               0x001F0000U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH				       5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH                       5U
 #define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_91
 #define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0
 
 #define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_MASK              0x1F000000U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH                      5U
 #define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_91
 #define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0
 
-#define LPDDR4__DENALI_PHY_92_READ_MASK				              0x003F1F1FU
-#define LPDDR4__DENALI_PHY_92_WRITE_MASK				             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_92_READ_MASK                              0x003F1F1FU
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK                             0x003F1F1FU
 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_MASK             0x0000001FU
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH                     5U
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_92
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0
 
 #define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_MASK            0x00001F00U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH                    5U
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_92
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0
 
 #define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_MASK          0x003F0000U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH                  6U
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_92
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0
 
-#define LPDDR4__DENALI_PHY_93_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_93_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_93_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_MASK          0x000003FFU
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_93
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_93
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_94_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_94_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_94_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_MASK          0x000003FFU
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_94
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_94
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_95_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_95_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_95_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_MASK          0x000003FFU
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_95
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_95
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_96_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PHY_96_WRITE_MASK				             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_96_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK                             0x03FF03FFU
 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_MASK          0x000003FFU
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_96
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH                 10U
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_96
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_97_READ_MASK				              0x000703FFU
-#define LPDDR4__DENALI_PHY_97_WRITE_MASK				             0x000703FFU
+#define LPDDR4__DENALI_PHY_97_READ_MASK                              0x000703FFU
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK                             0x000703FFU
 #define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH                  10U
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_97
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_MASK        0x00070000U
 #define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT               16U
-#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH				3U
+#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH                3U
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_97
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0
 
-#define LPDDR4__DENALI_PHY_98_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_98_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_98_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_MASK               0x000000FFU
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH				       8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH                       8U
 #define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_98
 #define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0
 
 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_MASK          0x0000FF00U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH                  8U
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_98
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0
 
 #define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_MASK          0x00FF0000U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH                  8U
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_98
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0
 
 #define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_MASK              0xFF000000U
-#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH                      8U
 #define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_98
 #define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0
 
-#define LPDDR4__DENALI_PHY_99_READ_MASK				              0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_99_WRITE_MASK				             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_99_READ_MASK                              0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK                             0xFFFFFF0FU
 #define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_MASK        0x0000000FU
-#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT				0U
-#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH				4U
+#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH                4U
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_99
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0
 
 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_MASK         0x0000FF00U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH                 8U
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_99
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0
 
 #define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_MASK           0x00FF0000U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH                   8U
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_99
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0
 
 #define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_MASK         0xFF000000U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT				24U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH                 8U
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_99
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0
 
-#define LPDDR4__DENALI_PHY_100_READ_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_100_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_100_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK                            0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH				16U
+#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH                16U
 #define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_100
 #define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0
 
 #define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_MASK          0x0FFF0000U
-#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH				 12U
+#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH                 12U
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_100
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0
 
-#define LPDDR4__DENALI_PHY_101_READ_MASK				             0x03FFFF01U
-#define LPDDR4__DENALI_PHY_101_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_101_READ_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK                            0x03FFFF01U
 #define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_MASK        0x00000001U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT				0U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH				1U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR				0U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET				0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH                1U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR                0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET                0U
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_101
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0
 
 #define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_MASK              0x0000FF00U
-#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH                      8U
 #define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_101
 #define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0
 
 #define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_MASK             0x00FF0000U
-#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH                     8U
 #define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_101
 #define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0
 
 #define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_MASK          0x03000000U
-#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH                  2U
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_101
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0
 
-#define LPDDR4__DENALI_PHY_102_READ_MASK				             0x1F1F0103U
-#define LPDDR4__DENALI_PHY_102_WRITE_MASK				            0x1F1F0103U
-#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK				   0x00000003U
-#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_102_READ_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK                            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH                           2U
 #define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_102
 #define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0
 
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK				  0x00000100U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT				          8U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET				          0U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK                  0x00000100U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET                          0U
 #define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_102
 #define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0
 
 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_MASK        0x001F0000U
 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT               16U
-#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH				5U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH                5U
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_102
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0
 
 #define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_MASK          0x1F000000U
-#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH				  5U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH                  5U
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_102
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0
 
-#define LPDDR4__DENALI_PHY_103_READ_MASK				             0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_103_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_103_READ_MASK                             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK                            0x3F07FF0FU
 #define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH                    4U
 #define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_103
 #define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0
 
 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_MASK        0x0007FF00U
-#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT				8U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT                8U
 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_WIDTH               11U
 #define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_103
 #define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0
 
 #define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_MASK         0x3F000000U
-#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT				24U
-#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH                 6U
 #define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_103
 #define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0
 
-#define LPDDR4__DENALI_PHY_104_READ_MASK				             0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_104_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_104_READ_MASK                             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK                            0xFF0FFFFFU
 #define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_MASK         0x000000FFU
-#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH                 8U
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_104
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0
 
@@ -1779,19 +1778,19 @@
 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0
 
 #define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_MASK               0x000F0000U
-#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH                       4U
 #define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_104
 #define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0
 
 #define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_MASK            0xFF000000U
-#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH                    8U
 #define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_104
 #define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0
 
-#define LPDDR4__DENALI_PHY_105_READ_MASK				             0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_105_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_105_READ_MASK                             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK                            0x1F0F3F0FU
 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH               4U
@@ -1805,8 +1804,8 @@
 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0
 
 #define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_MASK            0x000F0000U
-#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH                    4U
 #define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_105
 #define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0
 
@@ -1816,25 +1815,25 @@
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0
 
-#define LPDDR4__DENALI_PHY_106_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_106_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_106_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH                  10U
 #define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_106
 #define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0
 
 #define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH                 10U
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_106
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0
 
-#define LPDDR4__DENALI_PHY_107_READ_MASK				             0x0F010FFFU
-#define LPDDR4__DENALI_PHY_107_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_107_READ_MASK                             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK                            0x0F010FFFU
 #define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_MASK           0x000000FFU
-#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH                   8U
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_107
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0
 
@@ -1846,31 +1845,31 @@
 
 #define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_MASK        0x00010000U
 #define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT               16U
-#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH				1U
-#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR				0U
-#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET				0U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH                1U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR                0U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET                0U
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_107
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0
 
 #define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_MASK            0x0F000000U
-#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH                    4U
 #define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_107
 #define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0
 
-#define LPDDR4__DENALI_PHY_108_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_108_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_108_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_MASK            0x000003FFU
-#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH                   10U
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_108
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0
 
-#define LPDDR4__DENALI_PHY_109_READ_MASK				             0x3F0103FFU
-#define LPDDR4__DENALI_PHY_109_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_109_READ_MASK                             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK                            0x3F0103FFU
 #define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_MASK             0x000003FFU
-#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH				    10U
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH                    10U
 #define LPDDR4__PHY_RDLVL_DVW_MIN_0__REG DENALI_PHY_109
 #define LPDDR4__PHY_RDLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0
 
@@ -1888,8 +1887,8 @@
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__REG DENALI_PHY_109
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0
 
-#define LPDDR4__DENALI_PHY_110_READ_MASK				             0x00030703U
-#define LPDDR4__DENALI_PHY_110_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_110_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK                            0x00030703U
 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_MASK       0x00000003U
 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_WIDTH               2U
@@ -1897,8 +1896,8 @@
 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0
 
 #define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT				8U
-#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH				3U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH                3U
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_110
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0
 
@@ -1908,8 +1907,8 @@
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_110
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0
 
-#define LPDDR4__DENALI_PHY_111_READ_MASK				             0x07FF03FFU
-#define LPDDR4__DENALI_PHY_111_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_111_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK                            0x07FF03FFU
 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH       10U
@@ -1922,8 +1921,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_111
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0
 
-#define LPDDR4__DENALI_PHY_112_READ_MASK				             0xFFFF0101U
-#define LPDDR4__DENALI_PHY_112_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_112_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK                            0xFFFF0101U
 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH              1U
@@ -1952,11 +1951,11 @@
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_112
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0
 
-#define LPDDR4__DENALI_PHY_113_READ_MASK				             0x001F3F7FU
-#define LPDDR4__DENALI_PHY_113_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_113_READ_MASK                             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK                            0x001F3F7FU
 #define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_MASK             0x0000007FU
-#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH				     7U
+#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH                     7U
 #define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_113
 #define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0
 
@@ -1967,29 +1966,29 @@
 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0
 
 #define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_MASK             0x001F0000U
-#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH                     5U
 #define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_113
 #define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0
 
-#define LPDDR4__DENALI_PHY_114_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_114_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_114_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH				   32U
+#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH                   32U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_114
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0
 
-#define LPDDR4__DENALI_PHY_115_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PHY_115_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_115_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK                            0x0000000FU
 #define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH                    4U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_115
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0
 
-#define LPDDR4__DENALI_PHY_116_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_116_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH            11U
@@ -2002,8 +2001,8 @@
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_116
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_117_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_117_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_117_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH            11U
@@ -2016,8 +2015,8 @@
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_117
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_118_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_118_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_118_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH            11U
@@ -2030,8 +2029,8 @@
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_118
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_119_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_119_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_119_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH            11U
@@ -2044,8 +2043,8 @@
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_119
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_120_READ_MASK				             0x03FF07FFU
-#define LPDDR4__DENALI_PHY_120_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_120_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK                            0x03FF07FFU
 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK      0x000007FFU
 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH             11U
@@ -2058,8 +2057,8 @@
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_120
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_121_READ_MASK				             0x0003FF03U
-#define LPDDR4__DENALI_PHY_121_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_121_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK                            0x0003FF03U
 #define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK    0x00000003U
 #define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH            2U
@@ -2072,8 +2071,8 @@
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_122_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_122_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2086,8 +2085,8 @@
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_123_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_123_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2100,8 +2099,8 @@
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_124_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_124_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2114,8 +2113,8 @@
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_125_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_125_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2128,8 +2127,8 @@
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_126_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_126_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2142,8 +2141,8 @@
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_127_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_127_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2156,8 +2155,8 @@
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_127
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_128_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_128_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_128_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_128_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2170,8 +2169,8 @@
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_128
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_129_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_129_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_129_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_129_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH       10U
@@ -2184,8 +2183,8 @@
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_129
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_130_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_130_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_130_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_130_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT         0U
 #define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH        10U
@@ -2198,8 +2197,8 @@
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_130
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_131_READ_MASK				             0x03FF070FU
-#define LPDDR4__DENALI_PHY_131_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_131_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_131_WRITE_MASK                            0x03FF070FU
 #define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_MASK      0x0000000FU
 #define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH              4U
@@ -2207,8 +2206,8 @@
 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0
 
 #define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT				8U
-#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH				3U
+#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH                3U
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_131
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0
 
@@ -2218,8 +2217,8 @@
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_131
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
 
-#define LPDDR4__DENALI_PHY_132_READ_MASK				             0x000103FFU
-#define LPDDR4__DENALI_PHY_132_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_132_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_132_WRITE_MASK                            0x000103FFU
 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT      0U
 #define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH     10U
@@ -2234,8 +2233,8 @@
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_132
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0
 
-#define LPDDR4__DENALI_PHY_133_READ_MASK				             0x000F03FFU
-#define LPDDR4__DENALI_PHY_133_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_133_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_133_WRITE_MASK                            0x000F03FFU
 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT         0U
 #define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH        10U
@@ -2248,8 +2247,8 @@
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_133
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0
 
-#define LPDDR4__DENALI_PHY_134_READ_MASK				             0x010F07FFU
-#define LPDDR4__DENALI_PHY_134_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_134_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_134_WRITE_MASK                            0x010F07FFU
 #define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT         0U
 #define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH        11U
@@ -2257,29 +2256,29 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0
 
 #define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_MASK           0x000F0000U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH				   4U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH                   4U
 #define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_134
 #define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0
 
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK				  0x01000000U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT				         24U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET				          0U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET                          0U
 #define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_134
 #define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0
 
-#define LPDDR4__DENALI_PHY_135_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_135_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_135_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_135_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT      0U
 #define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH     10U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_135
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
 
-#define LPDDR4__DENALI_PHY_136_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_136_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_136_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_136_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH            8U
@@ -2304,8 +2303,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_136
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0
 
-#define LPDDR4__DENALI_PHY_137_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_137_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_137_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_137_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH            8U
@@ -2330,8 +2329,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_137
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0
 
-#define LPDDR4__DENALI_PHY_138_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_138_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_138_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_138_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT            0U
 #define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH            8U
@@ -2350,23 +2349,23 @@
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_138
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
 
-#define LPDDR4__DENALI_PHY_139_READ_MASK				             0x0003033FU
-#define LPDDR4__DENALI_PHY_139_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_139_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_139_WRITE_MASK                            0x0003033FU
 #define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU
 #define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT        0U
 #define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH        6U
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_139
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
 
-#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK				    0x00000300U
-#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT				            8U
-#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH				            2U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH                            2U
 #define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_139
 #define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0
 
-#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK				   0x00030000U
-#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT				          16U
-#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH                           2U
 #define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_139
 #define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0
 
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
index 124f58f7e8..5385e1e87b 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
@@ -1,17 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
  *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
 #define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
 
-#define LPDDR4__DENALI_PHY_256_READ_MASK				             0x000F07FFU
-#define LPDDR4__DENALI_PHY_256_WRITE_MASK				            0x000F07FFU
+#define LPDDR4__DENALI_PHY_256_READ_MASK                             0x000F07FFU
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK                            0x000F07FFU
 #define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH        11U
@@ -24,8 +23,8 @@
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_256
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
 
-#define LPDDR4__DENALI_PHY_257_READ_MASK				             0x000703FFU
-#define LPDDR4__DENALI_PHY_257_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_257_READ_MASK                             0x000703FFU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK                            0x000703FFU
 #define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT      0U
 #define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH     10U
@@ -38,8 +37,8 @@
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
 
-#define LPDDR4__DENALI_PHY_258_READ_MASK				             0x010303FFU
-#define LPDDR4__DENALI_PHY_258_WRITE_MASK				            0x010303FFU
+#define LPDDR4__DENALI_PHY_258_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK                            0x010303FFU
 #define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT     0U
 #define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH    10U
@@ -60,75 +59,75 @@
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
 
-#define LPDDR4__DENALI_PHY_259_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_259_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK                            0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK            0x0000003FU
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK            0x00003F00U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK            0x003F0000U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK            0x3F000000U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
 
-#define LPDDR4__DENALI_PHY_260_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_260_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK                            0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK            0x0000003FU
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK            0x00003F00U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK            0x003F0000U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK            0x3F000000U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
 
-#define LPDDR4__DENALI_PHY_261_READ_MASK				             0x01030F3FU
-#define LPDDR4__DENALI_PHY_261_WRITE_MASK				            0x01030F3FU
+#define LPDDR4__DENALI_PHY_261_READ_MASK                             0x01030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK                            0x01030F3FU
 #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK             0x0000003FU
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH				     6U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH                     6U
 #define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
 #define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK            0x00000F00U
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH                    4U
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK           0x00030000U
-#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH				   2U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH                   2U
 #define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261
 #define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1
 
@@ -140,8 +139,8 @@
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1
 
-#define LPDDR4__DENALI_PHY_262_READ_MASK				             0x1F1F0301U
-#define LPDDR4__DENALI_PHY_262_WRITE_MASK				            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262_READ_MASK                             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK                            0x1F1F0301U
 #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK     0x00000001U
 #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH             1U
@@ -168,8 +167,8 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
 
-#define LPDDR4__DENALI_PHY_263_READ_MASK				             0x1F030F0FU
-#define LPDDR4__DENALI_PHY_263_WRITE_MASK				            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263_READ_MASK                             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK                            0x1F030F0FU
 #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK      0x0000000FU
 #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH              4U
@@ -194,17 +193,17 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
 
-#define LPDDR4__DENALI_PHY_264_READ_MASK				             0x0101FF03U
-#define LPDDR4__DENALI_PHY_264_WRITE_MASK				            0x0101FF03U
+#define LPDDR4__DENALI_PHY_264_READ_MASK                             0x0101FF03U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK                            0x0101FF03U
 #define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK              0x00000003U
-#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH				      2U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH                      2U
 #define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264
 #define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1
 
 #define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK              0x0001FF00U
-#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH				      9U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH                      9U
 #define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264
 #define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1
 
@@ -216,33 +215,33 @@
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
 
-#define LPDDR4__DENALI_PHY_265_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_265_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH       32U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1
 
-#define LPDDR4__DENALI_PHY_266_READ_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_266_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK                            0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK    0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH           28U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1
 
-#define LPDDR4__DENALI_PHY_267_READ_MASK				             0x0101FF7FU
-#define LPDDR4__DENALI_PHY_267_WRITE_MASK				            0x0101FF7FU
+#define LPDDR4__DENALI_PHY_267_READ_MASK                             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK                            0x0101FF7FU
 #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK        0x0000007FU
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT				0U
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH				7U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH                7U
 #define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267
 #define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1
 
 #define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_MASK         0x0001FF00U
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH				 9U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH                 9U
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_267
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1
 
@@ -254,8 +253,8 @@
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_267
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1
 
-#define LPDDR4__DENALI_PHY_268_READ_MASK				             0x007F3F01U
-#define LPDDR4__DENALI_PHY_268_WRITE_MASK				            0x007F3F01U
+#define LPDDR4__DENALI_PHY_268_READ_MASK                             0x007F3F01U
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK                            0x007F3F01U
 #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT      0U
 #define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH      1U
@@ -271,13 +270,13 @@
 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1
 
 #define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_MASK            0x007F0000U
-#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH				    7U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH                    7U
 #define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_268
 #define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1
 
-#define LPDDR4__DENALI_PHY_269_READ_MASK				             0x000F03FFU
-#define LPDDR4__DENALI_PHY_269_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_269_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK                            0x000F03FFU
 #define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT       0U
 #define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH      10U
@@ -291,37 +290,37 @@
 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1
 
 #define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_MASK          0x01000000U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET				  0U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET                  0U
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_269
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1
 
-#define LPDDR4__DENALI_PHY_270_READ_MASK				             0x070101FFU
-#define LPDDR4__DENALI_PHY_270_WRITE_MASK				            0x070101FFU
+#define LPDDR4__DENALI_PHY_270_READ_MASK                             0x070101FFU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK                            0x070101FFU
 #define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK    0x000001FFU
 #define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH            9U
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK				     0x00010000U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT				            16U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH				             1U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR				             0U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET				             0U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK                     0x00010000U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT                            16U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET                             0U
 #define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_270
 #define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_270__PHY_LPDDR_1
 
-#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK				 0x07000000U
-#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT				        24U
-#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH				         3U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK                 0x07000000U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH                         3U
 #define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_270
 #define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1
 
-#define LPDDR4__DENALI_PHY_271_READ_MASK				             0x000301FFU
-#define LPDDR4__DENALI_PHY_271_WRITE_MASK				            0x000301FFU
+#define LPDDR4__DENALI_PHY_271_READ_MASK                             0x000301FFU
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK                            0x000301FFU
 #define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK    0x000001FFU
 #define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH            9U
@@ -329,101 +328,101 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1
 
 #define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_MASK         0x00030000U
-#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH				 2U
+#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH                 2U
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_271
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1
 
-#define LPDDR4__DENALI_PHY_272_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_272_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_272_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH				32U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH                32U
 #define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_272
 #define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1
 
-#define LPDDR4__DENALI_PHY_273_READ_MASK				             0x00000301U
-#define LPDDR4__DENALI_PHY_273_WRITE_MASK				            0x00000301U
+#define LPDDR4__DENALI_PHY_273_READ_MASK                             0x00000301U
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK                            0x00000301U
 #define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET				    0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET                    0U
 #define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_273
 #define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1
 
 #define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_MASK             0x00000300U
-#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT				     8U
-#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH                     2U
 #define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_273
 #define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1
 
-#define LPDDR4__DENALI_PHY_274_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_274_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_274
 #define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1
 
-#define LPDDR4__DENALI_PHY_275_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_275_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_275
 #define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1
 
-#define LPDDR4__DENALI_PHY_276_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_276_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_276
 #define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1
 
-#define LPDDR4__DENALI_PHY_277_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_277_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_277
 #define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1
 
-#define LPDDR4__DENALI_PHY_278_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_278_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_278
 #define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1
 
-#define LPDDR4__DENALI_PHY_279_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_279_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_279
 #define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1
 
-#define LPDDR4__DENALI_PHY_280_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_280_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_280
 #define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1
 
-#define LPDDR4__DENALI_PHY_281_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_281_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_281
 #define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1
 
-#define LPDDR4__DENALI_PHY_282_READ_MASK				             0x070F0107U
-#define LPDDR4__DENALI_PHY_282_WRITE_MASK				            0x070F0107U
+#define LPDDR4__DENALI_PHY_282_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK                            0x070F0107U
 #define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK     0x00000007U
 #define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH             3U
@@ -450,8 +449,8 @@
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_282
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1
 
-#define LPDDR4__DENALI_PHY_283_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_283_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_283_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK   0x0000000FU
 #define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT           0U
 #define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH           4U
@@ -459,8 +458,8 @@
 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
 
 #define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_MASK         0x00000F00U
-#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH				 4U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH                 4U
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_283
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1
 
@@ -476,41 +475,41 @@
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_283
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1
 
-#define LPDDR4__DENALI_PHY_284_READ_MASK				             0xFF030001U
-#define LPDDR4__DENALI_PHY_284_WRITE_MASK				            0xFF030001U
+#define LPDDR4__DENALI_PHY_284_READ_MASK                             0xFF030001U
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK                            0xFF030001U
 #define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET				    0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET                    0U
 #define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_284
 #define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1
 
 #define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET				 0U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET                 0U
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_284
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1
 
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK				0x00030000U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH				        2U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH                        2U
 #define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_284
 #define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1
 
 #define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_MASK           0xFF000000U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH                   8U
 #define LPDDR4__PHY_WRLVL_PER_START_1__REG DENALI_PHY_284
 #define LPDDR4__PHY_WRLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1
 
-#define LPDDR4__DENALI_PHY_285_READ_MASK				             0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_285_WRITE_MASK				            0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_285_READ_MASK                             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK                            0x00FF0F3FU
 #define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK         0x0000003FU
-#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH                 6U
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1
 
@@ -520,23 +519,23 @@
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_285
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1
 
-#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT				          16U
-#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH				           8U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH                           8U
 #define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_285
 #define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1
 
-#define LPDDR4__DENALI_PHY_286_READ_MASK				             0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_286_WRITE_MASK				            0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_286_READ_MASK                             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK                            0x0F3F03FFU
 #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH                  10U
 #define LPDDR4__PHY_GTLVL_PER_START_1__REG DENALI_PHY_286
 #define LPDDR4__PHY_GTLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1
 
 #define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK         0x003F0000U
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH                 6U
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1
 
@@ -546,11 +545,11 @@
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1
 
-#define LPDDR4__DENALI_PHY_287_READ_MASK				             0x1F030F3FU
-#define LPDDR4__DENALI_PHY_287_WRITE_MASK				            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK                            0x1F030F3FU
 #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK         0x0000003FU
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH                 6U
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1
 
@@ -561,8 +560,8 @@
 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1
 
 #define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK             0x00030000U
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH                     2U
 #define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287
 #define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1
 
@@ -572,8 +571,8 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
 
-#define LPDDR4__DENALI_PHY_288_READ_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_288_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_288_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK                            0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_WIDTH         8U
@@ -581,8 +580,8 @@
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1
 
 #define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK           0x0000FF00U
-#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH                   8U
 #define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288
 #define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1
 
@@ -593,16 +592,16 @@
 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
 
 #define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_MASK          0x3F000000U
-#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH                  6U
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_288
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1
 
-#define LPDDR4__DENALI_PHY_289_READ_MASK				             0x0F07FF07U
-#define LPDDR4__DENALI_PHY_289_WRITE_MASK				            0x0F07FF07U
+#define LPDDR4__DENALI_PHY_289_READ_MASK                             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK                            0x0F07FF07U
 #define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK               0x00000007U
-#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH				       3U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH                       3U
 #define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289
 #define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1
 
@@ -618,8 +617,8 @@
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_289
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1
 
-#define LPDDR4__DENALI_PHY_290_READ_MASK				             0x0000FF0FU
-#define LPDDR4__DENALI_PHY_290_WRITE_MASK				            0x0000FF0FU
+#define LPDDR4__DENALI_PHY_290_READ_MASK                             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK                            0x0000FF0FU
 #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK    0x0000000FU
 #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH            4U
@@ -640,64 +639,64 @@
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_290
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
 
-#define LPDDR4__DENALI_PHY_291_READ_MASK				             0x000001FFU
-#define LPDDR4__DENALI_PHY_291_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_291_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK                            0x000001FFU
 #define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_MASK        0x000001FFU
-#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT				0U
-#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH				9U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH                9U
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_291
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1
 
-#define LPDDR4__DENALI_PHY_292_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_292_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_292_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_292
 #define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1
 
-#define LPDDR4__DENALI_PHY_293_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_293_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_293
 #define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1
 
-#define LPDDR4__DENALI_PHY_294_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_294_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_294_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_294
 #define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1
 
-#define LPDDR4__DENALI_PHY_295_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_295_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_295_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_295
 #define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1
 
-#define LPDDR4__DENALI_PHY_296_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PHY_296_WRITE_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH				       16U
+#define LPDDR4__DENALI_PHY_296_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH                       16U
 #define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_296
 #define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1
 
 #define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_MASK            0x00010000U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET				    0U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET                    0U
 #define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_296
 #define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1
 
-#define LPDDR4__DENALI_PHY_297_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_297_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_297_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_MASK       0x000003FFU
 #define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_SHIFT               0U
 #define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_WIDTH              10U
@@ -710,8 +709,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_297
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1
 
-#define LPDDR4__DENALI_PHY_298_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_298_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK  0x000003FFU
 #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT          0U
 #define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH         10U
@@ -724,8 +723,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_298
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1
 
-#define LPDDR4__DENALI_PHY_299_READ_MASK				             0x00FF0001U
-#define LPDDR4__DENALI_PHY_299_WRITE_MASK				            0x00FF0001U
+#define LPDDR4__DENALI_PHY_299_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK                            0x00FF0001U
 #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK  0x00000001U
 #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT          0U
 #define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH          1U
@@ -735,27 +734,27 @@
 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1
 
 #define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_MASK           0x00003F00U
-#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH				   6U
+#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH                   6U
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_299
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1
 
 #define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_MASK              0x00FF0000U
-#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH                      8U
 #define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_299
 #define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1
 
-#define LPDDR4__DENALI_PHY_300_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_300_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_300_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH				  32U
+#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH                  32U
 #define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_300
 #define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1
 
-#define LPDDR4__DENALI_PHY_301_READ_MASK				             0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_301_WRITE_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_301_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK                            0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_MASK      0x0000FFFFU
 #define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH             16U
@@ -768,8 +767,8 @@
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_301
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1
 
-#define LPDDR4__DENALI_PHY_302_READ_MASK				             0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_302_WRITE_MASK				            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_302_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK                            0xFFFF7F7FU
 #define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK      0x0000007FU
 #define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH              7U
@@ -794,8 +793,8 @@
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
 
-#define LPDDR4__DENALI_PHY_303_READ_MASK				             0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_303_WRITE_MASK				            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_303_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK                            0x7F07FFFFU
 #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
 #define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
@@ -814,8 +813,8 @@
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
 
-#define LPDDR4__DENALI_PHY_304_READ_MASK				             0x0007FFFFU
-#define LPDDR4__DENALI_PHY_304_WRITE_MASK				            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_304_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK                            0x0007FFFFU
 #define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH         8U
@@ -829,13 +828,13 @@
 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
 
 #define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_MASK              0x00070000U
-#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH				      3U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH                      3U
 #define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_304
 #define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1
 
-#define LPDDR4__DENALI_PHY_305_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_305_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_305_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK     0x000003FFU
 #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH            10U
@@ -848,16 +847,16 @@
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_305
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1
 
-#define LPDDR4__DENALI_PHY_306_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PHY_306_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_306_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK                            0x0001FFFFU
 #define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_MASK          0x0001FFFFU
-#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH				 17U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH                 17U
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_306
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1
 
-#define LPDDR4__DENALI_PHY_307_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_307_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH       10U
@@ -870,11 +869,11 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
 
-#define LPDDR4__DENALI_PHY_308_READ_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_308_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_308_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK                            0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH				  16U
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH                  16U
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_308
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1
 
@@ -884,24 +883,24 @@
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_308
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1
 
-#define LPDDR4__DENALI_PHY_309_READ_MASK				             0x00003FFFU
-#define LPDDR4__DENALI_PHY_309_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_309_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK                            0x00003FFFU
 #define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK     0x00003FFFU
 #define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH            14U
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1
 
-#define LPDDR4__DENALI_PHY_310_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_310_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK                            0x0003FFFFU
 #define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK          0x0003FFFFU
-#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH				 18U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH                 18U
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1
 
-#define LPDDR4__DENALI_PHY_311_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_311_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH        10U
@@ -914,32 +913,32 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
 
-#define LPDDR4__DENALI_PHY_312_READ_MASK				             0x00000003U
-#define LPDDR4__DENALI_PHY_312_WRITE_MASK				            0x00000003U
+#define LPDDR4__DENALI_PHY_312_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK                            0x00000003U
 #define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
 #define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT    0U
 #define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH    2U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
 
-#define LPDDR4__DENALI_PHY_313_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_313_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH				 32U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH                 32U
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1
 
-#define LPDDR4__DENALI_PHY_314_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_314_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_314_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT                0U
 #define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_WIDTH               32U
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__REG DENALI_PHY_314
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1
 
-#define LPDDR4__DENALI_PHY_315_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_315_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_315_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK    0x000007FFU
 #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH           11U
@@ -952,56 +951,56 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_315
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
 
-#define LPDDR4__DENALI_PHY_316_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_316_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH				32U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH                32U
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_316
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1
 
-#define LPDDR4__DENALI_PHY_317_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_317_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT               0U
 #define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH              32U
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_317
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1
 
-#define LPDDR4__DENALI_PHY_318_READ_MASK				             0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_318_WRITE_MASK				            0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK				  0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH				         31U
+#define LPDDR4__DENALI_PHY_318_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH                         31U
 #define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_318
 #define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1
 
-#define LPDDR4__DENALI_PHY_319_READ_MASK				             0x0000003FU
-#define LPDDR4__DENALI_PHY_319_WRITE_MASK				            0x0000003FU
-#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK				  0x0000003FU
-#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH				          6U
+#define LPDDR4__DENALI_PHY_319_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH                          6U
 #define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_319
 #define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1
 
-#define LPDDR4__DENALI_PHY_320_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_320_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH                     32U
 #define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_320
 #define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1
 
-#define LPDDR4__DENALI_PHY_321_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_321_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK     0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH            32U
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_321
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1
 
-#define LPDDR4__DENALI_PHY_322_READ_MASK				             0x010001FFU
-#define LPDDR4__DENALI_PHY_322_WRITE_MASK				            0x010001FFU
+#define LPDDR4__DENALI_PHY_322_READ_MASK                             0x010001FFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK                            0x010001FFU
 #define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK   0x000000FFU
 #define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT           0U
 #define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH           8U
@@ -1009,34 +1008,34 @@
 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1
 
 #define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_MASK        0x00000100U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT				8U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH				1U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR				0U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET				0U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET                0U
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_322
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1
 
 #define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_MASK           0x00010000U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET				   0U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET                   0U
 #define LPDDR4__SC_PHY_RX_CAL_START_1__REG DENALI_PHY_322
 #define LPDDR4__SC_PHY_RX_CAL_START_1__FLD LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1
 
 #define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET				   0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET                   0U
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_1__REG DENALI_PHY_322
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1
 
-#define LPDDR4__DENALI_PHY_323_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_323_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK                            0x01FF01FFU
 #define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_MASK        0x000000FFU
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT				0U
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH				8U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH                8U
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_323
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1
 
@@ -1048,147 +1047,147 @@
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__REG DENALI_PHY_323
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__FLD LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1
 
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323
 #define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1
 
-#define LPDDR4__DENALI_PHY_324_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_324_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_324_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324
 #define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1
 
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324
 #define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1
 
-#define LPDDR4__DENALI_PHY_325_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_325_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_325_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325
 #define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1
 
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325
 #define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1
 
-#define LPDDR4__DENALI_PHY_326_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_326_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_326_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326
 #define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1
 
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326
 #define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1
 
-#define LPDDR4__DENALI_PHY_327_READ_MASK				             0x000001FFU
-#define LPDDR4__DENALI_PHY_327_WRITE_MASK				            0x000001FFU
-#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_327_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327
 #define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1
 
-#define LPDDR4__DENALI_PHY_328_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_328_WRITE_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK				 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH				        18U
+#define LPDDR4__DENALI_PHY_328_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH                        18U
 #define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328
 #define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1
 
-#define LPDDR4__DENALI_PHY_329_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_329_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_329_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329
 #define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1
 
 #define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK               0x01FF0000U
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH				       9U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH                       9U
 #define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329
 #define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1
 
-#define LPDDR4__DENALI_PHY_330_READ_MASK				             0x01FF07FFU
-#define LPDDR4__DENALI_PHY_330_WRITE_MASK				            0x01FF07FFU
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK				0x000007FFU
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH				       11U
+#define LPDDR4__DENALI_PHY_330_READ_MASK                             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK                            0x01FF07FFU
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK                0x000007FFU
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH                       11U
 #define LPDDR4__PHY_RX_CAL_OBS_1__REG DENALI_PHY_330
 #define LPDDR4__PHY_RX_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1
 
 #define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_MASK           0x01FF0000U
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH				   9U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH                   9U
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__REG DENALI_PHY_330
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1
 
-#define LPDDR4__DENALI_PHY_331_READ_MASK				             0x017F7F01U
-#define LPDDR4__DENALI_PHY_331_WRITE_MASK				            0x017F7F01U
+#define LPDDR4__DENALI_PHY_331_READ_MASK                             0x017F7F01U
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK                            0x017F7F01U
 #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET				    0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET                    0U
 #define LPDDR4__PHY_RX_CAL_DISABLE_1__REG DENALI_PHY_331
 #define LPDDR4__PHY_RX_CAL_DISABLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1
 
 #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_MASK          0x00007F00U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH				  7U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH                  7U
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__REG DENALI_PHY_331
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1
 
 #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_MASK        0x007F0000U
 #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_SHIFT               16U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH				7U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH                7U
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__REG DENALI_PHY_331
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1
 
 #define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET				   0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET                   0U
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_1__REG DENALI_PHY_331
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1
 
-#define LPDDR4__DENALI_PHY_332_READ_MASK				             0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_332_WRITE_MASK				            0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_332_READ_MASK                             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK                            0x07FF0FFFU
 #define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_MASK         0x00000FFFU
-#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH				12U
+#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH                12U
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__REG DENALI_PHY_332
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__FLD LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1
 
 #define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_MASK            0x07FF0000U
-#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH				   11U
+#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH                   11U
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_332
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1
 
-#define LPDDR4__DENALI_PHY_333_READ_MASK				             0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_333_WRITE_MASK				            0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_333_READ_MASK                             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK                            0x03FFFF1FU
 #define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_MASK        0x0000001FU
-#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT				0U
-#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH				5U
+#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH                5U
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_333
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1
 
@@ -1205,13 +1204,13 @@
 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1
 
 #define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_MASK            0x03000000U
-#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH				    2U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH                    2U
 #define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_333
 #define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1
 
-#define LPDDR4__DENALI_PHY_334_READ_MASK				             0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_334_WRITE_MASK				            0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_334_READ_MASK                             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK                            0x01FFFF3FU
 #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_MASK      0x0000003FU
 #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_WIDTH              6U
@@ -1238,8 +1237,8 @@
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_334
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1
 
-#define LPDDR4__DENALI_PHY_335_READ_MASK				             0x07030101U
-#define LPDDR4__DENALI_PHY_335_WRITE_MASK				            0x07030101U
+#define LPDDR4__DENALI_PHY_335_READ_MASK                             0x07030101U
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK                            0x07030101U
 #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WIDTH              1U
@@ -1249,27 +1248,27 @@
 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1
 
 #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET				 0U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET                 0U
 #define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_335
 #define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1
 
 #define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_MASK           0x00030000U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH				   2U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH                   2U
 #define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_335
 #define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1
 
 #define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_MASK             0x07000000U
-#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH				     3U
+#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH                     3U
 #define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_335
 #define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1
 
-#define LPDDR4__DENALI_PHY_336_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_PHY_336_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_PHY_336_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH         1U
@@ -1302,22 +1301,22 @@
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_336
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1
 
-#define LPDDR4__DENALI_PHY_337_READ_MASK				             0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_337_WRITE_MASK				            0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_337_READ_MASK                             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK                            0x3FFF07FFU
 #define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_MASK        0x000007FFU
-#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT				0U
+#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT                0U
 #define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_WIDTH               11U
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_1__REG DENALI_PHY_337
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_1__FLD LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1
 
 #define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_MASK         0x3FFF0000U
-#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH				14U
+#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH                14U
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__REG DENALI_PHY_337
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1
 
-#define LPDDR4__DENALI_PHY_338_READ_MASK				             0x00003FFFU
-#define LPDDR4__DENALI_PHY_338_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_338_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK                            0x00003FFFU
 #define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_MASK    0x00003FFFU
 #define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_WIDTH           14U
@@ -1330,8 +1329,8 @@
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_338
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1
 
-#define LPDDR4__DENALI_PHY_339_READ_MASK				             0x00001F1FU
-#define LPDDR4__DENALI_PHY_339_WRITE_MASK				            0x00001F1FU
+#define LPDDR4__DENALI_PHY_339_READ_MASK                             0x00001F1FU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK                            0x00001F1FU
 #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_MASK 0x0000001FU
 #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_WIDTH         5U
@@ -1350,37 +1349,37 @@
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__REG DENALI_PHY_339
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1
 
-#define LPDDR4__DENALI_PHY_340_READ_MASK				             0x07FFFF07U
-#define LPDDR4__DENALI_PHY_340_WRITE_MASK				            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_340_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK                            0x07FFFF07U
 #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_MASK            0x00000007U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH				    3U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH                    3U
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_340
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1
 
 #define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_MASK            0x00FFFF00U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH				   16U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH                   16U
 #define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_340
 #define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1
 
 #define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_MASK           0x07000000U
-#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH				   3U
+#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH                   3U
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_340
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1
 
-#define LPDDR4__DENALI_PHY_341_READ_MASK				             0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_341_WRITE_MASK				            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_341_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK                            0x7F03FFFFU
 #define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH				  16U
+#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH                  16U
 #define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_341
 #define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1
 
 #define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_MASK          0x00030000U
-#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH                  2U
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_341
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1
 
@@ -1390,8 +1389,8 @@
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_341
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1
 
-#define LPDDR4__DENALI_PHY_342_READ_MASK				             0xFF01037FU
-#define LPDDR4__DENALI_PHY_342_WRITE_MASK				            0xFF01037FU
+#define LPDDR4__DENALI_PHY_342_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK                            0xFF01037FU
 #define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_MASK   0x0000007FU
 #define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT           0U
 #define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH           7U
@@ -1399,50 +1398,50 @@
 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1
 
 #define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_MASK        0x00000300U
-#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT				8U
-#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH				2U
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH                2U
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_342
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1
 
 #define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_MASK              0x00010000U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH				      1U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR				      0U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET				      0U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET                      0U
 #define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_342
 #define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1
 
 #define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_MASK         0xFF000000U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT				24U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH                 8U
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_342
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1
 
-#define LPDDR4__DENALI_PHY_343_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_343_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_343_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_MASK             0x000007FFU
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH				    11U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH                    11U
 #define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_343
 #define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1
 
 #define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_MASK              0x07FF0000U
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH				     11U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH                     11U
 #define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_343
 #define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1
 
-#define LPDDR4__DENALI_PHY_344_READ_MASK				             0x0103FFFFU
-#define LPDDR4__DENALI_PHY_344_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_344_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK                            0x0103FFFFU
 #define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_MASK            0x000000FFU
-#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH                    8U
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_344
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1
 
 #define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_MASK            0x0003FF00U
-#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH                   10U
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_344
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1
 
@@ -1454,8 +1453,8 @@
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_344
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1
 
-#define LPDDR4__DENALI_PHY_345_READ_MASK				             0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_345_WRITE_MASK				            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_345_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK                            0x1F1F0F3FU
 #define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_MASK   0x0000003FU
 #define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT           0U
 #define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH           6U
@@ -1463,156 +1462,156 @@
 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1
 
 #define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_MASK               0x00000F00U
-#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT				       8U
-#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH                       4U
 #define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_345
 #define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1
 
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK				0x001F0000U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH				        5U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH                        5U
 #define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_345
 #define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1
 
 #define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_MASK              0x1F000000U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_345
 #define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1
 
-#define LPDDR4__DENALI_PHY_346_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_346_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_346_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_MASK              0x0000001FU
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_346
 #define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1
 
 #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_MASK              0x00001F00U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_346
 #define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1
 
 #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_MASK              0x001F0000U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_346
 #define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1
 
 #define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_MASK              0x1F000000U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_346
 #define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1
 
-#define LPDDR4__DENALI_PHY_347_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_347_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_347_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_MASK              0x0000001FU
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_347
 #define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1
 
 #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_MASK              0x00001F00U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_347
 #define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1
 
 #define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_MASK              0x001F0000U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_347
 #define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1
 
 #define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_MASK             0x1F000000U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH                     5U
 #define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_347
 #define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1
 
-#define LPDDR4__DENALI_PHY_348_READ_MASK				             0x003F1F1FU
-#define LPDDR4__DENALI_PHY_348_WRITE_MASK				            0x003F1F1FU
+#define LPDDR4__DENALI_PHY_348_READ_MASK                             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK                            0x003F1F1FU
 #define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_MASK            0x0000001FU
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH                    5U
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_348
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1
 
 #define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_MASK           0x00001F00U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH				   5U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH                   5U
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_348
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1
 
 #define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_MASK         0x003F0000U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH                 6U
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_348
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1
 
-#define LPDDR4__DENALI_PHY_349_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_349_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_349_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_349
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1
 
 #define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_349
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_350_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_350_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_350_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_350
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1
 
 #define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_350
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_351_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_351_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_351_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_351
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1
 
 #define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_351
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_352_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_352_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_352_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_352
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1
 
 #define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH				10U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH                10U
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_352
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_353_READ_MASK				             0x000703FFU
-#define LPDDR4__DENALI_PHY_353_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_353_READ_MASK                             0x000703FFU
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK                            0x000703FFU
 #define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_MASK          0x000003FFU
-#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH                 10U
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_353
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1
 
@@ -1622,34 +1621,34 @@
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_353
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1
 
-#define LPDDR4__DENALI_PHY_354_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_354_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_354_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_MASK              0x000000FFU
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH                      8U
 #define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_354
 #define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1
 
 #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_MASK         0x0000FF00U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH                 8U
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_354
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1
 
 #define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_MASK         0x00FF0000U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT				16U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH                 8U
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_354
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1
 
 #define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_MASK             0xFF000000U
-#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH                     8U
 #define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_354
 #define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1
 
-#define LPDDR4__DENALI_PHY_355_READ_MASK				             0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_355_WRITE_MASK				            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_355_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK                            0xFFFFFF0FU
 #define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_SHIFT               0U
 #define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_WIDTH               4U
@@ -1657,118 +1656,118 @@
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1
 
 #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_MASK        0x0000FF00U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT				8U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH				8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH                8U
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_355
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1
 
 #define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_MASK          0x00FF0000U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH                  8U
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_355
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1
 
 #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_MASK        0xFF000000U
 #define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_SHIFT               24U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH				8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH                8U
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_355
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1
 
-#define LPDDR4__DENALI_PHY_356_READ_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_356_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_356_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK                            0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH				16U
+#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH                16U
 #define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_356
 #define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1
 
 #define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_MASK          0x0FFF0000U
-#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH				 12U
+#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH                 12U
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_356
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1
 
-#define LPDDR4__DENALI_PHY_357_READ_MASK				             0x03FFFF01U
-#define LPDDR4__DENALI_PHY_357_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_357_READ_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK                            0x03FFFF01U
 #define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_MASK        0x00000001U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT				0U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH				1U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR				0U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET				0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET                0U
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_357
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1
 
 #define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_MASK              0x0000FF00U
-#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH                      8U
 #define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_357
 #define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1
 
 #define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_MASK             0x00FF0000U
-#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH                     8U
 #define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_357
 #define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1
 
 #define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_MASK          0x03000000U
-#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH                  2U
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_357
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1
 
-#define LPDDR4__DENALI_PHY_358_READ_MASK				             0x1F1F0103U
-#define LPDDR4__DENALI_PHY_358_WRITE_MASK				            0x1F1F0103U
-#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK				   0x00000003U
-#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_358_READ_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK                            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH                           2U
 #define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_358
 #define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1
 
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK				  0x00000100U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT				          8U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET				          0U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK                  0x00000100U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET                          0U
 #define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_358
 #define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1
 
 #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_MASK        0x001F0000U
 #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT               16U
-#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH				5U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH                5U
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_358
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1
 
 #define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_MASK          0x1F000000U
-#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH				  5U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH                  5U
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_358
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1
 
-#define LPDDR4__DENALI_PHY_359_READ_MASK				             0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_359_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_359_READ_MASK                             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK                            0x3F07FF0FU
 #define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH                    4U
 #define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_359
 #define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1
 
 #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_MASK        0x0007FF00U
-#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT				8U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT                8U
 #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_WIDTH               11U
 #define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_359
 #define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1
 
 #define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_MASK         0x3F000000U
-#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT				24U
-#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH                 6U
 #define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_359
 #define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1
 
-#define LPDDR4__DENALI_PHY_360_READ_MASK				             0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_360_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_360_READ_MASK                             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK                            0xFF0FFFFFU
 #define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_MASK         0x000000FFU
-#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH                 8U
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_360
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1
 
@@ -1779,19 +1778,19 @@
 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1
 
 #define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_MASK               0x000F0000U
-#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH                       4U
 #define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_360
 #define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1
 
 #define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_MASK            0xFF000000U
-#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH                    8U
 #define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_360
 #define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1
 
-#define LPDDR4__DENALI_PHY_361_READ_MASK				             0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_361_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_361_READ_MASK                             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK                            0x1F0F3F0FU
 #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT               0U
 #define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH               4U
@@ -1805,8 +1804,8 @@
 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1
 
 #define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_MASK            0x000F0000U
-#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH                    4U
 #define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_361
 #define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1
 
@@ -1816,25 +1815,25 @@
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1
 
-#define LPDDR4__DENALI_PHY_362_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_362_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_362_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH                  10U
 #define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_362
 #define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1
 
 #define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH                 10U
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_362
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1
 
-#define LPDDR4__DENALI_PHY_363_READ_MASK				             0x0F010FFFU
-#define LPDDR4__DENALI_PHY_363_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_363_READ_MASK                             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK                            0x0F010FFFU
 #define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_MASK           0x000000FFU
-#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH                   8U
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_363
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1
 
@@ -1846,31 +1845,31 @@
 
 #define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_MASK        0x00010000U
 #define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT               16U
-#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH				1U
-#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR				0U
-#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET				0U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET                0U
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_363
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1
 
 #define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_MASK            0x0F000000U
-#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH                    4U
 #define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_363
 #define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1
 
-#define LPDDR4__DENALI_PHY_364_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_364_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_364_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_MASK            0x000003FFU
-#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH                   10U
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_364
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1
 
-#define LPDDR4__DENALI_PHY_365_READ_MASK				             0x3F0103FFU
-#define LPDDR4__DENALI_PHY_365_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_365_READ_MASK                             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK                            0x3F0103FFU
 #define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_MASK             0x000003FFU
-#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH				    10U
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH                    10U
 #define LPDDR4__PHY_RDLVL_DVW_MIN_1__REG DENALI_PHY_365
 #define LPDDR4__PHY_RDLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1
 
@@ -1888,8 +1887,8 @@
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__REG DENALI_PHY_365
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1
 
-#define LPDDR4__DENALI_PHY_366_READ_MASK				             0x00030703U
-#define LPDDR4__DENALI_PHY_366_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_366_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK                            0x00030703U
 #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_MASK       0x00000003U
 #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_SHIFT               0U
 #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_WIDTH               2U
@@ -1897,8 +1896,8 @@
 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1
 
 #define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT				8U
-#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH				3U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH                3U
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_366
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1
 
@@ -1908,8 +1907,8 @@
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_366
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1
 
-#define LPDDR4__DENALI_PHY_367_READ_MASK				             0x07FF03FFU
-#define LPDDR4__DENALI_PHY_367_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_367_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK                            0x07FF03FFU
 #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH       10U
@@ -1922,8 +1921,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_367
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1
 
-#define LPDDR4__DENALI_PHY_368_READ_MASK				             0xFFFF0101U
-#define LPDDR4__DENALI_PHY_368_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_368_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK                            0xFFFF0101U
 #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH              1U
@@ -1952,11 +1951,11 @@
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_368
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1
 
-#define LPDDR4__DENALI_PHY_369_READ_MASK				             0x001F3F7FU
-#define LPDDR4__DENALI_PHY_369_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_369_READ_MASK                             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK                            0x001F3F7FU
 #define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_MASK             0x0000007FU
-#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH				     7U
+#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH                     7U
 #define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_369
 #define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1
 
@@ -1967,29 +1966,29 @@
 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1
 
 #define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_MASK             0x001F0000U
-#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH                     5U
 #define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_369
 #define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1
 
-#define LPDDR4__DENALI_PHY_370_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_370_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_370_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH				   32U
+#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH                   32U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_370
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1
 
-#define LPDDR4__DENALI_PHY_371_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PHY_371_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_371_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK                            0x0000000FU
 #define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH                    4U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_371
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1
 
-#define LPDDR4__DENALI_PHY_372_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_372_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH            11U
@@ -2002,8 +2001,8 @@
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_372
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_373_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_373_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_373_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH            11U
@@ -2016,8 +2015,8 @@
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_373
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_374_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_374_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_374_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH            11U
@@ -2030,8 +2029,8 @@
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_374
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_375_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_375_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_375_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH            11U
@@ -2044,8 +2043,8 @@
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_375
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_376_READ_MASK				             0x03FF07FFU
-#define LPDDR4__DENALI_PHY_376_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_376_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK                            0x03FF07FFU
 #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK      0x000007FFU
 #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH             11U
@@ -2058,8 +2057,8 @@
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_376
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_377_READ_MASK				             0x0003FF03U
-#define LPDDR4__DENALI_PHY_377_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_377_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK                            0x0003FF03U
 #define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK    0x00000003U
 #define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH            2U
@@ -2072,8 +2071,8 @@
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_378_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_378_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2086,8 +2085,8 @@
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_379_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_379_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2100,8 +2099,8 @@
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_380_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_380_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2114,8 +2113,8 @@
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_381_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_381_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2128,8 +2127,8 @@
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_382_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_382_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2142,8 +2141,8 @@
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_383_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_383_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2156,8 +2155,8 @@
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_383
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_384_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_384_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_384_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_384_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2170,8 +2169,8 @@
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_384
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_385_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_385_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_385_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_385_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH       10U
@@ -2184,8 +2183,8 @@
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_385
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_386_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_386_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_386_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_386_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH        10U
@@ -2198,8 +2197,8 @@
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_386
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_387_READ_MASK				             0x03FF070FU
-#define LPDDR4__DENALI_PHY_387_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_387_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_387_WRITE_MASK                            0x03FF070FU
 #define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_MASK      0x0000000FU
 #define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT              0U
 #define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH              4U
@@ -2207,8 +2206,8 @@
 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1
 
 #define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT				8U
-#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH				3U
+#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH                3U
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_387
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1
 
@@ -2218,8 +2217,8 @@
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_387
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
 
-#define LPDDR4__DENALI_PHY_388_READ_MASK				             0x000103FFU
-#define LPDDR4__DENALI_PHY_388_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_388_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_388_WRITE_MASK                            0x000103FFU
 #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT      0U
 #define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH     10U
@@ -2234,8 +2233,8 @@
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_388
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1
 
-#define LPDDR4__DENALI_PHY_389_READ_MASK				             0x000F03FFU
-#define LPDDR4__DENALI_PHY_389_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_389_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_389_WRITE_MASK                            0x000F03FFU
 #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH        10U
@@ -2248,8 +2247,8 @@
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_389
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1
 
-#define LPDDR4__DENALI_PHY_390_READ_MASK				             0x010F07FFU
-#define LPDDR4__DENALI_PHY_390_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_390_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_390_WRITE_MASK                            0x010F07FFU
 #define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT         0U
 #define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH        11U
@@ -2257,29 +2256,29 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1
 
 #define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_MASK           0x000F0000U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH				   4U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH                   4U
 #define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_390
 #define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1
 
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK				  0x01000000U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT				         24U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET				          0U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET                          0U
 #define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_390
 #define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1
 
-#define LPDDR4__DENALI_PHY_391_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_391_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_391_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_391_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT      0U
 #define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH     10U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_391
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
 
-#define LPDDR4__DENALI_PHY_392_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_392_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_392_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_392_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH            8U
@@ -2304,8 +2303,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_392
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1
 
-#define LPDDR4__DENALI_PHY_393_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_393_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_393_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_393_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH            8U
@@ -2330,8 +2329,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_393
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1
 
-#define LPDDR4__DENALI_PHY_394_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_394_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_394_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_394_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH            8U
@@ -2350,23 +2349,23 @@
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_394
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
 
-#define LPDDR4__DENALI_PHY_395_READ_MASK				             0x0003033FU
-#define LPDDR4__DENALI_PHY_395_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_395_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_395_WRITE_MASK                            0x0003033FU
 #define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU
 #define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT        0U
 #define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH        6U
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_395
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
 
-#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK				    0x00000300U
-#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT				            8U
-#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH				            2U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH                            2U
 #define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_395
 #define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1
 
-#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK				   0x00030000U
-#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT				          16U
-#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH                           2U
 #define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_395
 #define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1
 
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
index 7c3756ca85..f6edad4eab 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
@@ -1,17 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
  *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
 #define REG_LPDDR4_DATA_SLICE_2_MACROS_H_
 
-#define LPDDR4__DENALI_PHY_512_READ_MASK				             0x000F07FFU
-#define LPDDR4__DENALI_PHY_512_WRITE_MASK				            0x000F07FFU
+#define LPDDR4__DENALI_PHY_512_READ_MASK                             0x000F07FFU
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK                            0x000F07FFU
 #define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH        11U
@@ -24,8 +23,8 @@
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_512
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2
 
-#define LPDDR4__DENALI_PHY_513_READ_MASK				             0x000703FFU
-#define LPDDR4__DENALI_PHY_513_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_513_READ_MASK                             0x000703FFU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK                            0x000703FFU
 #define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT      0U
 #define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH     10U
@@ -38,8 +37,8 @@
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2
 
-#define LPDDR4__DENALI_PHY_514_READ_MASK				             0x010303FFU
-#define LPDDR4__DENALI_PHY_514_WRITE_MASK				            0x010303FFU
+#define LPDDR4__DENALI_PHY_514_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK                            0x010303FFU
 #define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT     0U
 #define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH    10U
@@ -60,75 +59,75 @@
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2
 
-#define LPDDR4__DENALI_PHY_515_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_515_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK                            0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK            0x0000003FU
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK            0x00003F00U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK            0x003F0000U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK            0x3F000000U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2
 
-#define LPDDR4__DENALI_PHY_516_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_516_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK                            0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK            0x0000003FU
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK            0x00003F00U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK            0x003F0000U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK            0x3F000000U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2
 
-#define LPDDR4__DENALI_PHY_517_READ_MASK				             0x01030F3FU
-#define LPDDR4__DENALI_PHY_517_WRITE_MASK				            0x01030F3FU
+#define LPDDR4__DENALI_PHY_517_READ_MASK                             0x01030F3FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK                            0x01030F3FU
 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK             0x0000003FU
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH				     6U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH                     6U
 #define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517
 #define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK            0x00000F00U
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH                    4U
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2
 
 #define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK           0x00030000U
-#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH				   2U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH                   2U
 #define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517
 #define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2
 
@@ -140,8 +139,8 @@
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2
 
-#define LPDDR4__DENALI_PHY_518_READ_MASK				             0x1F1F0301U
-#define LPDDR4__DENALI_PHY_518_WRITE_MASK				            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518_READ_MASK                             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK                            0x1F1F0301U
 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK     0x00000001U
 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH             1U
@@ -168,8 +167,8 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2
 
-#define LPDDR4__DENALI_PHY_519_READ_MASK				             0x1F030F0FU
-#define LPDDR4__DENALI_PHY_519_WRITE_MASK				            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519_READ_MASK                             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK                            0x1F030F0FU
 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK      0x0000000FU
 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH              4U
@@ -194,17 +193,17 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2
 
-#define LPDDR4__DENALI_PHY_520_READ_MASK				             0x0101FF03U
-#define LPDDR4__DENALI_PHY_520_WRITE_MASK				            0x0101FF03U
+#define LPDDR4__DENALI_PHY_520_READ_MASK                             0x0101FF03U
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK                            0x0101FF03U
 #define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK              0x00000003U
-#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH				      2U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH                      2U
 #define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520
 #define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2
 
 #define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK              0x0001FF00U
-#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH				      9U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH                      9U
 #define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520
 #define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2
 
@@ -216,33 +215,33 @@
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2
 
-#define LPDDR4__DENALI_PHY_521_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_521_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH       32U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_521
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2
 
-#define LPDDR4__DENALI_PHY_522_READ_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_522_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_522_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK                            0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK    0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH           28U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_522
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2
 
-#define LPDDR4__DENALI_PHY_523_READ_MASK				             0x0101FF7FU
-#define LPDDR4__DENALI_PHY_523_WRITE_MASK				            0x0101FF7FU
+#define LPDDR4__DENALI_PHY_523_READ_MASK                             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK                            0x0101FF7FU
 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_MASK        0x0000007FU
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT				0U
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH				7U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH                7U
 #define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_523
 #define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2
 
 #define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_MASK         0x0001FF00U
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH				 9U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH                 9U
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_523
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2
 
@@ -254,8 +253,8 @@
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_523
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2
 
-#define LPDDR4__DENALI_PHY_524_READ_MASK				             0x007F3F01U
-#define LPDDR4__DENALI_PHY_524_WRITE_MASK				            0x007F3F01U
+#define LPDDR4__DENALI_PHY_524_READ_MASK                             0x007F3F01U
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK                            0x007F3F01U
 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT      0U
 #define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH      1U
@@ -271,13 +270,13 @@
 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2
 
 #define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_MASK            0x007F0000U
-#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH				    7U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH                    7U
 #define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_524
 #define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2
 
-#define LPDDR4__DENALI_PHY_525_READ_MASK				             0x000F03FFU
-#define LPDDR4__DENALI_PHY_525_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_525_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK                            0x000F03FFU
 #define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT       0U
 #define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH      10U
@@ -291,37 +290,37 @@
 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2
 
 #define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_MASK          0x01000000U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET				  0U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET                  0U
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_525
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2
 
-#define LPDDR4__DENALI_PHY_526_READ_MASK				             0x070101FFU
-#define LPDDR4__DENALI_PHY_526_WRITE_MASK				            0x070101FFU
+#define LPDDR4__DENALI_PHY_526_READ_MASK                             0x070101FFU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK                            0x070101FFU
 #define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK    0x000001FFU
 #define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH            9U
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_526
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK				     0x00010000U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT				            16U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH				             1U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR				             0U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET				             0U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK                     0x00010000U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT                            16U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET                             0U
 #define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_526
 #define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_526__PHY_LPDDR_2
 
-#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK				 0x07000000U
-#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT				        24U
-#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH				         3U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK                 0x07000000U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH                         3U
 #define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_526
 #define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2
 
-#define LPDDR4__DENALI_PHY_527_READ_MASK				             0x000301FFU
-#define LPDDR4__DENALI_PHY_527_WRITE_MASK				            0x000301FFU
+#define LPDDR4__DENALI_PHY_527_READ_MASK                             0x000301FFU
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK                            0x000301FFU
 #define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK    0x000001FFU
 #define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH            9U
@@ -329,101 +328,101 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2
 
 #define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_MASK         0x00030000U
-#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH				 2U
+#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH                 2U
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_527
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2
 
-#define LPDDR4__DENALI_PHY_528_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_528_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_528_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH				32U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH                32U
 #define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_528
 #define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2
 
-#define LPDDR4__DENALI_PHY_529_READ_MASK				             0x00000301U
-#define LPDDR4__DENALI_PHY_529_WRITE_MASK				            0x00000301U
+#define LPDDR4__DENALI_PHY_529_READ_MASK                             0x00000301U
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK                            0x00000301U
 #define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET				    0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET                    0U
 #define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_529
 #define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2
 
 #define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_MASK             0x00000300U
-#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT				     8U
-#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH                     2U
 #define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_529
 #define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2
 
-#define LPDDR4__DENALI_PHY_530_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_530_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_530
 #define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2
 
-#define LPDDR4__DENALI_PHY_531_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_531_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_531
 #define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2
 
-#define LPDDR4__DENALI_PHY_532_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_532_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_532
 #define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2
 
-#define LPDDR4__DENALI_PHY_533_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_533_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_533
 #define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2
 
-#define LPDDR4__DENALI_PHY_534_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_534_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_534
 #define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2
 
-#define LPDDR4__DENALI_PHY_535_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_535_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_535
 #define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2
 
-#define LPDDR4__DENALI_PHY_536_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_536_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_536
 #define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2
 
-#define LPDDR4__DENALI_PHY_537_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_537_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_537
 #define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2
 
-#define LPDDR4__DENALI_PHY_538_READ_MASK				             0x070F0107U
-#define LPDDR4__DENALI_PHY_538_WRITE_MASK				            0x070F0107U
+#define LPDDR4__DENALI_PHY_538_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK                            0x070F0107U
 #define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK     0x00000007U
 #define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH             3U
@@ -450,8 +449,8 @@
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_538
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2
 
-#define LPDDR4__DENALI_PHY_539_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_539_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_539_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK   0x0000000FU
 #define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT           0U
 #define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH           4U
@@ -459,8 +458,8 @@
 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2
 
 #define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_MASK         0x00000F00U
-#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH				 4U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH                 4U
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_539
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2
 
@@ -476,41 +475,41 @@
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_539
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2
 
-#define LPDDR4__DENALI_PHY_540_READ_MASK				             0xFF030001U
-#define LPDDR4__DENALI_PHY_540_WRITE_MASK				            0xFF030001U
+#define LPDDR4__DENALI_PHY_540_READ_MASK                             0xFF030001U
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK                            0xFF030001U
 #define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET				    0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET                    0U
 #define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_540
 #define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2
 
 #define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET				 0U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET                 0U
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_540
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2
 
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK				0x00030000U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH				        2U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH                        2U
 #define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_540
 #define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2
 
 #define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_MASK           0xFF000000U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH                   8U
 #define LPDDR4__PHY_WRLVL_PER_START_2__REG DENALI_PHY_540
 #define LPDDR4__PHY_WRLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2
 
-#define LPDDR4__DENALI_PHY_541_READ_MASK				             0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_541_WRITE_MASK				            0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_541_READ_MASK                             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK                            0x00FF0F3FU
 #define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_MASK         0x0000003FU
-#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH                 6U
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_541
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2
 
@@ -520,23 +519,23 @@
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_541
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2
 
-#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT				          16U
-#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH				           8U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH                           8U
 #define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_541
 #define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2
 
-#define LPDDR4__DENALI_PHY_542_READ_MASK				             0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_542_WRITE_MASK				            0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_542_READ_MASK                             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK                            0x0F3F03FFU
 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH                  10U
 #define LPDDR4__PHY_GTLVL_PER_START_2__REG DENALI_PHY_542
 #define LPDDR4__PHY_GTLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2
 
 #define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_MASK         0x003F0000U
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH                 6U
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_542
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2
 
@@ -546,11 +545,11 @@
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_542
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2
 
-#define LPDDR4__DENALI_PHY_543_READ_MASK				             0x1F030F3FU
-#define LPDDR4__DENALI_PHY_543_WRITE_MASK				            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_543_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK                            0x1F030F3FU
 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_MASK         0x0000003FU
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH                 6U
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_543
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2
 
@@ -561,8 +560,8 @@
 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2
 
 #define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_MASK             0x00030000U
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH                     2U
 #define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_543
 #define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2
 
@@ -572,8 +571,8 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_543
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2
 
-#define LPDDR4__DENALI_PHY_544_READ_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_544_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_544_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK                            0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_WIDTH         8U
@@ -581,8 +580,8 @@
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2
 
 #define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_MASK           0x0000FF00U
-#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH                   8U
 #define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_544
 #define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2
 
@@ -593,16 +592,16 @@
 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
 
 #define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_MASK          0x3F000000U
-#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH                  6U
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_544
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2
 
-#define LPDDR4__DENALI_PHY_545_READ_MASK				             0x0F07FF07U
-#define LPDDR4__DENALI_PHY_545_WRITE_MASK				            0x0F07FF07U
+#define LPDDR4__DENALI_PHY_545_READ_MASK                             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK                            0x0F07FF07U
 #define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_MASK               0x00000007U
-#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH				       3U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH                       3U
 #define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_545
 #define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2
 
@@ -618,8 +617,8 @@
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_545
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2
 
-#define LPDDR4__DENALI_PHY_546_READ_MASK				             0x0000FF0FU
-#define LPDDR4__DENALI_PHY_546_WRITE_MASK				            0x0000FF0FU
+#define LPDDR4__DENALI_PHY_546_READ_MASK                             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK                            0x0000FF0FU
 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK    0x0000000FU
 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH            4U
@@ -640,64 +639,64 @@
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_546
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2
 
-#define LPDDR4__DENALI_PHY_547_READ_MASK				             0x000001FFU
-#define LPDDR4__DENALI_PHY_547_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_547_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK                            0x000001FFU
 #define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_MASK        0x000001FFU
-#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT				0U
-#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH				9U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH                9U
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_547
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2
 
-#define LPDDR4__DENALI_PHY_548_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_548_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_548_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_548
 #define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2
 
-#define LPDDR4__DENALI_PHY_549_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_549_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_549_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_549
 #define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2
 
-#define LPDDR4__DENALI_PHY_550_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_550_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_550_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_550
 #define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2
 
-#define LPDDR4__DENALI_PHY_551_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_551_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_551_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_551
 #define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2
 
-#define LPDDR4__DENALI_PHY_552_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PHY_552_WRITE_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH				       16U
+#define LPDDR4__DENALI_PHY_552_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH                       16U
 #define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_552
 #define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2
 
 #define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_MASK            0x00010000U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET				    0U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET                    0U
 #define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_552
 #define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2
 
-#define LPDDR4__DENALI_PHY_553_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_553_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_553_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_MASK       0x000003FFU
 #define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_SHIFT               0U
 #define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_WIDTH              10U
@@ -710,8 +709,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_553
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2
 
-#define LPDDR4__DENALI_PHY_554_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_554_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_554_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK  0x000003FFU
 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT          0U
 #define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH         10U
@@ -724,8 +723,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_554
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2
 
-#define LPDDR4__DENALI_PHY_555_READ_MASK				             0x00FF0001U
-#define LPDDR4__DENALI_PHY_555_WRITE_MASK				            0x00FF0001U
+#define LPDDR4__DENALI_PHY_555_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_555_WRITE_MASK                            0x00FF0001U
 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK  0x00000001U
 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT          0U
 #define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH          1U
@@ -735,27 +734,27 @@
 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2
 
 #define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_MASK           0x00003F00U
-#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH				   6U
+#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH                   6U
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_555
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2
 
 #define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_MASK              0x00FF0000U
-#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH                      8U
 #define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_555
 #define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2
 
-#define LPDDR4__DENALI_PHY_556_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_556_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_556_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_556_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH				  32U
+#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH                  32U
 #define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_556
 #define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2
 
-#define LPDDR4__DENALI_PHY_557_READ_MASK				             0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_557_WRITE_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_557_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_557_WRITE_MASK                            0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_MASK      0x0000FFFFU
 #define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH             16U
@@ -768,8 +767,8 @@
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_557
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2
 
-#define LPDDR4__DENALI_PHY_558_READ_MASK				             0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_558_WRITE_MASK				            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_558_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_558_WRITE_MASK                            0xFFFF7F7FU
 #define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK      0x0000007FU
 #define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH              7U
@@ -794,8 +793,8 @@
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2
 
-#define LPDDR4__DENALI_PHY_559_READ_MASK				             0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_559_WRITE_MASK				            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_559_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_559_WRITE_MASK                            0x7F07FFFFU
 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U
 #define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
@@ -814,8 +813,8 @@
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2
 
-#define LPDDR4__DENALI_PHY_560_READ_MASK				             0x0007FFFFU
-#define LPDDR4__DENALI_PHY_560_WRITE_MASK				            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_560_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_560_WRITE_MASK                            0x0007FFFFU
 #define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH         8U
@@ -829,13 +828,13 @@
 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2
 
 #define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_MASK              0x00070000U
-#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH				      3U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH                      3U
 #define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_560
 #define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2
 
-#define LPDDR4__DENALI_PHY_561_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_561_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_561_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_561_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK     0x000003FFU
 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH            10U
@@ -848,16 +847,16 @@
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_561
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2
 
-#define LPDDR4__DENALI_PHY_562_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PHY_562_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_562_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_562_WRITE_MASK                            0x0001FFFFU
 #define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_MASK          0x0001FFFFU
-#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH				 17U
+#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH                 17U
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_562
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2
 
-#define LPDDR4__DENALI_PHY_563_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_563_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH       10U
@@ -870,11 +869,11 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2
 
-#define LPDDR4__DENALI_PHY_564_READ_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_564_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_564_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_564_WRITE_MASK                            0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH				  16U
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH                  16U
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_564
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2
 
@@ -884,24 +883,24 @@
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_564
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2
 
-#define LPDDR4__DENALI_PHY_565_READ_MASK				             0x00003FFFU
-#define LPDDR4__DENALI_PHY_565_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_565_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_565_WRITE_MASK                            0x00003FFFU
 #define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK     0x00003FFFU
 #define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH            14U
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_565
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2
 
-#define LPDDR4__DENALI_PHY_566_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_566_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_566_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_566_WRITE_MASK                            0x0003FFFFU
 #define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_MASK          0x0003FFFFU
-#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH				 18U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH                 18U
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_566
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2
 
-#define LPDDR4__DENALI_PHY_567_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_567_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_567_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_567_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH        10U
@@ -914,32 +913,32 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_567
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2
 
-#define LPDDR4__DENALI_PHY_568_READ_MASK				             0x00000003U
-#define LPDDR4__DENALI_PHY_568_WRITE_MASK				            0x00000003U
+#define LPDDR4__DENALI_PHY_568_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_568_WRITE_MASK                            0x00000003U
 #define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U
 #define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT    0U
 #define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH    2U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_568
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2
 
-#define LPDDR4__DENALI_PHY_569_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_569_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_569_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_569_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH				 32U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH                 32U
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_569
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2
 
-#define LPDDR4__DENALI_PHY_570_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_570_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_570_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_570_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT                0U
 #define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_WIDTH               32U
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__REG DENALI_PHY_570
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2
 
-#define LPDDR4__DENALI_PHY_571_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_571_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_571_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_571_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK    0x000007FFU
 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH           11U
@@ -952,56 +951,56 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_571
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2
 
-#define LPDDR4__DENALI_PHY_572_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_572_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_572_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_572_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH				32U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH                32U
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_572
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2
 
-#define LPDDR4__DENALI_PHY_573_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_573_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT               0U
 #define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH              32U
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_573
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2
 
-#define LPDDR4__DENALI_PHY_574_READ_MASK				             0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_574_WRITE_MASK				            0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK				  0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH				         31U
+#define LPDDR4__DENALI_PHY_574_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH                         31U
 #define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_574
 #define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2
 
-#define LPDDR4__DENALI_PHY_575_READ_MASK				             0x0000003FU
-#define LPDDR4__DENALI_PHY_575_WRITE_MASK				            0x0000003FU
-#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK				  0x0000003FU
-#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH				          6U
+#define LPDDR4__DENALI_PHY_575_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_575_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH                          6U
 #define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_575
 #define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2
 
-#define LPDDR4__DENALI_PHY_576_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_576_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_576_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_576_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH                     32U
 #define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_576
 #define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2
 
-#define LPDDR4__DENALI_PHY_577_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_577_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK     0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH            32U
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_577
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2
 
-#define LPDDR4__DENALI_PHY_578_READ_MASK				             0x010001FFU
-#define LPDDR4__DENALI_PHY_578_WRITE_MASK				            0x010001FFU
+#define LPDDR4__DENALI_PHY_578_READ_MASK                             0x010001FFU
+#define LPDDR4__DENALI_PHY_578_WRITE_MASK                            0x010001FFU
 #define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK   0x000000FFU
 #define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT           0U
 #define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH           8U
@@ -1009,34 +1008,34 @@
 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2
 
 #define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_MASK        0x00000100U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT				8U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH				1U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR				0U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET				0U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH                1U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR                0U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET                0U
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_578
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2
 
 #define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_MASK           0x00010000U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET				   0U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET                   0U
 #define LPDDR4__SC_PHY_RX_CAL_START_2__REG DENALI_PHY_578
 #define LPDDR4__SC_PHY_RX_CAL_START_2__FLD LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2
 
 #define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET				   0U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET                   0U
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_2__REG DENALI_PHY_578
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2
 
-#define LPDDR4__DENALI_PHY_579_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_579_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579_WRITE_MASK                            0x01FF01FFU
 #define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_MASK        0x000000FFU
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT				0U
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH				8U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH                8U
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_579
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2
 
@@ -1048,147 +1047,147 @@
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__REG DENALI_PHY_579
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__FLD LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2
 
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579
 #define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2
 
-#define LPDDR4__DENALI_PHY_580_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_580_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_580_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580
 #define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2
 
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580
 #define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2
 
-#define LPDDR4__DENALI_PHY_581_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_581_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_581_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581
 #define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2
 
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581
 #define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2
 
-#define LPDDR4__DENALI_PHY_582_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_582_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_582_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582
 #define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2
 
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582
 #define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2
 
-#define LPDDR4__DENALI_PHY_583_READ_MASK				             0x000001FFU
-#define LPDDR4__DENALI_PHY_583_WRITE_MASK				            0x000001FFU
-#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_583_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_583_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583
 #define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2
 
-#define LPDDR4__DENALI_PHY_584_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_584_WRITE_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK				 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH				        18U
+#define LPDDR4__DENALI_PHY_584_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH                        18U
 #define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584
 #define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2
 
-#define LPDDR4__DENALI_PHY_585_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_585_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_585_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585
 #define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2
 
 #define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK               0x01FF0000U
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH				       9U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH                       9U
 #define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585
 #define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2
 
-#define LPDDR4__DENALI_PHY_586_READ_MASK				             0x01FF07FFU
-#define LPDDR4__DENALI_PHY_586_WRITE_MASK				            0x01FF07FFU
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK				0x000007FFU
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH				       11U
+#define LPDDR4__DENALI_PHY_586_READ_MASK                             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_586_WRITE_MASK                            0x01FF07FFU
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK                0x000007FFU
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH                       11U
 #define LPDDR4__PHY_RX_CAL_OBS_2__REG DENALI_PHY_586
 #define LPDDR4__PHY_RX_CAL_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2
 
 #define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_MASK           0x01FF0000U
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH				   9U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH                   9U
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__REG DENALI_PHY_586
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2
 
-#define LPDDR4__DENALI_PHY_587_READ_MASK				             0x017F7F01U
-#define LPDDR4__DENALI_PHY_587_WRITE_MASK				            0x017F7F01U
+#define LPDDR4__DENALI_PHY_587_READ_MASK                             0x017F7F01U
+#define LPDDR4__DENALI_PHY_587_WRITE_MASK                            0x017F7F01U
 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET				    0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET                    0U
 #define LPDDR4__PHY_RX_CAL_DISABLE_2__REG DENALI_PHY_587
 #define LPDDR4__PHY_RX_CAL_DISABLE_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2
 
 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_MASK          0x00007F00U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH				  7U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH                  7U
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__REG DENALI_PHY_587
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2
 
 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_MASK        0x007F0000U
 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_SHIFT               16U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH				7U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH                7U
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__REG DENALI_PHY_587
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2
 
 #define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET				   0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET                   0U
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_2__REG DENALI_PHY_587
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2
 
-#define LPDDR4__DENALI_PHY_588_READ_MASK				             0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_588_WRITE_MASK				            0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_588_READ_MASK                             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_588_WRITE_MASK                            0x07FF0FFFU
 #define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_MASK         0x00000FFFU
-#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH				12U
+#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH                12U
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__REG DENALI_PHY_588
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__FLD LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2
 
 #define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_MASK            0x07FF0000U
-#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH				   11U
+#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH                   11U
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_588
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2
 
-#define LPDDR4__DENALI_PHY_589_READ_MASK				             0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_589_WRITE_MASK				            0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_589_READ_MASK                             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_589_WRITE_MASK                            0x03FFFF1FU
 #define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_MASK        0x0000001FU
-#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT				0U
-#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH				5U
+#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH                5U
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_589
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2
 
@@ -1205,13 +1204,13 @@
 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2
 
 #define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_MASK            0x03000000U
-#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH				    2U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH                    2U
 #define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_589
 #define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2
 
-#define LPDDR4__DENALI_PHY_590_READ_MASK				             0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_590_WRITE_MASK				            0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_590_READ_MASK                             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_590_WRITE_MASK                            0x01FFFF3FU
 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_MASK      0x0000003FU
 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_WIDTH              6U
@@ -1238,8 +1237,8 @@
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_590
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2
 
-#define LPDDR4__DENALI_PHY_591_READ_MASK				             0x07030101U
-#define LPDDR4__DENALI_PHY_591_WRITE_MASK				            0x07030101U
+#define LPDDR4__DENALI_PHY_591_READ_MASK                             0x07030101U
+#define LPDDR4__DENALI_PHY_591_WRITE_MASK                            0x07030101U
 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WIDTH              1U
@@ -1249,27 +1248,27 @@
 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2
 
 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET				 0U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET                 0U
 #define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_591
 #define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2
 
 #define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_MASK           0x00030000U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH				   2U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH                   2U
 #define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_591
 #define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2
 
 #define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_MASK             0x07000000U
-#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH				     3U
+#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH                     3U
 #define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_591
 #define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2
 
-#define LPDDR4__DENALI_PHY_592_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_PHY_592_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_PHY_592_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_PHY_592_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH         1U
@@ -1302,22 +1301,22 @@
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_592
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2
 
-#define LPDDR4__DENALI_PHY_593_READ_MASK				             0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_593_WRITE_MASK				            0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_593_READ_MASK                             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_593_WRITE_MASK                            0x3FFF07FFU
 #define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_MASK        0x000007FFU
-#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT				0U
+#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT                0U
 #define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_WIDTH               11U
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_2__REG DENALI_PHY_593
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_2__FLD LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2
 
 #define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_MASK         0x3FFF0000U
-#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH				14U
+#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH                14U
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__REG DENALI_PHY_593
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2
 
-#define LPDDR4__DENALI_PHY_594_READ_MASK				             0x00003FFFU
-#define LPDDR4__DENALI_PHY_594_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_594_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_594_WRITE_MASK                            0x00003FFFU
 #define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_MASK    0x00003FFFU
 #define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_WIDTH           14U
@@ -1330,8 +1329,8 @@
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__REG DENALI_PHY_594
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2
 
-#define LPDDR4__DENALI_PHY_595_READ_MASK				             0x00001F1FU
-#define LPDDR4__DENALI_PHY_595_WRITE_MASK				            0x00001F1FU
+#define LPDDR4__DENALI_PHY_595_READ_MASK                             0x00001F1FU
+#define LPDDR4__DENALI_PHY_595_WRITE_MASK                            0x00001F1FU
 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_MASK 0x0000001FU
 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_WIDTH         5U
@@ -1350,37 +1349,37 @@
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__REG DENALI_PHY_595
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2
 
-#define LPDDR4__DENALI_PHY_596_READ_MASK				             0x07FFFF07U
-#define LPDDR4__DENALI_PHY_596_WRITE_MASK				            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_596_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_596_WRITE_MASK                            0x07FFFF07U
 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_MASK            0x00000007U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH				    3U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH                    3U
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_596
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2
 
 #define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_MASK            0x00FFFF00U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH				   16U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH                   16U
 #define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_596
 #define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2
 
 #define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_MASK           0x07000000U
-#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH				   3U
+#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH                   3U
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_596
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2
 
-#define LPDDR4__DENALI_PHY_597_READ_MASK				             0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_597_WRITE_MASK				            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_597_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_597_WRITE_MASK                            0x7F03FFFFU
 #define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH				  16U
+#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH                  16U
 #define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_597
 #define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2
 
 #define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_MASK          0x00030000U
-#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH                  2U
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_597
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2
 
@@ -1390,8 +1389,8 @@
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_597
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2
 
-#define LPDDR4__DENALI_PHY_598_READ_MASK				             0xFF01037FU
-#define LPDDR4__DENALI_PHY_598_WRITE_MASK				            0xFF01037FU
+#define LPDDR4__DENALI_PHY_598_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_598_WRITE_MASK                            0xFF01037FU
 #define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_MASK   0x0000007FU
 #define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT           0U
 #define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH           7U
@@ -1399,50 +1398,50 @@
 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2
 
 #define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_MASK        0x00000300U
-#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT				8U
-#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH				2U
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH                2U
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_598
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2
 
 #define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_MASK              0x00010000U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH				      1U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR				      0U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET				      0U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET                      0U
 #define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_598
 #define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2
 
 #define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_MASK         0xFF000000U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT				24U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH                 8U
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_598
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2
 
-#define LPDDR4__DENALI_PHY_599_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_599_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_599_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_599_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_MASK             0x000007FFU
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH				    11U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH                    11U
 #define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_599
 #define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2
 
 #define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_MASK              0x07FF0000U
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH				     11U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH                     11U
 #define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_599
 #define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2
 
-#define LPDDR4__DENALI_PHY_600_READ_MASK				             0x0103FFFFU
-#define LPDDR4__DENALI_PHY_600_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_600_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_600_WRITE_MASK                            0x0103FFFFU
 #define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_MASK            0x000000FFU
-#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH                    8U
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_600
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2
 
 #define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_MASK            0x0003FF00U
-#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH                   10U
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_600
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2
 
@@ -1454,8 +1453,8 @@
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_600
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2
 
-#define LPDDR4__DENALI_PHY_601_READ_MASK				             0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_601_WRITE_MASK				            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_601_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_601_WRITE_MASK                            0x1F1F0F3FU
 #define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_MASK   0x0000003FU
 #define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT           0U
 #define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH           6U
@@ -1463,156 +1462,156 @@
 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2
 
 #define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_MASK               0x00000F00U
-#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT				       8U
-#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH                       4U
 #define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_601
 #define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2
 
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK				0x001F0000U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH				        5U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH                        5U
 #define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_601
 #define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2
 
 #define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_MASK              0x1F000000U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_601
 #define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2
 
-#define LPDDR4__DENALI_PHY_602_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_602_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_602_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_602_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_MASK              0x0000001FU
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_602
 #define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2
 
 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_MASK              0x00001F00U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_602
 #define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2
 
 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_MASK              0x001F0000U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_602
 #define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2
 
 #define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_MASK              0x1F000000U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_602
 #define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2
 
-#define LPDDR4__DENALI_PHY_603_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_603_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_603_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_603_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_MASK              0x0000001FU
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_603
 #define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2
 
 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_MASK              0x00001F00U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_603
 #define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2
 
 #define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_MASK              0x001F0000U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_603
 #define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2
 
 #define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_MASK             0x1F000000U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH                     5U
 #define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_603
 #define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2
 
-#define LPDDR4__DENALI_PHY_604_READ_MASK				             0x003F1F1FU
-#define LPDDR4__DENALI_PHY_604_WRITE_MASK				            0x003F1F1FU
+#define LPDDR4__DENALI_PHY_604_READ_MASK                             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_604_WRITE_MASK                            0x003F1F1FU
 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_MASK            0x0000001FU
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH                    5U
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_604
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2
 
 #define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_MASK           0x00001F00U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH				   5U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH                   5U
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_604
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2
 
 #define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_MASK         0x003F0000U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH                 6U
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_604
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2
 
-#define LPDDR4__DENALI_PHY_605_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_605_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_605_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_605_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_605
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2
 
 #define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_605
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_606_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_606_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_606_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_606_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_606
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2
 
 #define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_606
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_607_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_607_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_607_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_607_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_607
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2
 
 #define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_607
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_608_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_608_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_608_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_608_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_608
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2
 
 #define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH				10U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH                10U
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_608
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_609_READ_MASK				             0x000703FFU
-#define LPDDR4__DENALI_PHY_609_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_609_READ_MASK                             0x000703FFU
+#define LPDDR4__DENALI_PHY_609_WRITE_MASK                            0x000703FFU
 #define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_MASK          0x000003FFU
-#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH                 10U
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_609
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2
 
@@ -1622,34 +1621,34 @@
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_609
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2
 
-#define LPDDR4__DENALI_PHY_610_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_610_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_610_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_610_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_MASK              0x000000FFU
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH                      8U
 #define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_610
 #define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2
 
 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_MASK         0x0000FF00U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH                 8U
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_610
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2
 
 #define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_MASK         0x00FF0000U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT				16U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH                 8U
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_610
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2
 
 #define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_MASK             0xFF000000U
-#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH                     8U
 #define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_610
 #define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2
 
-#define LPDDR4__DENALI_PHY_611_READ_MASK				             0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_611_WRITE_MASK				            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_611_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_611_WRITE_MASK                            0xFFFFFF0FU
 #define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_SHIFT               0U
 #define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_WIDTH               4U
@@ -1657,118 +1656,118 @@
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2
 
 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_MASK        0x0000FF00U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT				8U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH				8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH                8U
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_611
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2
 
 #define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_MASK          0x00FF0000U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH                  8U
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_611
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2
 
 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_MASK        0xFF000000U
 #define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_SHIFT               24U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH				8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH                8U
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_611
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2
 
-#define LPDDR4__DENALI_PHY_612_READ_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_612_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_612_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_612_WRITE_MASK                            0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH				16U
+#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH                16U
 #define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_612
 #define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2
 
 #define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_MASK          0x0FFF0000U
-#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH				 12U
+#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH                 12U
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_612
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2
 
-#define LPDDR4__DENALI_PHY_613_READ_MASK				             0x03FFFF01U
-#define LPDDR4__DENALI_PHY_613_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_613_READ_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_613_WRITE_MASK                            0x03FFFF01U
 #define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_MASK        0x00000001U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT				0U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH				1U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR				0U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET				0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH                1U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR                0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET                0U
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_613
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2
 
 #define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_MASK              0x0000FF00U
-#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH                      8U
 #define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_613
 #define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2
 
 #define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_MASK             0x00FF0000U
-#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH                     8U
 #define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_613
 #define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2
 
 #define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_MASK          0x03000000U
-#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH                  2U
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_613
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2
 
-#define LPDDR4__DENALI_PHY_614_READ_MASK				             0x1F1F0103U
-#define LPDDR4__DENALI_PHY_614_WRITE_MASK				            0x1F1F0103U
-#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK				   0x00000003U
-#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_614_READ_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_614_WRITE_MASK                            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH                           2U
 #define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_614
 #define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2
 
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK				  0x00000100U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT				          8U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET				          0U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK                  0x00000100U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET                          0U
 #define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_614
 #define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2
 
 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_MASK        0x001F0000U
 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT               16U
-#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH				5U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH                5U
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_614
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2
 
 #define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_MASK          0x1F000000U
-#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH				  5U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH                  5U
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_614
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2
 
-#define LPDDR4__DENALI_PHY_615_READ_MASK				             0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_615_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_615_READ_MASK                             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_615_WRITE_MASK                            0x3F07FF0FU
 #define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH                    4U
 #define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_615
 #define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2
 
 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_MASK        0x0007FF00U
-#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT				8U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT                8U
 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_WIDTH               11U
 #define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_615
 #define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2
 
 #define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_MASK         0x3F000000U
-#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT				24U
-#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH                 6U
 #define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_615
 #define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2
 
-#define LPDDR4__DENALI_PHY_616_READ_MASK				             0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_616_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_616_READ_MASK                             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_616_WRITE_MASK                            0xFF0FFFFFU
 #define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_MASK         0x000000FFU
-#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH                 8U
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_616
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2
 
@@ -1779,19 +1778,19 @@
 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2
 
 #define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_MASK               0x000F0000U
-#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH                       4U
 #define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_616
 #define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2
 
 #define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_MASK            0xFF000000U
-#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH                    8U
 #define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_616
 #define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2
 
-#define LPDDR4__DENALI_PHY_617_READ_MASK				             0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_617_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_617_READ_MASK                             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_617_WRITE_MASK                            0x1F0F3F0FU
 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT               0U
 #define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH               4U
@@ -1805,8 +1804,8 @@
 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2
 
 #define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_MASK            0x000F0000U
-#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH                    4U
 #define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_617
 #define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2
 
@@ -1816,25 +1815,25 @@
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2
 
-#define LPDDR4__DENALI_PHY_618_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_618_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_618_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_618_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH                  10U
 #define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_618
 #define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2
 
 #define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH                 10U
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_618
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2
 
-#define LPDDR4__DENALI_PHY_619_READ_MASK				             0x0F010FFFU
-#define LPDDR4__DENALI_PHY_619_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_619_READ_MASK                             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_619_WRITE_MASK                            0x0F010FFFU
 #define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_MASK           0x000000FFU
-#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH                   8U
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_619
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2
 
@@ -1846,31 +1845,31 @@
 
 #define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_MASK        0x00010000U
 #define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT               16U
-#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH				1U
-#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR				0U
-#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET				0U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH                1U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR                0U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET                0U
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_619
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2
 
 #define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_MASK            0x0F000000U
-#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH                    4U
 #define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_619
 #define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2
 
-#define LPDDR4__DENALI_PHY_620_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_620_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_620_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_620_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_MASK            0x000003FFU
-#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH                   10U
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_620
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2
 
-#define LPDDR4__DENALI_PHY_621_READ_MASK				             0x3F0103FFU
-#define LPDDR4__DENALI_PHY_621_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_621_READ_MASK                             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_621_WRITE_MASK                            0x3F0103FFU
 #define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_MASK             0x000003FFU
-#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH				    10U
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH                    10U
 #define LPDDR4__PHY_RDLVL_DVW_MIN_2__REG DENALI_PHY_621
 #define LPDDR4__PHY_RDLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2
 
@@ -1888,8 +1887,8 @@
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__REG DENALI_PHY_621
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2
 
-#define LPDDR4__DENALI_PHY_622_READ_MASK				             0x00030703U
-#define LPDDR4__DENALI_PHY_622_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_622_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_622_WRITE_MASK                            0x00030703U
 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_MASK       0x00000003U
 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_SHIFT               0U
 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_WIDTH               2U
@@ -1897,8 +1896,8 @@
 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2
 
 #define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT				8U
-#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH				3U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH                3U
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_622
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2
 
@@ -1908,8 +1907,8 @@
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_622
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2
 
-#define LPDDR4__DENALI_PHY_623_READ_MASK				             0x07FF03FFU
-#define LPDDR4__DENALI_PHY_623_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_623_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_623_WRITE_MASK                            0x07FF03FFU
 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH       10U
@@ -1922,8 +1921,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_623
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2
 
-#define LPDDR4__DENALI_PHY_624_READ_MASK				             0xFFFF0101U
-#define LPDDR4__DENALI_PHY_624_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_624_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_624_WRITE_MASK                            0xFFFF0101U
 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH              1U
@@ -1952,11 +1951,11 @@
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_624
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2
 
-#define LPDDR4__DENALI_PHY_625_READ_MASK				             0x001F3F7FU
-#define LPDDR4__DENALI_PHY_625_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_625_READ_MASK                             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_625_WRITE_MASK                            0x001F3F7FU
 #define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_MASK             0x0000007FU
-#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH				     7U
+#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH                     7U
 #define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_625
 #define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2
 
@@ -1967,29 +1966,29 @@
 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2
 
 #define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_MASK             0x001F0000U
-#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH                     5U
 #define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_625
 #define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2
 
-#define LPDDR4__DENALI_PHY_626_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_626_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_626_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_626_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH				   32U
+#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH                   32U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_626
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2
 
-#define LPDDR4__DENALI_PHY_627_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PHY_627_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_627_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_627_WRITE_MASK                            0x0000000FU
 #define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH                    4U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_627
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2
 
-#define LPDDR4__DENALI_PHY_628_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_628_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH            11U
@@ -2002,8 +2001,8 @@
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_628
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_629_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_629_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_629_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_629_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH            11U
@@ -2016,8 +2015,8 @@
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_629
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_630_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_630_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_630_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_630_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH            11U
@@ -2030,8 +2029,8 @@
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_630
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_631_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_631_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_631_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_631_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT             0U
 #define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH            11U
@@ -2044,8 +2043,8 @@
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_631
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_632_READ_MASK				             0x03FF07FFU
-#define LPDDR4__DENALI_PHY_632_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_632_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_632_WRITE_MASK                            0x03FF07FFU
 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK      0x000007FFU
 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH             11U
@@ -2058,8 +2057,8 @@
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_632
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_633_READ_MASK				             0x0003FF03U
-#define LPDDR4__DENALI_PHY_633_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_633_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_633_WRITE_MASK                            0x0003FF03U
 #define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK    0x00000003U
 #define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH            2U
@@ -2072,8 +2071,8 @@
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_634_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_634_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2086,8 +2085,8 @@
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_635_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_635_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2100,8 +2099,8 @@
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_636_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_636_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2114,8 +2113,8 @@
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_637_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_637_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2128,8 +2127,8 @@
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_638_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_638_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2142,8 +2141,8 @@
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_639_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_639_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2156,8 +2155,8 @@
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_639
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_640_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_640_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_640_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_640_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2170,8 +2169,8 @@
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_640
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_641_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_641_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_641_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_641_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH       10U
@@ -2184,8 +2183,8 @@
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_641
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_642_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_642_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_642_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_642_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH        10U
@@ -2198,8 +2197,8 @@
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_642
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2
 
-#define LPDDR4__DENALI_PHY_643_READ_MASK				             0x03FF070FU
-#define LPDDR4__DENALI_PHY_643_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_643_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_643_WRITE_MASK                            0x03FF070FU
 #define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_MASK      0x0000000FU
 #define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT              0U
 #define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH              4U
@@ -2207,8 +2206,8 @@
 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2
 
 #define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT				8U
-#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH				3U
+#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT                8U
+#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH                3U
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_643
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2
 
@@ -2218,8 +2217,8 @@
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_643
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2
 
-#define LPDDR4__DENALI_PHY_644_READ_MASK				             0x000103FFU
-#define LPDDR4__DENALI_PHY_644_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_644_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_644_WRITE_MASK                            0x000103FFU
 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT      0U
 #define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH     10U
@@ -2234,8 +2233,8 @@
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_644
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2
 
-#define LPDDR4__DENALI_PHY_645_READ_MASK				             0x000F03FFU
-#define LPDDR4__DENALI_PHY_645_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_645_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_645_WRITE_MASK                            0x000F03FFU
 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH        10U
@@ -2248,8 +2247,8 @@
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_645
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2
 
-#define LPDDR4__DENALI_PHY_646_READ_MASK				             0x010F07FFU
-#define LPDDR4__DENALI_PHY_646_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_646_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_646_WRITE_MASK                            0x010F07FFU
 #define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT         0U
 #define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH        11U
@@ -2257,29 +2256,29 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2
 
 #define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_MASK           0x000F0000U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH				   4U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH                   4U
 #define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_646
 #define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2
 
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK				  0x01000000U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT				         24U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET				          0U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET                          0U
 #define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_646
 #define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2
 
-#define LPDDR4__DENALI_PHY_647_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_647_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_647_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_647_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT      0U
 #define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH     10U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_647
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2
 
-#define LPDDR4__DENALI_PHY_648_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_648_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_648_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_648_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH            8U
@@ -2304,8 +2303,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_648
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2
 
-#define LPDDR4__DENALI_PHY_649_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_649_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_649_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_649_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH            8U
@@ -2330,8 +2329,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_649
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2
 
-#define LPDDR4__DENALI_PHY_650_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_650_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_650_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_650_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT            0U
 #define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH            8U
@@ -2350,23 +2349,23 @@
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_650
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2
 
-#define LPDDR4__DENALI_PHY_651_READ_MASK				             0x0003033FU
-#define LPDDR4__DENALI_PHY_651_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_651_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_651_WRITE_MASK                            0x0003033FU
 #define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU
 #define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT        0U
 #define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH        6U
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_651
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2
 
-#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK				    0x00000300U
-#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT				            8U
-#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH				            2U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH                            2U
 #define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_651
 #define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2
 
-#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK				   0x00030000U
-#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT				          16U
-#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH                           2U
 #define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_651
 #define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2
 
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
index bfde51d358..73e5f71df9 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
@@ -1,17 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
  *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
 #define REG_LPDDR4_DATA_SLICE_3_MACROS_H_
 
-#define LPDDR4__DENALI_PHY_768_READ_MASK				             0x000F07FFU
-#define LPDDR4__DENALI_PHY_768_WRITE_MASK				            0x000F07FFU
+#define LPDDR4__DENALI_PHY_768_READ_MASK                             0x000F07FFU
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK                            0x000F07FFU
 #define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH        11U
@@ -24,8 +23,8 @@
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_768
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3
 
-#define LPDDR4__DENALI_PHY_769_READ_MASK				             0x000703FFU
-#define LPDDR4__DENALI_PHY_769_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_769_READ_MASK                             0x000703FFU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK                            0x000703FFU
 #define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT      0U
 #define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH     10U
@@ -38,8 +37,8 @@
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3
 
-#define LPDDR4__DENALI_PHY_770_READ_MASK				             0x010303FFU
-#define LPDDR4__DENALI_PHY_770_WRITE_MASK				            0x010303FFU
+#define LPDDR4__DENALI_PHY_770_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK                            0x010303FFU
 #define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT     0U
 #define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH    10U
@@ -60,75 +59,75 @@
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770
 #define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3
 
-#define LPDDR4__DENALI_PHY_771_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_771_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK                            0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK            0x0000003FU
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771
 #define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK            0x00003F00U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771
 #define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK            0x003F0000U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771
 #define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK            0x3F000000U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771
 #define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3
 
-#define LPDDR4__DENALI_PHY_772_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_772_WRITE_MASK				            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK                            0x3F3F3F3FU
 #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK            0x0000003FU
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772
 #define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK            0x00003F00U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772
 #define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK            0x003F0000U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772
 #define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK            0x3F000000U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH				    6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH                    6U
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772
 #define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3
 
-#define LPDDR4__DENALI_PHY_773_READ_MASK				             0x01030F3FU
-#define LPDDR4__DENALI_PHY_773_WRITE_MASK				            0x01030F3FU
+#define LPDDR4__DENALI_PHY_773_READ_MASK                             0x01030F3FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK                            0x01030F3FU
 #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK             0x0000003FU
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH				     6U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH                     6U
 #define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773
 #define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK            0x00000F00U
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH                    4U
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773
 #define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3
 
 #define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK           0x00030000U
-#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH				   2U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH                   2U
 #define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773
 #define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3
 
@@ -140,8 +139,8 @@
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773
 #define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3
 
-#define LPDDR4__DENALI_PHY_774_READ_MASK				             0x1F1F0301U
-#define LPDDR4__DENALI_PHY_774_WRITE_MASK				            0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774_READ_MASK                             0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK                            0x1F1F0301U
 #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK     0x00000001U
 #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH             1U
@@ -168,8 +167,8 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3
 
-#define LPDDR4__DENALI_PHY_775_READ_MASK				             0x1F030F0FU
-#define LPDDR4__DENALI_PHY_775_WRITE_MASK				            0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775_READ_MASK                             0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK                            0x1F030F0FU
 #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK      0x0000000FU
 #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH              4U
@@ -194,17 +193,17 @@
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775
 #define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3
 
-#define LPDDR4__DENALI_PHY_776_READ_MASK				             0x0101FF03U
-#define LPDDR4__DENALI_PHY_776_WRITE_MASK				            0x0101FF03U
+#define LPDDR4__DENALI_PHY_776_READ_MASK                             0x0101FF03U
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK                            0x0101FF03U
 #define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK              0x00000003U
-#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH				      2U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH                      2U
 #define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776
 #define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3
 
 #define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK              0x0001FF00U
-#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH				      9U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH                      9U
 #define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776
 #define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3
 
@@ -216,33 +215,33 @@
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776
 #define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3
 
-#define LPDDR4__DENALI_PHY_777_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_777_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH       32U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_777
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3
 
-#define LPDDR4__DENALI_PHY_778_READ_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_778_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_778_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK                            0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK    0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH           28U
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_778
 #define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3
 
-#define LPDDR4__DENALI_PHY_779_READ_MASK				             0x0101FF7FU
-#define LPDDR4__DENALI_PHY_779_WRITE_MASK				            0x0101FF7FU
+#define LPDDR4__DENALI_PHY_779_READ_MASK                             0x0101FF7FU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK                            0x0101FF7FU
 #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_MASK        0x0000007FU
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT				0U
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH				7U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH                7U
 #define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_779
 #define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3
 
 #define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_MASK         0x0001FF00U
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH				 9U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH                 9U
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_779
 #define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3
 
@@ -254,8 +253,8 @@
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_779
 #define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3
 
-#define LPDDR4__DENALI_PHY_780_READ_MASK				             0x007F3F01U
-#define LPDDR4__DENALI_PHY_780_WRITE_MASK				            0x007F3F01U
+#define LPDDR4__DENALI_PHY_780_READ_MASK                             0x007F3F01U
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK                            0x007F3F01U
 #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT      0U
 #define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH      1U
@@ -271,13 +270,13 @@
 #define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3
 
 #define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_MASK            0x007F0000U
-#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH				    7U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH                    7U
 #define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_780
 #define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3
 
-#define LPDDR4__DENALI_PHY_781_READ_MASK				             0x000F03FFU
-#define LPDDR4__DENALI_PHY_781_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_781_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK                            0x000F03FFU
 #define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT       0U
 #define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH      10U
@@ -291,37 +290,37 @@
 #define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3
 
 #define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_MASK          0x01000000U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET				  0U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET                  0U
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_781
 #define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3
 
-#define LPDDR4__DENALI_PHY_782_READ_MASK				             0x070101FFU
-#define LPDDR4__DENALI_PHY_782_WRITE_MASK				            0x070101FFU
+#define LPDDR4__DENALI_PHY_782_READ_MASK                             0x070101FFU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK                            0x070101FFU
 #define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK    0x000001FFU
 #define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH            9U
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_782
 #define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK				     0x00010000U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT				            16U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH				             1U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR				             0U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET				             0U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK                     0x00010000U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT                            16U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET                             0U
 #define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_782
 #define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_782__PHY_LPDDR_3
 
-#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK				 0x07000000U
-#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT				        24U
-#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH				         3U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK                 0x07000000U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH                         3U
 #define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_782
 #define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3
 
-#define LPDDR4__DENALI_PHY_783_READ_MASK				             0x000301FFU
-#define LPDDR4__DENALI_PHY_783_WRITE_MASK				            0x000301FFU
+#define LPDDR4__DENALI_PHY_783_READ_MASK                             0x000301FFU
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK                            0x000301FFU
 #define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK    0x000001FFU
 #define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH            9U
@@ -329,101 +328,101 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3
 
 #define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_MASK         0x00030000U
-#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH				 2U
+#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH                 2U
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_783
 #define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3
 
-#define LPDDR4__DENALI_PHY_784_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_784_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_784_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH				32U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH                32U
 #define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_784
 #define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3
 
-#define LPDDR4__DENALI_PHY_785_READ_MASK				             0x00000301U
-#define LPDDR4__DENALI_PHY_785_WRITE_MASK				            0x00000301U
+#define LPDDR4__DENALI_PHY_785_READ_MASK                             0x00000301U
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK                            0x00000301U
 #define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET				    0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET                    0U
 #define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_785
 #define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3
 
 #define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_MASK             0x00000300U
-#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT				     8U
-#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH                     2U
 #define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_785
 #define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3
 
-#define LPDDR4__DENALI_PHY_786_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_786_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_786
 #define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3
 
-#define LPDDR4__DENALI_PHY_787_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_787_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH				      32U
+#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH                      32U
 #define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_787
 #define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3
 
-#define LPDDR4__DENALI_PHY_788_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_788_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_788
 #define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3
 
-#define LPDDR4__DENALI_PHY_789_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_789_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_789
 #define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3
 
-#define LPDDR4__DENALI_PHY_790_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_790_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_790
 #define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3
 
-#define LPDDR4__DENALI_PHY_791_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_791_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_791
 #define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3
 
-#define LPDDR4__DENALI_PHY_792_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_792_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_792
 #define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3
 
-#define LPDDR4__DENALI_PHY_793_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_793_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH                     32U
 #define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_793
 #define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3
 
-#define LPDDR4__DENALI_PHY_794_READ_MASK				             0x070F0107U
-#define LPDDR4__DENALI_PHY_794_WRITE_MASK				            0x070F0107U
+#define LPDDR4__DENALI_PHY_794_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK                            0x070F0107U
 #define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK     0x00000007U
 #define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH             3U
@@ -450,8 +449,8 @@
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_794
 #define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3
 
-#define LPDDR4__DENALI_PHY_795_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_795_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_795_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK   0x0000000FU
 #define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT           0U
 #define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH           4U
@@ -459,8 +458,8 @@
 #define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3
 
 #define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_MASK         0x00000F00U
-#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH				 4U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH                 4U
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_795
 #define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3
 
@@ -476,41 +475,41 @@
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_795
 #define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3
 
-#define LPDDR4__DENALI_PHY_796_READ_MASK				             0xFF030001U
-#define LPDDR4__DENALI_PHY_796_WRITE_MASK				            0xFF030001U
+#define LPDDR4__DENALI_PHY_796_READ_MASK                             0xFF030001U
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK                            0xFF030001U
 #define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET				    0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET                    0U
 #define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_796
 #define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3
 
 #define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET				 0U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET                 0U
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_796
 #define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3
 
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK				0x00030000U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH				        2U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH                        2U
 #define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_796
 #define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3
 
 #define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_MASK           0xFF000000U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH                   8U
 #define LPDDR4__PHY_WRLVL_PER_START_3__REG DENALI_PHY_796
 #define LPDDR4__PHY_WRLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3
 
-#define LPDDR4__DENALI_PHY_797_READ_MASK				             0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_797_WRITE_MASK				            0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_797_READ_MASK                             0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK                            0x00FF0F3FU
 #define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_MASK         0x0000003FU
-#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH                 6U
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_797
 #define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3
 
@@ -520,23 +519,23 @@
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_797
 #define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3
 
-#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT				          16U
-#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH				           8U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH                           8U
 #define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_797
 #define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3
 
-#define LPDDR4__DENALI_PHY_798_READ_MASK				             0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_798_WRITE_MASK				            0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_798_READ_MASK                             0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK                            0x0F3F03FFU
 #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH                  10U
 #define LPDDR4__PHY_GTLVL_PER_START_3__REG DENALI_PHY_798
 #define LPDDR4__PHY_GTLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3
 
 #define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_MASK         0x003F0000U
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH                 6U
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_798
 #define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3
 
@@ -546,11 +545,11 @@
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_798
 #define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3
 
-#define LPDDR4__DENALI_PHY_799_READ_MASK				             0x1F030F3FU
-#define LPDDR4__DENALI_PHY_799_WRITE_MASK				            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_799_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK                            0x1F030F3FU
 #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_MASK         0x0000003FU
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH                 6U
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_799
 #define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3
 
@@ -561,8 +560,8 @@
 #define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3
 
 #define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_MASK             0x00030000U
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH                     2U
 #define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_799
 #define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3
 
@@ -572,8 +571,8 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_799
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3
 
-#define LPDDR4__DENALI_PHY_800_READ_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_800_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_800_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK                            0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_WIDTH         8U
@@ -581,8 +580,8 @@
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3
 
 #define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_MASK           0x0000FF00U
-#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH                   8U
 #define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_800
 #define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3
 
@@ -593,16 +592,16 @@
 #define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3
 
 #define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_MASK          0x3F000000U
-#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH                  6U
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_800
 #define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3
 
-#define LPDDR4__DENALI_PHY_801_READ_MASK				             0x0F07FF07U
-#define LPDDR4__DENALI_PHY_801_WRITE_MASK				            0x0F07FF07U
+#define LPDDR4__DENALI_PHY_801_READ_MASK                             0x0F07FF07U
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK                            0x0F07FF07U
 #define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_MASK               0x00000007U
-#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH				       3U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH                       3U
 #define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_801
 #define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3
 
@@ -618,8 +617,8 @@
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_801
 #define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3
 
-#define LPDDR4__DENALI_PHY_802_READ_MASK				             0x0000FF0FU
-#define LPDDR4__DENALI_PHY_802_WRITE_MASK				            0x0000FF0FU
+#define LPDDR4__DENALI_PHY_802_READ_MASK                             0x0000FF0FU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK                            0x0000FF0FU
 #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK    0x0000000FU
 #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH            4U
@@ -640,64 +639,64 @@
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_802
 #define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3
 
-#define LPDDR4__DENALI_PHY_803_READ_MASK				             0x000001FFU
-#define LPDDR4__DENALI_PHY_803_WRITE_MASK				            0x000001FFU
+#define LPDDR4__DENALI_PHY_803_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK                            0x000001FFU
 #define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_MASK        0x000001FFU
-#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT				0U
-#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH				9U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH                9U
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_803
 #define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3
 
-#define LPDDR4__DENALI_PHY_804_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_804_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_804_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_804
 #define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3
 
-#define LPDDR4__DENALI_PHY_805_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_805_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_805_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_805
 #define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3
 
-#define LPDDR4__DENALI_PHY_806_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_806_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_806_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_806
 #define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3
 
-#define LPDDR4__DENALI_PHY_807_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_807_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH				       32U
+#define LPDDR4__DENALI_PHY_807_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH                       32U
 #define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_807
 #define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3
 
-#define LPDDR4__DENALI_PHY_808_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PHY_808_WRITE_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH				       16U
+#define LPDDR4__DENALI_PHY_808_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH                       16U
 #define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_808
 #define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3
 
 #define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_MASK            0x00010000U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET				    0U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET                    0U
 #define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_808
 #define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3
 
-#define LPDDR4__DENALI_PHY_809_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_809_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_809_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_MASK       0x000003FFU
 #define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_SHIFT               0U
 #define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_WIDTH              10U
@@ -710,8 +709,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_809
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3
 
-#define LPDDR4__DENALI_PHY_810_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_810_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_810_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK  0x000003FFU
 #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT          0U
 #define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH         10U
@@ -724,8 +723,8 @@
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_810
 #define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3
 
-#define LPDDR4__DENALI_PHY_811_READ_MASK				             0x00FF0001U
-#define LPDDR4__DENALI_PHY_811_WRITE_MASK				            0x00FF0001U
+#define LPDDR4__DENALI_PHY_811_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_811_WRITE_MASK                            0x00FF0001U
 #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK  0x00000001U
 #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT          0U
 #define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH          1U
@@ -735,27 +734,27 @@
 #define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3
 
 #define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_MASK           0x00003F00U
-#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH				   6U
+#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH                   6U
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_811
 #define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3
 
 #define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_MASK              0x00FF0000U
-#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH                      8U
 #define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_811
 #define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3
 
-#define LPDDR4__DENALI_PHY_812_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_812_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_812_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_812_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH				  32U
+#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH                  32U
 #define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_812
 #define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3
 
-#define LPDDR4__DENALI_PHY_813_READ_MASK				             0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_813_WRITE_MASK				            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_813_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_813_WRITE_MASK                            0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_MASK      0x0000FFFFU
 #define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH             16U
@@ -768,8 +767,8 @@
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_813
 #define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3
 
-#define LPDDR4__DENALI_PHY_814_READ_MASK				             0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_814_WRITE_MASK				            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_814_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_814_WRITE_MASK                            0xFFFF7F7FU
 #define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK      0x0000007FU
 #define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH              7U
@@ -794,8 +793,8 @@
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
 #define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3
 
-#define LPDDR4__DENALI_PHY_815_READ_MASK				             0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_815_WRITE_MASK				            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_815_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_815_WRITE_MASK                            0x7F07FFFFU
 #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U
 #define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
@@ -814,8 +813,8 @@
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
 #define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3
 
-#define LPDDR4__DENALI_PHY_816_READ_MASK				             0x0007FFFFU
-#define LPDDR4__DENALI_PHY_816_WRITE_MASK				            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_816_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_816_WRITE_MASK                            0x0007FFFFU
 #define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
 #define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH         8U
@@ -829,13 +828,13 @@
 #define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3
 
 #define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_MASK              0x00070000U
-#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH				      3U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH                      3U
 #define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_816
 #define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3
 
-#define LPDDR4__DENALI_PHY_817_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_817_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_817_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_817_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK     0x000003FFU
 #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH            10U
@@ -848,16 +847,16 @@
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_817
 #define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3
 
-#define LPDDR4__DENALI_PHY_818_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PHY_818_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_818_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_818_WRITE_MASK                            0x0001FFFFU
 #define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_MASK          0x0001FFFFU
-#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH				 17U
+#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH                 17U
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_818
 #define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3
 
-#define LPDDR4__DENALI_PHY_819_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_819_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH       10U
@@ -870,11 +869,11 @@
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819
 #define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3
 
-#define LPDDR4__DENALI_PHY_820_READ_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_820_WRITE_MASK				            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_820_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_820_WRITE_MASK                            0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH				  16U
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH                  16U
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_820
 #define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3
 
@@ -884,24 +883,24 @@
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_820
 #define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3
 
-#define LPDDR4__DENALI_PHY_821_READ_MASK				             0x00003FFFU
-#define LPDDR4__DENALI_PHY_821_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_821_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_821_WRITE_MASK                            0x00003FFFU
 #define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK     0x00003FFFU
 #define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH            14U
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_821
 #define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3
 
-#define LPDDR4__DENALI_PHY_822_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_822_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_822_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_822_WRITE_MASK                            0x0003FFFFU
 #define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_MASK          0x0003FFFFU
-#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH				 18U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH                 18U
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_822
 #define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3
 
-#define LPDDR4__DENALI_PHY_823_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_823_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_823_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_823_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH        10U
@@ -914,32 +913,32 @@
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_823
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3
 
-#define LPDDR4__DENALI_PHY_824_READ_MASK				             0x00000003U
-#define LPDDR4__DENALI_PHY_824_WRITE_MASK				            0x00000003U
+#define LPDDR4__DENALI_PHY_824_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_824_WRITE_MASK                            0x00000003U
 #define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U
 #define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT    0U
 #define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH    2U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_824
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3
 
-#define LPDDR4__DENALI_PHY_825_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_825_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_825_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_825_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH				 32U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH                 32U
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_825
 #define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3
 
-#define LPDDR4__DENALI_PHY_826_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_826_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_826_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_826_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT                0U
 #define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_WIDTH               32U
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__REG DENALI_PHY_826
 #define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3
 
-#define LPDDR4__DENALI_PHY_827_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_827_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_827_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_827_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK    0x000007FFU
 #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH           11U
@@ -952,56 +951,56 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_827
 #define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3
 
-#define LPDDR4__DENALI_PHY_828_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_828_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_828_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_828_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH				32U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH                32U
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_828
 #define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3
 
-#define LPDDR4__DENALI_PHY_829_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_829_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT               0U
 #define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH              32U
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_829
 #define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3
 
-#define LPDDR4__DENALI_PHY_830_READ_MASK				             0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_830_WRITE_MASK				            0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK				  0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH				         31U
+#define LPDDR4__DENALI_PHY_830_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH                         31U
 #define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_830
 #define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3
 
-#define LPDDR4__DENALI_PHY_831_READ_MASK				             0x0000003FU
-#define LPDDR4__DENALI_PHY_831_WRITE_MASK				            0x0000003FU
-#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK				  0x0000003FU
-#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH				          6U
+#define LPDDR4__DENALI_PHY_831_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_831_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH                          6U
 #define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_831
 #define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3
 
-#define LPDDR4__DENALI_PHY_832_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_832_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_832_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_832_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH                     32U
 #define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_832
 #define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3
 
-#define LPDDR4__DENALI_PHY_833_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_833_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK     0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH            32U
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_833
 #define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3
 
-#define LPDDR4__DENALI_PHY_834_READ_MASK				             0x010001FFU
-#define LPDDR4__DENALI_PHY_834_WRITE_MASK				            0x010001FFU
+#define LPDDR4__DENALI_PHY_834_READ_MASK                             0x010001FFU
+#define LPDDR4__DENALI_PHY_834_WRITE_MASK                            0x010001FFU
 #define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK   0x000000FFU
 #define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT           0U
 #define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH           8U
@@ -1009,34 +1008,34 @@
 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3
 
 #define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_MASK        0x00000100U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT				8U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH				1U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR				0U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET				0U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH                1U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR                0U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET                0U
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_834
 #define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3
 
 #define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_MASK           0x00010000U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET				   0U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET                   0U
 #define LPDDR4__SC_PHY_RX_CAL_START_3__REG DENALI_PHY_834
 #define LPDDR4__SC_PHY_RX_CAL_START_3__FLD LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3
 
 #define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET				   0U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET                   0U
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_3__REG DENALI_PHY_834
 #define LPDDR4__PHY_RX_CAL_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3
 
-#define LPDDR4__DENALI_PHY_835_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_835_WRITE_MASK				            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835_WRITE_MASK                            0x01FF01FFU
 #define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_MASK        0x000000FFU
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT				0U
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH				8U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH                8U
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_835
 #define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3
 
@@ -1048,147 +1047,147 @@
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__REG DENALI_PHY_835
 #define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__FLD LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3
 
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835
 #define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3
 
-#define LPDDR4__DENALI_PHY_836_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_836_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_836_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836
 #define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3
 
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836
 #define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3
 
-#define LPDDR4__DENALI_PHY_837_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_837_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_837_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837
 #define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3
 
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837
 #define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3
 
-#define LPDDR4__DENALI_PHY_838_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_838_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_838_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838
 #define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3
 
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK				0x01FF0000U
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838
 #define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3
 
-#define LPDDR4__DENALI_PHY_839_READ_MASK				             0x000001FFU
-#define LPDDR4__DENALI_PHY_839_WRITE_MASK				            0x000001FFU
-#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_839_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_839_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839
 #define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3
 
-#define LPDDR4__DENALI_PHY_840_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_840_WRITE_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK				 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH				        18U
+#define LPDDR4__DENALI_PHY_840_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH                        18U
 #define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840
 #define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3
 
-#define LPDDR4__DENALI_PHY_841_READ_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PHY_841_WRITE_MASK				            0x01FF01FFU
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK				0x000001FFU
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH				        9U
+#define LPDDR4__DENALI_PHY_841_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH                        9U
 #define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841
 #define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3
 
 #define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK               0x01FF0000U
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH				       9U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH                       9U
 #define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841
 #define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3
 
-#define LPDDR4__DENALI_PHY_842_READ_MASK				             0x01FF07FFU
-#define LPDDR4__DENALI_PHY_842_WRITE_MASK				            0x01FF07FFU
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK				0x000007FFU
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH				       11U
+#define LPDDR4__DENALI_PHY_842_READ_MASK                             0x01FF07FFU
+#define LPDDR4__DENALI_PHY_842_WRITE_MASK                            0x01FF07FFU
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK                0x000007FFU
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH                       11U
 #define LPDDR4__PHY_RX_CAL_OBS_3__REG DENALI_PHY_842
 #define LPDDR4__PHY_RX_CAL_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3
 
 #define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_MASK           0x01FF0000U
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH				   9U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH                   9U
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__REG DENALI_PHY_842
 #define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3
 
-#define LPDDR4__DENALI_PHY_843_READ_MASK				             0x017F7F01U
-#define LPDDR4__DENALI_PHY_843_WRITE_MASK				            0x017F7F01U
+#define LPDDR4__DENALI_PHY_843_READ_MASK                             0x017F7F01U
+#define LPDDR4__DENALI_PHY_843_WRITE_MASK                            0x017F7F01U
 #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_MASK            0x00000001U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH				    1U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR				    0U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET				    0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET                    0U
 #define LPDDR4__PHY_RX_CAL_DISABLE_3__REG DENALI_PHY_843
 #define LPDDR4__PHY_RX_CAL_DISABLE_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3
 
 #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_MASK          0x00007F00U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH				  7U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH                  7U
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__REG DENALI_PHY_843
 #define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3
 
 #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_MASK        0x007F0000U
 #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_SHIFT               16U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH				7U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH                7U
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__REG DENALI_PHY_843
 #define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3
 
 #define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET				   0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET                   0U
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_3__REG DENALI_PHY_843
 #define LPDDR4__PHY_RX_CAL_COMP_VAL_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3
 
-#define LPDDR4__DENALI_PHY_844_READ_MASK				             0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_844_WRITE_MASK				            0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_844_READ_MASK                             0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_844_WRITE_MASK                            0x07FF0FFFU
 #define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_MASK         0x00000FFFU
-#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH				12U
+#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH                12U
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__REG DENALI_PHY_844
 #define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__FLD LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3
 
 #define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_MASK            0x07FF0000U
-#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH				   11U
+#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH                   11U
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_844
 #define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3
 
-#define LPDDR4__DENALI_PHY_845_READ_MASK				             0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_845_WRITE_MASK				            0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_845_READ_MASK                             0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_845_WRITE_MASK                            0x03FFFF1FU
 #define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_MASK        0x0000001FU
-#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT				0U
-#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH				5U
+#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH                5U
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_845
 #define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3
 
@@ -1205,13 +1204,13 @@
 #define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3
 
 #define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_MASK            0x03000000U
-#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH				    2U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH                    2U
 #define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_845
 #define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3
 
-#define LPDDR4__DENALI_PHY_846_READ_MASK				             0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_846_WRITE_MASK				            0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_846_READ_MASK                             0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_846_WRITE_MASK                            0x01FFFF3FU
 #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_MASK      0x0000003FU
 #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_WIDTH              6U
@@ -1238,8 +1237,8 @@
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_846
 #define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3
 
-#define LPDDR4__DENALI_PHY_847_READ_MASK				             0x07030101U
-#define LPDDR4__DENALI_PHY_847_WRITE_MASK				            0x07030101U
+#define LPDDR4__DENALI_PHY_847_READ_MASK                             0x07030101U
+#define LPDDR4__DENALI_PHY_847_WRITE_MASK                            0x07030101U
 #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WIDTH              1U
@@ -1249,27 +1248,27 @@
 #define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3
 
 #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET				 0U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET                 0U
 #define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_847
 #define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3
 
 #define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_MASK           0x00030000U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH				   2U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH                   2U
 #define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_847
 #define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3
 
 #define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_MASK             0x07000000U
-#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH				     3U
+#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH                     3U
 #define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_847
 #define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3
 
-#define LPDDR4__DENALI_PHY_848_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_PHY_848_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_PHY_848_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_PHY_848_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH         1U
@@ -1302,22 +1301,22 @@
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_848
 #define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3
 
-#define LPDDR4__DENALI_PHY_849_READ_MASK				             0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_849_WRITE_MASK				            0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_849_READ_MASK                             0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_849_WRITE_MASK                            0x3FFF07FFU
 #define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_MASK        0x000007FFU
-#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT				0U
+#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT                0U
 #define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_WIDTH               11U
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_3__REG DENALI_PHY_849
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_3__FLD LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3
 
 #define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_MASK         0x3FFF0000U
-#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH				14U
+#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH                14U
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__REG DENALI_PHY_849
 #define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3
 
-#define LPDDR4__DENALI_PHY_850_READ_MASK				             0x00003FFFU
-#define LPDDR4__DENALI_PHY_850_WRITE_MASK				            0x00003FFFU
+#define LPDDR4__DENALI_PHY_850_READ_MASK                             0x00003FFFU
+#define LPDDR4__DENALI_PHY_850_WRITE_MASK                            0x00003FFFU
 #define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_MASK    0x00003FFFU
 #define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_WIDTH           14U
@@ -1330,8 +1329,8 @@
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__REG DENALI_PHY_850
 #define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3
 
-#define LPDDR4__DENALI_PHY_851_READ_MASK				             0x00001F1FU
-#define LPDDR4__DENALI_PHY_851_WRITE_MASK				            0x00001F1FU
+#define LPDDR4__DENALI_PHY_851_READ_MASK                             0x00001F1FU
+#define LPDDR4__DENALI_PHY_851_WRITE_MASK                            0x00001F1FU
 #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_MASK 0x0000001FU
 #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_WIDTH         5U
@@ -1350,37 +1349,37 @@
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__REG DENALI_PHY_851
 #define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3
 
-#define LPDDR4__DENALI_PHY_852_READ_MASK				             0x07FFFF07U
-#define LPDDR4__DENALI_PHY_852_WRITE_MASK				            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_852_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_852_WRITE_MASK                            0x07FFFF07U
 #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_MASK            0x00000007U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH				    3U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH                    3U
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_852
 #define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3
 
 #define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_MASK            0x00FFFF00U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH				   16U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH                   16U
 #define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_852
 #define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3
 
 #define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_MASK           0x07000000U
-#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH				   3U
+#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH                   3U
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_852
 #define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3
 
-#define LPDDR4__DENALI_PHY_853_READ_MASK				             0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_853_WRITE_MASK				            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_853_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_853_WRITE_MASK                            0x7F03FFFFU
 #define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH				  16U
+#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH                  16U
 #define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_853
 #define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3
 
 #define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_MASK          0x00030000U
-#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH                  2U
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_853
 #define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3
 
@@ -1390,8 +1389,8 @@
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_853
 #define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3
 
-#define LPDDR4__DENALI_PHY_854_READ_MASK				             0xFF01037FU
-#define LPDDR4__DENALI_PHY_854_WRITE_MASK				            0xFF01037FU
+#define LPDDR4__DENALI_PHY_854_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_854_WRITE_MASK                            0xFF01037FU
 #define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_MASK   0x0000007FU
 #define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT           0U
 #define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH           7U
@@ -1399,50 +1398,50 @@
 #define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3
 
 #define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_MASK        0x00000300U
-#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT				8U
-#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH				2U
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH                2U
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_854
 #define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3
 
 #define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_MASK              0x00010000U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH				      1U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR				      0U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET				      0U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET                      0U
 #define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_854
 #define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3
 
 #define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_MASK         0xFF000000U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT				24U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT                24U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH                 8U
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_854
 #define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3
 
-#define LPDDR4__DENALI_PHY_855_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_855_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_855_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_855_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_MASK             0x000007FFU
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH				    11U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH                    11U
 #define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_855
 #define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3
 
 #define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_MASK              0x07FF0000U
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH				     11U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH                     11U
 #define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_855
 #define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3
 
-#define LPDDR4__DENALI_PHY_856_READ_MASK				             0x0103FFFFU
-#define LPDDR4__DENALI_PHY_856_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_856_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_856_WRITE_MASK                            0x0103FFFFU
 #define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_MASK            0x000000FFU
-#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH                    8U
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_856
 #define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3
 
 #define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_MASK            0x0003FF00U
-#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH                   10U
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_856
 #define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3
 
@@ -1454,8 +1453,8 @@
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_856
 #define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3
 
-#define LPDDR4__DENALI_PHY_857_READ_MASK				             0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_857_WRITE_MASK				            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_857_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_857_WRITE_MASK                            0x1F1F0F3FU
 #define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_MASK   0x0000003FU
 #define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT           0U
 #define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH           6U
@@ -1463,156 +1462,156 @@
 #define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3
 
 #define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_MASK               0x00000F00U
-#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT				       8U
-#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH                       4U
 #define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_857
 #define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3
 
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK				0x001F0000U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH				        5U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH                        5U
 #define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_857
 #define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3
 
 #define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_MASK              0x1F000000U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_857
 #define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3
 
-#define LPDDR4__DENALI_PHY_858_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_858_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_858_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_858_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_MASK              0x0000001FU
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_858
 #define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3
 
 #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_MASK              0x00001F00U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_858
 #define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3
 
 #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_MASK              0x001F0000U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_858
 #define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3
 
 #define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_MASK              0x1F000000U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_858
 #define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3
 
-#define LPDDR4__DENALI_PHY_859_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_859_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_859_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_859_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_MASK              0x0000001FU
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_859
 #define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3
 
 #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_MASK              0x00001F00U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_859
 #define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3
 
 #define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_MASK              0x001F0000U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH				      5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH                      5U
 #define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_859
 #define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3
 
 #define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_MASK             0x1F000000U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH                     5U
 #define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_859
 #define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3
 
-#define LPDDR4__DENALI_PHY_860_READ_MASK				             0x003F1F1FU
-#define LPDDR4__DENALI_PHY_860_WRITE_MASK				            0x003F1F1FU
+#define LPDDR4__DENALI_PHY_860_READ_MASK                             0x003F1F1FU
+#define LPDDR4__DENALI_PHY_860_WRITE_MASK                            0x003F1F1FU
 #define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_MASK            0x0000001FU
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH                    5U
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_860
 #define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3
 
 #define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_MASK           0x00001F00U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT				   8U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH				   5U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH                   5U
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_860
 #define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3
 
 #define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_MASK         0x003F0000U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH                 6U
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_860
 #define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3
 
-#define LPDDR4__DENALI_PHY_861_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_861_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_861_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_861_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_861
 #define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3
 
 #define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_861
 #define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_862_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_862_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_862_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_862_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_862
 #define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3
 
 #define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_862
 #define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_863_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_863_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_863_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_863_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_863
 #define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3
 
 #define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_863
 #define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_864_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_864_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_864_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_864_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_MASK         0x000003FFU
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_864
 #define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3
 
 #define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH				10U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH                10U
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_864
 #define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_865_READ_MASK				             0x000703FFU
-#define LPDDR4__DENALI_PHY_865_WRITE_MASK				            0x000703FFU
+#define LPDDR4__DENALI_PHY_865_READ_MASK                             0x000703FFU
+#define LPDDR4__DENALI_PHY_865_WRITE_MASK                            0x000703FFU
 #define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_MASK          0x000003FFU
-#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH                 10U
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_865
 #define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3
 
@@ -1622,34 +1621,34 @@
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_865
 #define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3
 
-#define LPDDR4__DENALI_PHY_866_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_866_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_866_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_866_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_MASK              0x000000FFU
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH                      8U
 #define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_866
 #define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3
 
 #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_MASK         0x0000FF00U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH                 8U
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_866
 #define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3
 
 #define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_MASK         0x00FF0000U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT				16U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT                16U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH                 8U
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_866
 #define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3
 
 #define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_MASK             0xFF000000U
-#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH                     8U
 #define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_866
 #define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3
 
-#define LPDDR4__DENALI_PHY_867_READ_MASK				             0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_867_WRITE_MASK				            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_867_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_867_WRITE_MASK                            0xFFFFFF0FU
 #define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_SHIFT               0U
 #define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_WIDTH               4U
@@ -1657,118 +1656,118 @@
 #define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3
 
 #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_MASK        0x0000FF00U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT				8U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH				8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH                8U
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_867
 #define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3
 
 #define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_MASK          0x00FF0000U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH                  8U
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_867
 #define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3
 
 #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_MASK        0xFF000000U
 #define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_SHIFT               24U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH				8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH                8U
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_867
 #define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3
 
-#define LPDDR4__DENALI_PHY_868_READ_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_868_WRITE_MASK				            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_868_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_868_WRITE_MASK                            0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH				16U
+#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH                16U
 #define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_868
 #define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3
 
 #define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_MASK          0x0FFF0000U
-#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH				 12U
+#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH                 12U
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_868
 #define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3
 
-#define LPDDR4__DENALI_PHY_869_READ_MASK				             0x03FFFF01U
-#define LPDDR4__DENALI_PHY_869_WRITE_MASK				            0x03FFFF01U
+#define LPDDR4__DENALI_PHY_869_READ_MASK                             0x03FFFF01U
+#define LPDDR4__DENALI_PHY_869_WRITE_MASK                            0x03FFFF01U
 #define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_MASK        0x00000001U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT				0U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH				1U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR				0U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET				0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT                0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH                1U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR                0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET                0U
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_869
 #define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3
 
 #define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_MASK              0x0000FF00U
-#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT				      8U
-#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH				      8U
+#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH                      8U
 #define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_869
 #define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3
 
 #define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_MASK             0x00FF0000U
-#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH				     8U
+#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH                     8U
 #define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_869
 #define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3
 
 #define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_MASK          0x03000000U
-#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH				  2U
+#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH                  2U
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_869
 #define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3
 
-#define LPDDR4__DENALI_PHY_870_READ_MASK				             0x1F1F0103U
-#define LPDDR4__DENALI_PHY_870_WRITE_MASK				            0x1F1F0103U
-#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK				   0x00000003U
-#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_870_READ_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_870_WRITE_MASK                            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH                           2U
 #define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_870
 #define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3
 
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK				  0x00000100U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT				          8U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET				          0U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK                  0x00000100U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET                          0U
 #define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_870
 #define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3
 
 #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_MASK        0x001F0000U
 #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT               16U
-#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH				5U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH                5U
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_870
 #define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3
 
 #define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_MASK          0x1F000000U
-#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT				 24U
-#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH				  5U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH                  5U
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_870
 #define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3
 
-#define LPDDR4__DENALI_PHY_871_READ_MASK				             0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_871_WRITE_MASK				            0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_871_READ_MASK                             0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_871_WRITE_MASK                            0x3F07FF0FU
 #define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH                    4U
 #define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_871
 #define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3
 
 #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_MASK        0x0007FF00U
-#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT				8U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT                8U
 #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_WIDTH               11U
 #define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_871
 #define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3
 
 #define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_MASK         0x3F000000U
-#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT				24U
-#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH				 6U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT                24U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH                 6U
 #define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_871
 #define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3
 
-#define LPDDR4__DENALI_PHY_872_READ_MASK				             0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_872_WRITE_MASK				            0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_872_READ_MASK                             0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_872_WRITE_MASK                            0xFF0FFFFFU
 #define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_MASK         0x000000FFU
-#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH                 8U
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_872
 #define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3
 
@@ -1779,19 +1778,19 @@
 #define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3
 
 #define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_MASK               0x000F0000U
-#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH                       4U
 #define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_872
 #define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3
 
 #define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_MASK            0xFF000000U
-#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH                    8U
 #define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_872
 #define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3
 
-#define LPDDR4__DENALI_PHY_873_READ_MASK				             0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_873_WRITE_MASK				            0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_873_READ_MASK                             0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_873_WRITE_MASK                            0x1F0F3F0FU
 #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_MASK       0x0000000FU
 #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT               0U
 #define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH               4U
@@ -1805,8 +1804,8 @@
 #define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3
 
 #define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_MASK            0x000F0000U
-#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH                    4U
 #define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_873
 #define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3
 
@@ -1816,25 +1815,25 @@
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873
 #define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3
 
-#define LPDDR4__DENALI_PHY_874_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_874_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_874_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_874_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_MASK           0x000003FFU
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH				  10U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH                  10U
 #define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_874
 #define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3
 
 #define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_MASK          0x03FF0000U
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH				 10U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH                 10U
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_874
 #define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3
 
-#define LPDDR4__DENALI_PHY_875_READ_MASK				             0x0F010FFFU
-#define LPDDR4__DENALI_PHY_875_WRITE_MASK				            0x0F010FFFU
+#define LPDDR4__DENALI_PHY_875_READ_MASK                             0x0F010FFFU
+#define LPDDR4__DENALI_PHY_875_WRITE_MASK                            0x0F010FFFU
 #define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_MASK           0x000000FFU
-#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH				   8U
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH                   8U
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_875
 #define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3
 
@@ -1846,31 +1845,31 @@
 
 #define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_MASK        0x00010000U
 #define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT               16U
-#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH				1U
-#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR				0U
-#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET				0U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH                1U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR                0U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET                0U
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_875
 #define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3
 
 #define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_MASK            0x0F000000U
-#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH                    4U
 #define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_875
 #define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3
 
-#define LPDDR4__DENALI_PHY_876_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_876_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_876_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_876_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_MASK            0x000003FFU
-#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH				   10U
+#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH                   10U
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_876
 #define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3
 
-#define LPDDR4__DENALI_PHY_877_READ_MASK				             0x3F0103FFU
-#define LPDDR4__DENALI_PHY_877_WRITE_MASK				            0x3F0103FFU
+#define LPDDR4__DENALI_PHY_877_READ_MASK                             0x3F0103FFU
+#define LPDDR4__DENALI_PHY_877_WRITE_MASK                            0x3F0103FFU
 #define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_MASK             0x000003FFU
-#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH				    10U
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH                    10U
 #define LPDDR4__PHY_RDLVL_DVW_MIN_3__REG DENALI_PHY_877
 #define LPDDR4__PHY_RDLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3
 
@@ -1888,8 +1887,8 @@
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__REG DENALI_PHY_877
 #define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3
 
-#define LPDDR4__DENALI_PHY_878_READ_MASK				             0x00030703U
-#define LPDDR4__DENALI_PHY_878_WRITE_MASK				            0x00030703U
+#define LPDDR4__DENALI_PHY_878_READ_MASK                             0x00030703U
+#define LPDDR4__DENALI_PHY_878_WRITE_MASK                            0x00030703U
 #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_MASK       0x00000003U
 #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_SHIFT               0U
 #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_WIDTH               2U
@@ -1897,8 +1896,8 @@
 #define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3
 
 #define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT				8U
-#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH				3U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH                3U
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_878
 #define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3
 
@@ -1908,8 +1907,8 @@
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_878
 #define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3
 
-#define LPDDR4__DENALI_PHY_879_READ_MASK				             0x07FF03FFU
-#define LPDDR4__DENALI_PHY_879_WRITE_MASK				            0x07FF03FFU
+#define LPDDR4__DENALI_PHY_879_READ_MASK                             0x07FF03FFU
+#define LPDDR4__DENALI_PHY_879_WRITE_MASK                            0x07FF03FFU
 #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH       10U
@@ -1922,8 +1921,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_879
 #define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3
 
-#define LPDDR4__DENALI_PHY_880_READ_MASK				             0xFFFF0101U
-#define LPDDR4__DENALI_PHY_880_WRITE_MASK				            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_880_READ_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PHY_880_WRITE_MASK                            0xFFFF0101U
 #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_MASK      0x00000001U
 #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH              1U
@@ -1952,11 +1951,11 @@
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_880
 #define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3
 
-#define LPDDR4__DENALI_PHY_881_READ_MASK				             0x001F3F7FU
-#define LPDDR4__DENALI_PHY_881_WRITE_MASK				            0x001F3F7FU
+#define LPDDR4__DENALI_PHY_881_READ_MASK                             0x001F3F7FU
+#define LPDDR4__DENALI_PHY_881_WRITE_MASK                            0x001F3F7FU
 #define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_MASK             0x0000007FU
-#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH				     7U
+#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH                     7U
 #define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_881
 #define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3
 
@@ -1967,29 +1966,29 @@
 #define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3
 
 #define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_MASK             0x001F0000U
-#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH				     5U
+#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH                     5U
 #define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_881
 #define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3
 
-#define LPDDR4__DENALI_PHY_882_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_882_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_882_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_882_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH				   32U
+#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH                   32U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_882
 #define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3
 
-#define LPDDR4__DENALI_PHY_883_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PHY_883_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_PHY_883_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_883_WRITE_MASK                            0x0000000FU
 #define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH                    4U
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_883
 #define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3
 
-#define LPDDR4__DENALI_PHY_884_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_884_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH            11U
@@ -2002,8 +2001,8 @@
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_884
 #define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_885_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_885_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_885_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_885_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH            11U
@@ -2016,8 +2015,8 @@
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_885
 #define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_886_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_886_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_886_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_886_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH            11U
@@ -2030,8 +2029,8 @@
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_886
 #define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_887_READ_MASK				             0x07FF07FFU
-#define LPDDR4__DENALI_PHY_887_WRITE_MASK				            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_887_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_887_WRITE_MASK                            0x07FF07FFU
 #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT             0U
 #define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH            11U
@@ -2044,8 +2043,8 @@
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_887
 #define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_888_READ_MASK				             0x03FF07FFU
-#define LPDDR4__DENALI_PHY_888_WRITE_MASK				            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_888_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_888_WRITE_MASK                            0x03FF07FFU
 #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK      0x000007FFU
 #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH             11U
@@ -2058,8 +2057,8 @@
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_888
 #define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_889_READ_MASK				             0x0003FF03U
-#define LPDDR4__DENALI_PHY_889_WRITE_MASK				            0x0003FF03U
+#define LPDDR4__DENALI_PHY_889_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_889_WRITE_MASK                            0x0003FF03U
 #define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK    0x00000003U
 #define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH            2U
@@ -2072,8 +2071,8 @@
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889
 #define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_890_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_890_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2086,8 +2085,8 @@
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890
 #define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_891_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_891_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2100,8 +2099,8 @@
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891
 #define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_892_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_892_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2114,8 +2113,8 @@
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892
 #define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_893_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_893_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2128,8 +2127,8 @@
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893
 #define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_894_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_894_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2142,8 +2141,8 @@
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894
 #define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_895_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_895_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2156,8 +2155,8 @@
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_895
 #define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_896_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_896_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_896_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_896_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2170,8 +2169,8 @@
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_896
 #define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_897_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_897_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_897_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_897_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH       10U
@@ -2184,8 +2183,8 @@
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_897
 #define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_898_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PHY_898_WRITE_MASK				            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_898_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_898_WRITE_MASK                            0x03FF03FFU
 #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH        10U
@@ -2198,8 +2197,8 @@
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_898
 #define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3
 
-#define LPDDR4__DENALI_PHY_899_READ_MASK				             0x03FF070FU
-#define LPDDR4__DENALI_PHY_899_WRITE_MASK				            0x03FF070FU
+#define LPDDR4__DENALI_PHY_899_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_899_WRITE_MASK                            0x03FF070FU
 #define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_MASK      0x0000000FU
 #define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT              0U
 #define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH              4U
@@ -2207,8 +2206,8 @@
 #define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3
 
 #define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_MASK        0x00000700U
-#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT				8U
-#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH				3U
+#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT                8U
+#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH                3U
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_899
 #define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3
 
@@ -2218,8 +2217,8 @@
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_899
 #define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3
 
-#define LPDDR4__DENALI_PHY_900_READ_MASK				             0x000103FFU
-#define LPDDR4__DENALI_PHY_900_WRITE_MASK				            0x000103FFU
+#define LPDDR4__DENALI_PHY_900_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_900_WRITE_MASK                            0x000103FFU
 #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT      0U
 #define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH     10U
@@ -2234,8 +2233,8 @@
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_900
 #define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3
 
-#define LPDDR4__DENALI_PHY_901_READ_MASK				             0x000F03FFU
-#define LPDDR4__DENALI_PHY_901_WRITE_MASK				            0x000F03FFU
+#define LPDDR4__DENALI_PHY_901_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_901_WRITE_MASK                            0x000F03FFU
 #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH        10U
@@ -2248,8 +2247,8 @@
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_901
 #define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3
 
-#define LPDDR4__DENALI_PHY_902_READ_MASK				             0x010F07FFU
-#define LPDDR4__DENALI_PHY_902_WRITE_MASK				            0x010F07FFU
+#define LPDDR4__DENALI_PHY_902_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_902_WRITE_MASK                            0x010F07FFU
 #define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU
 #define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT         0U
 #define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH        11U
@@ -2257,29 +2256,29 @@
 #define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3
 
 #define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_MASK           0x000F0000U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH				   4U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH                   4U
 #define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_902
 #define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3
 
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK				  0x01000000U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT				         24U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET				          0U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET                          0U
 #define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_902
 #define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3
 
-#define LPDDR4__DENALI_PHY_903_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PHY_903_WRITE_MASK				            0x000003FFU
+#define LPDDR4__DENALI_PHY_903_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_903_WRITE_MASK                            0x000003FFU
 #define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT      0U
 #define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH     10U
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_903
 #define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3
 
-#define LPDDR4__DENALI_PHY_904_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_904_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_904_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_904_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH            8U
@@ -2304,8 +2303,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_904
 #define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3
 
-#define LPDDR4__DENALI_PHY_905_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_905_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_905_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_905_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH            8U
@@ -2330,8 +2329,8 @@
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_905
 #define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3
 
-#define LPDDR4__DENALI_PHY_906_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_906_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_906_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_906_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK    0x000000FFU
 #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT            0U
 #define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH            8U
@@ -2350,23 +2349,23 @@
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_906
 #define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3
 
-#define LPDDR4__DENALI_PHY_907_READ_MASK				             0x0003033FU
-#define LPDDR4__DENALI_PHY_907_WRITE_MASK				            0x0003033FU
+#define LPDDR4__DENALI_PHY_907_READ_MASK                             0x0003033FU
+#define LPDDR4__DENALI_PHY_907_WRITE_MASK                            0x0003033FU
 #define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU
 #define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT        0U
 #define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH        6U
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_907
 #define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3
 
-#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK				    0x00000300U
-#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT				            8U
-#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH				            2U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK                    0x00000300U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH                            2U
 #define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_907
 #define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3
 
-#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK				   0x00030000U
-#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT				          16U
-#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK                   0x00030000U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT                          16U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH                           2U
 #define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_907
 #define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3
 
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
new file mode 100644
index 0000000000..4e33d04d1c
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,7792 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK                               0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK                              0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH                                     1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET                                     0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH                                4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK                     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH                            16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK                               0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK                              0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH                               5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK                       0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH                               4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH                                2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK              0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH                      8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK          0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH                  8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK             0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH                     8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK         0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT                16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH                 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH                   16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK        0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT               16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH                8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH                          8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH                   8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK            0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH                    8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK          0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH                  8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK   0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT          24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH           8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK                          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH                                 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH                                24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH                                24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH                               24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH                                24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH                               24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH                               24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH                               24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH                                24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH                               24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH                               24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH                               24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET                         0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET                         0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET                          0U
+#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19
+#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS
+
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET                              0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK                        0x01000000U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET                                0U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK                              0x03013F01U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK                             0x03013F01U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET                     0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK                    0x00003F00U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH                            6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK              0x00010000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET                      0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK                 0x03000000U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH                         2U
+#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20
+#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK                              0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK                             0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH                         2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK                   0x00001F00U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK                              0x00030303U
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK                             0x00030303U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH                              32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK                     0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH                            32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET                             0U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK                     0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH                            24U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH                             8U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH                             8U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET                           0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK                              0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK                             0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK                   0x00007FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH                          15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH                        4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH                                 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH                                 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK                         0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH                                 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK           0x00FF0000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH                   8U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK           0xFF000000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH                   8U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH                          8U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK        0x0000FF00U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT                8U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH                8U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK               0xFFFF0000U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH                      16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK                              0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK                             0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET                          0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK             0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30
+#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31
+#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31
+#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32
+#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0
+
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32
+#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33
+#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33
+#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK                              0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK                             0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH                    16U
+#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34
+#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1
+
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK                    0x007F0000U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK                         0x7F000000U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH                                 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH                                 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK                    0x007F0000U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK                         0x7F000000U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH                                 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK                              0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK                             0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH                        3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_36__TCCD_MASK                             0x00001F00U
+#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT                                     8U
+#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH                                     5U
+#define LPDDR4__TCCD__REG DENALI_CTL_36
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD
+
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH                                  8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_36
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK                              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK                             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK                           0x000001FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH                                   9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_37
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0
+
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH                              8U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK                          0x3F000000U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH                                  6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_37
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH                                   8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_38
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0
+
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH                                  9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_38
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH                                  8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_38
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK                              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK                             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK                           0x000001FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH                                   9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_39
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1
+
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH                              8U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK                          0x3F000000U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH                                  6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_39
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH                                   8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_40
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1
+
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH                                  9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_40
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH                                  8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_40
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK                              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK                             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK                           0x000001FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH                                   9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_41
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2
+
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH                              8U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK                          0x3F000000U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH                                  6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_41
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK                              0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK                             0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH                                   8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_42
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2
+
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH                                  9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_42
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK                           0x3F000000U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH                                   6U
+#define LPDDR4__TCCDMW__REG DENALI_CTL_42
+#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH                                  8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_43
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH                                  8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_43
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH                                  8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_43
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK                      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH                             17U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH                                  5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_44
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH                                8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH                                  8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_45
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH                                  8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_45
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH                                  8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_45
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK                      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH                             17U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH                                  5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_46
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH                                8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH                                  8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_47
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH                                  8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_47
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH                                  8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_47
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK                      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH                             17U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH                                  5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_48
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK                              0x070707FFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK                             0x070707FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH                                8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_49__TPPD_MASK                             0x00000700U
+#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT                                     8U
+#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH                                     3U
+#define LPDDR4__TPPD__REG DENALI_CTL_49
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD
+
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK                     0x00070000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH                             3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH                             3U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET                              0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH                                  8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_50
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK                           0x00FF0000U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH                                   8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_50
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0
+
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH                                  8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_50
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH                                   8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_51
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1
+
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH                                  8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_51
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK                           0x00FF0000U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH                                   8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_51
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2
+
+#define LPDDR4__DENALI_CTL_51__TMRR_MASK                             0x0F000000U
+#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT                                    24U
+#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH                                     4U
+#define LPDDR4__TMRR__REG DENALI_CTL_51
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK                              0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK                             0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK                          0x0000001FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH                                  5U
+#define LPDDR4__TCACKEL__REG DENALI_CTL_52
+#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL
+
+#define LPDDR4__DENALI_CTL_52__TCAENT_MASK                           0x0003FF00U
+#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH                                  10U
+#define LPDDR4__TCAENT__REG DENALI_CTL_52
+#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT
+
+#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK                           0x3F000000U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH                                   6U
+#define LPDDR4__TCAMRD__REG DENALI_CTL_52
+#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK                           0x0000001FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH                                   5U
+#define LPDDR4__TCAEXT__REG DENALI_CTL_53
+#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT
+
+#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK                          0x00001F00U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH                                  5U
+#define LPDDR4__TCACKEH__REG DENALI_CTL_53
+#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH
+
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK                          0x001F0000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH                                  5U
+#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53
+#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0
+
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH                                  5U
+#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53
+#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK                              0x0101011FU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK                             0x0101011FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK                          0x0000001FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH                                  5U
+#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54
+#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2
+
+#define LPDDR4__DENALI_CTL_54__AP_MASK                               0x00000100U
+#define LPDDR4__DENALI_CTL_54__AP_SHIFT                                       8U
+#define LPDDR4__DENALI_CTL_54__AP_WIDTH                                       1U
+#define LPDDR4__DENALI_CTL_54__AP_WOCLR                                       0U
+#define LPDDR4__DENALI_CTL_54__AP_WOSET                                       0U
+#define LPDDR4__AP__REG DENALI_CTL_54
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP
+
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET                             0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET                             0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK                              0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK                             0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH                                  8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH                                  8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH                                  8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK                           0x1F000000U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH                                   5U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_55
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET                          0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK                     0x03000000U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH                             2U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK                              0x0101017FU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK                             0x0101017FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK                     0x0000007FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH                             7U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK                 0x00000100U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET                         0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET                             0U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET                             0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK                              0x07010100U
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK                             0x07010100U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK                         0x00000001U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET                                 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_59
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH
+
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET                              0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET                              0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH                             3U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK                              0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK                             0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK  0x0000003FU
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT          0U
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH          6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK                          0x0003FF00U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH                                 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_60
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH                                 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_61
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH                                 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_62
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH                                 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_63
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH                                 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_64
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH                                 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_65
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK                    0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH                           20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK                              0x03FF0101U
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK                             0x03FF0101U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK                           0x00000001U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH                                   1U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR                                   0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET                                   0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_67
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN
+
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK                0x00000100U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET                        0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK                       0x03FF0000U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH                             16U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK                       0x03FF0000U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH                             16U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK                       0x03FF0000U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH                             16U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH                       16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK                              0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK                             0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK            0x0000000FU
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH                    4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET                          0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK       0x001F0000U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT              16U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH               5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK      0x1F000000U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT             24U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH              5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH                                16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH                                16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH                                16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK                         0x00FF0000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH                                 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH                                 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK                              0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK                             0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH                                 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH                                5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH                               5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK                              0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK                             0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH                                4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH                                5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK                              0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH                               5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK                        0x0F000000U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH                                4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK                              0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK                             0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH                                5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH                               5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK                              0x00010F1FU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK                             0x00010F1FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH                                4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH                                 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_79
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH                                16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH                                 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_80
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH                                16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH                                 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_81
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH                                16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK                              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH                              5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH                              5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH                               5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH                                   8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_82
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK                              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK                        0x00000007U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH                                3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH                               5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH                               5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH                               5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK                              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH                              5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH                              5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH                               5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH                                   8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_84
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK                              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK                        0x00000007U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH                                3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH                               5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH                               5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH                               5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK                              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH                              5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH                              5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH                               5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH                                   8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_86
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK                              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK                        0x00000007U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH                                3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH                               5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH                               5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH                               5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK                              0x07010101U
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK                             0x07010101U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK              0x00000001U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET                      0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET                            0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK            0x00010000U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET                    0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK                        0x07000000U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH                                3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK                              0x01010300U
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK                             0x01010300U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK                    0x0000001FU
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH                            5U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK                       0x00000300U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH                               2U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK                        0x00010000U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET                                0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET                             0U
+#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89
+#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK                              0x00010101U
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET                             0U
+#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN
+
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET                             0U
+#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN
+
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET                        0U
+#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK                              0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK                             0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK                    0x00070000U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH                            3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK                    0x07000000U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH                            3U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK                              0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK                             0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH                            3U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH                            8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH                            8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH                            8U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT            0U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT           16U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH                  16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT     16U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH     16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT      0U
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH     16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT           16U
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT            0U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH                  16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT      0U
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH     16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT     16U
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH     16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT            0U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT           16U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH           16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT    16U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT     0U
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT       0U
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT       0U
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT       0U
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET                         0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK                             0x00010103U
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK                            0x00010103U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK            0x00000003U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK       0x00000100U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT               8U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH               1U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR               0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET               0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT      16U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH       1U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR       0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET       0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET                             0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH                             3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH                         8U
+#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129
+#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW
+
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK                 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH                        17U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK                             0x01030107U
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK                            0x01030107U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH                        3U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET                          0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK                      0x00030000U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH                              2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK               0x01000000U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET                       0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK                             0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK                            0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK         0x00000003U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH                 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH                                8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH                                8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH                                8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH                                8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH                                8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH                                8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK                          0x7F000000U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH                                  7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_132
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK         0x0000000FU
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH                 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK          0x00000F00U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK           0x000F0000U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT       24U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK                0x0000000FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK        0x00000F00U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT                8U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK         0x000F0000U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT     24U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK         0x00000F00U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH                 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK           0x0F000000U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT        0U
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK        0x000F0000U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK         0x0F000000U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT                24U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT      0U
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK             0x00000F00U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK         0x000F0000U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH                 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK          0x0F000000U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK           0x0000000FU
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT        8U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK        0x0F000000U
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT               24U
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK                             0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK                            0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK         0x0000000FU
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT      8U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK             0x000F0000U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK                   0x3F000000U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH                           6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK                             0x070FFF01U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK                            0x070FFF01U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET                         0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK              0x000FFF00U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH                     12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK                    0x07000000U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH                            3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK                             0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK                            0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH                            7U
+#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141
+#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0
+
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH                            7U
+#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141
+#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1
+
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH                        4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH                         4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK                             0x000FFF07U
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK                            0x000FFF07U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK             0x00000007U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH                     3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK                 0x000FFF00U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH                        12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK                             0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK                            0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK           0x00000FFFU
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH                  12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK            0x00FF0000U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH                    8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK    0xFF000000U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT           24U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH            8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK                0x00000100U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET                        0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK               0x00010000U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET                           0U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK                             0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK                            0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET                            0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET                             0U
+#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK            0x003F0000U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH                    6U
+#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK             0x3F000000U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH                     6U
+#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK                             0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK                            0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK            0x000000FFU
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH                    8U
+#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149
+#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER
+
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK                   0x00000300U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH                           2U
+#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149
+#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK
+
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH                           8U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET                              0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK                            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK              0x000003FFU
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH                     10U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH                  16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK                            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH                     10U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH                  16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK                            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK              0x000003FFU
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH                     10U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH                  16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK                             0x00000103U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK                            0x00000103U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK                0x00000003U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH                        2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET                    0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH                 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK                             0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK                            0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH                  4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK          0x00FFFF00U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH                 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK                   0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH                          27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH                              8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK                    0x01FFFF00U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH                           17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH                  32U
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH                   8U
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1
+
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK              0x00FFFF00U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH                     16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH                     16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK            0x00010000U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET                    0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK                             0x03FF0003U
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK                            0x03FF0003U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH                      2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK                          0x03FF0000U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH                                 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_165
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK                             0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK                            0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH                          16U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH                                 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_168
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1
+
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH                          16U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK                          0x03FF0000U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH                                 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_170
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK                             0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK                            0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH                          16U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH                           8U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH                           8U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH                           8U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH                           8U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH                           8U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH                           8U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH                         8U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH                           8U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH                           8U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH                           8U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH                           8U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH                           8U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH                           8U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH                              8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH                          8U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH                          8U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH                          8U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH                             8U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH                          8U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH                          8U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH                          8U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH                             8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH                             8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH                             8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH                          8U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH                          8U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH                          8U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH                           8U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH                           8U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH                           8U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH                           8U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH                           8U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH                           8U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH                         8U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH                           8U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH                           8U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH                           8U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH                           8U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH                           8U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH                           8U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH                              8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH                          8U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH                          8U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH                          8U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH                             8U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH                          8U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH                          8U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH                          8U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH                             8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH                             8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH                             8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH                          8U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH                          8U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH                          8U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH                               8U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_190
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK            0x00010000U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK            0x01000000U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK                             0x01010103U
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK                            0x01010103U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK                  0x00000003U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH                          2U
+#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191
+#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN
+
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET                           0U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET                           0U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK              0x01000000U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET                      0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET                    0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET                              0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK                             0x03030101U
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK                            0x03030101U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH                                2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK                        0x03000000U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH                                2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK                             0x013F0300U
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK                            0x013F0300U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK                         0x00000001U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET                                 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_194
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO
+
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK                     0x00000300U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH                             2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK                      0x003F0000U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH                              6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET                         0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET                         0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH                   32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK            0x00000007U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH                    3U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH                       32U
+#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198
+#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH                       32U
+#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199
+#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK                  0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH                          3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203
+#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204
+#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK                             0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK                            0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET                     0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET                          0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK                   0x0FFF0000U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH                          12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK                             0x07030FFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK                            0x07030FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK                  0x00000FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH                         12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK                      0x00030000U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH                              2U
+#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206
+#define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE
+
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK          0x07000000U
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH                  3U
+#define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206
+#define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET
+
+#define LPDDR4__DENALI_CTL_207_READ_MASK                             0x010F0101U
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK                            0x010F0101U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET                     0U
+#define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207
+#define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN
+
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK          0x00000100U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET                  0U
+#define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207
+#define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN
+
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH                           4U
+#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207
+#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21
+
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET                           0U
+#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207
+#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22
+
+#define LPDDR4__DENALI_CTL_208_READ_MASK                             0x01FFFF01U
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK                            0x01FFFF01U
+#define LPDDR4__DENALI_CTL_208__FWC_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_208__FWC_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_208__FWC_WIDTH                                     1U
+#define LPDDR4__DENALI_CTL_208__FWC_WOCLR                                     0U
+#define LPDDR4__DENALI_CTL_208__FWC_WOSET                                     0U
+#define LPDDR4__FWC__REG DENALI_CTL_208
+#define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC
+
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK                  0x00FFFF00U
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH                         16U
+#define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208
+#define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS
+
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK                0x01000000U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET                        0U
+#define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208
+#define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN
+
+#define LPDDR4__DENALI_CTL_209_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET                    0U
+#define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209
+#define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR
+
+#define LPDDR4__DENALI_CTL_210_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH                           32U
+#define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210
+#define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0
+
+#define LPDDR4__DENALI_CTL_211_READ_MASK                             0x0000FF07U
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK                            0x0000FF07U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH                            3U
+#define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211
+#define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1
+
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH                              8U
+#define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211
+#define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND
+
+#define LPDDR4__DENALI_CTL_212_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH                           32U
+#define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212
+#define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0
+
+#define LPDDR4__DENALI_CTL_213_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH                           32U
+#define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213
+#define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1
+
+#define LPDDR4__DENALI_CTL_214_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH                           32U
+#define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214
+#define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0
+
+#define LPDDR4__DENALI_CTL_215_READ_MASK                             0x0000FF07U
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK                            0x0000FF07U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH                            3U
+#define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215
+#define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1
+
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH                              8U
+#define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215
+#define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND
+
+#define LPDDR4__DENALI_CTL_216_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH                           32U
+#define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216
+#define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0
+
+#define LPDDR4__DENALI_CTL_217_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH                           32U
+#define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217
+#define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1
+
+#define LPDDR4__DENALI_CTL_218_READ_MASK                             0x7FFF3F3FU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK                            0x7FFF3F3FU
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK                        0x0000003FU
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH                                6U
+#define LPDDR4__ECC_U_ID__REG DENALI_CTL_218
+#define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID
+
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH                                6U
+#define LPDDR4__ECC_C_ID__REG DENALI_CTL_218
+#define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID
+
+#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK     0x7FFF0000U
+#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT            16U
+#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH            15U
+#define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218
+#define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0
+
+#define LPDDR4__DENALI_CTL_219_READ_MASK                             0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK                            0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK       0x00007FFFU
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH              15U
+#define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219
+#define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0
+
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK     0x7FFF0000U
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT            16U
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH            15U
+#define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219
+#define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1
+
+#define LPDDR4__DENALI_CTL_220_READ_MASK                             0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK                            0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK       0x00007FFFU
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH              15U
+#define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220
+#define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1
+
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK     0x7FFF0000U
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT            16U
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH            15U
+#define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220
+#define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2
+
+#define LPDDR4__DENALI_CTL_221_READ_MASK                             0x00077FFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK                            0x00077FFFU
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK       0x00007FFFU
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH              15U
+#define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221
+#define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2
+
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK           0x00070000U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH                   3U
+#define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221
+#define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE
+
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET                         0U
+#define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221
+#define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START
+
+#define LPDDR4__DENALI_CTL_222_READ_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK                            0x010FFF01U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK           0x00000001U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET                   0U
+#define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222
+#define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS
+
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK                   0x000FFF00U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH                          12U
+#define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222
+#define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN
+
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET                          0U
+#define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222
+#define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE
+
+#define LPDDR4__DENALI_CTL_223_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH                     16U
+#define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223
+#define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL
+
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK              0xFFFF0000U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH                     16U
+#define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223
+#define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT
+
+#define LPDDR4__DENALI_CTL_224_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH                 32U
+#define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224
+#define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0
+
+#define LPDDR4__DENALI_CTL_225_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK          0x00000007U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH                  3U
+#define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225
+#define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1
+
+#define LPDDR4__DENALI_CTL_226_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH                   32U
+#define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226
+#define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0
+
+#define LPDDR4__DENALI_CTL_227_READ_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK                            0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK            0x00000007U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH                    3U
+#define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227
+#define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1
+
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK                 0x00001F00U
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH                         5U
+#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227
+#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK             0x001F0000U
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227
+#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK             0x1F000000U
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227
+#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_228_READ_MASK                             0x000F1F1FU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK                            0x000F1F1FU
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK                0x0000001FU
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH                        5U
+#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228
+#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT
+
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK                 0x00001F00U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH                         5U
+#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228
+#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT
+
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH                  4U
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI
+
+#define LPDDR4__DENALI_CTL_229_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_230_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_231_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_232_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_233_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_234_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_235_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_236_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_237_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_238_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_239_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_240_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_241_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_242_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH                           3U
+#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242
+#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23
+
+#define LPDDR4__DENALI_CTL_243_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT          0U
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH         16U
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0
+
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH          16U
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0
+
+#define LPDDR4__DENALI_CTL_244_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT     0U
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH    16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0
+
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT            16U
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH            16U
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0
+
+#define LPDDR4__DENALI_CTL_245_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT          0U
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH         16U
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0
+
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0
+
+#define LPDDR4__DENALI_CTL_246_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT   0U
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH  16U
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0
+
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT  16U
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH  16U
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0
+
+#define LPDDR4__DENALI_CTL_247_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT          0U
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH         16U
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1
+
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH          16U
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1
+
+#define LPDDR4__DENALI_CTL_248_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT     0U
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH    16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1
+
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT            16U
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH            16U
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1
+
+#define LPDDR4__DENALI_CTL_249_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT          0U
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH         16U
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1
+
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1
+
+#define LPDDR4__DENALI_CTL_250_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT   0U
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH  16U
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1
+
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT  16U
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH  16U
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1
+
+#define LPDDR4__DENALI_CTL_251_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT          0U
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH         16U
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2
+
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH          16U
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2
+
+#define LPDDR4__DENALI_CTL_252_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT     0U
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH    16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2
+
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT            16U
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH            16U
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2
+
+#define LPDDR4__DENALI_CTL_253_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT          0U
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH         16U
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2
+
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2
+
+#define LPDDR4__DENALI_CTL_254_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT   0U
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH  16U
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2
+
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT  16U
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH  16U
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2
+
+#define LPDDR4__DENALI_CTL_255_READ_MASK                             0x0000FF00U
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK                            0x0000FF00U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH                         8U
+#define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255
+#define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD
+
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK        0x0000FF00U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT                8U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH                8U
+#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255
+#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE
+
+#define LPDDR4__DENALI_CTL_256_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK               0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH                      20U
+#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256
+#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG
+
+#define LPDDR4__DENALI_CTL_257_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH                              12U
+#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257
+#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0
+
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH                                12U
+#define LPDDR4__ZQCL_F0__REG DENALI_CTL_257
+#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0
+
+#define LPDDR4__DENALI_CTL_258_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH                                12U
+#define LPDDR4__ZQCS_F0__REG DENALI_CTL_258
+#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0
+
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK                       0x0FFF0000U
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH                              12U
+#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258
+#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0
+
+#define LPDDR4__DENALI_CTL_259_READ_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK                            0x000FFF7FU
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK                       0x0000007FU
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH                               7U
+#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259
+#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0
+
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH                              12U
+#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259
+#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1
+
+#define LPDDR4__DENALI_CTL_260_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH                                12U
+#define LPDDR4__ZQCL_F1__REG DENALI_CTL_260
+#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1
+
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH                                12U
+#define LPDDR4__ZQCS_F1__REG DENALI_CTL_260
+#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1
+
+#define LPDDR4__DENALI_CTL_261_READ_MASK                             0x007F0FFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK                            0x007F0FFFU
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH                              12U
+#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261
+#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1
+
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH                               7U
+#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261
+#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1
+
+#define LPDDR4__DENALI_CTL_262_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH                              12U
+#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262
+#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2
+
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH                                12U
+#define LPDDR4__ZQCL_F2__REG DENALI_CTL_262
+#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2
+
+#define LPDDR4__DENALI_CTL_263_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH                                12U
+#define LPDDR4__ZQCS_F2__REG DENALI_CTL_263
+#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2
+
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK                       0x0FFF0000U
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH                              12U
+#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263
+#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2
+
+#define LPDDR4__DENALI_CTL_264_READ_MASK                             0x0100037FU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK                            0x0100037FU
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK                       0x0000007FU
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH                               7U
+#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264
+#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2
+
+#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK       0x00000300U
+#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT               8U
+#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH               2U
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP
+
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK                          0x000F0000U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH                                  4U
+#define LPDDR4__ZQ_REQ__REG DENALI_CTL_264
+#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ
+
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET                          0U
+#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264
+#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_CTL_265_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK                      0x00000FFFU
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH                             12U
+#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265
+#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0
+
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH                             12U
+#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265
+#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1
+
+#define LPDDR4__DENALI_CTL_266_READ_MASK                             0x01010FFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK                            0x01010FFFU
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK                      0x00000FFFU
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH                             12U
+#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266
+#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2
+
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET                              0U
+#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266
+#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT
+
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET                             0U
+#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266
+#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE
+
+#define LPDDR4__DENALI_CTL_267_READ_MASK                             0x03030303U
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK                            0x03030303U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_CTL_268_READ_MASK                             0x07070303U
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK                            0x07070303U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK                     0x00000003U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268
+#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0
+
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK                     0x00000300U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268
+#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1
+
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK                      0x00070000U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268
+#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0
+
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK                      0x07000000U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268
+#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1
+
+#define LPDDR4__DENALI_CTL_269_READ_MASK                             0xFFFF0F0FU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK                            0xFFFF0F0FU
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK                      0x0000000FU
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH                              4U
+#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269
+#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0
+
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK                      0x00000F00U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH                              4U
+#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269
+#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1
+
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269
+#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0
+
+#define LPDDR4__DENALI_CTL_270_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270
+#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0
+
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK                 0x00070000U
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH                         3U
+#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270
+#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0
+
+#define LPDDR4__DENALI_CTL_271_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271
+#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1
+
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271
+#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1
+
+#define LPDDR4__DENALI_CTL_272_READ_MASK                             0xFFFF0307U
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK                            0xFFFF0307U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH                         3U
+#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272
+#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1
+
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK                 0x00000300U
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH                         2U
+#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272
+#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2
+
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK                        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH                               16U
+#define LPDDR4__CS_MSK_0__REG DENALI_CTL_272
+#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0
+
+#define LPDDR4__DENALI_CTL_273_READ_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK                            0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK                        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH                               16U
+#define LPDDR4__CS_MSK_1__REG DENALI_CTL_273
+#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1
+
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET                        0U
+#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273
+#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN
+
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH                           5U
+#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273
+#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24
+
+#define LPDDR4__DENALI_CTL_274_READ_MASK                             0xFFFF1F01U
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK                            0xFFFF1F01U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET                           0U
+#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274
+#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25
+
+#define LPDDR4__DENALI_CTL_274__APREBIT_MASK                         0x00001F00U
+#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH                                 5U
+#define LPDDR4__APREBIT__REG DENALI_CTL_274
+#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT
+
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH                               8U
+#define LPDDR4__AGE_COUNT__REG DENALI_CTL_274
+#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH                       8U
+#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274
+#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_275_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET                             0U
+#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275
+#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN
+
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK          0x00000100U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET                  0U
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS
+
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET                           0U
+#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275
+#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK                    0x01000000U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET                            0U
+#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275
+#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN
+
+#define LPDDR4__DENALI_CTL_276_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET                             0U
+#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276
+#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN
+
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET                              0U
+#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276
+#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN
+
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET                         0U
+#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276
+#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN
+
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET                              0U
+#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276
+#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN
+
+#define LPDDR4__DENALI_CTL_277_READ_MASK                             0x011F0301U
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK                            0x011F0301U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET                            0U
+#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277
+#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT         8U
+#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH         2U
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT
+
+#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK       0x001F0000U
+#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT              16U
+#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH               5U
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE
+
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK                         0x01000000U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET                                 0U
+#define LPDDR4__SWAP_EN__REG DENALI_CTL_277
+#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN
+
+#define LPDDR4__DENALI_CTL_278_READ_MASK                             0x01030301U
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK                            0x01030301U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK           0x00000001U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET                   0U
+#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278
+#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE
+
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH                        2U
+#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278
+#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD
+
+#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK                          0x00030000U
+#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH                                  2U
+#define LPDDR4__CS_MAP__REG DENALI_CTL_278
+#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP
+
+#define LPDDR4__DENALI_CTL_278__REDUC_MASK                           0x01000000U
+#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH                                   1U
+#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR                                   0U
+#define LPDDR4__DENALI_CTL_278__REDUC_WOSET                                   0U
+#define LPDDR4__REDUC__REG DENALI_CTL_278
+#define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC
+
+#define LPDDR4__DENALI_CTL_279_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK        0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT                0U
+#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH               18U
+#define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279
+#define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_280_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK    0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT            0U
+#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH           18U
+#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280
+#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS
+
+#define LPDDR4__DENALI_CTL_281_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT      0U
+#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH     18U
+#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281
+#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK       0x01000000U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT              24U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH               1U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR               0U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET               0U
+#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281
+#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282_READ_MASK                             0x01010103U
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK                            0x01010103U
+#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK       0x00000003U
+#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT               0U
+#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH               2U
+#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK       0x00000100U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT               8U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH               1U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR               0U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET               0U
+#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK        0x00010000U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT               16U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH                1U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR                0U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET                0U
+#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK        0x01000000U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT               24U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH                1U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR                0U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET                0U
+#define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_283_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET                           0U
+#define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283
+#define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26
+
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET                           0U
+#define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283
+#define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27
+
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK       0x00010000U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT              16U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH               1U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR               0U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET               0U
+#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283
+#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN
+
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK        0x01000000U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT               24U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH                1U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR                0U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET                0U
+#define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283
+#define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN
+
+#define LPDDR4__DENALI_CTL_284_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT       0U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH       1U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR       0U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET       0U
+#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT       8U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH       1U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR       0U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET       0U
+#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT      16U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH       1U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR       0U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET       0U
+#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT       24U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH        1U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR        0U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET        0U
+#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_285_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT        0U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH        1U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR        0U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET        0U
+#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285
+#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK  0x00000100U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT          8U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH          1U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR          0U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET          0U
+#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285
+#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT
+
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT        16U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH         1U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR         0U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET         0U
+#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285
+#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN
+
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK   0x01000000U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT          24U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH           1U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR           0U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET           0U
+#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285
+#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_286_READ_MASK                             0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK                            0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286
+#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286
+#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286
+#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286
+#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_287_READ_MASK                             0x0F0F070FU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK                            0x0F0F070FU
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK               0x0000000FU
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH                       4U
+#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287
+#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK                 0x00000700U
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287
+#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287
+#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287
+#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_288_READ_MASK                             0x011F0F0FU
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK                            0x011F0F0FU
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK               0x0000000FU
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288
+#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH                       4U
+#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288
+#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH                              5U
+#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288
+#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS
+
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET                         0U
+#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288
+#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT
+
+#define LPDDR4__DENALI_CTL_289_READ_MASK                             0x01000103U
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK                            0x01000103U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK                    0x00000003U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH                            2U
+#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289
+#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ
+
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK                 0x00000100U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET                         0U
+#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289
+#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY
+
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET                             0U
+#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289
+#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ
+
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT                24U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET                 0U
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_CTL_290_READ_MASK                             0x03030301U
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK                            0x03030301U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK          0x00000001U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET                  0U
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE
+
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK             0x00000300U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290
+#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290
+#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK             0x03000000U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290
+#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_CTL_291_READ_MASK                             0x1F010101U
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK                            0x1F010101U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK         0x00000001U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET                 0U
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET                               0U
+#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291
+#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN
+
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET                               0U
+#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291
+#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN
+
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH                               5U
+#define LPDDR4__DFI_ERROR__REG DENALI_CTL_291
+#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR
+
+#define LPDDR4__DENALI_CTL_292_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH                         20U
+#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292
+#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET                           0U
+#define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292
+#define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28
+
+#define LPDDR4__DENALI_CTL_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH                           32U
+#define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293
+#define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0
+
+#define LPDDR4__DENALI_CTL_294_READ_MASK                             0x00001FFFU
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK                    0x00001FFFU
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH                           13U
+#define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294
+#define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1
+
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH                              32U
+#define LPDDR4__INT_ACK_0__REG DENALI_CTL_295
+#define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0
+
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH                              12U
+#define LPDDR4__INT_ACK_1__REG DENALI_CTL_296
+#define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1
+
+#define LPDDR4__DENALI_CTL_297_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH                             32U
+#define LPDDR4__INT_MASK_0__REG DENALI_CTL_297
+#define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0
+
+#define LPDDR4__DENALI_CTL_298_READ_MASK                             0x00001FFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK                      0x00001FFFU
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH                             13U
+#define LPDDR4__INT_MASK_1__REG DENALI_CTL_298
+#define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1
+
+#define LPDDR4__DENALI_CTL_299_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH                    32U
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0
+
+#define LPDDR4__DENALI_CTL_300_READ_MASK                             0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK                            0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK             0x00000007U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH                     3U
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1
+
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK             0x000FFF00U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH                    12U
+#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300
+#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH
+
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK               0x7F000000U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH                       7U
+#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300
+#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE
+
+#define LPDDR4__DENALI_CTL_301_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK          0x0000003FU
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH                  6U
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID
+
+#define LPDDR4__DENALI_CTL_302_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302
+#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_CTL_303_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303
+#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_CTL_304_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304
+#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_CTL_305_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305
+#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_CTL_306_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306
+#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_CTL_307_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307
+#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_CTL_308_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308
+#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_CTL_309_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309
+#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_CTL_310_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310
+#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_CTL_311_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH                        3U
+#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311
+#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_CTL_312_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH                  32U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0
+
+#define LPDDR4__DENALI_CTL_313_READ_MASK                             0x03033F07U
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK                            0x03033F07U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK           0x00000007U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH                   3U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1
+
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK               0x00003F00U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH                       6U
+#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313
+#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID
+
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH                     2U
+#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313
+#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK                  0x03000000U
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313
+#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_314_READ_MASK                             0xFF030303U
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK                            0xFF030303U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK                  0x00000003U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314
+#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK                  0x00000300U
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314
+#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK                  0x00030000U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314
+#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314
+#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_CTL_315_READ_MASK                             0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK                            0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315
+#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0
+
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK                     0x00000F00U
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315
+#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0
+
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315
+#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315
+#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1
+
+#define LPDDR4__DENALI_CTL_316_READ_MASK                             0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK                            0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316
+#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1
+
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316
+#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316
+#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2
+
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316
+#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2
+
+#define LPDDR4__DENALI_CTL_317_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET                               0U
+#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317
+#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0
+
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET                               0U
+#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317
+#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1
+
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET                               0U
+#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317
+#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2
+
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT                24U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET                 0U
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD
+
+#define LPDDR4__DENALI_CTL_318_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318
+#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318
+#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318
+#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK                   0x3F000000U
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318
+#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_319_READ_MASK                             0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK                            0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319
+#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319
+#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319
+#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0
+
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319
+#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1
+
+#define LPDDR4__DENALI_CTL_320_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320
+#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2
+
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
+#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320
+#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
+#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_321_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321
+#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
+#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321
+#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
+#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_322_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322
+#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
+#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322
+#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
+#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_323_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323
+#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK                  0x00001F00U
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323
+#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323
+#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323
+#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_324_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK                            0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324
+#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK                  0x00001F00U
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324
+#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK                  0x001F0000U
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324
+#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324
+#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_CTL_325_READ_MASK                             0x0F070F07U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK                            0x0F070F07U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0
+
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1
+
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_CTL_326_READ_MASK                             0x00000707U
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK                            0x00000707U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326
+#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2
+
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK                0x00000700U
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH                        3U
+#define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326
+#define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET                              0U
+#define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326
+#define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD
+
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET                             0U
+#define LPDDR4__SWLVL_START__REG DENALI_CTL_326
+#define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START
+
+#define LPDDR4__DENALI_CTL_327_READ_MASK                             0x01010100U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK                            0x01010100U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET                              0U
+#define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT
+
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET                           0U
+#define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET                            0U
+#define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0
+
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK                    0x01000000U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET                            0U
+#define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1
+
+#define LPDDR4__DENALI_CTL_328_READ_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK                            0x00010101U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET                            0U
+#define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328
+#define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2
+
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET                            0U
+#define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328
+#define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3
+
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET                        0U
+#define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328
+#define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN
+
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK                       0x01000000U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET                               0U
+#define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328
+#define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ
+
+#define LPDDR4__DENALI_CTL_329_READ_MASK                             0x013F3F01U
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK                            0x013F3F01U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK                        0x00000001U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET                                0U
+#define LPDDR4__WRLVL_CS__REG DENALI_CTL_329
+#define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS
+
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK                         0x00003F00U
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH                                 6U
+#define LPDDR4__WLDQSEN__REG DENALI_CTL_329
+#define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN
+
+#define LPDDR4__DENALI_CTL_329__WLMRD_MASK                           0x003F0000U
+#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH                                   6U
+#define LPDDR4__WLMRD__REG DENALI_CTL_329
+#define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD
+
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK                        0x01000000U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET                                0U
+#define LPDDR4__WRLVL_EN__REG DENALI_CTL_329
+#define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN
+
+#define LPDDR4__DENALI_CTL_330_READ_MASK                             0x0F010101U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK                            0x0F010101U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK              0x00000001U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET                      0U
+#define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330
+#define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE
+
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET                          0U
+#define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330
+#define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC
+
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK              0x00010000U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET                      0U
+#define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330
+#define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH                         4U
+#define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330
+#define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_CTL_331_READ_MASK                             0x07030101U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK                            0x07030101U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET                           0U
+#define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN
+
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET                            0U
+#define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE
+
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK                    0x00030000U
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH                            2U
+#define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK              0x07000000U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH                      3U
+#define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_332_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_333_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH                       16U
+#define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333
+#define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_334_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
+#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_335_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH                       16U
+#define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335
+#define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_336_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT         16U
+#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH         16U
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_337_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_338_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH                       16U
+#define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338
+#define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_339_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
+#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET                               0U
+#define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339
+#define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ
+
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET                          0U
+#define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339
+#define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_CTL_340_READ_MASK                             0x010F0F01U
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK                            0x010F0F01U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK                        0x00000001U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET                                0U
+#define LPDDR4__RDLVL_CS__REG DENALI_CTL_340
+#define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS
+
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK                    0x00000F00U
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH                            4U
+#define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340
+#define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH                       4U
+#define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340
+#define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN
+
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK              0x01000000U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET                      0U
+#define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340
+#define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE
+
+#define LPDDR4__DENALI_CTL_341_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_341_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK         0x00000001U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET                 0U
+#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341
+#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE
+
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET                          0U
+#define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341
+#define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC
+
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK              0x00010000U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET                      0U
+#define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341
+#define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK             0x01000000U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET                     0U
+#define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341
+#define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC
+
+#define LPDDR4__DENALI_CTL_342_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK         0x00000001U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET                 0U
+#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342
+#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET                           0U
+#define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342
+#define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN
+
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK              0x00010000U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET                      0U
+#define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342
+#define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN
+
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET                           0U
+#define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342
+#define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29
+
+#define LPDDR4__DENALI_CTL_343_READ_MASK                             0x03030101U
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK                            0x03030101U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET                            0U
+#define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE
+
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK               0x00000100U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET                       0U
+#define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK                    0x00030000U
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH                            2U
+#define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK               0x03000000U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH                       2U
+#define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_CTL_344_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_345_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH                       16U
+#define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345
+#define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_346_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
+#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT           16U
+#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH           16U
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_347_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT            0U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH           16U
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH                  16U
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_348_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT      0U
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH     16U
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT    16U
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH    16U
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_349_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_350_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH                       16U
+#define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350
+#define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_351_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_351_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT          0U
+#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH         16U
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT           16U
+#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH           16U
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_352_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT            0U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH           16U
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH                  16U
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_353_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT      0U
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH     16U
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT    16U
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH    16U
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_354_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_355_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH                       16U
+#define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355
+#define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_356_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
+#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK    0xFFFF0000U
+#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT           16U
+#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH           16U
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_357_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT            0U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH           16U
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK           0xFFFF0000U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH                  16U
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_358_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT      0U
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH     16U
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT    16U
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_359_READ_MASK                             0x00000100U
+#define LPDDR4__DENALI_CTL_359_WRITE_MASK                            0x00000100U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET                               0U
+#define LPDDR4__CALVL_REQ__REG DENALI_CTL_359
+#define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ
+
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK                        0x00000100U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET                                0U
+#define LPDDR4__CALVL_CS__REG DENALI_CTL_359
+#define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS
+
+#define LPDDR4__DENALI_CTL_360_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH                            20U
+#define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360
+#define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0
+
+#define LPDDR4__DENALI_CTL_361_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH                         20U
+#define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361
+#define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0
+
+#define LPDDR4__DENALI_CTL_362_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH                            20U
+#define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362
+#define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1
+
+#define LPDDR4__DENALI_CTL_363_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH                         20U
+#define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363
+#define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1
+
+#define LPDDR4__DENALI_CTL_364_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH                            20U
+#define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364
+#define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2
+
+#define LPDDR4__DENALI_CTL_365_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH                         20U
+#define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365
+#define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2
+
+#define LPDDR4__DENALI_CTL_366_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH                            20U
+#define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366
+#define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3
+
+#define LPDDR4__DENALI_CTL_367_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH                         20U
+#define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367
+#define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3
+
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET                           0U
+#define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367
+#define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30
+
+#define LPDDR4__DENALI_CTL_368_READ_MASK                             0x0101030FU
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK                            0x0101030FU
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH                           4U
+#define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368
+#define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31
+
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK                    0x00000300U
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH                            2U
+#define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368
+#define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK              0x00010000U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET                      0U
+#define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368
+#define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE
+
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET                          0U
+#define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368
+#define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC
+
+#define LPDDR4__DENALI_CTL_369_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK                            0x03010101U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK              0x00000001U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET                      0U
+#define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369
+#define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET                           0U
+#define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369
+#define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN
+
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET                            0U
+#define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369
+#define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE
+
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK                    0x03000000U
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH                            2U
+#define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369
+#define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP
+
+#define LPDDR4__DENALI_CTL_370_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370
+#define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_371_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH                       16U
+#define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371
+#define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_372_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
+#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372
+#define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_373_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH                       16U
+#define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373
+#define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_374_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT         16U
+#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH         16U
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_375_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375
+#define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_376_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH                       16U
+#define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376
+#define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_377_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
+#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK    0x00010000U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT           16U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH            1U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR            0U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET            0U
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE
+
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT        24U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH         1U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR         0U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET         0U
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE
+
+#define LPDDR4__DENALI_CTL_378_READ_MASK                             0x00000707U
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK                            0x00000707U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378
+#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY
+
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK                 0x00000700U
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378
+#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY
+
+#define LPDDR4__DENALI_CTL_379_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH                 32U
+#define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379
+#define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_380_READ_MASK                             0x1FFF3F07U
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK                            0x1FFF3F07U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK          0x00000007U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH                  3U
+#define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380
+#define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK          0x00003F00U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH                  6U
+#define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380
+#define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID
+
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK        0x1FFF0000U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT               16U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH               13U
+#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380
+#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL
+
+#define LPDDR4__DENALI_CTL_381_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH              32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0
+
+#define LPDDR4__DENALI_CTL_382_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH              32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1
+
+#define LPDDR4__DENALI_CTL_383_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH              32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2
+
+#define LPDDR4__DENALI_CTL_384_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT               0U
+#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH              32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3
+
+#define LPDDR4__DENALI_CTL_385_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT   0U
+#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH  16U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
+
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK                      0x00030000U
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH                              2U
+#define LPDDR4__CKE_STATUS__REG DENALI_CTL_385
+#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS
+
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET                           0U
+#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385
+#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID
+
+#define LPDDR4__DENALI_CTL_386_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH                          16U
+#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386
+#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY
+
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH                         8U
+#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386
+#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK                  0x7F000000U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH                          7U
+#define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386
+#define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_CTL_387_READ_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK                            0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK             0x0000007FU
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH                     7U
+#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387
+#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK               0x00007F00U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH                       7U
+#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0
+
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK               0x007F0000U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH                       7U
+#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1
+
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK               0x7F000000U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH                       7U
+#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2
+
+#define LPDDR4__DENALI_CTL_388_READ_MASK                             0x00FF037FU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK                            0x00FF037FU
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK                  0x0000007FU
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH                          7U
+#define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388
+#define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH                        2U
+#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388
+#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK                0x00FF0000U
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH                        8U
+#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388
+#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_CTL_389_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_CTL_390_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_391_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_392_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_393_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_394_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0
+
+#define LPDDR4__DENALI_CTL_395_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_CTL_396_READ_MASK                             0x00007F7FU
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK                            0x00007F7FU
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH                            7U
+#define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396
+#define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH                            7U
+#define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396
+#define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_CTL_397_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_CTL_398_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_399_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_400_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_401_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_402_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1
+
+#define LPDDR4__DENALI_CTL_403_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_CTL_404_READ_MASK                             0x00007F7FU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK                            0x00007F7FU
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH                            7U
+#define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404
+#define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH                            7U
+#define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404
+#define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_CTL_405_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_CTL_406_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_407_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_408_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_409_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_410_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2
+
+#define LPDDR4__DENALI_CTL_411_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_CTL_412_READ_MASK                             0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK                            0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH                            7U
+#define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412
+#define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH                            7U
+#define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412
+#define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412
+#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412
+#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_CTL_413_READ_MASK                             0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK                            0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413
+#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH                   4U
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK            0x000F0000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH                    4U
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
+
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH                           8U
+#define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413
+#define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_CTL_414_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK                   0x000003FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH                          10U
+#define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414
+#define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW
+
+#define LPDDR4__DENALI_CTL_415_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH                        32U
+#define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415
+#define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_CTL_416_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH                         32U
+#define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416
+#define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_CTL_417_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH                           8U
+#define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417
+#define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK                   0x0003FF00U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH                          10U
+#define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417
+#define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_CTL_418_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH                        32U
+#define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418
+#define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_CTL_419_READ_MASK                             0x000101FFU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK                            0x000101FFU
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH                         8U
+#define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419
+#define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK                        0x00000100U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET                                0U
+#define LPDDR4__RDLVL_EN__REG DENALI_CTL_419
+#define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN
+
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET                           0U
+#define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419
+#define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN
+
+#define LPDDR4__DENALI_CTL_420_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH                         32U
+#define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420
+#define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_CTL_421_READ_MASK                             0x00FF0707U
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK                            0x00FF0707U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK              0x00000007U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH                      3U
+#define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421
+#define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK         0x00000700U
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH                 3U
+#define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421
+#define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH                           8U
+#define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421
+#define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_CTL_422_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH                       10U
+#define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK           0x03FF0000U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH                  10U
+#define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_CTL_423_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_423_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH                       10U
+#define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423
+#define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK           0x03FF0000U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH                  10U
+#define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423
+#define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_CTL_424_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_424_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH                       10U
+#define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424
+#define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK           0x03FF0000U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH                  10U
+#define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424
+#define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_CTL_425_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH                        32U
+#define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425
+#define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_CTL_426_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH                         32U
+#define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426
+#define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_CTL_427_READ_MASK                             0x070F0101U
+#define LPDDR4__DENALI_CTL_427_WRITE_MASK                            0x070F0101U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET                         0U
+#define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427
+#define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK                        0x00000100U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET                                0U
+#define LPDDR4__CALVL_EN__REG DENALI_CTL_427
+#define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN
+
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH                      4U
+#define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427
+#define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK              0x07000000U
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427
+#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_CTL_428_READ_MASK                             0x7F7F0707U
+#define LPDDR4__DENALI_CTL_428_WRITE_MASK                            0x7F7F0707U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK              0x00000007U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428
+#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428
+#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK                 0x007F0000U
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH                         7U
+#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428
+#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK                 0x7F000000U
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH                         7U
+#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428
+#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_429_READ_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_429_WRITE_MASK                            0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK                 0x0000007FU
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH                         7U
+#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429
+#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK                 0x00007F00U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH                         7U
+#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429
+#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK                 0x007F0000U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH                         7U
+#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429
+#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK                 0x7F000000U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH                         7U
+#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429
+#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_430_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_CTL_430_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK               0x000000FFU
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH                       8U
+#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430
+#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY
+
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET                            0U
+#define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430
+#define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING
+
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK     0x00010000U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT            16U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH             1U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR             0U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET             0U
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE
+
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK                0x01000000U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET                        0U
+#define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430
+#define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE
+
+#define LPDDR4__DENALI_CTL_431_READ_MASK                             0x07070701U
+#define LPDDR4__DENALI_CTL_431_WRITE_MASK                            0x07070701U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET                           0U
+#define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32
+
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK                   0x00000700U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH                           3U
+#define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33
+
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH                           3U
+#define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34
+
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK                   0x07000000U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH                           3U
+#define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35
+
+#define LPDDR4__DENALI_CTL_432_READ_MASK                             0x0F070707U
+#define LPDDR4__DENALI_CTL_432_WRITE_MASK                            0x0F070707U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH                           3U
+#define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36
+
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK                   0x00000700U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH                           3U
+#define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37
+
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH                           3U
+#define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38
+
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH                           4U
+#define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39
+
+#define LPDDR4__DENALI_CTL_433_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_433_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH                           4U
+#define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40
+
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH                           4U
+#define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41
+
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH                           4U
+#define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42
+
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH                           4U
+#define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43
+
+#define LPDDR4__DENALI_CTL_434_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_434_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH                           4U
+#define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44
+
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH                           4U
+#define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45
+
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH                           4U
+#define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46
+
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH                           4U
+#define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47
+
+#define LPDDR4__DENALI_CTL_435_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_435_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH                           4U
+#define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48
+
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH                           4U
+#define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49
+
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH                           4U
+#define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50
+
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH                           4U
+#define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51
+
+#define LPDDR4__DENALI_CTL_436_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_436_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH                           4U
+#define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52
+
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH                           4U
+#define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53
+
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH                           4U
+#define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54
+
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH                           4U
+#define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55
+
+#define LPDDR4__DENALI_CTL_437_READ_MASK                             0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_437_WRITE_MASK                            0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH                           4U
+#define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437
+#define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56
+
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH                           4U
+#define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437
+#define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57
+
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH                           4U
+#define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437
+#define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58
+
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH                       8U
+#define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437
+#define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_438_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_438_WRITE_MASK                            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK               0x000000FFU
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH                       8U
+#define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438
+#define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK
+
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK         0x00000300U
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH                 2U
+#define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438
+#define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH                                  8U
+#define LPDDR4__NWR_F0__REG DENALI_CTL_438
+#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0
+
+#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH                                  8U
+#define LPDDR4__NWR_F1__REG DENALI_CTL_438
+#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1
+
+#define LPDDR4__DENALI_CTL_439_READ_MASK                             0x001F01FFU
+#define LPDDR4__DENALI_CTL_439_WRITE_MASK                            0x001F01FFU
+#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH                                  8U
+#define LPDDR4__NWR_F2__REG DENALI_CTL_439
+#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2
+
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET                           0U
+#define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439
+#define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59
+
+#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH  5U
+#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439
+#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS
+
+#define LPDDR4__DENALI_CTL_440_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT       0U
+#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH      32U
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0
+
+#define LPDDR4__DENALI_CTL_441_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT       0U
+#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH      32U
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1
+
+#define LPDDR4__DENALI_CTL_442_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_442_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET                    0U
+#define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442
+#define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT       8U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH       1U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR       0U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET       0U
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH  1U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR  0U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET  0U
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT     24U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH      1U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR      0U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET      0U
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_443_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_443_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT       0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH       1U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR       0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET       0U
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK   0x00000100U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT           8U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH           1U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR           0U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET           0U
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_444_READ_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_444_WRITE_MASK                            0x00010101U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_445_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH                        32U
+#define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445
+#define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0
+
+#define LPDDR4__DENALI_CTL_446_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH                        32U
+#define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446
+#define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1
+
+#define LPDDR4__DENALI_CTL_447_READ_MASK                             0x00000107U
+#define LPDDR4__DENALI_CTL_447_WRITE_MASK                            0x00000107U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH                         3U
+#define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447
+#define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2
+
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK      0x00000100U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT              8U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH              1U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR              0U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET              0U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447
+#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_448_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT  0U
+#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0
+
+#define LPDDR4__DENALI_CTL_449_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT  0U
+#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1
+
+#define LPDDR4__DENALI_CTL_450_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_450_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT  0U
+#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH  3U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2
+
+#define LPDDR4__DENALI_CTL_451_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH                        32U
+#define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451
+#define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0
+
+#define LPDDR4__DENALI_CTL_452_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH                        32U
+#define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452
+#define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1
+
+#define LPDDR4__DENALI_CTL_453_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH                        32U
+#define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453
+#define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2
+
+#define LPDDR4__DENALI_CTL_454_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_CTL_454_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK                 0x0000000FU
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH                         4U
+#define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454
+#define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3
+
+#define LPDDR4__DENALI_CTL_455_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT            0U
+#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH           32U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0
+
+#define LPDDR4__DENALI_CTL_456_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT            0U
+#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH           32U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1
+
+#define LPDDR4__DENALI_CTL_457_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT            0U
+#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH           32U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2
+
+#define LPDDR4__DENALI_CTL_458_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_CTL_458_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK    0x0000000FU
+#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT            0U
+#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH            4U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3
+
+#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
index e8579ff7a2..d8c7a5222e 100644
--- a/drivers/ram/k3-j721e/lpddr4_phy_core_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
@@ -1,30 +1,29 @@
 /* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
  *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
 #define REG_LPDDR4_PHY_CORE_MACROS_H_
 
-#define LPDDR4__DENALI_PHY_1280_READ_MASK				            0x00000003U
-#define LPDDR4__DENALI_PHY_1280_WRITE_MASK				           0x00000003U
-#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK				   0x00000003U
-#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH				           2U
+#define LPDDR4__DENALI_PHY_1280_READ_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_1280_WRITE_MASK                           0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH                           2U
 #define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280
 #define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL
 
-#define LPDDR4__DENALI_PHY_1281_READ_MASK				            0x1F030101U
-#define LPDDR4__DENALI_PHY_1281_WRITE_MASK				           0x1F030101U
+#define LPDDR4__DENALI_PHY_1281_READ_MASK                            0x1F030101U
+#define LPDDR4__DENALI_PHY_1281_WRITE_MASK                           0x1F030101U
 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK        0x00000001U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT				0U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET				0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET                0U
 #define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281
 #define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF
 
@@ -37,65 +36,65 @@
 #define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN
 
 #define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK             0x00030000U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH                     2U
 #define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281
 #define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX
 
 #define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK            0x1F000000U
-#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281
 #define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0
 
-#define LPDDR4__DENALI_PHY_1282_READ_MASK				            0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_1282_WRITE_MASK				           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282_WRITE_MASK                           0x1F1F1F1FU
 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK            0x0000001FU
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282
 #define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK            0x00001F00U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282
 #define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK            0x001F0000U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282
 #define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0
 
 #define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK            0x1F000000U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT				   24U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282
 #define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1
 
-#define LPDDR4__DENALI_PHY_1283_READ_MASK				            0x001F1F1FU
-#define LPDDR4__DENALI_PHY_1283_WRITE_MASK				           0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1283_READ_MASK                            0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1283_WRITE_MASK                           0x001F1F1FU
 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK            0x0000001FU
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283
 #define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK            0x00001F00U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283
 #define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1
 
 #define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK            0x001F0000U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH				    5U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH                    5U
 #define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283
 #define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1
 
-#define LPDDR4__DENALI_PHY_1284_READ_MASK				            0x011F07FFU
-#define LPDDR4__DENALI_PHY_1284_WRITE_MASK				           0x011F07FFU
+#define LPDDR4__DENALI_PHY_1284_READ_MASK                            0x011F07FFU
+#define LPDDR4__DENALI_PHY_1284_WRITE_MASK                           0x011F07FFU
 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_MASK     0x000007FFU
 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH            11U
@@ -104,25 +103,25 @@
 
 #define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_MASK        0x001F0000U
 #define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_WIDTH				5U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_WIDTH                5U
 #define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1284
 #define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT
 
 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_MASK        0x01000000U
 #define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_SHIFT               24U
-#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOSET				0U
+#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOSET                0U
 #define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1284
 #define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE
 
-#define LPDDR4__DENALI_PHY_1285_READ_MASK				            0x07FF0100U
-#define LPDDR4__DENALI_PHY_1285_WRITE_MASK				           0x07FF0100U
+#define LPDDR4__DENALI_PHY_1285_READ_MASK                            0x07FF0100U
+#define LPDDR4__DENALI_PHY_1285_WRITE_MASK                           0x07FF0100U
 #define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_MASK           0x00000001U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOSET				   0U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOSET                   0U
 #define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1285
 #define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE
 
@@ -134,75 +133,75 @@
 #define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1285
 #define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
 
-#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_MASK				0x07FF0000U
-#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_WIDTH				       11U
+#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_MASK                0x07FF0000U
+#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_WIDTH                       11U
 #define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1285
 #define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START
 
-#define LPDDR4__DENALI_PHY_1286_READ_MASK				            0x000107FFU
-#define LPDDR4__DENALI_PHY_1286_WRITE_MASK				           0x000107FFU
+#define LPDDR4__DENALI_PHY_1286_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1286_WRITE_MASK                           0x000107FFU
 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_MASK           0x000007FFU
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_WIDTH				  11U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_WIDTH                  11U
 #define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1286
 #define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY
 
 #define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_MASK           0x00010000U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOSET				   0U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOSET                   0U
 #define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1286
 #define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE
 
 #define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_MASK        0x01000000U
 #define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_SHIFT               24U
-#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOSET				0U
+#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOSET                0U
 #define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1286
 #define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT
 
 #define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_MASK         0x00000001U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOSET				 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOSET                 0U
 #define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1287
 #define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR
 
-#define LPDDR4__DENALI_PHY_1288_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1288_WRITE_MASK				           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_WIDTH				        32U
+#define LPDDR4__DENALI_PHY_1288_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1288_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_WIDTH                        32U
 #define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1288
 #define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0
 
-#define LPDDR4__DENALI_PHY_1289_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1289_WRITE_MASK				           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_WIDTH				        32U
+#define LPDDR4__DENALI_PHY_1289_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_WIDTH                        32U
 #define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1289
 #define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1
 
-#define LPDDR4__DENALI_PHY_1290_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1290_WRITE_MASK				           0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_WIDTH				        32U
+#define LPDDR4__DENALI_PHY_1290_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_WIDTH                        32U
 #define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1290
 #define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2
 
-#define LPDDR4__DENALI_PHY_1291_READ_MASK				            0x0101FF01U
-#define LPDDR4__DENALI_PHY_1291_WRITE_MASK				           0x0101FF01U
+#define LPDDR4__DENALI_PHY_1291_READ_MASK                            0x0101FF01U
+#define LPDDR4__DENALI_PHY_1291_WRITE_MASK                           0x0101FF01U
 #define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_MASK               0x00000001U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WIDTH				       1U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOCLR				       0U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOSET				       0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOSET                       0U
 #define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1291
 #define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE
 
@@ -213,32 +212,32 @@
 #define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET
 
 #define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOSET				   0U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOSET                   0U
 #define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1291
 #define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE
 
-#define LPDDR4__DENALI_PHY_1292_READ_MASK				            0x0007FF0FU
-#define LPDDR4__DENALI_PHY_1292_WRITE_MASK				           0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1292_READ_MASK                            0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1292_WRITE_MASK                           0x0007FF0FU
 #define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_MASK               0x0000000FU
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_WIDTH				       4U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_WIDTH                       4U
 #define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1292
 #define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP
 
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_MASK				  0x0007FF00U
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_SHIFT				          8U
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_WIDTH				         11U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_MASK                  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_WIDTH                         11U
 #define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1292
 #define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR
 
-#define LPDDR4__DENALI_PHY_1293_READ_MASK				            0xFF0F07FFU
-#define LPDDR4__DENALI_PHY_1293_WRITE_MASK				           0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1293_READ_MASK                            0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1293_WRITE_MASK                           0xFF0F07FFU
 #define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_MASK           0x000007FFU
-#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_WIDTH				  11U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_WIDTH                  11U
 #define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1293
 #define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK
 
@@ -249,13 +248,13 @@
 #define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT
 
 #define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_MASK               0xFF000000U
-#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_SHIFT				      24U
-#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_WIDTH				       8U
+#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_WIDTH                       8U
 #define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1293
 #define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP
 
-#define LPDDR4__DENALI_PHY_1294_READ_MASK				            0x01030007U
-#define LPDDR4__DENALI_PHY_1294_WRITE_MASK				           0x01030007U
+#define LPDDR4__DENALI_PHY_1294_READ_MASK                            0x01030007U
+#define LPDDR4__DENALI_PHY_1294_WRITE_MASK                           0x01030007U
 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U
 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT       0U
 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH       3U
@@ -271,34 +270,34 @@
 #define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS
 
 #define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_MASK            0x00030000U
-#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_WIDTH				    2U
+#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_WIDTH                    2U
 #define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1294
 #define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE
 
 #define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_MASK               0x01000000U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_SHIFT				      24U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WIDTH				       1U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOCLR				       0U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOSET				       0U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOSET                       0U
 #define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1294
 #define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR
 
-#define LPDDR4__DENALI_PHY_1295_READ_MASK				            0xFFFF0101U
-#define LPDDR4__DENALI_PHY_1295_WRITE_MASK				           0xFFFF0101U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_MASK				 0x00000001U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WIDTH				         1U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOCLR				         0U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOSET				         0U
+#define LPDDR4__DENALI_PHY_1295_READ_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1295_WRITE_MASK                           0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOSET                         0U
 #define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1295
 #define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE
 
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_MASK				  0x00000100U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_SHIFT				          8U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WIDTH				          1U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOCLR				          0U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOSET				          0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_MASK                  0x00000100U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOSET                          0U
 #define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1295
 #define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS
 
@@ -309,30 +308,30 @@
 #define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT
 
 #define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_MASK         0xFF000000U
-#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_SHIFT				24U
-#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_WIDTH                 8U
 #define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1295
 #define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT
 
-#define LPDDR4__DENALI_PHY_1296_READ_MASK				            0xFF3F0103U
-#define LPDDR4__DENALI_PHY_1296_WRITE_MASK				           0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1296_READ_MASK                            0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1296_WRITE_MASK                           0xFF3F0103U
 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_MASK              0x00000003U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_WIDTH				      2U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_WIDTH                      2U
 #define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1296
 #define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT
 
 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_MASK        0x00000100U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT				8U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET				0U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET                0U
 #define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1296
 #define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ
 
 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_MASK        0x003F0000U
 #define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_WIDTH				6U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_WIDTH                6U
 #define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1296
 #define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START
 
@@ -342,8 +341,8 @@
 #define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1296
 #define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT
 
-#define LPDDR4__DENALI_PHY_1297_READ_MASK				            0x010101FFU
-#define LPDDR4__DENALI_PHY_1297_WRITE_MASK				           0x010101FFU
+#define LPDDR4__DENALI_PHY_1297_READ_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_1297_WRITE_MASK                           0x010101FFU
 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_MASK      0x000000FFU
 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT              0U
 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH              8U
@@ -360,22 +359,22 @@
 
 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_MASK        0x00010000U
 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOSET				0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOSET                0U
 #define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1297
 #define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY
 
 #define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_MASK           0x01000000U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_SHIFT				  24U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOSET				   0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOSET                   0U
 #define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1297
 #define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START
 
-#define LPDDR4__DENALI_PHY_1298_READ_MASK				            0x0F0F0100U
-#define LPDDR4__DENALI_PHY_1298_WRITE_MASK				           0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1298_READ_MASK                            0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1298_WRITE_MASK                           0x0F0F0100U
 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK   0x00000001U
 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH           1U
@@ -393,24 +392,24 @@
 #define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE
 
 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_MASK             0x000F0000U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_SHIFT				    16U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_WIDTH				     4U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_WIDTH                     4U
 #define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1298
 #define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0
 
 #define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK             0x0F000000U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH				     4U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH                     4U
 #define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298
 #define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1
 
-#define LPDDR4__DENALI_PHY_1299_READ_MASK				            0x010F0F01U
-#define LPDDR4__DENALI_PHY_1299_WRITE_MASK				           0x010F0F01U
+#define LPDDR4__DENALI_PHY_1299_READ_MASK                            0x010F0F01U
+#define LPDDR4__DENALI_PHY_1299_WRITE_MASK                           0x010F0F01U
 #define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_MASK        0x00000001U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT				0U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOSET				0U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOSET                0U
 #define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1299
 #define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL
 
@@ -434,8 +433,8 @@
 #define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1299
 #define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL
 
-#define LPDDR4__DENALI_PHY_1300_READ_MASK				            0xFFFF0101U
-#define LPDDR4__DENALI_PHY_1300_WRITE_MASK				           0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1300_READ_MASK                            0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1300_WRITE_MASK                           0xFFFF0101U
 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK     0x00000001U
 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH             1U
@@ -453,13 +452,13 @@
 #define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
 
 #define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_SHIFT				16U
-#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_WIDTH				16U
+#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_WIDTH                16U
 #define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1300
 #define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL
 
-#define LPDDR4__DENALI_PHY_1301_READ_MASK				            0x0001010FU
-#define LPDDR4__DENALI_PHY_1301_WRITE_MASK				           0x0001010FU
+#define LPDDR4__DENALI_PHY_1301_READ_MASK                            0x0001010FU
+#define LPDDR4__DENALI_PHY_1301_WRITE_MASK                           0x0001010FU
 #define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK  0x0000000FU
 #define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH          4U
@@ -476,49 +475,49 @@
 
 #define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_MASK        0x00010000U
 #define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOSET				0U
+#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOSET                0U
 #define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1301
 #define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS
 
-#define LPDDR4__DENALI_PHY_1302_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1302_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1302_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1302_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_WIDTH				    32U
+#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_WIDTH                    32U
 #define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1302
 #define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS
 
-#define LPDDR4__DENALI_PHY_1303_READ_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1303_WRITE_MASK				           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_MASK				   0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_WIDTH				          16U
+#define LPDDR4__DENALI_PHY_1303_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1303_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_WIDTH                          16U
 #define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1303
 #define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT
 
-#define LPDDR4__DENALI_PHY_1304_READ_MASK				            0x00000001U
-#define LPDDR4__DENALI_PHY_1304_WRITE_MASK				           0x00000001U
+#define LPDDR4__DENALI_PHY_1304_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1304_WRITE_MASK                           0x00000001U
 #define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_MASK              0x00000001U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WIDTH				      1U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOCLR				      0U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOSET				      0U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOSET                      0U
 #define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1304
 #define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS
 
-#define LPDDR4__DENALI_PHY_1305_READ_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_1305_WRITE_MASK				           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1305_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1305_WRITE_MASK                           0x0F0F0F0FU
 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_MASK            0x0000000FU
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_WIDTH                    4U
 #define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1305
 #define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0
 
 #define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_MASK            0x00000F00U
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_WIDTH				    4U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_WIDTH                    4U
 #define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1305
 #define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1
 
@@ -534,8 +533,8 @@
 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1305
 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0
 
-#define LPDDR4__DENALI_PHY_1306_READ_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_1306_WRITE_MASK				           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306_WRITE_MASK                           0x0F0F0F0FU
 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK   0x0000000FU
 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH           4U
@@ -560,8 +559,8 @@
 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1306
 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1
 
-#define LPDDR4__DENALI_PHY_1307_READ_MASK				            0x01FF0F0FU
-#define LPDDR4__DENALI_PHY_1307_WRITE_MASK				           0x01FF0F0FU
+#define LPDDR4__DENALI_PHY_1307_READ_MASK                            0x01FF0F0FU
+#define LPDDR4__DENALI_PHY_1307_WRITE_MASK                           0x01FF0F0FU
 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK   0x0000000FU
 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH           4U
@@ -575,38 +574,38 @@
 #define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1
 
 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_MASK            0x00FF0000U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_SHIFT				   16U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_WIDTH				    8U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_WIDTH                    8U
 #define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1307
 #define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0
 
 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_MASK        0x01000000U
 #define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_SHIFT               24U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOSET				0U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOSET                0U
 #define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1307
 #define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE
 
-#define LPDDR4__DENALI_PHY_1308_READ_MASK				            0x001FFFFFU
-#define LPDDR4__DENALI_PHY_1308_WRITE_MASK				           0x001FFFFFU
+#define LPDDR4__DENALI_PHY_1308_READ_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_PHY_1308_WRITE_MASK                           0x001FFFFFU
 #define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_MASK          0x000000FFU
-#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_WIDTH                  8U
 #define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1308
 #define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD
 
 #define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_MASK          0x001FFF00U
-#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_WIDTH				 13U
+#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_WIDTH                 13U
 #define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1308
 #define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL
 
-#define LPDDR4__DENALI_PHY_1309_READ_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1309_WRITE_MASK				           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1309_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1309_WRITE_MASK                           0x0001FFFFU
 #define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_WIDTH				 16U
+#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_WIDTH                 16U
 #define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1309
 #define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE
 
@@ -618,11 +617,11 @@
 #define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1309
 #define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK
 
-#define LPDDR4__DENALI_PHY_1310_READ_MASK				            0x0007FFFFU
-#define LPDDR4__DENALI_PHY_1310_WRITE_MASK				           0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1310_READ_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1310_WRITE_MASK                           0x0007FFFFU
 #define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_MASK           0x0007FFFFU
-#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_WIDTH				  19U
+#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_WIDTH                  19U
 #define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1310
 #define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL
 
@@ -632,8 +631,8 @@
 #define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1310
 #define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS
 
-#define LPDDR4__DENALI_PHY_1311_READ_MASK				            0x000003FFU
-#define LPDDR4__DENALI_PHY_1311_WRITE_MASK				           0x000003FFU
+#define LPDDR4__DENALI_PHY_1311_READ_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_1311_WRITE_MASK                           0x000003FFU
 #define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_MASK    0x000003FFU
 #define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_SHIFT            0U
 #define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_WIDTH           10U
@@ -642,52 +641,52 @@
 
 #define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_MASK        0x00030000U
 #define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_WIDTH				2U
+#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_WIDTH                2U
 #define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__REG DENALI_PHY_1311
 #define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__FLD LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS
 
-#define LPDDR4__DENALI_PHY_1312_READ_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1312_WRITE_MASK				           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_MASK				  0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_WIDTH				         16U
+#define LPDDR4__DENALI_PHY_1312_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1312_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_WIDTH                         16U
 #define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1312
 #define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0
 
-#define LPDDR4__DENALI_PHY_1313_READ_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1313_WRITE_MASK				           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1313_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1313_WRITE_MASK                           0x0001FFFFU
 #define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_MASK          0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_WIDTH				 17U
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_WIDTH                 17U
 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1313
 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0
 
-#define LPDDR4__DENALI_PHY_1314_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1314_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1314_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1314_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_MASK     0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_WIDTH            18U
 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__REG DENALI_PHY_1314
 #define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0
 
-#define LPDDR4__DENALI_PHY_1315_READ_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1315_WRITE_MASK				           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_MASK				  0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_SHIFT				          0U
-#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_WIDTH				         16U
+#define LPDDR4__DENALI_PHY_1315_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1315_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_WIDTH                         16U
 #define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1315
 #define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1
 
-#define LPDDR4__DENALI_PHY_1316_READ_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1316_WRITE_MASK				           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1316_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1316_WRITE_MASK                           0x0001FFFFU
 #define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_MASK          0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_WIDTH				 17U
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_WIDTH                 17U
 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1316
 #define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1
 
-#define LPDDR4__DENALI_PHY_1317_READ_MASK				            0x0103FFFFU
-#define LPDDR4__DENALI_PHY_1317_WRITE_MASK				           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1317_READ_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1317_WRITE_MASK                           0x0103FFFFU
 #define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_MASK     0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_WIDTH            18U
@@ -702,167 +701,167 @@
 #define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1317
 #define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL
 
-#define LPDDR4__DENALI_PHY_1318_READ_MASK				            0x0001FF0FU
-#define LPDDR4__DENALI_PHY_1318_WRITE_MASK				           0x0001FF0FU
-#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_MASK				0x0000000FU
-#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_WIDTH				        4U
+#define LPDDR4__DENALI_PHY_1318_READ_MASK                            0x0001FF0FU
+#define LPDDR4__DENALI_PHY_1318_WRITE_MASK                           0x0001FF0FU
+#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_MASK                0x0000000FU
+#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_WIDTH                        4U
 #define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1318
 #define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT
 
-#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_SHIFT				          8U
-#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_WIDTH				          8U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_WIDTH                          8U
 #define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1318
 #define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP
 
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_MASK				 0x00010000U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_SHIFT				        16U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WIDTH				         1U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOCLR				         0U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOSET				         0U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_MASK                 0x00010000U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOSET                         0U
 #define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1318
 #define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN
 
-#define LPDDR4__DENALI_PHY_1319_READ_MASK				            0x000103FFU
-#define LPDDR4__DENALI_PHY_1319_WRITE_MASK				           0x000103FFU
+#define LPDDR4__DENALI_PHY_1319_READ_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_1319_WRITE_MASK                           0x000103FFU
 #define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_MASK        0x000003FFU
-#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH               10U
 #define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1319
 #define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG
 
 #define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_MASK           0x00010000U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WIDTH				   1U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOCLR				   0U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOSET				   0U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOSET                   0U
 #define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1319
 #define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY
 
-#define LPDDR4__DENALI_PHY_1320_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1320_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1320_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1320_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_MASK              0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_WIDTH				     18U
+#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_WIDTH                     18U
 #define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1320
 #define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM
 
-#define LPDDR4__DENALI_PHY_1321_READ_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1321_WRITE_MASK				           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1321_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1321_WRITE_MASK                           0x0001FFFFU
 #define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_MASK              0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_WIDTH				     17U
+#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_WIDTH                     17U
 #define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1321
 #define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM
 
-#define LPDDR4__DENALI_PHY_1322_READ_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1322_WRITE_MASK				           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1322_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1322_WRITE_MASK                           0x0001FFFFU
 #define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_MASK               0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_WIDTH				      17U
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_WIDTH                      17U
 #define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1322
 #define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM
 
-#define LPDDR4__DENALI_PHY_1323_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1323_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1323_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1323_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_MASK              0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_WIDTH				     18U
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_WIDTH                     18U
 #define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1323
 #define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM
 
-#define LPDDR4__DENALI_PHY_1324_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1324_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1324_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1324_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_MASK               0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_WIDTH				      18U
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_WIDTH                      18U
 #define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1324
 #define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM
 
-#define LPDDR4__DENALI_PHY_1325_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1325_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_MASK               0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_WIDTH				      18U
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_WIDTH                      18U
 #define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1325
 #define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM
 
-#define LPDDR4__DENALI_PHY_1326_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1326_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_MASK               0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_WIDTH				      18U
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_WIDTH                      18U
 #define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1326
 #define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM
 
-#define LPDDR4__DENALI_PHY_1327_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1327_WRITE_MASK				           0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_MASK				0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_WIDTH				       18U
+#define LPDDR4__DENALI_PHY_1327_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_MASK                0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_WIDTH                       18U
 #define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1327
 #define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM
 
-#define LPDDR4__DENALI_PHY_1328_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1328_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_MASK               0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_WIDTH				      18U
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_WIDTH                      18U
 #define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1328
 #define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM
 
-#define LPDDR4__DENALI_PHY_1329_READ_MASK				            0x1FFF03FFU
-#define LPDDR4__DENALI_PHY_1329_WRITE_MASK				           0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1329_READ_MASK                            0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1329_WRITE_MASK                           0x1FFF03FFU
 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_MASK              0x000003FFU
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_WIDTH				     10U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_WIDTH                     10U
 #define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1329
 #define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL
 
 #define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_MASK          0x1FFF0000U
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_WIDTH				 13U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_WIDTH                 13U
 #define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1329
 #define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL
 
-#define LPDDR4__DENALI_PHY_1330_READ_MASK				            0x00001FFFU
-#define LPDDR4__DENALI_PHY_1330_WRITE_MASK				           0x00001FFFU
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_MASK				 0x00001FFFU
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_WIDTH				        13U
+#define LPDDR4__DENALI_PHY_1330_READ_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_PHY_1330_WRITE_MASK                           0x00001FFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_MASK                 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_WIDTH                        13U
 #define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1330
 #define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0
 
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_MASK				0x00010000U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_SHIFT				       16U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WIDTH				        1U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOCLR				        0U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOSET				        0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_MASK                0x00010000U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOSET                        0U
 #define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1330
 #define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0
 
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_MASK				0x01000000U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_SHIFT				       24U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WIDTH				        1U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOCLR				        0U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOSET				        0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_SHIFT                       24U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOSET                        0U
 #define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1330
 #define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0
 
-#define LPDDR4__DENALI_PHY_1331_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1331_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1331_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1331_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_WIDTH              32U
 #define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1331
 #define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0
 
-#define LPDDR4__DENALI_PHY_1332_READ_MASK				            0x000007FFU
-#define LPDDR4__DENALI_PHY_1332_WRITE_MASK				           0x000007FFU
+#define LPDDR4__DENALI_PHY_1332_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1332_WRITE_MASK                           0x000007FFU
 #define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_MASK          0x000000FFU
-#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_WIDTH                  8U
 #define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1332
 #define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0
 
@@ -872,139 +871,139 @@
 #define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1332
 #define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0
 
-#define LPDDR4__DENALI_PHY_1333_READ_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1333_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1333_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1333_WRITE_MASK                           0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_MASK           0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_WIDTH				  24U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_WIDTH                  24U
 #define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1333
 #define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0
 
-#define LPDDR4__DENALI_PHY_1334_READ_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1334_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1334_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1334_WRITE_MASK                           0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_MASK          0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_WIDTH				 24U
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_WIDTH                 24U
 #define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1334
 #define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0
 
-#define LPDDR4__DENALI_PHY_1335_READ_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1335_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1335_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1335_WRITE_MASK                           0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_MASK          0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_WIDTH				 24U
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_WIDTH                 24U
 #define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1335
 #define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0
 
-#define LPDDR4__DENALI_PHY_1336_READ_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1336_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336_WRITE_MASK                           0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_MASK          0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_WIDTH				 24U
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_WIDTH                 24U
 #define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1336
 #define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0
 
-#define LPDDR4__DENALI_PHY_1337_READ_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1337_WRITE_MASK				           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337_WRITE_MASK                           0x00FFFFFFU
 #define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_MASK          0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_WIDTH				 24U
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_WIDTH                 24U
 #define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1337
 #define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0
 
-#define LPDDR4__DENALI_PHY_1338_READ_MASK				            0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_1338_WRITE_MASK				           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1338_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1338_WRITE_MASK                           0x7FFFFFFFU
 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_MASK          0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_WIDTH				 24U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_WIDTH                 24U
 #define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1338
 #define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0
 
 #define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_MASK             0x7F000000U
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_WIDTH				     7U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_WIDTH                     7U
 #define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1338
 #define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0
 
-#define LPDDR4__DENALI_PHY_1339_READ_MASK				            0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1339_WRITE_MASK				           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1339_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1339_WRITE_MASK                           0x01FFFFFFU
 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_MASK          0x000000FFU
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_WIDTH                  8U
 #define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1339
 #define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0
 
 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_MASK          0x0000FF00U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_WIDTH				  8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_WIDTH                  8U
 #define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1339
 #define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0
 
 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_MASK         0x00FF0000U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_SHIFT				16U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_WIDTH				 8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_WIDTH                 8U
 #define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1339
 #define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0
 
 #define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_MASK              0x01000000U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_SHIFT				     24U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WIDTH				      1U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOCLR				      0U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOSET				      0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOSET                      0U
 #define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1339
 #define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0
 
 #define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_MASK          0x00000001U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOSET				  0U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOSET                  0U
 #define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1340
 #define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0
 
-#define LPDDR4__DENALI_PHY_1341_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1341_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1341_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1341_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_WIDTH				 32U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_WIDTH                 32U
 #define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1341
 #define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0
 
-#define LPDDR4__DENALI_PHY_1342_READ_MASK				            0x0FFFFF7FU
-#define LPDDR4__DENALI_PHY_1342_WRITE_MASK				           0x0FFFFF7FU
+#define LPDDR4__DENALI_PHY_1342_READ_MASK                            0x0FFFFF7FU
+#define LPDDR4__DENALI_PHY_1342_WRITE_MASK                           0x0FFFFF7FU
 #define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_MASK           0x0000007FU
-#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_WIDTH				   7U
+#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_WIDTH                   7U
 #define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1342
 #define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0
 
 #define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_MASK            0x0FFFFF00U
-#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_SHIFT				    8U
-#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_WIDTH				   20U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_WIDTH                   20U
 #define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1342
 #define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0
 
-#define LPDDR4__DENALI_PHY_1343_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1343_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1343_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1343_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK      0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT              0U
 #define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH             20U
 #define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1343
 #define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0
 
-#define LPDDR4__DENALI_PHY_1344_READ_MASK				            0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1344_WRITE_MASK				           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1344_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1344_WRITE_MASK                           0x01FFFFFFU
 #define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_MASK         0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_WIDTH				25U
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_WIDTH                25U
 #define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1344
 #define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0
 
-#define LPDDR4__DENALI_PHY_1345_READ_MASK				            0x3F7FFFFFU
-#define LPDDR4__DENALI_PHY_1345_WRITE_MASK				           0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1345_READ_MASK                            0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1345_WRITE_MASK                           0x3F7FFFFFU
 #define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_MASK           0x007FFFFFU
-#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_WIDTH				  23U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_WIDTH                  23U
 #define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1345
 #define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0
 
@@ -1014,8 +1013,8 @@
 #define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1345
 #define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
 
-#define LPDDR4__DENALI_PHY_1346_READ_MASK				            0x3F3F1F3FU
-#define LPDDR4__DENALI_PHY_1346_WRITE_MASK				           0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1346_READ_MASK                            0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1346_WRITE_MASK                           0x3F3F1F3FU
 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT     0U
 #define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH     6U
@@ -1040,8 +1039,8 @@
 #define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1346
 #define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
 
-#define LPDDR4__DENALI_PHY_1347_READ_MASK				            0x1F3F3F1FU
-#define LPDDR4__DENALI_PHY_1347_WRITE_MASK				           0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1347_READ_MASK                            0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1347_WRITE_MASK                           0x1F3F3F1FU
 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT     0U
 #define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH     5U
@@ -1066,8 +1065,8 @@
 #define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1347
 #define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
 
-#define LPDDR4__DENALI_PHY_1348_READ_MASK				            0x001F3F3FU
-#define LPDDR4__DENALI_PHY_1348_WRITE_MASK				           0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1348_READ_MASK                            0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1348_WRITE_MASK                           0x001F3F3FU
 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT     0U
 #define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH     6U
@@ -1086,11 +1085,11 @@
 #define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1348
 #define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
 
-#define LPDDR4__DENALI_PHY_1349_READ_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1349_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1349_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1349_WRITE_MASK                           0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_MASK               0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_WIDTH				      16U
+#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_WIDTH                      16U
 #define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1349
 #define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL
 
@@ -1100,8 +1099,8 @@
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__REG DENALI_PHY_1349
 #define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__FLD LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC
 
-#define LPDDR4__DENALI_PHY_1350_READ_MASK				            0x03010000U
-#define LPDDR4__DENALI_PHY_1350_WRITE_MASK				           0x03010000U
+#define LPDDR4__DENALI_PHY_1350_READ_MASK                            0x03010000U
+#define LPDDR4__DENALI_PHY_1350_WRITE_MASK                           0x03010000U
 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_MASK       0x00000001U
 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WIDTH               1U
@@ -1111,32 +1110,32 @@
 #define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE
 
 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_MASK          0x00000100U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_SHIFT				  8U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WIDTH				  1U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOCLR				  0U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOSET				  0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOSET                  0U
 #define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1350
 #define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR
 
 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_MASK         0x00010000U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_SHIFT				16U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOSET				 0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOSET                 0U
 #define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1350
 #define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT
 
 #define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_MASK             0x03000000U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_WIDTH				     2U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_WIDTH                     2U
 #define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1350
 #define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE
 
-#define LPDDR4__DENALI_PHY_1351_READ_MASK				            0x0F7F01FFU
-#define LPDDR4__DENALI_PHY_1351_WRITE_MASK				           0x0F7F01FFU
+#define LPDDR4__DENALI_PHY_1351_READ_MASK                            0x0F7F01FFU
+#define LPDDR4__DENALI_PHY_1351_WRITE_MASK                           0x0F7F01FFU
 #define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_MASK            0x000001FFU
-#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_WIDTH				    9U
+#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_WIDTH                    9U
 #define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1351
 #define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL
 
@@ -1152,16 +1151,16 @@
 #define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1351
 #define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK
 
-#define LPDDR4__DENALI_PHY_1352_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1352_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1352_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1352_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_MASK         0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_WIDTH				32U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_WIDTH                32U
 #define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1352
 #define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS
 
-#define LPDDR4__DENALI_PHY_1353_READ_MASK				            0x003F0101U
-#define LPDDR4__DENALI_PHY_1353_WRITE_MASK				           0x003F0101U
+#define LPDDR4__DENALI_PHY_1353_READ_MASK                            0x003F0101U
+#define LPDDR4__DENALI_PHY_1353_WRITE_MASK                           0x003F0101U
 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_MASK     0x00000001U
 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH             1U
@@ -1171,21 +1170,21 @@
 #define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT
 
 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_MASK         0x00000100U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOSET				 0U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOSET                 0U
 #define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1353
 #define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE
 
 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_MASK        0x003F0000U
 #define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_WIDTH				6U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_WIDTH                6U
 #define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1353
 #define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL
 
-#define LPDDR4__DENALI_PHY_1354_READ_MASK				            0x0101FFFFU
-#define LPDDR4__DENALI_PHY_1354_WRITE_MASK				           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1354_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1354_WRITE_MASK                           0x0101FFFFU
 #define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_MASK     0x0000FFFFU
 #define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH            16U
@@ -1193,23 +1192,23 @@
 #define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS
 
 #define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_MASK         0x00010000U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_SHIFT				16U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WIDTH				 1U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOCLR				 0U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOSET				 0U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOSET                 0U
 #define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1354
 #define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE
 
 #define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_MASK        0x01000000U
 #define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_SHIFT               24U
-#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOSET				0U
+#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOSET                0U
 #define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1354
 #define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE
 
-#define LPDDR4__DENALI_PHY_1355_READ_MASK				            0x00000001U
-#define LPDDR4__DENALI_PHY_1355_WRITE_MASK				           0x00000001U
+#define LPDDR4__DENALI_PHY_1355_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1355_WRITE_MASK                           0x00000001U
 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT       0U
 #define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH       1U
@@ -1218,16 +1217,16 @@
 #define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1355
 #define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
 
-#define LPDDR4__DENALI_PHY_1356_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1356_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1356_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1356_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_WIDTH               32U
 #define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1356
 #define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL
 
-#define LPDDR4__DENALI_PHY_1357_READ_MASK				            0x031F01FFU
-#define LPDDR4__DENALI_PHY_1357_WRITE_MASK				           0x031F01FFU
+#define LPDDR4__DENALI_PHY_1357_READ_MASK                            0x031F01FFU
+#define LPDDR4__DENALI_PHY_1357_WRITE_MASK                           0x031F01FFU
 #define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK   0x000000FFU
 #define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH           8U
@@ -1235,16 +1234,16 @@
 #define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH
 
 #define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_MASK             0x00000100U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_SHIFT				     8U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WIDTH				     1U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOCLR				     0U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOSET				     0U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOSET                     0U
 #define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1357
 #define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT
 
 #define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_MASK           0x001F0000U
-#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_SHIFT				  16U
-#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_WIDTH				   5U
+#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_WIDTH                   5U
 #define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1357
 #define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP
 
@@ -1254,41 +1253,41 @@
 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1357
 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
 
-#define LPDDR4__DENALI_PHY_1358_READ_MASK				            0x00000003U
-#define LPDDR4__DENALI_PHY_1358_WRITE_MASK				           0x00000003U
+#define LPDDR4__DENALI_PHY_1358_READ_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_1358_WRITE_MASK                           0x00000003U
 #define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK  0x00000003U
 #define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT          0U
 #define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH          2U
 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1358
 #define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
 
-#define LPDDR4__DENALI_PHY_1359_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1359_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_WIDTH                     32U
 #define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1359
 #define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE
 
-#define LPDDR4__DENALI_PHY_1360_READ_MASK				            0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1360_WRITE_MASK				           0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_MASK				0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_WIDTH				       26U
+#define LPDDR4__DENALI_PHY_1360_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1360_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_MASK                0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_WIDTH                       26U
 #define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1360
 #define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE
 
-#define LPDDR4__DENALI_PHY_1361_READ_MASK				            0x07FF073FU
-#define LPDDR4__DENALI_PHY_1361_WRITE_MASK				           0x07FF073FU
-#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_MASK				0x0000003FU
-#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_WIDTH				        6U
+#define LPDDR4__DENALI_PHY_1361_READ_MASK                            0x07FF073FU
+#define LPDDR4__DENALI_PHY_1361_WRITE_MASK                           0x07FF073FU
+#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_MASK                0x0000003FU
+#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_WIDTH                        6U
 #define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1361
 #define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK
 
 #define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_MASK         0x00000700U
-#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_WIDTH				 3U
+#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_WIDTH                 3U
 #define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1361
 #define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG
 
@@ -1298,57 +1297,57 @@
 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1361
 #define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC
 
-#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_MASK				0x07000000U
-#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_SHIFT				       24U
-#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_WIDTH				        3U
+#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_MASK                0x07000000U
+#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_SHIFT                       24U
+#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_WIDTH                        3U
 #define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1361
 #define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN
 
-#define LPDDR4__DENALI_PHY_1362_READ_MASK				            0x00000007U
-#define LPDDR4__DENALI_PHY_1362_WRITE_MASK				           0x00000007U
-#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_MASK				 0x00000007U
-#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_WIDTH				         3U
+#define LPDDR4__DENALI_PHY_1362_READ_MASK                            0x00000007U
+#define LPDDR4__DENALI_PHY_1362_WRITE_MASK                           0x00000007U
+#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_MASK                 0x00000007U
+#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_WIDTH                         3U
 #define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1362
 #define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS
 
-#define LPDDR4__DENALI_PHY_1363_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1363_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1363_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1363_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_WIDTH               32U
 #define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1363
 #define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER
 
-#define LPDDR4__DENALI_PHY_1364_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1364_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1364_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1364_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_WIDTH               32U
 #define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1364
 #define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER
 
-#define LPDDR4__DENALI_PHY_1365_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1365_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1365_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1365_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_WIDTH               32U
 #define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1365
 #define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER
 
-#define LPDDR4__DENALI_PHY_1366_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1366_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_WIDTH               32U
 #define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1366
 #define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER
 
-#define LPDDR4__DENALI_PHY_1367_READ_MASK				            0x0F03FF03U
-#define LPDDR4__DENALI_PHY_1367_WRITE_MASK				           0x0F03FF03U
-#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_MASK				 0x00000003U
-#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_WIDTH				         2U
+#define LPDDR4__DENALI_PHY_1367_READ_MASK                            0x0F03FF03U
+#define LPDDR4__DENALI_PHY_1367_WRITE_MASK                           0x0F03FF03U
+#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_MASK                 0x00000003U
+#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_WIDTH                         2U
 #define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1367
 #define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN
 
@@ -1364,13 +1363,13 @@
 #define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1367
 #define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS
 
-#define LPDDR4__DENALI_PHY_1368_READ_MASK				            0x070F0101U
-#define LPDDR4__DENALI_PHY_1368_WRITE_MASK				           0x070F0101U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_MASK				0x00000001U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_SHIFT				        0U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WIDTH				        1U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOCLR				        0U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOSET				        0U
+#define LPDDR4__DENALI_PHY_1368_READ_MASK                            0x070F0101U
+#define LPDDR4__DENALI_PHY_1368_WRITE_MASK                           0x070F0101U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_MASK                0x00000001U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOSET                        0U
 #define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1368
 #define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK
 
@@ -1394,22 +1393,22 @@
 #define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1368
 #define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT
 
-#define LPDDR4__DENALI_PHY_1369_READ_MASK				            0x000707FFU
-#define LPDDR4__DENALI_PHY_1369_WRITE_MASK				           0x000707FFU
+#define LPDDR4__DENALI_PHY_1369_READ_MASK                            0x000707FFU
+#define LPDDR4__DENALI_PHY_1369_WRITE_MASK                           0x000707FFU
 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_MASK        0x000007FFU
-#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH               11U
 #define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1369
 #define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS
 
 #define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_MASK              0x00070000U
-#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SHIFT				     16U
-#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_WIDTH				      3U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_WIDTH                      3U
 #define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1369
 #define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS
 
-#define LPDDR4__DENALI_PHY_1370_READ_MASK				            0x0707FF01U
-#define LPDDR4__DENALI_PHY_1370_WRITE_MASK				           0x0707FF01U
+#define LPDDR4__DENALI_PHY_1370_READ_MASK                            0x0707FF01U
+#define LPDDR4__DENALI_PHY_1370_WRITE_MASK                           0x0707FF01U
 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_MASK 0x00000001U
 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_SHIFT      0U
 #define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WIDTH      1U
@@ -1430,11 +1429,11 @@
 #define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__REG DENALI_PHY_1370
 #define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__FLD LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK
 
-#define LPDDR4__DENALI_PHY_1371_READ_MASK				            0x00007F7FU
-#define LPDDR4__DENALI_PHY_1371_WRITE_MASK				           0x00007F7FU
+#define LPDDR4__DENALI_PHY_1371_READ_MASK                            0x00007F7FU
+#define LPDDR4__DENALI_PHY_1371_WRITE_MASK                           0x00007F7FU
 #define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK          0x0000007FU
-#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_WIDTH				  7U
+#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_WIDTH                  7U
 #define LPDDR4__PHY_PARITY_ERROR_INFO__REG DENALI_PHY_1371
 #define LPDDR4__PHY_PARITY_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO
 
@@ -1450,11 +1449,11 @@
 #define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__REG DENALI_PHY_1371
 #define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR
 
-#define LPDDR4__DENALI_PHY_1372_READ_MASK				            0x3FFF3FFFU
-#define LPDDR4__DENALI_PHY_1372_WRITE_MASK				           0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1372_READ_MASK                            0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1372_WRITE_MASK                           0x3FFF3FFFU
 #define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK         0x00003FFFU
-#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_WIDTH				14U
+#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_WIDTH                14U
 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO__REG DENALI_PHY_1372
 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO
 
@@ -1464,8 +1463,8 @@
 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__REG DENALI_PHY_1372
 #define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK
 
-#define LPDDR4__DENALI_PHY_1373_READ_MASK				            0x3F0F0000U
-#define LPDDR4__DENALI_PHY_1373_WRITE_MASK				           0x3F0F0000U
+#define LPDDR4__DENALI_PHY_1373_READ_MASK                            0x3F0F0000U
+#define LPDDR4__DENALI_PHY_1373_WRITE_MASK                           0x3F0F0000U
 #define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_MASK 0x00003FFFU
 #define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_SHIFT        0U
 #define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_WIDTH       14U
@@ -1474,7 +1473,7 @@
 
 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK        0x000F0000U
 #define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_WIDTH				4U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_WIDTH                4U
 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR__REG DENALI_PHY_1373
 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR
 
@@ -1484,8 +1483,8 @@
 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__REG DENALI_PHY_1373
 #define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK
 
-#define LPDDR4__DENALI_PHY_1374_READ_MASK				            0x000FFF00U
-#define LPDDR4__DENALI_PHY_1374_WRITE_MASK				           0x000FFF00U
+#define LPDDR4__DENALI_PHY_1374_READ_MASK                            0x000FFF00U
+#define LPDDR4__DENALI_PHY_1374_WRITE_MASK                           0x000FFF00U
 #define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_MASK 0x0000003FU
 #define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_SHIFT       0U
 #define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_WIDTH       6U
@@ -1493,15 +1492,15 @@
 #define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__FLD LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR
 
 #define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_MASK        0x000FFF00U
-#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_SHIFT				8U
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_SHIFT                8U
 #define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_WIDTH               12U
 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__REG DENALI_PHY_1374
 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN
 
-#define LPDDR4__DENALI_PHY_1375_READ_MASK				            0x03030FFFU
-#define LPDDR4__DENALI_PHY_1375_WRITE_MASK				           0x03030FFFU
+#define LPDDR4__DENALI_PHY_1375_READ_MASK                            0x03030FFFU
+#define LPDDR4__DENALI_PHY_1375_WRITE_MASK                           0x03030FFFU
 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_MASK        0x00000FFFU
-#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_SHIFT				0U
+#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_SHIFT                0U
 #define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_WIDTH               12U
 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__REG DENALI_PHY_1375
 #define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX
@@ -1518,8 +1517,8 @@
 #define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__REG DENALI_PHY_1375
 #define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK
 
-#define LPDDR4__DENALI_PHY_1376_READ_MASK				            0x0001FF00U
-#define LPDDR4__DENALI_PHY_1376_WRITE_MASK				           0x0001FF00U
+#define LPDDR4__DENALI_PHY_1376_READ_MASK                            0x0001FF00U
+#define LPDDR4__DENALI_PHY_1376_WRITE_MASK                           0x0001FF00U
 #define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_MASK 0x00000003U
 #define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_SHIFT 0U
 #define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_WIDTH 2U
@@ -1527,13 +1526,13 @@
 #define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR
 
 #define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_MASK         0x0001FF00U
-#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_SHIFT				 8U
-#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_WIDTH				 9U
+#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_WIDTH                 9U
 #define LPDDR4__PHY_TOP_FSM_ERROR_INFO__REG DENALI_PHY_1376
 #define LPDDR4__PHY_TOP_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO
 
-#define LPDDR4__DENALI_PHY_1377_READ_MASK				            0x000001FFU
-#define LPDDR4__DENALI_PHY_1377_WRITE_MASK				           0x000001FFU
+#define LPDDR4__DENALI_PHY_1377_READ_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_1377_WRITE_MASK                           0x000001FFU
 #define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_MASK    0x000001FFU
 #define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_SHIFT            0U
 #define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_WIDTH            9U
@@ -1546,8 +1545,8 @@
 #define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__REG DENALI_PHY_1377
 #define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR
 
-#define LPDDR4__DENALI_PHY_1378_READ_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_PHY_1378_WRITE_MASK				           0x03FF03FFU
+#define LPDDR4__DENALI_PHY_1378_READ_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_1378_WRITE_MASK                           0x03FF03FFU
 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK   0x000003FFU
 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_SHIFT           0U
 #define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_WIDTH          10U
@@ -1560,8 +1559,8 @@
 #define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__REG DENALI_PHY_1378
 #define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK
 
-#define LPDDR4__DENALI_PHY_1379_READ_MASK				            0x03030000U
-#define LPDDR4__DENALI_PHY_1379_WRITE_MASK				           0x03030000U
+#define LPDDR4__DENALI_PHY_1379_READ_MASK                            0x03030000U
+#define LPDDR4__DENALI_PHY_1379_WRITE_MASK                           0x03030000U
 #define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_MASK 0x000003FFU
 #define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_SHIFT  0U
 #define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_WIDTH 10U
@@ -1580,8 +1579,8 @@
 #define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1379
 #define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK
 
-#define LPDDR4__DENALI_PHY_1380_READ_MASK				            0x007F7F00U
-#define LPDDR4__DENALI_PHY_1380_WRITE_MASK				           0x007F7F00U
+#define LPDDR4__DENALI_PHY_1380_READ_MASK                            0x007F7F00U
+#define LPDDR4__DENALI_PHY_1380_WRITE_MASK                           0x007F7F00U
 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x00000003U
 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 0U
 #define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 2U
@@ -1606,11 +1605,11 @@
 #define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380
 #define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR
 
-#define LPDDR4__DENALI_PHY_1381_READ_MASK				            0x00003F3FU
-#define LPDDR4__DENALI_PHY_1381_WRITE_MASK				           0x00003F3FU
+#define LPDDR4__DENALI_PHY_1381_READ_MASK                            0x00003F3FU
+#define LPDDR4__DENALI_PHY_1381_WRITE_MASK                           0x00003F3FU
 #define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK          0x0000003FU
-#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_SHIFT				  0U
-#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_WIDTH				  6U
+#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_WIDTH                  6U
 #define LPDDR4__PHY_GLOBAL_ERROR_INFO__REG DENALI_PHY_1381
 #define LPDDR4__PHY_GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO
 
@@ -1620,40 +1619,40 @@
 #define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__REG DENALI_PHY_1381
 #define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK
 
-#define LPDDR4__DENALI_PHY_1382_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1382_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1382_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1382_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_MASK     0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_WIDTH            20U
 #define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__REG DENALI_PHY_1382
 #define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE
 
-#define LPDDR4__DENALI_PHY_1383_READ_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1383_WRITE_MASK				           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1383_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1383_WRITE_MASK                           0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_MASK         0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_WIDTH				20U
+#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_WIDTH                20U
 #define LPDDR4__PHY_INIT_TIMEOUT_VALUE__REG DENALI_PHY_1383
 #define LPDDR4__PHY_INIT_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE
 
-#define LPDDR4__DENALI_PHY_1384_READ_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1384_WRITE_MASK				           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1384_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1384_WRITE_MASK                           0x0000FFFFU
 #define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_WIDTH				  16U
+#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_WIDTH                  16U
 #define LPDDR4__PHY_LP_TIMEOUT_VALUE__REG DENALI_PHY_1384
 #define LPDDR4__PHY_LP_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE
 
-#define LPDDR4__DENALI_PHY_1385_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1385_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1385_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1385_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_SHIFT               0U
 #define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_WIDTH              32U
 #define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__REG DENALI_PHY_1385
 #define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE
 
-#define LPDDR4__DENALI_PHY_1386_READ_MASK				            0x1F0FFFFFU
-#define LPDDR4__DENALI_PHY_1386_WRITE_MASK				           0x1F0FFFFFU
+#define LPDDR4__DENALI_PHY_1386_READ_MASK                            0x1F0FFFFFU
+#define LPDDR4__DENALI_PHY_1386_WRITE_MASK                           0x1F0FFFFFU
 #define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_MASK      0x000FFFFFU
 #define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_SHIFT              0U
 #define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_WIDTH             20U
@@ -1666,8 +1665,8 @@
 #define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__REG DENALI_PHY_1386
 #define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE
 
-#define LPDDR4__DENALI_PHY_1387_READ_MASK				            0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_1387_WRITE_MASK				           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387_WRITE_MASK                           0x0FFFFFFFU
 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_MASK     0x0000FFFFU
 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_SHIFT             0U
 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_WIDTH            16U
@@ -1682,12 +1681,12 @@
 
 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_MASK        0x0F000000U
 #define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_SHIFT               24U
-#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_WIDTH				4U
+#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_WIDTH                4U
 #define LPDDR4__PHY_PLL_FREQUENCY_DELTA__REG DENALI_PHY_1387
 #define LPDDR4__PHY_PLL_FREQUENCY_DELTA__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA
 
-#define LPDDR4__DENALI_PHY_1388_READ_MASK				            0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1388_WRITE_MASK				           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1388_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1388_WRITE_MASK                           0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_SHIFT     0U
 #define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_WIDTH    16U
@@ -1700,8 +1699,8 @@
 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__REG DENALI_PHY_1388
 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0
 
-#define LPDDR4__DENALI_PHY_1389_READ_MASK				            0x00003FFFU
-#define LPDDR4__DENALI_PHY_1389_WRITE_MASK				           0x00003FFFU
+#define LPDDR4__DENALI_PHY_1389_READ_MASK                            0x00003FFFU
+#define LPDDR4__DENALI_PHY_1389_WRITE_MASK                           0x00003FFFU
 #define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
 #define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_SHIFT       0U
 #define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_WIDTH      14U
@@ -1714,8 +1713,8 @@
 #define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1389
 #define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0
 
-#define LPDDR4__DENALI_PHY_1390_READ_MASK				            0x3FFF3FFFU
-#define LPDDR4__DENALI_PHY_1390_WRITE_MASK				           0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1390_READ_MASK                            0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1390_WRITE_MASK                           0x3FFF3FFFU
 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_MASK    0x00003FFFU
 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_SHIFT            0U
 #define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_WIDTH           14U
@@ -1728,8 +1727,8 @@
 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_1390
 #define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1
 
-#define LPDDR4__DENALI_PHY_1391_READ_MASK				            0x3FFF0000U
-#define LPDDR4__DENALI_PHY_1391_WRITE_MASK				           0x3FFF0000U
+#define LPDDR4__DENALI_PHY_1391_READ_MASK                            0x3FFF0000U
+#define LPDDR4__DENALI_PHY_1391_WRITE_MASK                           0x3FFF0000U
 #define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_MASK 0x00003FFFU
 #define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_SHIFT   0U
 #define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_WIDTH  14U
@@ -1742,8 +1741,8 @@
 #define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__REG DENALI_PHY_1391
 #define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0
 
-#define LPDDR4__DENALI_PHY_1392_READ_MASK				            0x00003FFFU
-#define LPDDR4__DENALI_PHY_1392_WRITE_MASK				           0x00003FFFU
+#define LPDDR4__DENALI_PHY_1392_READ_MASK                            0x00003FFFU
+#define LPDDR4__DENALI_PHY_1392_WRITE_MASK                           0x00003FFFU
 #define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
 #define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_SHIFT       0U
 #define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_WIDTH      14U
@@ -1756,81 +1755,81 @@
 #define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1392
 #define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0
 
-#define LPDDR4__DENALI_PHY_1393_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1393_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1393_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1393_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_MASK           0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_WIDTH				  18U
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_WIDTH                  18U
 #define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1393
 #define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0
 
-#define LPDDR4__DENALI_PHY_1394_READ_MASK				            0x00003FFFU
-#define LPDDR4__DENALI_PHY_1394_WRITE_MASK				           0x00003FFFU
+#define LPDDR4__DENALI_PHY_1394_READ_MASK                            0x00003FFFU
+#define LPDDR4__DENALI_PHY_1394_WRITE_MASK                           0x00003FFFU
 #define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_MASK             0x00003FFFU
-#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_WIDTH				    14U
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_WIDTH                    14U
 #define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1394
 #define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG
 
-#define LPDDR4__DENALI_PHY_1395_READ_MASK				            0x00000001U
-#define LPDDR4__DENALI_PHY_1395_WRITE_MASK				           0x00000001U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_MASK				 0x00000001U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_SHIFT				         0U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WIDTH				         1U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOCLR				         0U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOSET				         0U
+#define LPDDR4__DENALI_PHY_1395_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1395_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOSET                         0U
 #define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1395
 #define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS
 
-#define LPDDR4__DENALI_PHY_1396_READ_MASK				            0x00011FFFU
-#define LPDDR4__DENALI_PHY_1396_WRITE_MASK				           0x00011FFFU
-#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_MASK				   0x00001FFFU
-#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_SHIFT				           0U
-#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_WIDTH				          13U
+#define LPDDR4__DENALI_PHY_1396_READ_MASK                            0x00011FFFU
+#define LPDDR4__DENALI_PHY_1396_WRITE_MASK                           0x00011FFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_MASK                   0x00001FFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_WIDTH                          13U
 #define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1396
 #define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL
 
 #define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_MASK               0x00010000U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_SHIFT				      16U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WIDTH				       1U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOCLR				       0U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOSET				       0U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOSET                       0U
 #define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1396
 #define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL
 
-#define LPDDR4__DENALI_PHY_1397_READ_MASK				            0x0F0F0FFFU
-#define LPDDR4__DENALI_PHY_1397_WRITE_MASK				           0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1397_READ_MASK                            0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1397_WRITE_MASK                           0x0F0F0FFFU
 #define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_MASK           0x00000FFFU
-#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_WIDTH				  12U
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_WIDTH                  12U
 #define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1397
 #define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC
 
 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_MASK          0x000F0000U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_SHIFT				 16U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_WIDTH				  4U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_WIDTH                  4U
 #define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1397
 #define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT
 
 #define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_MASK             0x0F000000U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_SHIFT				    24U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_WIDTH				     4U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_WIDTH                     4U
 #define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1397
 #define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP
 
-#define LPDDR4__DENALI_PHY_1398_READ_MASK				            0x010101FFU
-#define LPDDR4__DENALI_PHY_1398_WRITE_MASK				           0x010101FFU
+#define LPDDR4__DENALI_PHY_1398_READ_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_1398_WRITE_MASK                           0x010101FFU
 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_MASK           0x000001FFU
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_WIDTH				   9U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_WIDTH                   9U
 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1398
 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN
 
 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_MASK        0x00010000U
 #define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT               16U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH				1U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR				0U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOSET				0U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOSET                0U
 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1398
 #define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN
 
@@ -1842,207 +1841,207 @@
 #define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1398
 #define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE
 
-#define LPDDR4__DENALI_PHY_1399_READ_MASK				            0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1399_WRITE_MASK				           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1399_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1399_WRITE_MASK                           0x07FF07FFU
 #define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_MASK         0x000007FFU
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_WIDTH                11U
 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1399
 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_MASK         0x07FF0000U
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_SHIFT				16U
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_WIDTH                11U
 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1399
 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1400_READ_MASK				            0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1400_WRITE_MASK				           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1400_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1400_WRITE_MASK                           0x07FF07FFU
 #define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_MASK         0x000007FFU
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_WIDTH                11U
 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1400
 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0
 
 #define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_MASK         0x07FF0000U
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_SHIFT				16U
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_WIDTH                11U
 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1400
 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0
 
-#define LPDDR4__DENALI_PHY_1401_READ_MASK				            0x000007FFU
-#define LPDDR4__DENALI_PHY_1401_WRITE_MASK				           0x000007FFU
+#define LPDDR4__DENALI_PHY_1401_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1401_WRITE_MASK                           0x000007FFU
 #define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_MASK         0x000007FFU
-#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_WIDTH                11U
 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1401
 #define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_1402_READ_MASK				            0x000007FFU
-#define LPDDR4__DENALI_PHY_1402_WRITE_MASK				           0x000007FFU
+#define LPDDR4__DENALI_PHY_1402_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1402_WRITE_MASK                           0x000007FFU
 #define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_MASK         0x000007FFU
-#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_WIDTH                11U
 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1402
 #define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_1403_READ_MASK				            0x000007FFU
-#define LPDDR4__DENALI_PHY_1403_WRITE_MASK				           0x000007FFU
+#define LPDDR4__DENALI_PHY_1403_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1403_WRITE_MASK                           0x000007FFU
 #define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_MASK         0x000007FFU
-#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_WIDTH                11U
 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1403
 #define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_1404_READ_MASK				            0x000007FFU
-#define LPDDR4__DENALI_PHY_1404_WRITE_MASK				           0x000007FFU
+#define LPDDR4__DENALI_PHY_1404_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1404_WRITE_MASK                           0x000007FFU
 #define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_MASK         0x000007FFU
-#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_WIDTH				11U
+#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_WIDTH                11U
 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1404
 #define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1
 
-#define LPDDR4__DENALI_PHY_1405_READ_MASK				            0x00000007U
-#define LPDDR4__DENALI_PHY_1405_WRITE_MASK				           0x00000007U
+#define LPDDR4__DENALI_PHY_1405_READ_MASK                            0x00000007U
+#define LPDDR4__DENALI_PHY_1405_WRITE_MASK                           0x00000007U
 #define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_MASK         0x00000007U
-#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_SHIFT				 0U
-#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_WIDTH				 3U
+#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_WIDTH                 3U
 #define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1405
 #define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL
 
-#define LPDDR4__DENALI_PHY_1406_READ_MASK				            0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1406_WRITE_MASK				           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1406_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1406_WRITE_MASK                           0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_MASK             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_WIDTH				    30U
+#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_WIDTH                    30U
 #define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1406
 #define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE
 
-#define LPDDR4__DENALI_PHY_1407_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1407_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1407_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1407_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_MASK            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_WIDTH				   18U
+#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_WIDTH                   18U
 #define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1407
 #define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2
 
-#define LPDDR4__DENALI_PHY_1408_READ_MASK				            0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_1408_WRITE_MASK				           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1408_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1408_WRITE_MASK                           0x7FFFFFFFU
 #define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_MASK             0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_WIDTH				    31U
+#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_WIDTH                    31U
 #define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1408
 #define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE
 
-#define LPDDR4__DENALI_PHY_1409_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1409_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1409_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1409_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_WIDTH                     32U
 #define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1409
 #define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE
 
-#define LPDDR4__DENALI_PHY_1410_READ_MASK				            0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1410_WRITE_MASK				           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1410_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1410_WRITE_MASK                           0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_MASK             0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_WIDTH				    30U
+#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_WIDTH                    30U
 #define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1410
 #define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE
 
-#define LPDDR4__DENALI_PHY_1411_READ_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1411_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1411_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1411_WRITE_MASK                           0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_MASK            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_SHIFT				    0U
-#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_WIDTH				   27U
+#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_WIDTH                   27U
 #define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1411
 #define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2
 
-#define LPDDR4__DENALI_PHY_1412_READ_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1412_WRITE_MASK				           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1412_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1412_WRITE_MASK                           0xFFFFFFFFU
 #define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_WIDTH				     32U
+#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_WIDTH                     32U
 #define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1412
 #define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE
 
-#define LPDDR4__DENALI_PHY_1413_READ_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1413_WRITE_MASK				           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1413_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1413_WRITE_MASK                           0x0003FFFFU
 #define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_MASK             0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_WIDTH				    18U
+#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_WIDTH                    18U
 #define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1413
 #define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2
 
-#define LPDDR4__DENALI_PHY_1414_READ_MASK				            0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1414_WRITE_MASK				           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1414_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1414_WRITE_MASK                           0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_MASK              0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_WIDTH				     30U
+#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_WIDTH                     30U
 #define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1414
 #define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE
 
-#define LPDDR4__DENALI_PHY_1415_READ_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1415_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1415_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1415_WRITE_MASK                           0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_MASK             0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_WIDTH				    27U
+#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_WIDTH                    27U
 #define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1415
 #define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2
 
-#define LPDDR4__DENALI_PHY_1416_READ_MASK				            0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1416_WRITE_MASK				           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1416_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1416_WRITE_MASK                           0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_MASK              0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_WIDTH				     30U
+#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_WIDTH                     30U
 #define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1416
 #define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE
 
-#define LPDDR4__DENALI_PHY_1417_READ_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1417_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1417_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1417_WRITE_MASK                           0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_MASK             0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_WIDTH				    27U
+#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_WIDTH                    27U
 #define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1417
 #define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2
 
-#define LPDDR4__DENALI_PHY_1418_READ_MASK				            0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1418_WRITE_MASK				           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1418_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1418_WRITE_MASK                           0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_MASK               0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_SHIFT				       0U
-#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_WIDTH				      30U
+#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_WIDTH                      30U
 #define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1418
 #define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE
 
-#define LPDDR4__DENALI_PHY_1419_READ_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1419_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1419_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1419_WRITE_MASK                           0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_MASK              0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_WIDTH				     27U
+#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_WIDTH                     27U
 #define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1419
 #define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2
 
-#define LPDDR4__DENALI_PHY_1420_READ_MASK				            0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1420_WRITE_MASK				           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1420_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1420_WRITE_MASK                           0x3FFFFFFFU
 #define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_MASK              0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_SHIFT				      0U
-#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_WIDTH				     30U
+#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_WIDTH                     30U
 #define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1420
 #define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE
 
-#define LPDDR4__DENALI_PHY_1421_READ_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1421_WRITE_MASK				           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1421_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1421_WRITE_MASK                           0x07FFFFFFU
 #define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_MASK             0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_SHIFT				     0U
-#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_WIDTH				    27U
+#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_WIDTH                    27U
 #define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1421
 #define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2
 
-#define LPDDR4__DENALI_PHY_1422_READ_MASK				            0x7FFFFF07U
-#define LPDDR4__DENALI_PHY_1422_WRITE_MASK				           0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1422_READ_MASK                            0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1422_WRITE_MASK                           0x7FFFFF07U
 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_MASK           0x00000007U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_SHIFT				   0U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_WIDTH				   3U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_WIDTH                   3U
 #define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1422
 #define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0
 
@@ -2053,8 +2052,8 @@
 #define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0
 
 #define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_MASK         0x7F000000U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_SHIFT				24U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_WIDTH				 7U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_WIDTH                 7U
 #define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1422
 #define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0
 
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
new file mode 100644
index 0000000000..7f1754a499
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
@@ -0,0 +1,5396 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PI_MACROS_H_
+#define REG_LPDDR4_PI_MACROS_H_
+
+#define LPDDR4__DENALI_PI_0_READ_MASK                                0x00000F01U
+#define LPDDR4__DENALI_PI_0_WRITE_MASK                               0x00000F01U
+#define LPDDR4__DENALI_PI_0__PI_START_MASK                           0x00000001U
+#define LPDDR4__DENALI_PI_0__PI_START_SHIFT                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WIDTH                                   1U
+#define LPDDR4__DENALI_PI_0__PI_START_WOCLR                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WOSET                                   0U
+#define LPDDR4__PI_START__REG DENALI_PI_0
+#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
+
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT                              8U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH                              4U
+#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
+#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
+
+#define LPDDR4__DENALI_PI_1_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH                              32U
+#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
+#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
+
+#define LPDDR4__DENALI_PI_2_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH                              32U
+#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
+#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
+
+#define LPDDR4__DENALI_PI_3_READ_MASK                                0x0000FFFFU
+#define LPDDR4__DENALI_PI_3_WRITE_MASK                               0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT                                      0U
+#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH                                     16U
+#define LPDDR4__PI_ID__REG DENALI_PI_3
+#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
+
+#define LPDDR4__DENALI_PI_4_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_4_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT                     0U
+#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH                    32U
+#define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4
+#define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0
+
+#define LPDDR4__DENALI_PI_5_READ_MASK                                0x00010101U
+#define LPDDR4__DENALI_PI_5_WRITE_MASK                               0x00010101U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT                          0U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH                          1U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR                          0U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET                          0U
+#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5
+#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ
+
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT                             8U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET                             0U
+#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5
+#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN
+
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK                  0x00010000U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT                         16U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH                          1U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR                          0U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET                          0U
+#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5
+#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD
+
+#define LPDDR4__DENALI_PI_6_READ_MASK                                0x00FFFFFFU
+#define LPDDR4__DENALI_PI_6_WRITE_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK                        0x0000FFFFU
+#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT                                0U
+#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH                               16U
+#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6
+#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP
+
+#define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT                              16U
+#define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH                               8U
+#define LPDDR4__PI_RESERVED0__REG DENALI_PI_6
+#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0
+
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK              0x01000000U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT                     24U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH                      1U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR                      0U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET                      0U
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ
+
+#define LPDDR4__DENALI_PI_7_READ_MASK                                0x01010301U
+#define LPDDR4__DENALI_PI_7_WRITE_MASK                               0x01010301U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK                     0x00000001U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT                             0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH                             1U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR                             0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET                             0U
+#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION
+
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK                0x00000300U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT                        8U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH                        2U
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK          0x00010000U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT                 16U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH                  1U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR                  0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET                  0U
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R
+
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK         0x01000000U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT                24U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH                 1U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR                 0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET                 0U
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R
+
+#define LPDDR4__DENALI_PI_8_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_8_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX
+
+#define LPDDR4__DENALI_PI_9_READ_MASK                                0x000FFFFFU
+#define LPDDR4__DENALI_PI_9_WRITE_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK               0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH                      20U
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP
+
+#define LPDDR4__DENALI_PI_10_READ_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_10_WRITE_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK               0x000FFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH                      20U
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP
+
+#define LPDDR4__DENALI_PI_11_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_11_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX
+
+#define LPDDR4__DENALI_PI_12_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT                               0U
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH                              32U
+#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
+#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
+
+#define LPDDR4__DENALI_PI_13_READ_MASK                               0x0101011FU
+#define LPDDR4__DENALI_PI_13_WRITE_MASK                              0x0101011FU
+#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK                 0x0000001FU
+#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT                         0U
+#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH                         5U
+#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13
+#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ
+
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK            0x00000100U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT                    8U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET                    0U
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY
+
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK                       0x00010000U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT                              16U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH                               1U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR                               0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET                               0U
+#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
+#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
+
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT                             24U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH                              1U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR                              0U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET                              0U
+#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
+#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
+
+#define LPDDR4__DENALI_PI_14_READ_MASK                               0x0F011F0FU
+#define LPDDR4__DENALI_PI_14_WRITE_MASK                              0x0F011F0FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK                         0x0000000FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT                                 0U
+#define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH                                 4U
+#define LPDDR4__PI_CS_MAP__REG DENALI_PI_14
+#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP
+
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK               0x00001F00U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT                       8U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH                       5U
+#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
+#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
+
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK           0x00010000U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT                  16U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH                   1U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR                   0U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET                   0U
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
+
+#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK                           0x0F000000U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT                                  24U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH                                   4U
+#define LPDDR4__PI_TMRR__REG DENALI_PI_14
+#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
+
+#define LPDDR4__DENALI_PI_15_READ_MASK                               0x00010103U
+#define LPDDR4__DENALI_PI_15_WRITE_MASK                              0x00010103U
+#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT                       0U
+#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH                       2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15
+#define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT
+
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK            0x00000100U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT                    8U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET                    0U
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
+
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT                             16U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH                              1U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR                              0U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET                              0U
+#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
+#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
+
+#define LPDDR4__DENALI_PI_16_READ_MASK                               0x010FFFFFU
+#define LPDDR4__DENALI_PI_16_WRITE_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT                          0U
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH                         20U
+#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
+#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
+
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT                             24U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH                              1U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR                              0U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET                              0U
+#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
+#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
+
+#define LPDDR4__DENALI_PI_17_READ_MASK                               0x01010001U
+#define LPDDR4__DENALI_PI_17_WRITE_MASK                              0x01010001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH                         1U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET                         0U
+#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
+#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT                             8U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH                             1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR                             0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET                             0U
+#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK                  0x00010000U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT                         16U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH                          1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR                          0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET                          0U
+#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH                        1U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR                        0U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
+#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18_READ_MASK                               0x03010101U
+#define LPDDR4__DENALI_PI_18_WRITE_MASK                              0x03010101U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK                0x00000100U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_19_READ_MASK                               0x03030303U
+#define LPDDR4__DENALI_PI_19_WRITE_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK                0x00000003U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK                0x00000300U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19
+#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0
+
+#define LPDDR4__DENALI_PI_20_READ_MASK                               0x00000007U
+#define LPDDR4__DENALI_PI_20_WRITE_MASK                              0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK               0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT                       0U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH                       3U
+#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20
+#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT                            8U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH                            1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR                            0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET                            0U
+#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT                            16U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH                             1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR                             0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET                             0U
+#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT                      24U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0
+
+#define LPDDR4__DENALI_PI_21_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_21_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT              8U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH              1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR              0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT                      24U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1
+
+#define LPDDR4__DENALI_PI_22_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_22_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT              8U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH              1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR              0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT                      16U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT                      24U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH                       1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR                       0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2
+
+#define LPDDR4__DENALI_PI_23_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_23_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH                       1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR                       0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT              8U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH              1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR              0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT                      16U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK               0x01000000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT                      24U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH                       1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR                       0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET                       0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3
+
+#define LPDDR4__DENALI_PI_24_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_24_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT                       0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH                       1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR                       0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET                       0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK      0x00000100U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT              8U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH              1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR              0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET              0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT                      16U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH                       2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT                       24U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH                        1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR                        0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET                        0U
+#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START
+
+#define LPDDR4__DENALI_PI_25_READ_MASK                               0x01000000U
+#define LPDDR4__DENALI_PI_25_WRITE_MASK                              0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK                   0x00000001U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT                           0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH                           1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR                           0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET                           0U
+#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR
+
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK                   0x00000100U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT                           8U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH                           1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR                           0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET                           0U
+#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD
+
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT                    16U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH                     1U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR                     0U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET                     0U
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ
+
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT                         24U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25
+#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26_READ_MASK                               0x00010101U
+#define LPDDR4__DENALI_PI_26_WRITE_MASK                              0x00010101U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT                          0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET                          0U
+#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26
+#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK                 0x00000100U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT                         8U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH                         1U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR                         0U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET                         0U
+#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26
+#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY
+
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT                    16U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET                     0U
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT                             24U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET                              0U
+#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ
+
+#define LPDDR4__DENALI_PI_27_READ_MASK                               0x003F3F03U
+#define LPDDR4__DENALI_PI_27_WRITE_MASK                              0x003F3F03U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK                       0x00000003U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT                               0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH                               2U
+#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS
+
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK                        0x00003F00U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT                                8U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH                                6U
+#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27
+#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN
+
+#define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK                          0x003F0000U
+#define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT                                 16U
+#define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH                                  6U
+#define LPDDR4__PI_WLMRD__REG DENALI_PI_27
+#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD
+
+#define LPDDR4__DENALI_PI_28_READ_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_28_WRITE_MASK                              0x0101FFFFU
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT                         0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK                 0x00010000U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT                        16U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET                         0U
+#define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT                    24U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_29_READ_MASK                               0x0F010F01U
+#define LPDDR4__DENALI_PI_29_WRITE_MASK                              0x0F010F01U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT                      0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK                0x00000F00U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT                        8U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH                        4U
+#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK                   0x00010000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT                          16U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK                   0x0F000000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT                          24U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH                           4U
+#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_30_READ_MASK                               0x0000FF01U
+#define LPDDR4__DENALI_PI_30_WRITE_MASK                              0x0000FF01U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT                     0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET                     0U
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30
+#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_PI_31_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31
+#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_PI_32_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32
+#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_PI_33_READ_MASK                               0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33_WRITE_MASK                              0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK               0x0000001FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT                       0U
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33
+#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK                       0x00000F00U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT                               8U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH                               4U
+#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK                       0x000F0000U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT                              16U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH                               4U
+#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD
+
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK                      0x0F000000U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT                             24U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH                              4U
+#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33
+#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE
+
+#define LPDDR4__DENALI_PI_34_READ_MASK                               0x00030000U
+#define LPDDR4__DENALI_PI_34_WRITE_MASK                              0x00030000U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK                      0x00000001U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT                              0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET                              0U
+#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ
+
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK                 0x00000100U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT                         8U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH                         1U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR                         0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET                         0U
+#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK                       0x00030000U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT                              16U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH                               2U
+#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS
+
+#define LPDDR4__DENALI_PI_35_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35
+#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0
+
+#define LPDDR4__DENALI_PI_36_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT                            0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1
+
+#define LPDDR4__DENALI_PI_37_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2
+
+#define LPDDR4__DENALI_PI_38_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT                            0U
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38
+#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3
+
+#define LPDDR4__DENALI_PI_39_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT                            0U
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39
+#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4
+
+#define LPDDR4__DENALI_PI_40_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT                            0U
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40
+#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5
+
+#define LPDDR4__DENALI_PI_41_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT                            0U
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41
+#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6
+
+#define LPDDR4__DENALI_PI_42_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT                            0U
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH                           32U
+#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42
+#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7
+
+#define LPDDR4__DENALI_PI_43_READ_MASK                               0x0101010FU
+#define LPDDR4__DENALI_PI_43_WRITE_MASK                              0x0101010FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK                   0x0000000FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT                           0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH                           4U
+#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK                 0x00000100U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT                         8U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET                         0U
+#define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT                    16U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK              0x01000000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT                     24U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_44_READ_MASK                               0x01010101U
+#define LPDDR4__DENALI_PI_44_WRITE_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK            0x00000001U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT                    0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH                    1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR                    0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET                    0U
+#define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK        0x00000100U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT                8U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH                1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR                0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET                0U
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK         0x00010000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT                16U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH                 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR                 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET                 0U
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT                          24U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_45_READ_MASK                               0x000F0F01U
+#define LPDDR4__DENALI_PI_45_WRITE_MASK                              0x000F0F01U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT                      0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH                      1U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR                      0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET                      0U
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK                   0x00000F00U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT                           8U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH                           4U
+#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK              0x000F0000U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT                     16U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH                      4U
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_PI_46_READ_MASK                               0x000003FFU
+#define LPDDR4__DENALI_PI_46_WRITE_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK                  0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT                          0U
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH                         10U
+#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46
+#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_PI_47_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47
+#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_PI_48_READ_MASK                               0x0000FF0FU
+#define LPDDR4__DENALI_PI_48_WRITE_MASK                              0x0000FF0FU
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK                0x0000000FU
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH                        4U
+#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48
+#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_PI_49_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49
+#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_PI_50_READ_MASK                               0x00FFFF01U
+#define LPDDR4__DENALI_PI_50_WRITE_MASK                              0x00FFFF01U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT                     0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET                     0U
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK                 0x00FFFF00U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT                         8U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_51_READ_MASK                               0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51_WRITE_MASK                              0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT                    0U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH                   16U
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK            0x000F0000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT                   16U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH                    4U
+#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK              0x0F000000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT                     24U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH                      4U
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM
+
+#define LPDDR4__DENALI_PI_52_READ_MASK                               0x01011F1FU
+#define LPDDR4__DENALI_PI_52_WRITE_MASK                              0x01011F1FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK               0x0000001FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT                       0U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK          0x00001F00U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT                  8U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH                  5U
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK        0x00010000U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT               16U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH                1U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR                0U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET                0U
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT                       24U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH                        1U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR                        0U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET                        0U
+#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52
+#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_PI_53_READ_MASK                               0x03007F7FU
+#define LPDDR4__DENALI_PI_53_WRITE_MASK                              0x03007F7FU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK                 0x0000007FU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH                         7U
+#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK                 0x00007F00U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT                         8U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH                         7U
+#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK                      0x00010000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT                             16U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH                              1U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR                              0U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET                              0U
+#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK                       0x03000000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT                              24U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH                               2U
+#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS
+
+#define LPDDR4__DENALI_PI_54_READ_MASK                               0x01030F01U
+#define LPDDR4__DENALI_PI_54_WRITE_MASK                              0x01030F01U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK                      0x00000001U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT                              0U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH                              1U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR                              0U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET                              0U
+#define LPDDR4__PI_RESERVED3__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3
+
+#define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT                              8U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH                              4U
+#define LPDDR4__PI_RESERVED4__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4
+
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT                          16U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH                           2U
+#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK                 0x01000000U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT                        24U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET                         0U
+#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_55_READ_MASK                               0x0F010101U
+#define LPDDR4__DENALI_PI_55_WRITE_MASK                              0x0F010101U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT                     0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET                     0U
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT                      8U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH                      1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR                      0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET                      0U
+#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK                   0x00010000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT                          16U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH                           1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR                           0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET                           0U
+#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK                   0x0F000000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT                          24U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH                           4U
+#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_56_READ_MASK                               0x000000FFU
+#define LPDDR4__DENALI_PI_56_WRITE_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK                  0x000000FFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT                          0U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH                          8U
+#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_PI_57_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH                       32U
+#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57
+#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_PI_58_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT                         0U
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH                        32U
+#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58
+#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_PI_59_READ_MASK                               0xFFFF0301U
+#define LPDDR4__DENALI_PI_59_WRITE_MASK                              0xFFFF0301U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH                        1U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR                        0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET                        0U
+#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK             0x00000300U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT                     8U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH                     2U
+#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK                 0xFFFF0000U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT                        16U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH                        16U
+#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_60_READ_MASK                               0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60_WRITE_MASK                              0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK                        0x0000001FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT                                0U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH                                5U
+#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL
+
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK                         0x00003F00U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT                                 8U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH                                 6U
+#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60
+#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD
+
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT                               16U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH                                5U
+#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH
+
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK                         0x1F000000U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT                                24U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH                                 5U
+#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60
+#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT
+
+#define LPDDR4__DENALI_PI_61_READ_MASK                               0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61_WRITE_MASK                              0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT                       0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH                       1U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR                       0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET                       0U
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK    0x00000F00U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT            8U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH            4U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK     0x000F0000U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT            16U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH             4U
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK            0xFF000000U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT                   24U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH                    8U
+#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61
+#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN
+
+#define LPDDR4__DENALI_PI_62_READ_MASK                               0x7F1F0FFFU
+#define LPDDR4__DENALI_PI_62_WRITE_MASK                              0x7F1F0FFFU
+#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK         0x000000FFU
+#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT                 0U
+#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH                 8U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN
+
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK                        0x00000F00U
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT                                8U
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH                                4U
+#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62
+#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK               0x001F0000U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT                      16U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH                       5U
+#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK               0x7F000000U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT                      24U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH                       7U
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF
+
+#define LPDDR4__DENALI_PI_63_READ_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_63_WRITE_MASK                              0x0101FFFFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK        0x000000FFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT                0U
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH                8U
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START
+
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT      8U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH      8U
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
+
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK  0x00010000U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT         16U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH          1U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR          0U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET          0U
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
+
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT       24U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH        1U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR        0U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET        0U
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
+
+#define LPDDR4__DENALI_PI_64_READ_MASK                               0x00FFFF01U
+#define LPDDR4__DENALI_PI_64_WRITE_MASK                              0x00FFFF01U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK      0x00000001U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT              0U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH              1U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR              0U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET              0U
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE
+
+#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT                    8U
+#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH                   16U
+#define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64
+#define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK
+
+#define LPDDR4__DENALI_PI_65_READ_MASK                               0xFFFF0000U
+#define LPDDR4__DENALI_PI_65_WRITE_MASK                              0xFFFF0000U
+#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT                0U
+#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH               16U
+#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65
+#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR
+
+#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK                 0xFFFF0000U
+#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT                        16U
+#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH                        16U
+#define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65
+#define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO
+
+#define LPDDR4__DENALI_PI_66_READ_MASK                               0x010F0701U
+#define LPDDR4__DENALI_PI_66_WRITE_MASK                              0x010F0701U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH                         1U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR                         0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET                         0U
+#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK                 0x00000700U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT                         8U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH                         3U
+#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK               0x000F0000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT                      16U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH                       4U
+#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT                         24U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH                          1U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR                          0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_67_READ_MASK                               0x011F1F0FU
+#define LPDDR4__DENALI_PI_67_WRITE_MASK                              0x011F1F0FU
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK                  0x0000000FU
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT                          0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH                          4U
+#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK   0x00001F00U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT           8U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH           5U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK    0x001F0000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT           16U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH            5U
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT                       24U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH                        1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR                        0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET                        0U
+#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_68_READ_MASK                               0x00FF0300U
+#define LPDDR4__DENALI_PI_68_WRITE_MASK                              0x00FF0300U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK                     0x00000001U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT                             0U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET                             0U
+#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK                      0x00000300U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT                              8U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH                              2U
+#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS
+
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT                        16U
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH                         8U
+#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68
+#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_69_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH                      32U
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP
+
+#define LPDDR4__DENALI_PI_70_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX
+
+#define LPDDR4__DENALI_PI_71_READ_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_71_WRITE_MASK                              0x0101FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH                       16U
+#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT                   16U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH                    1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR                    0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET                    0U
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT                    24U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH                     1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR                     0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET                     0U
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_72_READ_MASK                               0x01010103U
+#define LPDDR4__DENALI_PI_72_WRITE_MASK                              0x01010103U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK            0x00000003U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT                    0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET                          0U
+#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN
+
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK              0x00010000U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT                     16U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH                      1U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR                      0U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET                      0U
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT                    24U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH                     1U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR                     0U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET                     0U
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_73_READ_MASK                               0x0F1F0703U
+#define LPDDR4__DENALI_PI_73_WRITE_MASK                              0x0F1F0703U
+#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK                      0x00000003U
+#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT                              0U
+#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH                              2U
+#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73
+#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF
+
+#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK                       0x00000700U
+#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT                               8U
+#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH                               3U
+#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73
+#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF
+
+#define LPDDR4__DENALI_PI_73__PI_TCCD_MASK                           0x001F0000U
+#define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT                                  16U
+#define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH                                   5U
+#define LPDDR4__PI_TCCD__REG DENALI_PI_73
+#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD
+
+#define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK                      0x0F000000U
+#define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT                             24U
+#define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH                              4U
+#define LPDDR4__PI_RESERVED5__REG DENALI_PI_73
+#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5
+
+#define LPDDR4__DENALI_PI_74_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_74_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK                      0x0000000FU
+#define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT                              0U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH                              4U
+#define LPDDR4__PI_RESERVED6__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6
+
+#define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT                              8U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH                              4U
+#define LPDDR4__PI_RESERVED7__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7
+
+#define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK                      0x000F0000U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT                             16U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH                              4U
+#define LPDDR4__PI_RESERVED8__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8
+
+#define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK                      0x0F000000U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT                             24U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH                              4U
+#define LPDDR4__PI_RESERVED9__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9
+
+#define LPDDR4__DENALI_PI_75_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_75_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT                             0U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH                             4U
+#define LPDDR4__PI_RESERVED10__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10
+
+#define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT                             8U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH                             4U
+#define LPDDR4__PI_RESERVED11__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11
+
+#define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT                            16U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH                             4U
+#define LPDDR4__PI_RESERVED12__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12
+
+#define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT                            24U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH                             4U
+#define LPDDR4__PI_RESERVED13__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13
+
+#define LPDDR4__DENALI_PI_76_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_76_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT                             0U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH                             4U
+#define LPDDR4__PI_RESERVED14__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14
+
+#define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT                             8U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH                             4U
+#define LPDDR4__PI_RESERVED15__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15
+
+#define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT                            16U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH                             4U
+#define LPDDR4__PI_RESERVED16__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16
+
+#define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT                            24U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH                             4U
+#define LPDDR4__PI_RESERVED17__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17
+
+#define LPDDR4__DENALI_PI_77_READ_MASK                               0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_77_WRITE_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT                             0U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH                             4U
+#define LPDDR4__PI_RESERVED18__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18
+
+#define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT                             8U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH                             4U
+#define LPDDR4__PI_RESERVED19__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19
+
+#define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT                            16U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH                             4U
+#define LPDDR4__PI_RESERVED20__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20
+
+#define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT                            24U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH                             4U
+#define LPDDR4__PI_RESERVED21__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21
+
+#define LPDDR4__DENALI_PI_78_READ_MASK                               0x000F0F0FU
+#define LPDDR4__DENALI_PI_78_WRITE_MASK                              0x000F0F0FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT                             0U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH                             4U
+#define LPDDR4__PI_RESERVED22__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT                             8U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH                             4U
+#define LPDDR4__PI_RESERVED23__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT                            16U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH                             4U
+#define LPDDR4__PI_RESERVED24__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24
+
+#define LPDDR4__DENALI_PI_79_READ_MASK                               0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_79_WRITE_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK                     0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT                             0U
+#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH                            28U
+#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79
+#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS
+
+#define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK                        0x07FFFFFFU
+#define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT                                0U
+#define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH                               27U
+#define LPDDR4__PI_INT_ACK__REG DENALI_PI_80
+#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK
+
+#define LPDDR4__DENALI_PI_81_READ_MASK                               0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_81_WRITE_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK                       0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT                               0U
+#define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH                              28U
+#define LPDDR4__PI_INT_MASK__REG DENALI_PI_81
+#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK
+
+#define LPDDR4__DENALI_PI_82_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_82_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82
+#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_PI_83_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_83_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83
+#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_PI_84_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_84_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84
+#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_PI_85_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_85_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH                       32U
+#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85
+#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_PI_86_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86
+#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_PI_87_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87
+#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_PI_88_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88
+#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_PI_89_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT                       0U
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89
+#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_PI_90_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_PI_91_READ_MASK                               0x011F1F07U
+#define LPDDR4__DENALI_PI_91_WRITE_MASK                              0x011F1F07U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK               0x00000007U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH                       3U
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK                         0x00001F00U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT                                 8U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH                                 5U
+#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91
+#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN
+
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT                       16U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH                        5U
+#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91
+#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT                           24U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH                            1U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR                            0U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET                            0U
+#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91
+#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN
+
+#define LPDDR4__DENALI_PI_92_READ_MASK                               0x03030301U
+#define LPDDR4__DENALI_PI_92_WRITE_MASK                              0x03030301U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT                      0U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH                      1U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR                      0U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET                      0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN
+
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK          0x00000300U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT                  8U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH                  2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0
+
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK          0x00030000U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT                 16U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH                  2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1
+
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK          0x03000000U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT                 24U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH                  2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2
+
+#define LPDDR4__DENALI_PI_93_READ_MASK                               0x03FF0103U
+#define LPDDR4__DENALI_PI_93_WRITE_MASK                              0x03FF0103U
+#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK          0x00000003U
+#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT                  0U
+#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH                  2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3
+
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK        0x00000100U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT                8U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH                1U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR                0U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET                0U
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK               0x00FF0000U
+#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT                      16U
+#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH                       8U
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK            0x03000000U
+#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT                   24U
+#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_94_READ_MASK                               0x013F0301U
+#define LPDDR4__DENALI_PI_94_WRITE_MASK                              0x013F0301U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK                        0x00000001U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT                                0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH                                1U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR                                0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET                                0U
+#define LPDDR4__PI_BIST_GO__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO
+
+#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK                    0x00000300U
+#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT                            8U
+#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH                            2U
+#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT
+
+#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK                     0x003F0000U
+#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT                            16U
+#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH                             6U
+#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94
+#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE
+
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT                       24U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH                        1U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR                        0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET                        0U
+#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_PI_95_READ_MASK                               0x00000001U
+#define LPDDR4__DENALI_PI_95_WRITE_MASK                              0x00000001U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT                        0U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH                        1U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR                        0U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET                        0U
+#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95
+#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_PI_96_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH                  32U
+#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_PI_97_READ_MASK                               0x0000FF07U
+#define LPDDR4__DENALI_PI_97_WRITE_MASK                              0x0000FF07U
+#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK           0x00000007U
+#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH                   3U
+#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK             0x0000FF00U
+#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT                     8U
+#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH                     8U
+#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97
+#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN
+
+#define LPDDR4__DENALI_PI_98_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98
+#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_PI_99_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_99_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH                      32U
+#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99
+#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_PI_100_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_100_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK                0x00000FFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT                        0U
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH                       12U
+#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100
+#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK                 0x0FFF0000U
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT                        16U
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH                        12U
+#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100
+#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP
+
+#define LPDDR4__DENALI_PI_101_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_101_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0
+
+#define LPDDR4__DENALI_PI_102_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_102_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1
+
+#define LPDDR4__DENALI_PI_103_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_103_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0
+
+#define LPDDR4__DENALI_PI_104_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_104_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1
+
+#define LPDDR4__DENALI_PI_105_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_105_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0
+
+#define LPDDR4__DENALI_PI_106_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_106_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1
+
+#define LPDDR4__DENALI_PI_107_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0
+
+#define LPDDR4__DENALI_PI_108_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_108_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1
+
+#define LPDDR4__DENALI_PI_109_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0
+
+#define LPDDR4__DENALI_PI_110_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_110_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1
+
+#define LPDDR4__DENALI_PI_111_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_111_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0
+
+#define LPDDR4__DENALI_PI_112_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_112_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1
+
+#define LPDDR4__DENALI_PI_113_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_113_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0
+
+#define LPDDR4__DENALI_PI_114_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_114_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1
+
+#define LPDDR4__DENALI_PI_115_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_115_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0
+
+#define LPDDR4__DENALI_PI_116_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_116_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1
+
+#define LPDDR4__DENALI_PI_117_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_117_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0
+
+#define LPDDR4__DENALI_PI_118_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_118_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1
+
+#define LPDDR4__DENALI_PI_119_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_119_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH                   32U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0
+
+#define LPDDR4__DENALI_PI_120_READ_MASK                              0x0303070FU
+#define LPDDR4__DENALI_PI_120_WRITE_MASK                             0x0303070FU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH                    4U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1
+
+#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK                     0x00000700U
+#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT                             8U
+#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH                             3U
+#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE
+
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT                       16U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH                        2U
+#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE
+
+#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK                 0x03000000U
+#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT                        24U
+#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH                         2U
+#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE
+
+#define LPDDR4__DENALI_PI_121_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_121_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0
+
+#define LPDDR4__DENALI_PI_122_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122
+#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1
+
+#define LPDDR4__DENALI_PI_123_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123
+#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2
+
+#define LPDDR4__DENALI_PI_124_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT                       0U
+#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH                      32U
+#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124
+#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3
+
+#define LPDDR4__DENALI_PI_125_READ_MASK                              0x0000000FU
+#define LPDDR4__DENALI_PI_125_WRITE_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK                  0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT                          0U
+#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH                          4U
+#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125
+#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM
+
+#define LPDDR4__DENALI_PI_126_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT                          0U
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126
+#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0
+
+#define LPDDR4__DENALI_PI_127_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127
+#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1
+
+#define LPDDR4__DENALI_PI_128_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128
+#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2
+
+#define LPDDR4__DENALI_PI_129_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT                          0U
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129
+#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3
+
+#define LPDDR4__DENALI_PI_130_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT                          0U
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130
+#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4
+
+#define LPDDR4__DENALI_PI_131_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT                          0U
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5
+
+#define LPDDR4__DENALI_PI_132_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT                          0U
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132
+#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6
+
+#define LPDDR4__DENALI_PI_133_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_133_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK                  0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT                          0U
+#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH                         30U
+#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133
+#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7
+
+#define LPDDR4__DENALI_PI_134_READ_MASK                              0x0101010FU
+#define LPDDR4__DENALI_PI_134_WRITE_MASK                             0x0101010FU
+#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK                      0x0000000FU
+#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT                              0U
+#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH                              4U
+#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134
+#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF
+
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK               0x00000100U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT                       8U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH                       1U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR                       0U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET                       0U
+#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134
+#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN
+
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK           0x00010000U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT                  16U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH                   1U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR                   0U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET                   0U
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK      0x01000000U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT             24U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH              1U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR              0U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET              0U
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_PI_135_READ_MASK                              0x01010100U
+#define LPDDR4__DENALI_PI_135_WRITE_MASK                             0x01010100U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT                        0U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH                        1U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR                        0U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET                        0U
+#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135
+#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ
+
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK                0x00000100U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT                        8U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH                        1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR                        0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET                        0U
+#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK                   0x00010000U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT                          16U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH                           1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR                           0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET                           0U
+#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK         0x01000000U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT                24U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH                 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR                 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET                 0U
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT
+
+#define LPDDR4__DENALI_PI_136_READ_MASK                              0x00000001U
+#define LPDDR4__DENALI_PI_136_WRITE_MASK                             0x00000001U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK              0x00000001U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT                      0U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH                      1U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR                      0U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET                      0U
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_PI_137_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT                            0U
+#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH                           32U
+#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137
+#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON
+
+#define LPDDR4__DENALI_PI_138_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_138_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH                         32U
+#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138
+#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE
+
+#define LPDDR4__DENALI_PI_139_READ_MASK                              0xFFFF0101U
+#define LPDDR4__DENALI_PI_139_WRITE_MASK                             0xFFFF0101U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT                               0U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH                               1U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR                               0U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET                               0U
+#define LPDDR4__PI_DLL_RST__REG DENALI_PI_139
+#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST
+
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT                          8U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH                          1U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR                          0U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET                          0U
+#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139
+#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN
+
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK                 0xFFFF0000U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT                        16U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH                        16U
+#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139
+#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY
+
+#define LPDDR4__DENALI_PI_140_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_140_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK               0x000000FFU
+#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT                       0U
+#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH                       8U
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_PI_141_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_141_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK                 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT                         0U
+#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH                        26U
+#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141
+#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG
+
+#define LPDDR4__DENALI_PI_142_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_PI_142_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK                    0x000000FFU
+#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT                            0U
+#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH                            8U
+#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142
+#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS
+
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT                          8U
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH                         17U
+#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142
+#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG
+
+#define LPDDR4__DENALI_PI_143_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK         0x00FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT                 0U
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH                24U
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT                           24U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH                            1U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR                            0U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET                            0U
+#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143
+#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT
+
+#define LPDDR4__DENALI_PI_144_READ_MASK                              0x0101000FU
+#define LPDDR4__DENALI_PI_144_WRITE_MASK                             0x0101000FU
+#define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK                    0x0000000FU
+#define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT                            0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH                            4U
+#define LPDDR4__PI_RESERVED25__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK                    0x00000F00U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT                            8U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH                            4U
+#define LPDDR4__PI_RESERVED26__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26
+
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT                       16U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH                        1U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR                        0U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET                        0U
+#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144
+#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT                           24U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH                            1U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR                            0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET                            0U
+#define LPDDR4__PI_RESERVED27__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27
+
+#define LPDDR4__DENALI_PI_145_READ_MASK                              0xFF010F07U
+#define LPDDR4__DENALI_PI_145_WRITE_MASK                             0xFF010F07U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK                    0x00000007U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT                            0U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH                            3U
+#define LPDDR4__PI_RESERVED28__REG DENALI_PI_145
+#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK             0x00000F00U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT                     8U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT                    16U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH                     1U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR                     0U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT                            24U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0
+
+#define LPDDR4__DENALI_PI_146_READ_MASK                              0x0FFF010FU
+#define LPDDR4__DENALI_PI_146_WRITE_MASK                             0x0FFF010FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK             0x0000000FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT                     8U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH                     1U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR                     0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK             0x0F000000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT                    24U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2
+
+#define LPDDR4__DENALI_PI_147_READ_MASK                              0x010FFF01U
+#define LPDDR4__DENALI_PI_147_WRITE_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH                     1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR                     0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK             0x000F0000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT                    16U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT                    24U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH                     1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR                     0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3
+
+#define LPDDR4__DENALI_PI_148_READ_MASK                              0xFF010FFFU
+#define LPDDR4__DENALI_PI_148_WRITE_MASK                             0xFF010FFFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT                             0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK             0x00000F00U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT                     8U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT                    16U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH                     1U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR                     0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK                     0xFF000000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT                            24U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4
+
+#define LPDDR4__DENALI_PI_149_READ_MASK                              0x0FFF010FU
+#define LPDDR4__DENALI_PI_149_WRITE_MASK                             0x0FFF010FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK             0x0000000FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT                     0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK             0x00000100U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT                     8U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH                     1U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR                     0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT                            16U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK             0x0F000000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT                    24U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6
+
+#define LPDDR4__DENALI_PI_150_READ_MASK                              0x010FFF01U
+#define LPDDR4__DENALI_PI_150_WRITE_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK             0x00000001U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT                     0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH                     1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR                     0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT                             8U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK             0x000F0000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT                    16U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH                     4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK             0x01000000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT                    24U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH                     1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR                     0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET                     0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7
+
+#define LPDDR4__DENALI_PI_151_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_151_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK                     0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT                             0U
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH                             8U
+#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151
+#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7
+
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT                        0U
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH                        8U
+#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152
+#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE
+
+#define LPDDR4__DENALI_PI_153_READ_MASK                              0x011F1F01U
+#define LPDDR4__DENALI_PI_153_WRITE_MASK                             0x011F1F01U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK                      0x00000001U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT                              0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH                              1U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR                              0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET                              0U
+#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153
+#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK            0x00001F00U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT                    8U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH                    5U
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK            0x001F0000U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT                   16U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH                    5U
+#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM
+
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT                           24U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH                            1U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR                            0U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET                            0U
+#define LPDDR4__PI_RESERVED29__REG DENALI_PI_153
+#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29
+
+#define LPDDR4__DENALI_PI_154_READ_MASK                              0x01010103U
+#define LPDDR4__DENALI_PI_154_WRITE_MASK                             0x01010103U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK                  0x00000003U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT                          0U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH                          2U
+#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154
+#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT                            8U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH                            1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR                            0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET                            0U
+#define LPDDR4__PI_RESERVED30__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30
+
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT                       16U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH                        1U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR                        0U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET                        0U
+#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154
+#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT                           24U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH                            1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR                            0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET                            0U
+#define LPDDR4__PI_RESERVED31__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31
+
+#define LPDDR4__DENALI_PI_155_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_155_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET                            0U
+#define LPDDR4__PI_RESERVED32__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT                            8U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET                            0U
+#define LPDDR4__PI_RESERVED33__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT                           16U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET                            0U
+#define LPDDR4__PI_RESERVED34__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT                           24U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH                            1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR                            0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET                            0U
+#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35
+
+#define LPDDR4__DENALI_PI_156_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_156_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET                            0U
+#define LPDDR4__PI_RESERVED36__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT                            8U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET                            0U
+#define LPDDR4__PI_RESERVED37__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT                           16U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET                            0U
+#define LPDDR4__PI_RESERVED38__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT                           24U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH                            1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR                            0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET                            0U
+#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39
+
+#define LPDDR4__DENALI_PI_157_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_157_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET                            0U
+#define LPDDR4__PI_RESERVED40__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT                            8U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET                            0U
+#define LPDDR4__PI_RESERVED41__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT                           16U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET                            0U
+#define LPDDR4__PI_RESERVED42__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT                           24U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH                            1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR                            0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET                            0U
+#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43
+
+#define LPDDR4__DENALI_PI_158_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_158_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK                    0x00000001U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET                            0U
+#define LPDDR4__PI_RESERVED44__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT                            8U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET                            0U
+#define LPDDR4__PI_RESERVED45__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK                    0x00010000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT                           16U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET                            0U
+#define LPDDR4__PI_RESERVED46__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK                    0x01000000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT                           24U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH                            1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR                            0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET                            0U
+#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47
+
+#define LPDDR4__DENALI_PI_159_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PI_159_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK         0x000000FFU
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT                 0U
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH                 8U
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND
+
+#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK                    0x0001FF00U
+#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT                            8U
+#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH                            9U
+#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159
+#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR
+
+#define LPDDR4__DENALI_PI_160_READ_MASK                              0x0000001FU
+#define LPDDR4__DENALI_PI_160_WRITE_MASK                             0x0000001FU
+#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK          0x0000001FU
+#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT                  0U
+#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH                  5U
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY
+
+#define LPDDR4__DENALI_PI_161_READ_MASK                              0x0F011F01U
+#define LPDDR4__DENALI_PI_161_WRITE_MASK                             0x0F011F01U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK           0x00000001U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT                   0U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH                   1U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR                   0U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET                   0U
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK                    0x00001F00U
+#define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT                            8U
+#define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH                            5U
+#define LPDDR4__PI_RESERVED48__REG DENALI_PI_161
+#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48
+
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK             0x00010000U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT                    16U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH                     1U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR                     0U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET                     0U
+#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161
+#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN
+
+#define LPDDR4__DENALI_PI_161__PI_CATR_MASK                          0x0F000000U
+#define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT                                 24U
+#define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH                                  4U
+#define LPDDR4__PI_CATR__REG DENALI_PI_161
+#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR
+
+#define LPDDR4__DENALI_PI_162_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PI_162_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK                  0x00000001U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT                          0U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH                          1U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR                          0U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET                          0U
+#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162
+#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ
+
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK            0x00000100U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT                    8U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH                    1U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR                    0U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET                    0U
+#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162
+#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE
+
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK                 0x00010000U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT                        16U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH                         1U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR                         0U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET                         0U
+#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162
+#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC
+
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK         0x01000000U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT                24U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH                 1U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR                 0U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET                 0U
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START
+
+#define LPDDR4__DENALI_PI_163_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_PI_163_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT                         0U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH                         1U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR                         0U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET                         0U
+#define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163
+#define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13
+
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163
+#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0
+
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163
+#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1
+
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT                              24U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH                               8U
+#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163
+#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2
+
+#define LPDDR4__DENALI_PI_164_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_164_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT             0U
+#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0
+
+#define LPDDR4__DENALI_PI_165_READ_MASK                              0x000000FFU
+#define LPDDR4__DENALI_PI_165_WRITE_MASK                             0x000000FFU
+#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT             0U
+#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1
+
+#define LPDDR4__DENALI_PI_166_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_166_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK     0x000000FFU
+#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT             0U
+#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH             8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2
+
+#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK                     0x000FFF00U
+#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166
+#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0
+
+#define LPDDR4__DENALI_PI_167_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_167_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK                     0x00000FFFU
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167
+#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1
+
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH                            12U
+#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167
+#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2
+
+#define LPDDR4__DENALI_PI_168_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_168_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK                      0x0000007FU
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168
+#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0
+
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK                 0x00007F00U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT                         8U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168
+#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK                      0x007F0000U
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT                             16U
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168
+#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1
+
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK                 0x7F000000U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT                        24U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168
+#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_PI_169_READ_MASK                              0x03FF7F7FU
+#define LPDDR4__DENALI_PI_169_WRITE_MASK                             0x03FF7F7FU
+#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK                      0x0000007FU
+#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT                              0U
+#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH                              7U
+#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169
+#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2
+
+#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK                 0x00007F00U
+#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT                         8U
+#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH                         7U
+#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169
+#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK                       0x03FF0000U
+#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT                              16U
+#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169
+#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0
+
+#define LPDDR4__DENALI_PI_170_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_170_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH                              20U
+#define LPDDR4__PI_TREF_F0__REG DENALI_PI_170
+#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0
+
+#define LPDDR4__DENALI_PI_171_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_171_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171
+#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1
+
+#define LPDDR4__DENALI_PI_172_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PI_172_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH                              20U
+#define LPDDR4__PI_TREF_F1__REG DENALI_PI_172
+#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1
+
+#define LPDDR4__DENALI_PI_173_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_PI_173_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK                       0x000003FFU
+#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH                              10U
+#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173
+#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2
+
+#define LPDDR4__DENALI_PI_174_READ_MASK                              0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_174_WRITE_MASK                             0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK                       0x000FFFFFU
+#define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH                              20U
+#define LPDDR4__PI_TREF_F2__REG DENALI_PI_174
+#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2
+
+#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK            0x0F000000U
+#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT                   24U
+#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_PI_175_READ_MASK                              0x03030F0FU
+#define LPDDR4__DENALI_PI_175_WRITE_MASK                             0x03030F0FU
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT                    0U
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK            0x00000F00U
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT                    8U
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH                    4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175
+#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK                   0x03000000U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175
+#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_176_READ_MASK                              0x0003FF03U
+#define LPDDR4__DENALI_PI_176_WRITE_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176
+#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK              0x0003FF00U
+#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT                      8U
+#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0
+
+#define LPDDR4__DENALI_PI_177_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_177_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT                      0U
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1
+
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK              0x03FF0000U
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT                     16U
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH                     10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2
+
+#define LPDDR4__DENALI_PI_178_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PI_178_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178
+#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH                             1U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR                             0U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178
+#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0
+
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178
+#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK                     0x01000000U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH                             1U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR                             0U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178
+#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1
+
+#define LPDDR4__DENALI_PI_179_READ_MASK                              0x0F0F01FFU
+#define LPDDR4__DENALI_PI_179_WRITE_MASK                             0x0F0F01FFU
+#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH                         8U
+#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179
+#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH                             1U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR                             0U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET                             0U
+#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179
+#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2
+
+#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179
+#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0
+
+#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK                 0x0F000000U
+#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179
+#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0
+
+#define LPDDR4__DENALI_PI_180_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_180_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180
+#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1
+
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK                 0x00000F00U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180
+#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1
+
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH                             4U
+#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180
+#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2
+
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK                 0x0F000000U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT                        24U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH                         4U
+#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180
+#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2
+
+#define LPDDR4__DENALI_PI_181_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_181_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK              0x00000300U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT                      8U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0
+
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK              0x03000000U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT                     24U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1
+
+#define LPDDR4__DENALI_PI_182_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_182_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK              0x00000300U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT                      8U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2
+
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK              0x00030000U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT                     16U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0
+
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK             0x03000000U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT                    24U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0
+
+#define LPDDR4__DENALI_PI_183_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_183_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT                       0U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0
+
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK             0x00000300U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT                     8U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0
+
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK              0x00030000U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT                     16U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1
+
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK             0x03000000U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT                    24U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1
+
+#define LPDDR4__DENALI_PI_184_READ_MASK                              0x03030303U
+#define LPDDR4__DENALI_PI_184_WRITE_MASK                             0x03030303U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1
+
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK             0x00000300U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT                     8U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1
+
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK              0x00030000U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT                     16U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH                      2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2
+
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK             0x03000000U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT                    24U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2
+
+#define LPDDR4__DENALI_PI_185_READ_MASK                              0x7F7F0303U
+#define LPDDR4__DENALI_PI_185_WRITE_MASK                             0x7F7F0303U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT                       0U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH                       2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2
+
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK             0x00000300U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT                     8U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH                     2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2
+
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK                  0x007F0000U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT                         16U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH                          7U
+#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185
+#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK                  0x7F000000U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH                          7U
+#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185
+#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_186_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_186_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK                  0x0000007FU
+#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT                          0U
+#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH                          7U
+#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186
+#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK                  0x00007F00U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT                          8U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH                          7U
+#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186
+#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK                  0x007F0000U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT                         16U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH                          7U
+#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186
+#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK                  0x7F000000U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT                         24U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH                          7U
+#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186
+#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_187_READ_MASK                              0x00070707U
+#define LPDDR4__DENALI_PI_187_WRITE_MASK                             0x00070707U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK            0x00000007U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK            0x00000700U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT                    8U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK            0x00070000U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT                   16U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH                    3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_PI_188_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_188_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT                      0U
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT                16U
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_PI_189_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_189_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT                      0U
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT                16U
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_PI_190_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_190_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK              0x000003FFU
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT                      0U
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH                     10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT                16U
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH                10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_PI_191_READ_MASK                              0x1F030303U
+#define LPDDR4__DENALI_PI_191_WRITE_MASK                             0x1F030303U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK                   0x00000003U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK                   0x00000300U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191
+#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1
+
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK                   0x00030000U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH                           2U
+#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191
+#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2
+
+#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191
+#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0
+
+#define LPDDR4__DENALI_PI_192_READ_MASK                              0x001F3FFFU
+#define LPDDR4__DENALI_PI_192_WRITE_MASK                             0x001F3FFFU
+#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192
+#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0
+
+#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192
+#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1
+
+#define LPDDR4__DENALI_PI_193_READ_MASK                              0x001F3FFFU
+#define LPDDR4__DENALI_PI_193_WRITE_MASK                             0x001F3FFFU
+#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193
+#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1
+
+#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT                              16U
+#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH                               5U
+#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193
+#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2
+
+#define LPDDR4__DENALI_PI_194_READ_MASK                              0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_194_WRITE_MASK                             0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK                     0x00003FFFU
+#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH                            14U
+#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194
+#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2
+
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194
+#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0
+
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194
+#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0
+
+#define LPDDR4__DENALI_PI_195_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_195_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK                0x000003FFU
+#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195
+#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0
+
+#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195
+#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0
+
+#define LPDDR4__DENALI_PI_196_READ_MASK                              0x03FF1F1FU
+#define LPDDR4__DENALI_PI_196_WRITE_MASK                             0x03FF1F1FU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK                0x0000001FU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1
+
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK                 0x00001F00U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1
+
+#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1
+
+#define LPDDR4__DENALI_PI_197_READ_MASK                              0x1F1F03FFU
+#define LPDDR4__DENALI_PI_197_WRITE_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197
+#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1
+
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK                0x001F0000U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH                        5U
+#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2
+
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK                 0x1F000000U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT                        24U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH                         5U
+#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2
+
+#define LPDDR4__DENALI_PI_198_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_198_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK                0x000003FFU
+#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH                       10U
+#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2
+
+#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH                        10U
+#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2
+
+#define LPDDR4__DENALI_PI_199_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_199_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT     0U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT      8U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT    16U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT     24U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_200_READ_MASK                              0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_200_WRITE_MASK                             0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT     0U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH     7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT      8U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH      7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK           0x000F0000U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT                  16U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK           0x0F000000U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT                  24U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_201_READ_MASK                              0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_201_WRITE_MASK                             0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK           0x0000000FU
+#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH                   4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT                  8U
+#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0
+
+#define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH                                5U
+#define LPDDR4__PI_TXP_F0__REG DENALI_PI_201
+#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0
+
+#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201
+#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0
+
+#define LPDDR4__DENALI_PI_202_READ_MASK                              0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_202_WRITE_MASK                             0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT                            0U
+#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0
+
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT                  8U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1
+
+#define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT                               16U
+#define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH                                5U
+#define LPDDR4__PI_TXP_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1
+
+#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1
+
+#define LPDDR4__DENALI_PI_203_READ_MASK                              0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_203_WRITE_MASK                             0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT                            0U
+#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203
+#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1
+
+#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK          0x00000F00U
+#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT                  8U
+#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH                  4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2
+
+#define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK                        0x001F0000U
+#define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT                               16U
+#define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH                                5U
+#define LPDDR4__PI_TXP_F2__REG DENALI_PI_203
+#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2
+
+#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH                           8U
+#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203
+#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2
+
+#define LPDDR4__DENALI_PI_204_READ_MASK                              0x0003FF1FU
+#define LPDDR4__DENALI_PI_204_WRITE_MASK                             0x0003FF1FU
+#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK                    0x0000001FU
+#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT                            0U
+#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH                            5U
+#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204
+#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2
+
+#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT                    8U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH                   10U
+#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204
+#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_PI_205_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_205_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT                 0U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH                16U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK            0x03FF0000U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT                   16U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH                   10U
+#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_PI_206_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PI_206_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT                 0U
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH                16U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK            0x03FF0000U
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT                   16U
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH                   10U
+#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206
+#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_PI_207_READ_MASK                              0x003FFFFFU
+#define LPDDR4__DENALI_PI_207_WRITE_MASK                             0x003FFFFFU
+#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT                 0U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH                16U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK                   0x003F0000U
+#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207
+#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0
+
+#define LPDDR4__DENALI_PI_208_READ_MASK                              0x003F03FFU
+#define LPDDR4__DENALI_PI_208_WRITE_MASK                             0x003F03FFU
+#define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT                                0U
+#define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH                               10U
+#define LPDDR4__PI_TFC_F0__REG DENALI_PI_208
+#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0
+
+#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK                   0x003F0000U
+#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208
+#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1
+
+#define LPDDR4__DENALI_PI_209_READ_MASK                              0x003F03FFU
+#define LPDDR4__DENALI_PI_209_WRITE_MASK                             0x003F03FFU
+#define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT                                0U
+#define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH                               10U
+#define LPDDR4__PI_TFC_F1__REG DENALI_PI_209
+#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1
+
+#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH                           6U
+#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209
+#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2
+
+#define LPDDR4__DENALI_PI_210_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_210_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK                        0x000003FFU
+#define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT                                0U
+#define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH                               10U
+#define LPDDR4__PI_TFC_F2__REG DENALI_PI_210
+#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2
+
+#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK             0x03FF0000U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT                    16U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0
+
+#define LPDDR4__DENALI_PI_211_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_211_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT                     0U
+#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0
+
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT   16U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT    24U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_212_READ_MASK                              0x0003030FU
+#define LPDDR4__DENALI_PI_212_WRITE_MASK                             0x0003030FU
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT                  0U
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT                          8U
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212
+#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT                      16U
+#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0
+
+#define LPDDR4__DENALI_PI_213_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PI_213_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT                     0U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1
+
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK             0x03FF0000U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT                    16U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1
+
+#define LPDDR4__DENALI_PI_214_READ_MASK                              0x030F7F7FU
+#define LPDDR4__DENALI_PI_214_WRITE_MASK                             0x030F7F7FU
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT    0U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT     8U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK          0x000F0000U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT                 16U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK                  0x03000000U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT                         24U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_215_READ_MASK                              0x0003FF03U
+#define LPDDR4__DENALI_PI_215_WRITE_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK               0x00000003U
+#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1
+
+#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK             0x0003FF00U
+#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT                     8U
+#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2
+
+#define LPDDR4__DENALI_PI_216_READ_MASK                              0x7F7F03FFU
+#define LPDDR4__DENALI_PI_216_WRITE_MASK                             0x7F7F03FFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK             0x000003FFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT                     0U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH                    10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2
+
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT   16U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH    7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT    24U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH     7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_217_READ_MASK                              0xFF03030FU
+#define LPDDR4__DENALI_PI_217_WRITE_MASK                             0xFF03030FU
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK          0x0000000FU
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT                  0U
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH                  4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT                          8U
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH                          2U
+#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217
+#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK               0x00030000U
+#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT                      16U
+#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH                       2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2
+
+#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217
+#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0
+
+#define LPDDR4__DENALI_PI_218_READ_MASK                              0xFF3FFFFFU
+#define LPDDR4__DENALI_PI_218_WRITE_MASK                             0xFF3FFFFFU
+#define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT                                0U
+#define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH                                8U
+#define LPDDR4__PI_TRP_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT                               8U
+#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK                       0x003F0000U
+#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT                              16U
+#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK                        0xFF000000U
+#define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT                               24U
+#define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH                                8U
+#define LPDDR4__PI_TWR_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0
+
+#define LPDDR4__DENALI_PI_219_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_219_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH                          17U
+#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219
+#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0
+
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH                           8U
+#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219
+#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0
+
+#define LPDDR4__DENALI_PI_220_READ_MASK                              0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_220_WRITE_MASK                             0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK                 0x0000000FU
+#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK                     0x00003F00U
+#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT                             8U
+#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0
+
+#define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT                               16U
+#define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH                                8U
+#define LPDDR4__PI_TSR_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0
+
+#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT                              24U
+#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0
+
+#define LPDDR4__DENALI_PI_221_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_221_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0
+
+#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT                               8U
+#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221
+#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1
+
+#define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT                               16U
+#define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH                                8U
+#define LPDDR4__PI_TRP_F1__REG DENALI_PI_221
+#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1
+
+#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT                              24U
+#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221
+#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1
+
+#define LPDDR4__DENALI_PI_222_READ_MASK                              0x0000FF3FU
+#define LPDDR4__DENALI_PI_222_WRITE_MASK                             0x0000FF3FU
+#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK                       0x0000003FU
+#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1
+
+#define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT                                8U
+#define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH                                8U
+#define LPDDR4__PI_TWR_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1
+
+#define LPDDR4__DENALI_PI_223_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_223_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH                          17U
+#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223
+#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1
+
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH                           8U
+#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223
+#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1
+
+#define LPDDR4__DENALI_PI_224_READ_MASK                              0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_224_WRITE_MASK                             0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK                 0x0000000FU
+#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK                     0x00003F00U
+#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT                             8U
+#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1
+
+#define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT                               16U
+#define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH                                8U
+#define LPDDR4__PI_TSR_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1
+
+#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT                              24U
+#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1
+
+#define LPDDR4__DENALI_PI_225_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_225_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225
+#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1
+
+#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK                       0x0000FF00U
+#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT                               8U
+#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH                               8U
+#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225
+#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2
+
+#define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT                               16U
+#define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH                                8U
+#define LPDDR4__PI_TRP_F2__REG DENALI_PI_225
+#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2
+
+#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT                              24U
+#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH                               8U
+#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225
+#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2
+
+#define LPDDR4__DENALI_PI_226_READ_MASK                              0x0000FF3FU
+#define LPDDR4__DENALI_PI_226_WRITE_MASK                             0x0000FF3FU
+#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK                       0x0000003FU
+#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH                               6U
+#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226
+#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2
+
+#define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT                                8U
+#define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH                                8U
+#define LPDDR4__PI_TWR_F2__REG DENALI_PI_226
+#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2
+
+#define LPDDR4__DENALI_PI_227_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_PI_227_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH                          17U
+#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227
+#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2
+
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH                           8U
+#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227
+#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2
+
+#define LPDDR4__DENALI_PI_228_READ_MASK                              0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_228_WRITE_MASK                             0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK                 0x0000000FU
+#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH                         4U
+#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK                     0x00003F00U
+#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH                             6U
+#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2
+
+#define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT                               16U
+#define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH                                8U
+#define LPDDR4__PI_TSR_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2
+
+#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT                              24U
+#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH                               8U
+#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2
+
+#define LPDDR4__DENALI_PI_229_READ_MASK                              0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_229_WRITE_MASK                             0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH                               8U
+#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229
+#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2
+
+#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK           0x1FFFFF00U
+#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT                   8U
+#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_PI_230_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_230_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT              0U
+#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_PI_231_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_231_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT                   0U
+#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_PI_232_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_232_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT              0U
+#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_PI_233_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PI_233_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT                   0U
+#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH                  21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_PI_234_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_234_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT              0U
+#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH             32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_PI_235_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK                       0xFFFF0000U
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT                              16U
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235
+#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1
+
+#define LPDDR4__DENALI_PI_236_READ_MASK                              0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_236_WRITE_MASK                             0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK                       0x0000FFFFU
+#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT                               0U
+#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH                              16U
+#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236
+#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2
+
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK                     0x003F0000U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236
+#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK                     0x3F000000U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT                            24U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1
+
+#define LPDDR4__DENALI_PI_237_READ_MASK                              0xFFFFFF3FU
+#define LPDDR4__DENALI_PI_237_WRITE_MASK                             0xFFFFFF3FU
+#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK                     0x0000003FU
+#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH                             6U
+#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237
+#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2
+
+#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK                      0xFFFFFF00U
+#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT                              8U
+#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237
+#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0
+
+#define LPDDR4__DENALI_PI_238_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_238_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238
+#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0
+
+#define LPDDR4__DENALI_PI_239_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_239_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239
+#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0
+
+#define LPDDR4__DENALI_PI_240_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_240_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240
+#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0
+
+#define LPDDR4__DENALI_PI_241_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_241_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT                              0U
+#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241
+#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0
+
+#define LPDDR4__DENALI_PI_242_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_242_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242
+#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1
+
+#define LPDDR4__DENALI_PI_243_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_243_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243
+#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1
+
+#define LPDDR4__DENALI_PI_244_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_244_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244
+#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1
+
+#define LPDDR4__DENALI_PI_245_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_245_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245
+#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1
+
+#define LPDDR4__DENALI_PI_246_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_246_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246
+#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1
+
+#define LPDDR4__DENALI_PI_247_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_247_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK                      0x00FFFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT                              0U
+#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH                             24U
+#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247
+#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2
+
+#define LPDDR4__DENALI_PI_248_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_248_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248
+#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2
+
+#define LPDDR4__DENALI_PI_249_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_249_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249
+#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2
+
+#define LPDDR4__DENALI_PI_250_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_PI_250_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK                     0x00FFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH                            24U
+#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250
+#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2
+
+#define LPDDR4__DENALI_PI_251_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_251_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT                              0U
+#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH                             16U
+#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251
+#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2
+
+#define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK                    0x0FFF0000U
+#define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT                           16U
+#define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH                           12U
+#define LPDDR4__PI_RESERVED49__REG DENALI_PI_251
+#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49
+
+#define LPDDR4__DENALI_PI_252_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_252_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT                            0U
+#define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH                           12U
+#define LPDDR4__PI_RESERVED50__REG DENALI_PI_252
+#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50
+
+#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT                            16U
+#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252
+#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0
+
+#define LPDDR4__DENALI_PI_253_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_253_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT                             0U
+#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253
+#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0
+
+#define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT                            8U
+#define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH                           12U
+#define LPDDR4__PI_RESERVED51__REG DENALI_PI_253
+#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51
+
+#define LPDDR4__DENALI_PI_254_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_254_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT                            0U
+#define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH                           12U
+#define LPDDR4__PI_RESERVED52__REG DENALI_PI_254
+#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52
+
+#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT                            16U
+#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254
+#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1
+
+#define LPDDR4__DENALI_PI_255_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_255_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255
+#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1
+
+#define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT                            8U
+#define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH                           12U
+#define LPDDR4__PI_RESERVED53__REG DENALI_PI_255
+#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53
+
+#define LPDDR4__DENALI_PI_256_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_256_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT                            0U
+#define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH                           12U
+#define LPDDR4__PI_RESERVED54__REG DENALI_PI_256
+#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54
+
+#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK                     0x0FFF0000U
+#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT                            16U
+#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH                            12U
+#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2
+
+#define LPDDR4__DENALI_PI_257_READ_MASK                              0x000FFF7FU
+#define LPDDR4__DENALI_PI_257_WRITE_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK                     0x0000007FU
+#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT                             0U
+#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH                             7U
+#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2
+
+#define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK                    0x000FFF00U
+#define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT                            8U
+#define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH                           12U
+#define LPDDR4__PI_RESERVED55__REG DENALI_PI_257
+#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55
+
+#define LPDDR4__DENALI_PI_258_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_258_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK                    0x00000FFFU
+#define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT                            0U
+#define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH                           12U
+#define LPDDR4__PI_RESERVED56__REG DENALI_PI_258
+#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56
+
+#define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK                    0x0FFF0000U
+#define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT                           16U
+#define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH                           12U
+#define LPDDR4__PI_RESERVED57__REG DENALI_PI_258
+#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57
+
+#define LPDDR4__DENALI_PI_259_READ_MASK                              0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_259_WRITE_MASK                             0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT                0U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0
+
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK        0x00000F00U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT                8U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1
+
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK        0x000F0000U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT               16U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH                4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2
+
+#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259
+#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0
+
+#define LPDDR4__DENALI_PI_260_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0
+
+#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT                           8U
+#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0
+
+#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT                          16U
+#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0
+
+#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT                          24U
+#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0
+
+#define LPDDR4__DENALI_PI_261_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_261_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT                           0U
+#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261
+#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0
+
+#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT                           8U
+#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261
+#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0
+
+#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261
+#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1
+
+#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261
+#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1
+
+#define LPDDR4__DENALI_PI_262_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1
+
+#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT                           8U
+#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1
+
+#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT                          16U
+#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1
+
+#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT                          24U
+#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1
+
+#define LPDDR4__DENALI_PI_263_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_263_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT                           0U
+#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263
+#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1
+
+#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT                           8U
+#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263
+#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2
+
+#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263
+#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2
+
+#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263
+#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2
+
+#define LPDDR4__DENALI_PI_264_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT                           0U
+#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2
+
+#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT                           8U
+#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2
+
+#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT                          16U
+#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2
+
+#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT                          24U
+#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2
+
+#define LPDDR4__DENALI_PI_265_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT                           0U
+#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3
+
+#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT                           8U
+#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3
+
+#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT                          16U
+#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3
+
+#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK                   0xFF000000U
+#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT                          24U
+#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3
+
+#define LPDDR4__DENALI_PI_266_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_266_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK                   0x000000FFU
+#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT                           0U
+#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266
+#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3
+
+#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT                           8U
+#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266
+#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3
+
+#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT                          16U
+#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH                           8U
+#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266
+#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3
+
+#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK                     0x0F000000U
+#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT                            24U
+#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH                             4U
+#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266
+#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0
+
+#define LPDDR4__DENALI_PI_267_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_267_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT                             0U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH                             4U
+#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267
+#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1
+
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK                     0x00000F00U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT                             8U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH                             4U
+#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267
+#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2
+
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK                     0x000F0000U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT                            16U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH                             4U
+#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267
+#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3
+
+#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK                      0x0F000000U
+#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT                             24U
+#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH                              4U
+#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267
+#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0
+
+#define LPDDR4__DENALI_PI_268_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_268_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK                      0x0000000FU
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT                              0U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH                              4U
+#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268
+#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1
+
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT                              8U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH                              4U
+#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268
+#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2
+
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK                      0x000F0000U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT                             16U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH                              4U
+#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268
+#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3
+
+#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK                 0x0F000000U
+#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT                        24U
+#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH                         4U
+#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268
+#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0
+
+#define LPDDR4__DENALI_PI_269_READ_MASK                              0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_269_WRITE_MASK                             0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK                 0x0000000FU
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH                         4U
+#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269
+#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1
+
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK                 0x00000F00U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT                         8U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH                         4U
+#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269
+#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2
+
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK                 0x000F0000U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT                        16U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH                         4U
+#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269
+#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3
+
+#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK               0xFF000000U
+#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT                      24U
+#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH                       8U
+#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269
+#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_PI_270_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_270_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK               0x000000FFU
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT                       0U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH                       8U
+#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270
+#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK               0x0000FF00U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT                       8U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH                       8U
+#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270
+#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2
+
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK               0x00FF0000U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT                      16U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH                       8U
+#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270
+#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3
+
+#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK            0x0F000000U
+#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT                   24U
+#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_PI_271_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_271_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT                    0U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK            0x000F0000U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT                   16U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK            0x0F000000U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT                   24U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2
+
+#define LPDDR4__DENALI_PI_272_READ_MASK                              0x000F0F0FU
+#define LPDDR4__DENALI_PI_272_WRITE_MASK                             0x000F0F0FU
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK            0x0000000FU
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT                    0U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2
+
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK            0x00000F00U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT                    8U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3
+
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK            0x000F0000U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT                   16U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH                    4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3
+
+#define LPDDR4__DENALI_PI_273_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_273_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT                0U
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0
+
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT               16U
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0
+
+#define LPDDR4__DENALI_PI_274_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_274_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT                0U
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1
+
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT               16U
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH               16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1
+
+#define LPDDR4__DENALI_PI_275_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_275_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT                         8U
+#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_276_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_277_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_277_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT                         8U
+#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_278_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_279_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_279_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT                         8U
+#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT                        16U
+#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_280_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT                        0U
+#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT                       16U
+#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_281_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_281_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_282_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_283_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_283_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_284_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_285_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_285_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT                         0U
+#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT                         8U
+#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT                        16U
+#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_286_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT                        8U
+#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT                       24U
+#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_287_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_287_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT                         8U
+#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_288_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_289_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT                         8U
+#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_290_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_291_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_291_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT                         0U
+#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT                         8U
+#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT                        16U
+#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_292_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT                        0U
+#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT                        8U
+#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT                       16U
+#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT                       24U
+#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_293_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_293_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT                         8U
+#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT                        16U
+#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_294_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT                        8U
+#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_295_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_295_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT                         8U
+#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT                        16U
+#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT                        8U
+#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_297_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_297_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK                 0x000000FFU
+#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT                         0U
+#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH                         8U
+#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT                         8U
+#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH                         8U
+#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT                        16U
+#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH                         8U
+#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_298_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK                0x000000FFU
+#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT                        0U
+#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK                0x0000FF00U
+#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT                        8U
+#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK                0x00FF0000U
+#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT                       16U
+#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK                0xFF000000U
+#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT                       24U
+#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH                        8U
+#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_299_READ_MASK                              0x000007FFU
+#define LPDDR4__DENALI_PI_299_WRITE_MASK                             0x000007FFU
+#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK            0x000007FFU
+#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT                    0U
+#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH                   11U
+#define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299
+#define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF
+
+#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
new file mode 100644
index 0000000000..8be00118f5
--- /dev/null
+++ b/drivers/ram/k3-ddrss/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+
+obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
+obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o
+obj-$(CONFIG_K3_DDRSS) += lpddr4.o
+ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
+
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
+
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
diff --git a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
new file mode 100644
index 0000000000..298aa5e6cb
--- /dev/null
+++ b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef CPS_DRV_H_
+#define CPS_DRV_H_
+
+#ifdef DEMO_TB
+#include <cdn_demo.h>
+#else
+#include <asm/io.h>
+#endif
+
+#define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg)))
+
+#define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value)))
+
+#define CPS_FLD_MASK(fld)  (fld ## _MASK)
+#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
+#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
+#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
+#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
+
+#define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)),  \
+						  (u32)(CPS_FLD_SHIFT(fld)), \
+						  (u32)(reg_value)))
+
+#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)),  \
+							   (u32)(CPS_FLD_SHIFT(fld)), \
+							   (u32)(reg_value), (u32)(value)))
+
+#define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \
+						(u32)(CPS_FLD_MASK(fld)),  \
+						(u32)(CPS_FLD_WOCLR(fld)), \
+						(u32)(reg_value)))
+
+#ifdef CLR_USED
+#define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \
+							 (u32)(CPS_FLD_MASK(fld)),  \
+							 (u32)(CPS_FLD_WOSET(fld)), \
+							 (u32)(CPS_FLD_WOCLR(fld)), \
+							 (u32)(reg_value)))
+
+#endif
+static inline u32 cps_regread(volatile u32 *reg);
+static inline u32 cps_regread(volatile u32 *reg)
+{
+	return readl(reg);
+}
+
+static inline void cps_regwrite(volatile u32 *reg, u32 value);
+static inline void cps_regwrite(volatile u32 *reg, u32 value)
+{
+	writel(value, reg);
+}
+
+static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
+static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value)
+{
+	u32 result = (reg_value & mask) >> shift;
+
+	return result;
+}
+
+static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value);
+static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value)
+{
+	u32 new_value = (value << shift) & mask;
+
+	new_value = (reg_value & ~mask) | new_value;
+	return new_value;
+}
+
+static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
+static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value)
+{
+	u32 new_value = reg_value;
+
+	if ((width == 1U) && (is_woclr == 0U))
+		new_value |= mask;
+
+	return new_value;
+}
+
+#ifdef CLR_USED
+static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
+static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value)
+{
+	u32 new_value = reg_value;
+
+	if ((width == 1U) && (is_woset == 0U))
+		new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
+
+	return new_value;
+}
+#endif /* CLR_USED */
+
+#endif /* CPS_DRV_H_ */
diff --git a/drivers/ram/k3-j721e/k3-j721e-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 9fb1eeea45..cb8edcbc15 100644
--- a/drivers/ram/k3-j721e/k3-j721e-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -1,20 +1,21 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Texas Instruments' J721E DDRSS driver
+ * Texas Instruments' K3 DDRSS driver
  *
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
  */
 
 #include <common.h>
 #include <clk.h>
 #include <dm.h>
+#include <dm/device_compat.h>
+#include <ram.h>
 #include <hang.h>
 #include <log.h>
-#include <ram.h>
 #include <asm/io.h>
 #include <power-domain.h>
 #include <wait_bit.h>
-#include <dm/device_compat.h>
+#include <power/regulator.h>
 
 #include "lpddr4_obj_if.h"
 #include "lpddr4_if.h"
@@ -26,7 +27,10 @@
 #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS	0x80
 #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS	0xc0
 
-struct j721e_ddrss_desc {
+#define DDRSS_V2A_R1_MAT_REG 			0x0020
+#define DDRSS_ECC_CTRL_REG 			0x0120
+
+struct k3_ddrss_desc {
 	struct udevice *dev;
 	void __iomem *ddrss_ss_cfg;
 	void __iomem *ddrss_ctrl_mmr;
@@ -37,13 +41,23 @@ struct j721e_ddrss_desc {
 	u32 ddr_freq1;
 	u32 ddr_freq2;
 	u32 ddr_fhs_cnt;
+	struct udevice *vtt_supply;
 };
 
-static LPDDR4_OBJ *driverdt;
+static lpddr4_obj *driverdt;
 static lpddr4_config config;
 static lpddr4_privatedata pd;
 
-static struct j721e_ddrss_desc *ddrss;
+static struct k3_ddrss_desc *ddrss;
+
+struct reginitdata {
+	u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
+	u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
+	u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
+	u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
+	u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
+	u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
+};
 
 #define TH_MACRO_EXP(fld, str) (fld##str)
 
@@ -56,21 +70,41 @@ static struct j721e_ddrss_desc *ddrss;
 #define str(s) #s
 #define xstr(s) str(s)
 
-#define  CTL_SHIFT 11
-#define  PHY_SHIFT 11
-#define  PI_SHIFT 10
+#define CTL_SHIFT 11
+#define PHY_SHIFT 11
+#define PI_SHIFT 10
+
+#define DENALI_CTL_0_DRAM_CLASS_DDR4		0xA
+#define DENALI_CTL_0_DRAM_CLASS_LPDDR4		0xB
 
 #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
-	char *i, *pstr= xstr(REG); offset = 0;\
+	char *i, *pstr = xstr(REG); offset = 0;\
 	for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
-		offset = offset * 10 + (*i - '0'); }\
+		offset = offset * 10 + (*i - '0'); } \
 	} while (0)
 
-static void j721e_lpddr4_ack_freq_upd_req(void)
+static u32 k3_lpddr4_read_ddr_type(void)
 {
-	unsigned int req_type, counter;
+	u32 status = 0U;
+	u32 offset = 0U;
+	u32 regval = 0U;
+	u32 dram_class = 0U;
 
-	debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
+	TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
+	status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
+	if (status > 0U) {
+		printf("%s: Failed to read DRAM_CLASS\n", __func__);
+		hang();
+	}
+
+	dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
+		TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
+	return dram_class;
+}
+
+static void k3_lpddr4_freq_update(void)
+{
+	unsigned int req_type, counter;
 
 	for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
 		if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
@@ -83,7 +117,7 @@ static void j721e_lpddr4_ack_freq_upd_req(void)
 		req_type = readl(ddrss->ddrss_ctrl_mmr +
 				 CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
 
-		debug("%s: received freq change req: req type = %d, req no. = %d \n",
+		debug("%s: received freq change req: req type = %d, req no. = %d\n",
 		      __func__, req_type, counter);
 
 		if (req_type == 1)
@@ -110,15 +144,62 @@ static void j721e_lpddr4_ack_freq_upd_req(void)
 	}
 }
 
-static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
-				      lpddr4_infotype infotype)
+static void k3_lpddr4_ack_freq_upd_req(void)
 {
-	if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
-		j721e_lpddr4_ack_freq_upd_req();
+	u32 dram_class;
+
+	debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
+
+	dram_class = k3_lpddr4_read_ddr_type();
+
+	switch (dram_class) {
+	case DENALI_CTL_0_DRAM_CLASS_DDR4:
+		break;
+	case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
+		k3_lpddr4_freq_update();
+		break;
+	default:
+		printf("Unrecognized dram_class cannot update frequency!\n");
 	}
 }
 
-static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
+static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
+{
+	u32 dram_class;
+	int ret;
+
+	dram_class = k3_lpddr4_read_ddr_type();
+
+	switch (dram_class) {
+	case DENALI_CTL_0_DRAM_CLASS_DDR4:
+		/* Set to ddr_freq1 from DT for DDR4 */
+		ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
+		break;
+	case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
+		/* Set to bypass frequency for LPDDR4*/
+		ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
+		break;
+	default:
+		ret = -EINVAL;
+		printf("Unrecognized dram_class cannot init frequency!\n");
+	}
+
+	if (ret < 0)
+		dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
+	else
+		ret = 0;
+
+	return ret;
+}
+
+static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
+				   lpddr4_infotype infotype)
+{
+	if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
+		k3_lpddr4_ack_freq_upd_req();
+}
+
+static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
 {
 	int ret;
 
@@ -136,12 +217,24 @@ static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
 		return ret;
 	}
 
+	ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
+					  &ddrss->vtt_supply);
+	if (ret) {
+		dev_dbg(ddrss->dev, "vtt-supply not found.\n");
+	} else {
+		ret = regulator_set_value(ddrss->vtt_supply, 3300000);
+		if (ret)
+			return ret;
+		dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
+			regulator_get_value(ddrss->vtt_supply));
+	}
+
 	return 0;
 }
 
-static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
+static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
 {
-	struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
+	struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
 	phys_addr_t reg;
 	int ret;
 
@@ -193,42 +286,37 @@ static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
 	if (ret)
 		dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
 
-	/* Put DDR pll in bypass mode */
-	ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
-	if (ret)
-		dev_err(dev, "ddr clk bypass failed\n");
-
 	return ret;
 }
 
-void j721e_lpddr4_probe(void)
+void k3_lpddr4_probe(void)
 {
-	uint32_t status = 0U;
-	uint16_t configsize = 0U;
+	u32 status = 0U;
+	u16 configsize = 0U;
 
 	status = driverdt->probe(&config, &configsize);
 
 	if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
 	    || (configsize > SRAM_MAX)) {
-		printf("LPDDR4_Probe: FAIL\n");
+		printf("%s: FAIL\n", __func__);
 		hang();
 	} else {
-		debug("LPDDR4_Probe: PASS\n");
+		debug("%s: PASS\n", __func__);
 	}
 }
 
-void j721e_lpddr4_init(void)
+void k3_lpddr4_init(void)
 {
-	uint32_t status = 0U;
+	u32 status = 0U;
 
 	if ((sizeof(pd) != sizeof(lpddr4_privatedata))
 	    || (sizeof(pd) > SRAM_MAX)) {
-		printf("LPDDR4_Init: FAIL\n");
+		printf("%s: FAIL\n", __func__);
 		hang();
 	}
 
 	config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
-	config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
+	config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
 
 	status = driverdt->init(&pd, &config);
 
@@ -236,140 +324,155 @@ void j721e_lpddr4_init(void)
 	    (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
 	    (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
 	    (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
-		printf("LPDDR4_Init: FAIL\n");
+		printf("%s: FAIL\n", __func__);
 		hang();
 	} else {
-		debug("LPDDR4_Init: PASS\n");
+		debug("%s: PASS\n", __func__);
 	}
 }
 
-void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
+void populate_data_array_from_dt(struct reginitdata *reginit_data)
 {
 	int ret, i;
 
 	ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
-				 (u32 *) reginit_data->denalictlreg,
-				 LPDDR4_CTL_REG_COUNT);
+				 (u32 *)reginit_data->ctl_regs,
+				 LPDDR4_INTR_CTL_REG_COUNT);
 	if (ret)
-		printf("Error reading ctrl data\n");
+		printf("Error reading ctrl data %d\n", ret);
 
-	for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
-		reginit_data->updatectlreg[i] = true;
+	for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
+		reginit_data->ctl_regs_offs[i] = i;
 
 	ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
-				 (u32 *) reginit_data->denaliphyindepreg,
-				 LPDDR4_PHY_INDEP_REG_COUNT);
+				 (u32 *)reginit_data->pi_regs,
+				 LPDDR4_INTR_PHY_INDEP_REG_COUNT);
 	if (ret)
 		printf("Error reading PI data\n");
 
-	for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
-		reginit_data->updatephyindepreg[i] = true;
+	for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+		reginit_data->pi_regs_offs[i] = i;
 
 	ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
-				 (u32 *) reginit_data->denaliphyreg,
-				 LPDDR4_PHY_REG_COUNT);
+				 (u32 *)reginit_data->phy_regs,
+				 LPDDR4_INTR_PHY_REG_COUNT);
 	if (ret)
-		printf("Error reading PHY data\n");
+		printf("Error reading PHY data %d\n", ret);
 
-	for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
-		reginit_data->updatephyreg[i] = true;
+	for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
+		reginit_data->phy_regs_offs[i] = i;
 }
 
-void j721e_lpddr4_hardware_reg_init(void)
+void k3_lpddr4_hardware_reg_init(void)
 {
-	uint32_t status = 0U;
-	lpddr4_reginitdata reginitdata;
+	u32 status = 0U;
+	struct reginitdata reginitdata;
 
 	populate_data_array_from_dt(&reginitdata);
 
-	status = driverdt->writectlconfig(&pd, &reginitdata);
-	if (!status) {
-		status = driverdt->writephyindepconfig(&pd, &reginitdata);
-	}
-	if (!status) {
-		status = driverdt->writephyconfig(&pd, &reginitdata);
-	}
+	status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs,
+					  reginitdata.ctl_regs_offs,
+					  LPDDR4_INTR_CTL_REG_COUNT);
+	if (!status)
+		status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs,
+						       reginitdata.pi_regs_offs,
+						       LPDDR4_INTR_PHY_INDEP_REG_COUNT);
+	if (!status)
+		status = driverdt->writephyconfig(&pd, reginitdata.phy_regs,
+						  reginitdata.phy_regs_offs,
+						  LPDDR4_INTR_PHY_REG_COUNT);
 	if (status) {
-		printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
+		printf("%s: FAIL\n", __func__);
 		hang();
 	}
-
-	return;
 }
 
-void j721e_lpddr4_start(void)
+void k3_lpddr4_start(void)
 {
-	uint32_t status = 0U;
-	uint32_t regval = 0U;
-	uint32_t offset = 0U;
+	u32 status = 0U;
+	u32 regval = 0U;
+	u32 offset = 0U;
 
 	TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
 
 	status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 	if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
-		printf("LPDDR4_StartTest: FAIL\n");
+		printf("%s: Pre start FAIL\n", __func__);
 		hang();
 	}
 
 	status = driverdt->start(&pd);
 	if (status > 0U) {
-		printf("LPDDR4_StartTest: FAIL\n");
+		printf("%s: FAIL\n", __func__);
 		hang();
 	}
 
 	status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, &regval);
 	if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
-		printf("LPDDR4_Start: FAIL\n");
+		printf("%s: Post start FAIL\n", __func__);
 		hang();
 	} else {
-		debug("LPDDR4_Start: PASS\n");
+		debug("%s: Post start PASS\n", __func__);
 	}
 }
 
-static int j721e_ddrss_probe(struct udevice *dev)
+static int k3_ddrss_probe(struct udevice *dev)
 {
 	int ret;
+
 	ddrss = dev_get_priv(dev);
 
 	debug("%s(dev=%p)\n", __func__, dev);
 
-	ret = j721e_ddrss_ofdata_to_priv(dev);
+	ret = k3_ddrss_ofdata_to_priv(dev);
 	if (ret)
 		return ret;
 
 	ddrss->dev = dev;
-	ret = j721e_ddrss_power_on(ddrss);
+	ret = k3_ddrss_power_on(ddrss);
 	if (ret)
 		return ret;
 
+#ifdef CONFIG_K3_AM64_DDRSS
+
+	writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
+	writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
+#endif
+
 	driverdt = lpddr4_getinstance();
-	j721e_lpddr4_probe();
-	j721e_lpddr4_init();
-	j721e_lpddr4_hardware_reg_init();
-	j721e_lpddr4_start();
+	k3_lpddr4_probe();
+	k3_lpddr4_init();
+	k3_lpddr4_hardware_reg_init();
+
+	ret = k3_ddrss_init_freq(ddrss);
+	if (ret)
+		return ret;
+
+	k3_lpddr4_start();
 
 	return ret;
 }
 
-static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
+static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
 {
 	return 0;
 }
 
-static struct ram_ops j721e_ddrss_ops = {
-	.get_info = j721e_ddrss_get_info,
+static struct ram_ops k3_ddrss_ops = {
+	.get_info = k3_ddrss_get_info,
 };
 
-static const struct udevice_id j721e_ddrss_ids[] = {
+static const struct udevice_id k3_ddrss_ids[] = {
+	{.compatible = "ti,am64-ddrss"},
 	{.compatible = "ti,j721e-ddrss"},
 	{}
 };
 
-U_BOOT_DRIVER(j721e_ddrss) = {
-	.name = "j721e_ddrss",
-	.id = UCLASS_RAM,
-	.of_match = j721e_ddrss_ids,
-	.ops = &j721e_ddrss_ops,
-	.probe = j721e_ddrss_probe,
-	.priv_auto	= sizeof(struct j721e_ddrss_desc),
+U_BOOT_DRIVER(k3_ddrss) = {
+	.name			= "k3_ddrss",
+	.id			= UCLASS_RAM,
+	.of_match		= k3_ddrss_ids,
+	.ops			= &k3_ddrss_ops,
+	.probe			= k3_ddrss_probe,
+	.priv_auto		= sizeof(struct k3_ddrss_desc),
 };
diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c
new file mode 100644
index 0000000000..78ad966a17
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4.c
@@ -0,0 +1,1079 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <errno.h>
+
+#include "cps_drv_lpddr4.h"
+#include "lpddr4_if.h"
+#include "lpddr4.h"
+#include "lpddr4_structs_if.h"
+
+#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
+#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
+#endif
+
+#ifndef LPDDR4_CPS_NS_DELAY_TIME
+#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
+#endif
+
+static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
+static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
+static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
+static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval);
+static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits);
+static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
+static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
+static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
+static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
+static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
+static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
+#ifdef REG_WRITE_VERIF
+static u32 lpddr4_getphyrwmask(u32 regoffset);
+static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
+#endif
+
+u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
+{
+	u32 result = 0U;
+	u32 timeout = 0U;
+	bool irqstatus = false;
+
+	do {
+		if (++timeout == delay) {
+			result = (u32)EIO;
+			break;
+		}
+		result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
+	} while ((irqstatus == (bool)false) && (result == (u32)0));
+
+	return result;
+}
+
+static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay)
+{
+	u32 result = 0U;
+	u32 timeout = 0U;
+	bool irqstatus = false;
+
+	do {
+		if (++timeout == delay) {
+			result = (u32)EIO;
+			break;
+		}
+		result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
+	} while ((irqstatus == (bool)false) && (result == (u32)0));
+
+	return result;
+}
+
+static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd)
+{
+	u32 result = 0U;
+
+	result = lpddr4_pollphyindepirq(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT, LPDDR4_CUSTOM_TIMEOUT_DELAY);
+
+	if (result == (u32)0)
+		result = lpddr4_ackphyindepinterrupt(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT);
+	if (result == (u32)0)
+		result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MC_INIT_DONE, LPDDR4_CUSTOM_TIMEOUT_DELAY);
+	if (result == (u32)0)
+		result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MC_INIT_DONE);
+	return result;
+}
+
+static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+	lpddr4_infotype infotype;
+
+	regval = CPS_FLD_SET(LPDDR4__PI_START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
+	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
+
+	regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
+
+	if (pd->infohandler != (lpddr4_infocallback)NULL) {
+		infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
+		pd->infohandler(pd, infotype);
+	}
+
+	result = lpddr4_pollandackirq(pd);
+
+	return result;
+}
+
+volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset)
+{
+	volatile u32 *local_addr = addr;
+	volatile u32 *regaddr = &local_addr[regoffset];
+
+	return regaddr;
+}
+
+u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize)
+{
+	u32 result;
+
+	result = (u32)(lpddr4_probesf(config, configsize));
+	if (result == (u32)0)
+		*configsize = (u16)(sizeof(lpddr4_privatedata));
+	return result;
+}
+
+u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg)
+{
+	u32 result = 0U;
+
+	result = lpddr4_initsf(pd, cfg);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)cfg->ctlbase;
+		pd->ctlbase = ctlregbase;
+		pd->infohandler = (lpddr4_infocallback)cfg->infohandler;
+		pd->ctlinterrupthandler = (lpddr4_ctlcallback)cfg->ctlinterrupthandler;
+		pd->phyindepinterrupthandler = (lpddr4_phyindepcallback)cfg->phyindepinterrupthandler;
+	}
+	return result;
+}
+
+u32 lpddr4_start(const lpddr4_privatedata *pd)
+{
+	u32 result = 0U;
+
+	result = lpddr4_startsf(pd);
+	if (result == (u32)0) {
+		result = lpddr4_enablepiinitiator(pd);
+		result = lpddr4_startsequencecontroller(pd);
+	}
+	return result;
+}
+
+u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue)
+{
+	u32 result = 0U;
+
+	result = lpddr4_readregsf(pd, cpp, regvalue);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		if (cpp == LPDDR4_CTL_REGS) {
+			if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
+				result = (u32)EINVAL;
+			else
+				*regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset));
+		} else if (cpp == LPDDR4_PHY_REGS) {
+			if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
+				result = (u32)EINVAL;
+			else
+				*regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset));
+
+		} else {
+			if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
+				result = (u32)EINVAL;
+			else
+				*regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset));
+		}
+	}
+	return result;
+}
+
+#ifdef REG_WRITE_VERIF
+
+static u32 lpddr4_getphyrwmask(u32 regoffset)
+{
+	u32 rwmask = 0U;
+	u32 arrayoffset = 0U;
+	u32 slicenum, sliceoffset = 0U;
+
+	for (slicenum = (u32)0U; slicenum <= (DSLICE_NUM + ASLICE_NUM); slicenum++) {
+		sliceoffset = sliceoffset + (u32)SLICE_WIDTH;
+		if (regoffset < sliceoffset)
+			break;
+	}
+	arrayoffset = regoffset - (sliceoffset - (u32)SLICE_WIDTH);
+
+	if (slicenum < DSLICE_NUM) {
+		rwmask = lpddr4_getdslicemask(slicenum, arrayoffset);
+	} else {
+		if (slicenum == DSLICE_NUM) {
+			if (arrayoffset < ASLICE0_REG_COUNT)
+				rwmask = g_lpddr4_address_slice_0_rw_mask[arrayoffset];
+		} else {
+			if (arrayoffset < PHY_CORE_REG_COUNT)
+				rwmask = g_lpddr4_phy_core_rw_mask[arrayoffset];
+		}
+	}
+	return rwmask;
+}
+
+static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
+{
+	u32 result = (u32)0;
+	u32 regreadval = 0U;
+	u32 rwmask = 0U;
+
+	result = lpddr4_readreg(pd, cpp, regoffset, &regreadval);
+
+	if (result == (u32)0) {
+		switch (cpp) {
+		case LPDDR4_PHY_INDEP_REGS:
+			rwmask = g_lpddr4_pi_rw_mask[regoffset];
+			break;
+		case LPDDR4_PHY_REGS:
+			rwmask = lpddr4_getphyrwmask(regoffset);
+			break;
+		default:
+			rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset];
+			break;
+		}
+
+		if ((rwmask & regreadval) != (regvalue & rwmask))
+			result = EIO;
+	}
+	return result;
+}
+#endif
+
+u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
+{
+	u32 result = 0U;
+
+	result = lpddr4_writeregsf(pd, cpp);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		if (cpp == LPDDR4_CTL_REGS) {
+			if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
+				result = (u32)EINVAL;
+			else
+				CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset), regvalue);
+		} else if (cpp == LPDDR4_PHY_REGS) {
+			if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
+				result = (u32)EINVAL;
+			else
+				CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset), regvalue);
+		} else {
+			if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
+				result = (u32)EINVAL;
+			else
+				CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
+		}
+	}
+#ifdef REG_WRITE_VERIF
+	if (result == (u32)0)
+		result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue);
+
+#endif
+
+	return result;
+}
+
+u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus)
+{
+	u32 result = 0U;
+	u32 tdelay = 1000U;
+	u32 regval = 0U;
+
+	result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		regval = CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__READ_MODEREG__REG)), readmoderegval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
+
+		result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_READ_DONE, tdelay);
+	}
+	if (result == (u32)0)
+		result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
+	return result;
+}
+
+static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval)
+{
+	u32 result = (u32)0;
+	u32 tdelay = 1000U;
+	u32 regval = 0U;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+	regval = CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG)), writemoderegval);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
+
+	result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_WRITE_DONE, tdelay);
+
+	return result;
+}
+
+u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus)
+{
+	u32 result = 0U;
+
+	result = lpddr4_setmmrregistersf(pd, mrwstatus);
+	if (result == (u32)0) {
+		result = lpddr4_writemmrregister(pd, writemoderegval);
+
+		if (result == (u32)0)
+			result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_WRITE_DONE);
+		if (result == (u32)0) {
+			lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+			*mrwstatus = (u8)CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRW_STATUS__REG)));
+			if ((*mrwstatus) != 0U)
+				result = (u32)EIO;
+		}
+	}
+
+#ifdef ASILC
+#endif
+
+	return result;
+}
+
+u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+	u32 result;
+	u32 aindex;
+
+	result = lpddr4_writectlconfigsf(pd);
+	if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+		result = EINVAL;
+
+	if (result == (u32)0) {
+		for (aindex = 0; aindex < regcount; aindex++)
+			result = (u32)lpddr4_writereg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
+							   (u32)regvalues[aindex]);
+	}
+	return result;
+}
+
+u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+	u32 result;
+	u32 aindex;
+
+	result = lpddr4_writephyindepconfigsf(pd);
+	if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+		result = EINVAL;
+	if (result == (u32)0) {
+		for (aindex = 0; aindex < regcount; aindex++)
+			result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
+							   (u32)regvalues[aindex]);
+	}
+	return result;
+}
+
+u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+	u32 result;
+	u32 aindex;
+
+	result = lpddr4_writephyconfigsf(pd);
+	if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+		result = EINVAL;
+	if (result == (u32)0) {
+		for (aindex = 0; aindex < regcount; aindex++)
+			result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
+							   (u32)regvalues[aindex]);
+	}
+	return result;
+}
+
+u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+	u32 result;
+	u32 aindex;
+
+	result = lpddr4_readctlconfigsf(pd);
+	if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+		result = EINVAL;
+	if (result == (u32)0) {
+		for (aindex = 0; aindex < regcount; aindex++)
+			result = (u32)lpddr4_readreg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
+							  (u32 *)(&regvalues[aindex]));
+	}
+	return result;
+}
+
+u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+	u32 result;
+	u32 aindex;
+
+	result = lpddr4_readphyindepconfigsf(pd);
+	if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+		result = EINVAL;
+	if (result == (u32)0) {
+		for (aindex = 0; aindex < regcount; aindex++)
+			result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
+							  (u32 *)(&regvalues[aindex]));
+	}
+	return result;
+}
+
+u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+	u32 result;
+	u32 aindex;
+
+	result = lpddr4_readphyconfigsf(pd);
+	if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+		result = EINVAL;
+	if (result == (u32)0) {
+		for (aindex = 0; aindex < regcount; aindex++)
+			result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
+							  (u32 *)(&regvalues[aindex]));
+	}
+	return result;
+}
+
+u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask)
+{
+	u32 result;
+
+	result = lpddr4_getphyindepinterruptmsf(pd, mask);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		*mask = CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)));
+	}
+	return result;
+}
+
+u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask)
+{
+	u32 result;
+	u32 regval = 0;
+	const u32 ui32irqcount = (u32)LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
+
+	result = lpddr4_setphyindepinterruptmsf(pd, mask);
+	if ((result == (u32)0) && (ui32irqcount < WORD_SHIFT)) {
+		if (*mask >= (1U << ui32irqcount))
+			result = (u32)EINVAL;
+	}
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		regval = CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)), *mask);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
+	}
+	return result;
+}
+
+u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus)
+{
+	u32 result = 0;
+	u32 phyindepirqstatus = 0;
+
+	result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus);
+	if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
+		*irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U);
+	}
+	return result;
+}
+
+u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	result = LPDDR4_INTR_AckPhyIndepIntSF(pd, intr);
+	if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		regval = ((u32)LPDDR4_BIT_MASK << (u32)intr);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
+	}
+
+	return result;
+}
+
+static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+	u32 regval;
+	u32 errbitmask = 0U;
+	u32 snum;
+	volatile u32 *regaddress;
+
+	regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
+	errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
+	for (snum = 0U; snum < ASLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != CA_TRAIN_RL) {
+			debuginfo->catraingerror = CDN_TRUE;
+			*errfoundptr = true;
+		}
+		regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+	}
+}
+
+static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+	u32 regval;
+	u32 errbitmask = 0U;
+	u32 snum;
+	volatile u32 *regaddress;
+
+	regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
+	errbitmask = GATE_LVL_ERROR_FIELDS;
+	for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->gatelvlerror = CDN_TRUE;
+			*errfoundptr = true;
+		}
+		regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+	}
+}
+
+static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+	u32 regval;
+	u32 errbitmask = 0U;
+	u32 snum;
+	volatile u32 *regaddress;
+
+	regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
+	errbitmask = READ_LVL_ERROR_FIELDS;
+	for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->readlvlerror = CDN_TRUE;
+			*errfoundptr = true;
+		}
+		regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+	}
+}
+
+static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+	u32 regval;
+	u32 errbitmask = 0U;
+	u32 snum;
+	volatile u32 *regaddress;
+
+	regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
+	errbitmask = DQ_LVL_STATUS;
+	for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->dqtrainingerror = CDN_TRUE;
+			*errfoundptr = true;
+		}
+		regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+	}
+}
+
+bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound)
+{
+	bool localerrfound = errfound;
+
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+	if (localerrfound == (bool)false)
+		lpddr4_checkcatrainingerror(ctlregbase, debuginfo, &localerrfound);
+
+	if (localerrfound == (bool)false)
+		lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
+
+	if (localerrfound == (bool)false)
+		lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
+
+	if (localerrfound == (bool)false)
+		lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
+
+	if (localerrfound == (bool)false)
+		lpddr4_checkdqtrainingerror(ctlregbase, debuginfo, &localerrfound);
+	return localerrfound;
+}
+
+static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits)
+{
+	u32 regval = 0U;
+
+	regval = CPS_REG_READ(reg);
+	if ((regval & errbitmask) != errorinfobits)
+		*errfoundptr = CDN_TRUE;
+	return *errfoundptr;
+}
+
+void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr)
+{
+	u32 errbitmask = (LPDDR4_BIT_MASK << 0x1U) | (LPDDR4_BIT_MASK);
+
+	debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
+					      errbitmask, errfoundptr, PLL_READY);
+	if (*errfoundptr == CDN_FALSE)
+		debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
+						      errbitmask, errfoundptr, PLL_READY);
+
+	if (*errfoundptr == CDN_FALSE)
+		debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
+							  IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
+	if (*errfoundptr == CDN_FALSE)
+		debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
+							  IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
+	if (*errfoundptr == CDN_FALSE)
+		debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
+							  IO_CALIB_FIELD, errfoundptr, IO_CALIB_STATE);
+}
+
+static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
+{
+	u32 snum = 0U;
+	volatile u32 *regaddress;
+	u32 regval = 0U;
+
+	if (errorfound == (bool)false) {
+		regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
+		for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+			regval = CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
+			CPS_REG_WRITE(regaddress, regval);
+			regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+		}
+	}
+}
+
+static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
+{
+	u32 snum = 0U;
+	volatile u32 *regaddress;
+	u32 regval = 0U;
+
+	if (errorfound == (bool)false) {
+		regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
+		for (snum = (u32)0U; snum < ASLICE_NUM; snum++) {
+			regval = CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
+			CPS_REG_WRITE(regaddress, regval);
+			regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+		}
+	}
+}
+
+void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
+{
+	lpddr4_setphysnapsettings(ctlregbase, errorfound);
+	lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
+}
+
+static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+	if (*fspnum == LPDDR4_FSP_0)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)));
+	else if (*fspnum == LPDDR4_FSP_1)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)));
+	else
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)));
+}
+
+static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+	if (*fspnum == LPDDR4_FSP_0)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
+	else if (*fspnum == LPDDR4_FSP_1)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
+	else
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
+}
+
+static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+	if (*fspnum == LPDDR4_FSP_0)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
+	else if (*fspnum == LPDDR4_FSP_1)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
+	else
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
+}
+
+static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+	if (*fspnum == LPDDR4_FSP_0)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
+	else if (*fspnum == LPDDR4_FSP_1)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
+	else
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
+}
+
+static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+	if (*fspnum == LPDDR4_FSP_0)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
+	else if (*fspnum == LPDDR4_FSP_1)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
+	else
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
+}
+
+static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+	if (*fspnum == LPDDR4_FSP_0)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
+	else if (*fspnum == LPDDR4_FSP_1)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
+	else
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
+}
+
+static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+	if (*fspnum == LPDDR4_FSP_0)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
+	else if (*fspnum == LPDDR4_FSP_1)
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
+	else
+		*cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
+
+}
+
+static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
+{
+	if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
+		readpdwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
+		readsrshortwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
+		readsrlongwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
+		readsrlonggatewakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
+		readsrdpshortwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
+		readsrdplongwakeup(fspnum, ctlregbase, cycles);
+	else
+		readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
+}
+
+u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
+{
+	u32 result = 0U;
+
+	result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
+	}
+	return result;
+}
+
+static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+	u32 regval = 0U;
+
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), regval);
+	} else {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+	u32 regval = 0U;
+
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG), regval);
+	} else {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+	u32 regval = 0U;
+
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), regval);
+	} else {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+	u32 regval = 0U;
+
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
+	} else {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+	u32 regval = 0U;
+
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
+	} else {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+	u32 regval = 0U;
+
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
+	} else {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
+	}
+}
+static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+	u32 regval = 0U;
+
+	if (*fspnum == LPDDR4_FSP_0) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
+	} else if (*fspnum == LPDDR4_FSP_1) {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
+	} else {
+		regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
+	}
+}
+
+static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
+{
+	if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
+		writepdwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
+		writesrshortwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
+		writesrlongwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
+		writesrlonggatewakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
+		writesrdpshortwakeup(fspnum, ctlregbase, cycles);
+	else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
+		writesrdplongwakeup(fspnum, ctlregbase, cycles);
+	else
+		writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
+}
+
+u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
+{
+	u32 result = 0U;
+
+	result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
+	if (result == (u32)0) {
+		if (*cycles > NIBBLE_MASK)
+			result = (u32)EINVAL;
+	}
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
+	}
+	return result;
+}
+
+u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off)
+{
+	u32 result = 0U;
+
+	result = lpddr4_getdbireadmodesf(pd, on_off);
+
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		if (CPS_FLD_READ(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) == 0U)
+			*on_off = false;
+		else
+			*on_off = true;
+	}
+	return result;
+}
+
+u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off)
+{
+	u32 result = 0U;
+
+	result = lpddr4_getdbireadmodesf(pd, on_off);
+
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		if (CPS_FLD_READ(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) == 0U)
+			*on_off = false;
+		else
+			*on_off = true;
+	}
+	return result;
+}
+
+u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	result = lpddr4_setdbimodesf(pd, mode);
+
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		if (*mode == LPDDR4_DBI_RD_ON)
+			regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 1U);
+		else if (*mode == LPDDR4_DBI_RD_OFF)
+			regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 0U);
+		else if (*mode == LPDDR4_DBI_WR_ON)
+			regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 1U);
+		else
+			regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 0U);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
+	}
+	return result;
+}
+
+u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max)
+{
+	u32 result = 0U;
+
+	result = lpddr4_getrefreshratesf(pd, fspnum, tref, tras_max);
+
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		switch (*fspnum) {
+		case LPDDR4_FSP_2:
+			*tref = CPS_FLD_READ(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)));
+			*tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)));
+			break;
+		case LPDDR4_FSP_1:
+			*tref = CPS_FLD_READ(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)));
+			*tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)));
+			break;
+		default:
+			*tref = CPS_FLD_READ(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)));
+			*tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)));
+			break;
+		}
+	}
+	return result;
+}
+
+static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
+{
+	u32 regval = 0U;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+	regval = CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)), *tref);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), regval);
+	regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)), *tras_max);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG), regval);
+}
+
+static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
+{
+	u32 regval = 0U;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+	regval = CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)), *tref);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), regval);
+	regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)), *tras_max);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG), regval);;
+}
+
+static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
+{
+	u32 regval = 0U;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+	regval = CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)), *tref);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), regval);
+	regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)), *tras_max);
+	CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG), regval);
+}
+
+u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+{
+	u32 result = 0U;
+
+	result = lpddr4_setrefreshratesf(pd, fspnum, tref, tras_max);
+
+	if (result == (u32)0) {
+		switch (*fspnum) {
+		case LPDDR4_FSP_2:
+			lpddr4_updatefsp2refrateparams(pd, tref, tras_max);
+			break;
+		case LPDDR4_FSP_1:
+			lpddr4_updatefsp1refrateparams(pd, tref, tras_max);
+			break;
+		default:
+			lpddr4_updatefsp0refrateparams(pd, tref, tras_max);
+			break;
+		}
+	}
+	return result;
+}
+
+u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	result = lpddr4_refreshperchipselectsf(pd);
+
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		regval = CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG)), trefinterval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), regval);
+	}
+	return result;
+}
diff --git a/drivers/ram/k3-ddrss/lpddr4.h b/drivers/ram/k3-ddrss/lpddr4.h
new file mode 100644
index 0000000000..5b77ea9e6e
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_H
+#define LPDDR4_H
+
+#include "lpddr4_ctl_regs.h"
+#include "lpddr4_sanity.h"
+#ifdef CONFIG_K3_AM64_DDRSS
+#include "lpddr4_16bit.h"
+#include "lpddr4_16bit_sanity.h"
+#else
+#include "lpddr4_32bit.h"
+#include "lpddr4_32bit_sanity.h"
+#endif
+
+#ifdef REG_WRITE_VERIF
+#include "lpddr4_ctl_regs_rw_masks.h"
+#endif
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PRODUCT_ID (0x1046U)
+
+#define LPDDR4_BIT_MASK    (0x1U)
+#define BYTE_MASK   (0xffU)
+#define NIBBLE_MASK (0xfU)
+
+#define WORD_SHIFT (32U)
+#define WORD_MASK (0xffffffffU)
+#define SLICE_WIDTH (0x100)
+
+#define CTL_OFFSET 0
+#define PI_OFFSET (((u32)1) << 11)
+#define PHY_OFFSET (((u32)1) << 12)
+
+#define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT)
+
+#define PLL_READY (0x3U)
+#define IO_CALIB_DONE ((u32)0x1U << 23U)
+#define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U)
+#define IO_CALIB_STATE ((u32)0xBU << 28U)
+#define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U)
+#define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U))
+#define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U)
+#define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U))
+#define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U))
+#define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U))
+
+#define CDN_TRUE  1U
+#define CDN_FALSE 0U
+
+void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
+volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
+u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
+bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound);
+void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr);
+
+u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
+void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
+u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* LPDDR4_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.c b/drivers/ram/k3-ddrss/lpddr4_16bit.c
new file mode 100644
index 0000000000..b749b74897
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <errno.h>
+
+#include "cps_drv_lpddr4.h"
+#include "lpddr4_ctl_regs.h"
+#include "lpddr4_if.h"
+#include "lpddr4.h"
+#include "lpddr4_structs_if.h"
+
+static u32 ctlintmap[51][3] = {
+	{ 0,  0,  7  },
+	{ 1,  0,  8  },
+	{ 2,  0,  9  },
+	{ 3,  0,  14 },
+	{ 4,  0,  15 },
+	{ 5,  0,  16 },
+	{ 6,  0,  17 },
+	{ 7,  0,  19 },
+	{ 8,  1,  0  },
+	{ 9,  2,  0  },
+	{ 10, 2,  3  },
+	{ 11, 3,  0  },
+	{ 12, 4,  0  },
+	{ 13, 5,  11 },
+	{ 14, 5,  12 },
+	{ 15, 5,  13 },
+	{ 16, 5,  14 },
+	{ 17, 5,  15 },
+	{ 18, 6,  0  },
+	{ 19, 6,  1  },
+	{ 20, 6,  2  },
+	{ 21, 6,  6  },
+	{ 22, 6,  7  },
+	{ 23, 7,  3  },
+	{ 24, 7,  4  },
+	{ 25, 7,  5  },
+	{ 26, 7,  6  },
+	{ 27, 7,  7  },
+	{ 28, 8,  0  },
+	{ 29, 9,  0  },
+	{ 30, 10, 0  },
+	{ 31, 10, 1  },
+	{ 32, 10, 2  },
+	{ 33, 10, 3  },
+	{ 34, 10, 4  },
+	{ 35, 10, 5  },
+	{ 36, 11, 0  },
+	{ 37, 12, 0  },
+	{ 38, 12, 1  },
+	{ 39, 12, 2  },
+	{ 40, 12, 3  },
+	{ 41, 12, 4  },
+	{ 42, 12, 5  },
+	{ 43, 13, 0  },
+	{ 44, 13, 1  },
+	{ 45, 13, 3  },
+	{ 46, 14, 0  },
+	{ 47, 14, 2  },
+	{ 48, 14, 3  },
+	{ 49, 15, 2  },
+	{ 50, 16, 0  },
+};
+
+static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
+static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
+static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
+static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
+static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
+static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
+
+u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+	regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)));
+	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
+	regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
+	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
+	return result;
+}
+
+u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
+{
+	u32 result = 0U;
+
+	result = lpddr4_getctlinterruptmasksf(pd, mask);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG))));
+	}
+	return result;
+}
+
+u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
+{
+	u32 result;
+	u32 regval = 0;
+	const u64 ui64one = 1ULL;
+	const u32 ui32irqcount = (u32)32U;
+
+	result = lpddr4_setctlinterruptmasksf(pd, mask);
+	if ((result == (u32)0) && (ui32irqcount < 64U)) {
+		if (*mask >= (ui64one << ui32irqcount))
+			result = (u32)EINVAL;
+	}
+
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)), *mask);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval);
+	}
+	return result;
+}
+
+static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
+				       u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
+{
+	if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE))
+		*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_INIT__REG)));
+	else if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE))
+		*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG));
+	else if (intr == LPDDR4_INTR_BIST_DONE)
+		*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_BIST__REG)));
+	else if (intr == LPDDR4_INTR_PARITY_ERROR)
+		*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_PARITY__REG)));
+	else
+		*ctlmasterintflag = (u32)1U;
+}
+
+static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
+				       u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
+{
+	if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE))
+		*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_FREQ__REG)));
+	else if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT))
+		*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_LOWPOWER__REG)));
+	else
+		lpddr4_checkctlinterrupt_4(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
+}
+
+static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
+				       u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
+{
+	if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
+		*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG));
+	else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
+		*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG));
+	else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
+		*ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG));
+	else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
+		*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_MISC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MISC__REG)));
+	else if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT))
+		*ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_DFI__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_DFI__REG)));
+	else
+		lpddr4_checkctlinterrupt_3(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
+}
+
+u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
+{
+	u32 result;
+	u32 ctlmasterirqstatus = 0U;
+	u32 ctlgrpirqstatus = 0U;
+	u32 ctlmasterintflag = 0U;
+
+	result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 31)));
+
+		lpddr4_checkctlinterrupt_2(ctlregbase, intr, &ctlgrpirqstatus, &ctlmasterintflag);
+
+		if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) {
+			if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
+			    (((ctlgrpirqstatus >> ctlintmap[intr][INT_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
+			    (ctlmasterintflag == (u32)0))
+				*irqstatus = true;
+			else if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
+				 (ctlmasterintflag == (u32)1U))
+				*irqstatus = true;
+			else
+				*irqstatus = false;
+		}
+	}
+	return result;
+}
+
+static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
+{
+	u32 regval = 0;
+
+	if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
+	} else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG)),
+				       (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval);
+	} else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG)),
+				       (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval);
+	} else {
+	}
+}
+
+static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
+{
+	u32 regval = 0;
+
+	if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG)),
+				       (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval);
+	} else if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG)),
+				       (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval);
+	} else {
+		lpddr4_ackctlinterrupt_4(ctlregbase, intr);
+	}
+}
+
+static void  lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
+{
+	u32 regval = 0;
+
+	if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_DFI__REG), (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+	} else if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG)),
+				       (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval);
+	} else {
+		lpddr4_ackctlinterrupt_3(ctlregbase, intr);
+	}
+}
+
+u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
+{
+	u32 result;
+
+	result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
+	if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TIMEOUT__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+		else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TRAINING__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+		else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_USERIF__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+		else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+		else
+			lpddr4_ackctlinterrupt_2(ctlregbase, intr);
+	}
+
+	return result;
+}
+
+void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+	u32 regval;
+	u32 errbitmask = 0U;
+	u32 snum;
+	volatile u32 *regaddress;
+
+	regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG));
+	errbitmask = ((u32)LPDDR4_BIT_MASK << (u32)12U);
+	for (snum = 0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->wrlvlerror = CDN_TRUE;
+			*errfoundptr = true;
+		}
+		regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+	}
+}
+
+u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
+{
+	u32 result = 0U;
+	bool errorfound = false;
+
+	result = lpddr4_getdebuginitinfosf(pd, debuginfo);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
+		lpddr4_setsettings(ctlregbase, errorfound);
+		errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
+	}
+
+	if (errorfound == (bool)true)
+		result = (u32)EPROTO;
+
+	return result;
+}
+
+u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
+{
+	u32 result = 0U;
+
+	result = lpddr4_getreducmodesf(pd, mode);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		if (CPS_FLD_READ(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG))) == 0U)
+			*mode = LPDDR4_REDUC_ON;
+		else
+			*mode = LPDDR4_REDUC_OFF;
+	}
+	return result;
+}
+
+u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	result = lpddr4_setreducmodesf(pd, mode);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		regval = (u32)CPS_FLD_WRITE(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG)), *mode);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG), regval);
+	}
+	return result;
+}
+
+u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
+{
+	u32 lowerdata;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+	u32 result = (u32)0;
+
+	if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
+		*mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
+		*mmrvalue = (u64)0;
+		result = (u32)EIO;
+	} else {
+		*mrrstatus = (u8)0;
+		lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
+		*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
+		result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
+	}
+	return result;
+}
+
+#ifdef REG_WRITE_VERIF
+
+u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
+{
+	u32 rwmask = 0U;
+
+	switch (dslicenum) {
+	case 0:
+		if (arrayoffset < DSLICE0_REG_COUNT)
+			rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
+		break;
+	default:
+		if (arrayoffset < DSLICE1_REG_COUNT)
+			rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
+		break;
+	}
+	return rwmask;
+}
+#endif
+
+u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
+{
+	u32 result = 0U;
+
+	result = lpddr4_geteccenablesf(pd, eccparam);
+	if (result == (u32)0) {
+		*eccparam = LPDDR4_ECC_DISABLED;
+		result = (u32)EOPNOTSUPP;
+	}
+
+	return result;
+}
+u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+	u32 result = 0U;
+
+	result = lpddr4_seteccenablesf(pd, eccparam);
+	if (result == (u32)0)
+		result = (u32)EOPNOTSUPP;
+
+	return result;
+}
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.h b/drivers/ram/k3-ddrss/lpddr4_16bit.h
new file mode 100644
index 0000000000..d663389e60
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_H
+#define LPDDR4_16BIT_H
+
+#define DSLICE_NUM (2U)
+#define ASLICE_NUM (3U)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DSLICE0_REG_COUNT  (126U)
+#define DSLICE1_REG_COUNT  (126U)
+#define ASLICE0_REG_COUNT  (42U)
+#define ASLICE1_REG_COUNT  (42U)
+#define ASLICE2_REG_COUNT  (42U)
+#define PHY_CORE_REG_COUNT (126U)
+
+#define GRP_SHIFT 1
+#define INT_SHIFT 2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPDDR4_16BIT_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
new file mode 100644
index 0000000000..09b0e3c5a0
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
@@ -0,0 +1,1309 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/types.h>
+#include "lpddr4_ctl_regs_rw_masks.h"
+
+u32 g_lpddr4_ddr_controller_rw_mask[] = {
+	0x00000F01U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x01FFFFFFU,
+	0x03030300U,
+	0x01030100U,
+	0x1F1F013FU,
+	0x0303031FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0xFFFFFF01U,
+	0x0001FFFFU,
+	0x000F7FFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFF00FFFFU,
+	0x0000FFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x0F3F7F7FU,
+	0xFFFFFFFFU,
+	0x0F3F7F7FU,
+	0xFFFFFFFFU,
+	0x0F3F7F7FU,
+	0xFFFFFFFFU,
+	0xFF1F1F07U,
+	0x0001FFFFU,
+	0x3F3F01FFU,
+	0x1F01FFFFU,
+	0x01FFFFFFU,
+	0x3F3F01FFU,
+	0x1F01FFFFU,
+	0x01FFFFFFU,
+	0x3F3F01FFU,
+	0xFF01FFFFU,
+	0x00FFFFFFU,
+	0x1F0FFFFFU,
+	0xFFFF3FFFU,
+	0x0000FFFFU,
+	0x1F0FFFFFU,
+	0xFFFF3FFFU,
+	0x0000FFFFU,
+	0x1F0FFFFFU,
+	0x07073FFFU,
+	0xFFFF0107U,
+	0xFFFFFFFFU,
+	0x0101010FU,
+	0x3FFFFFFFU,
+	0xFFFFFFFFU,
+	0x0301FFFFU,
+	0x00010101U,
+	0x03FFFFFFU,
+	0x01000000U,
+	0x03FF3F07U,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x010FFFFFU,
+	0x0FFFFF01U,
+	0x001F1F01U,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x00000000U,
+	0x1FFFFFFFU,
+	0x1F0F1F1FU,
+	0x1F0F1F1FU,
+	0x1F0F1F1FU,
+	0x1F011F01U,
+	0x00FFFF01U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x1F1F07FFU,
+	0xFF1F1F1FU,
+	0x1F1F1F07U,
+	0x07FF1F1FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x07010101U,
+	0x00017F00U,
+	0xFFFFFFFFU,
+	0x0700FFFFU,
+	0xFFFFFF07U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x000FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x000FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x010FFFFFU,
+	0x00010100U,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x01FFFFFFU,
+	0x0000FF00U,
+	0x0001FFFFU,
+	0x0F01FFFFU,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF0100U,
+	0xFFFFFFFFU,
+	0x0F0F0003U,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x00013F0FU,
+	0x0FFF0FFFU,
+	0x0F0F0007U,
+	0x000FFF07U,
+	0xFFFF0FFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x01010101U,
+	0x0101FF01U,
+	0x00000107U,
+	0xFFFFFFFFU,
+	0x00FFFF0FU,
+	0x00000303U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x07FFFFFFU,
+	0x01FFFF00U,
+	0x00000000U,
+	0x00030100U,
+	0x03FF03FFU,
+	0x1F1F03FFU,
+	0x000FFFFFU,
+	0x03FF03FFU,
+	0x1F1F03FFU,
+	0x000FFFFFU,
+	0x03FF03FFU,
+	0x1F1F03FFU,
+	0x000FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x01FFFF01U,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x01FFFF00U,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x01FFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x01FFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0101FFFFU,
+	0x00000101U,
+	0x01010101U,
+	0x03010101U,
+	0x3F000003U,
+	0x00000101U,
+	0xFFFFFFFFU,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0x00000007U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x000FFF00U,
+	0x1F000000U,
+	0x1F1F1F1FU,
+	0xFFFF070FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x000FFF00U,
+	0x0FFF0FFFU,
+	0x007F0FFFU,
+	0x0FFF0FFFU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0x037F0FFFU,
+	0x0FFF0000U,
+	0x0FFF0FFFU,
+	0x03030101U,
+	0x03030303U,
+	0x0F0F0707U,
+	0xFFFFFFFFU,
+	0x00FFFF03U,
+	0xFFFFFFFFU,
+	0x03FFFF03U,
+	0x1F011F01U,
+	0x0101FFFFU,
+	0x01010101U,
+	0x03010101U,
+	0x0301011FU,
+	0x07010F03U,
+	0x03030307U,
+	0x03011F03U,
+	0x01010000U,
+	0x01030303U,
+	0x00000101U,
+	0x00010000U,
+	0x00000000U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0xFF000000U,
+	0x0FFF0F0FU,
+	0x0F0FFF0FU,
+	0x01010101U,
+	0x033F3F3FU,
+	0x3F030303U,
+	0x1F1F3F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x0F1F1F1FU,
+	0x0F070F07U,
+	0x07010107U,
+	0xFF000007U,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x007FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF070FU,
+	0x00FFFFFFU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x007FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF070FU,
+	0x00FFFFFFU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x007FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF070FU,
+	0xFFFFFFFFU,
+	0x000300FFU,
+	0x0F0FFFFFU,
+	0x0701FF07U,
+	0x07070707U,
+	0x0F0F0F07U,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0xFFFFFF0FU,
+	0x007F7F7FU
+};
+
+u32 g_lpddr4_pi_rw_mask[] = {
+	0x00000F01U,
+	0x00000000U,
+	0x00000000U,
+	0x01000000U,
+	0xFFFF0301U,
+	0x030100FFU,
+	0x00000101U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x0000011FU,
+	0xFFFFFFFFU,
+	0x01030101U,
+	0x0F011F03U,
+	0x0101070FU,
+	0x000FFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000007U,
+	0x00000000U,
+	0x00000000U,
+	0x01000000U,
+	0x00010101U,
+	0x3F3F0103U,
+	0x0101FFFFU,
+	0x01030103U,
+	0x0000FF00U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x030F0F1FU,
+	0x00000003U,
+	0x03FFFFFFU,
+	0x00000F07U,
+	0x00000103U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0101010FU,
+	0x01010101U,
+	0x00030301U,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0x0000FF03U,
+	0xFFFFFFFFU,
+	0x00FFFF00U,
+	0x0F0FFFFFU,
+	0x01011F1FU,
+	0x03000000U,
+	0x030F0101U,
+	0x01010101U,
+	0x0000FF03U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF0001U,
+	0x1F1F3F1FU,
+	0xFF0F0F01U,
+	0x017F1FFFU,
+	0xFF01FFFFU,
+	0x01010101U,
+	0x030701FFU,
+	0x1F1F0301U,
+	0x01030001U,
+	0x000000FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0101FFFFU,
+	0x00030001U,
+	0xFFFFFFFFU,
+	0x00010101U,
+	0x010003FFU,
+	0x01010101U,
+	0x1F070303U,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x00000000U,
+	0x00000000U,
+	0x3FFFFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x011F3F00U,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x0101011FU,
+	0x00FFFF01U,
+	0x00000107U,
+	0x000101FFU,
+	0xFFFFFFFFU,
+	0x0000FF01U,
+	0xFFFFFFFFU,
+	0x0FFF0000U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x03030703U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000003FU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x0101010FU,
+	0x00010101U,
+	0x01010101U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF0101U,
+	0x000000FFU,
+	0x03FFFFFFU,
+	0x00000100U,
+	0x0001FFFFU,
+	0x01000000U,
+	0x01000003U,
+	0x00010F07U,
+	0x0F00010FU,
+	0x010F0001U,
+	0x00010F00U,
+	0x0F00010FU,
+	0x010F0001U,
+	0x00000000U,
+	0x00000000U,
+	0x011F0000U,
+	0x01010103U,
+	0x01010101U,
+	0x01010101U,
+	0x01010101U,
+	0x01010101U,
+	0x00FF0101U,
+	0x000001FFU,
+	0x0000001FU,
+	0x01031F01U,
+	0x01010101U,
+	0x00FFFF07U,
+	0xFFFFFFFFU,
+	0x00FFFFFFU,
+	0x000000FFU,
+	0x000000FFU,
+	0x000FFFFFU,
+	0x0FFF0FFFU,
+	0xFF0F3F7FU,
+	0x0F3F7F7FU,
+	0x3F7F7FFFU,
+	0x007FFF0FU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x0F0FFFFFU,
+	0x03030F0FU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x01FF01FFU,
+	0x0F0F01FFU,
+	0x0F0F0F0FU,
+	0x3F3F3F3FU,
+	0x03033F3FU,
+	0x03030303U,
+	0x03FFFFFFU,
+	0x03030303U,
+	0x03030303U,
+	0xFF030303U,
+	0xFFFFFFFFU,
+	0x070707FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x1F030303U,
+	0x001F3FFFU,
+	0x001F3FFFU,
+	0x1F1F3FFFU,
+	0x03FF03FFU,
+	0x03FF1F1FU,
+	0x1F1F03FFU,
+	0x03FF03FFU,
+	0x7F7F7F7FU,
+	0x0F0F7F7FU,
+	0xFF1F0F0FU,
+	0xFF1F0F1FU,
+	0xFF1F0F1FU,
+	0xFFFFFF1FU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x3FFFFFFFU,
+	0x003F03FFU,
+	0x003F03FFU,
+	0x030303FFU,
+	0x0003FF03U,
+	0x7F7F03FFU,
+	0x1F03030FU,
+	0x03FFFFFFU,
+	0x7F7F03FFU,
+	0x1F03030FU,
+	0x03FFFFFFU,
+	0x7F7F03FFU,
+	0x1F03030FU,
+	0x0303FFFFU,
+	0xFFFFFF03U,
+	0x00FF3F1FU,
+	0x000FFFFFU,
+	0x3F0F01FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFF3F1FFFU,
+	0x000FFFFFU,
+	0x3F0F01FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFF3F1FFFU,
+	0x000FFFFFU,
+	0x3F0F01FFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x3F3FFFFFU,
+	0x00FFFF3FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x0000FFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x0000FFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x0FFFFFFFU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0x030F0F0FU,
+	0x07070303U,
+	0x03030303U,
+	0x7F7F7F7FU,
+	0x00000303U,
+	0xFFFF0000U,
+	0x00FFFFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x01FFFFFFU,
+	0x1F1F1FFFU,
+	0x1F1F1F1FU,
+	0x01FFFF1FU,
+	0x0301FFFFU,
+	0x00030303U,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0xFF01FFFFU,
+	0xFFFFFFFFU
+};
+
+u32 g_lpddr4_data_slice_0_rw_mask[] = {
+	0x07FF7F07U,
+	0x0703FF0FU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x1F030F3FU,
+	0x030F0F1FU,
+	0x01FF031FU,
+	0x00000101U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x7F0101FFU,
+	0x010101FFU,
+	0x03FF003FU,
+	0x01FF000FU,
+	0x01FF0701U,
+	0x00000003U,
+	0x00000000U,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0x3F030001U,
+	0x0F3FFF0FU,
+	0x1F030F3FU,
+	0x03FFFFFFU,
+	0x00073FFFU,
+	0x0F0F07FFU,
+	0x000FFFFFU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0x071F07FFU,
+	0x01010101U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x007F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x1F0703FFU,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x0303FFFFU,
+	0x1F1F0103U,
+	0x000F1F1FU,
+	0xFF3F07FFU,
+	0x0FFF0FFFU,
+	0x001F0F3FU,
+	0x03FF03FFU,
+	0x01FF0FFFU,
+	0x00000F01U,
+	0x000003FFU,
+	0x7F7F0703U,
+	0x0000001FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0x003FFFFFU
+};
+
+u32 g_lpddr4_data_slice_1_rw_mask[] = {
+	0x07FF7F07U,
+	0x0703FF0FU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x1F030F3FU,
+	0x030F0F1FU,
+	0x01FF031FU,
+	0x00000101U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x7F0101FFU,
+	0x010101FFU,
+	0x03FF003FU,
+	0x01FF000FU,
+	0x01FF0701U,
+	0x00000003U,
+	0x00000000U,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0x3F030001U,
+	0x0F3FFF0FU,
+	0x1F030F3FU,
+	0x03FFFFFFU,
+	0x00073FFFU,
+	0x0F0F07FFU,
+	0x000FFFFFU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0x071F07FFU,
+	0x01010101U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x007F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x1F0703FFU,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x0303FFFFU,
+	0x1F1F0103U,
+	0x000F1F1FU,
+	0xFF3F07FFU,
+	0x0FFF0FFFU,
+	0x001F0F3FU,
+	0x03FF03FFU,
+	0x01FF0FFFU,
+	0x00000F01U,
+	0x000003FFU,
+	0x7F7F0703U,
+	0x0000001FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0x003FFFFFU
+};
+
+u32 g_lpddr4_address_slice_0_rw_mask[] = {
+	0x000107FFU,
+	0x00000000U,
+	0x0F000000U,
+	0x00000000U,
+	0x01000707U,
+	0x011F7F7FU,
+	0x01000301U,
+	0x07FFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x07FF07FFU,
+	0x000007FFU,
+	0x00FFFFFFU,
+	0x03FFFFFFU,
+	0x01FF0F03U,
+	0x07000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x3FFFFFFFU,
+	0x3F3F03FFU,
+	0x3F0F3F3FU,
+	0x0000003FU,
+	0x0707FFFFU,
+	0x1F07FF1FU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x000F07FFU,
+	0xFF3F07FFU,
+	0x0103FFFFU,
+	0x0000000FU,
+	0x0000010FU
+};
+
+u32 g_lpddr4_address_slice_1_rw_mask[] = {
+	0x000107FFU,
+	0x00000000U,
+	0x0F000000U,
+	0x00000000U,
+	0x01000707U,
+	0x011F7F7FU,
+	0x01000301U,
+	0x07FFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x07FF07FFU,
+	0x000007FFU,
+	0x00FFFFFFU,
+	0x03FFFFFFU,
+	0x01FF0F03U,
+	0x07000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x3FFFFFFFU,
+	0x3F3F03FFU,
+	0x3F0F3F3FU,
+	0x0000003FU,
+	0x0707FFFFU,
+	0x1F07FF1FU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x000F07FFU,
+	0xFF3F07FFU,
+	0x0103FFFFU,
+	0x0000000FU,
+	0x0000010FU
+};
+
+u32 g_lpddr4_address_slice_2_rw_mask[] = {
+	0x000107FFU,
+	0x00000000U,
+	0x0F000000U,
+	0x00000000U,
+	0x01000707U,
+	0x011F7F7FU,
+	0x01000301U,
+	0x07FFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x07FF07FFU,
+	0x000007FFU,
+	0x00FFFFFFU,
+	0x03FFFFFFU,
+	0x01FF0F03U,
+	0x07000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x3FFFFFFFU,
+	0x3F3F03FFU,
+	0x3F0F3F3FU,
+	0x0000003FU,
+	0x0707FFFFU,
+	0x1F07FF1FU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x000F07FFU,
+	0xFF3F07FFU,
+	0x0103FFFFU,
+	0x0000000FU,
+	0x0000010FU
+};
+
+u32 g_lpddr4_phy_core_rw_mask[] = {
+	0x00000003U,
+	0x1F030101U,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x001F1F1FU,
+	0x011F07FFU,
+	0x07FF0100U,
+	0x000107FFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x0101FF01U,
+	0x0007FF03U,
+	0x070F07FFU,
+	0x01010300U,
+	0x0F010001U,
+	0x010F0F0FU,
+	0x0F0F0F0FU,
+	0x00010101U,
+	0x010FFFFFU,
+	0x00000001U,
+	0x00000000U,
+	0x0000FFFFU,
+	0x00000001U,
+	0x0F0F0F0FU,
+	0x03030303U,
+	0x03030303U,
+	0x03030303U,
+	0x03030303U,
+	0xFFFF1FFFU,
+	0x0000FF01U,
+	0x00000000U,
+	0x00000000U,
+	0x0FFF0FFFU,
+	0x00000000U,
+	0x00000000U,
+	0x0FFF0FFFU,
+	0xFF0F0101U,
+	0x0003FF01U,
+	0x0101FFFFU,
+	0x0003FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x1FFF03FFU,
+	0x00001FFFU,
+	0xFFFFFFFFU,
+	0x000007FFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7F000000U,
+	0x01FFFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x0FFFFFFFU,
+	0x000FFFFFU,
+	0x01FFFFFFU,
+	0x3F7FFFFFU,
+	0x3F3F1F3FU,
+	0x1F3F3F1FU,
+	0x001F3F3FU,
+	0x0000FFFFU,
+	0x01FF0F03U,
+	0x00000F7FU,
+	0x00000000U,
+	0x003F0101U,
+	0x01010000U,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0x03071FFFU,
+	0x00030303U,
+	0xFFFFFFFFU,
+	0x03FFFFFFU,
+	0x00FF073FU,
+	0x0707FFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000003U,
+	0x0F1F0101U,
+	0x00000000U,
+	0x0003FFFFU,
+	0x0007FFFFU,
+	0x00000001U,
+	0x00011FFFU,
+	0x0F0F0FFFU,
+	0x010103FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x000007FFU,
+	0x000007FFU,
+	0x000007FFU,
+	0x000007FFU,
+	0x3FFFFFFFU,
+	0x0003FFFFU,
+	0x7FFFFFFFU,
+	0xFFFFFFFFU,
+	0x3FFFFFFFU,
+	0x0FFFFFFFU,
+	0xFFFFFFFFU,
+	0x0007FFFFU,
+	0x3FFFFFFFU,
+	0x0FFFFFFFU,
+	0x3FFFFFFFU,
+	0x0FFFFFFFU,
+	0x3FFFFFFFU,
+	0x0FFFFFFFU,
+	0x3FFFFFFFU,
+	0x0FFFFFFFU,
+	0x3FFFFFFFU,
+	0x0FFFFFFFU,
+	0x7FFFFF07U
+};
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h
new file mode 100644
index 0000000000..fde05cea1f
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h
@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_SANITY_H
+#define LPDDR4_16BIT_SANITY_H
+
+#include <errno.h>
+#include <linux/types.h>
+#include <lpddr4_if.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
+
+#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
+#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
+#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
+#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (irqstatus == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
+		(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
+		(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
+		(intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
+		(intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
+		(intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
+		(intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
+		(intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
+		(intr != LPDDR4_INTR_ECC_ERROR) &&
+		(intr != LPDDR4_INTR_LP_DONE) &&
+		(intr != LPDDR4_INTR_LP_TIMEOUT) &&
+		(intr != LPDDR4_INTR_PORT_TIMEOUT) &&
+		(intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
+		(intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
+		(intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
+		(intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
+		(intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
+		(intr != LPDDR4_INTR_USERIF_WRAP) &&
+		(intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
+		(intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
+		(intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
+		(intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
+		(intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
+		(intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
+		(intr != LPDDR4_INTR_BIST_DONE) &&
+		(intr != LPDDR4_INTR_CRC) &&
+		(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
+		(intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
+		(intr != LPDDR4_INTR_DFI_TIMEOUT) &&
+		(intr != LPDDR4_INTR_DIMM) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
+		(intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
+		(intr != LPDDR4_INTR_MC_INIT_DONE) &&
+		(intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
+		(intr != LPDDR4_INTR_MRR_ERROR) &&
+		(intr != LPDDR4_INTR_MR_READ_DONE) &&
+		(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+		(intr != LPDDR4_INTR_PARITY_ERROR) &&
+		(intr != LPDDR4_INTR_LOR_BITS)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
+		(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
+		(intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
+		(intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
+		(intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
+		(intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
+		(intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
+		(intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
+		(intr != LPDDR4_INTR_ECC_ERROR) &&
+		(intr != LPDDR4_INTR_LP_DONE) &&
+		(intr != LPDDR4_INTR_LP_TIMEOUT) &&
+		(intr != LPDDR4_INTR_PORT_TIMEOUT) &&
+		(intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
+		(intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
+		(intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
+		(intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
+		(intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
+		(intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
+		(intr != LPDDR4_INTR_USERIF_WRAP) &&
+		(intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
+		(intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
+		(intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
+		(intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
+		(intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
+		(intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
+		(intr != LPDDR4_INTR_BIST_DONE) &&
+		(intr != LPDDR4_INTR_CRC) &&
+		(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
+		(intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
+		(intr != LPDDR4_INTR_DFI_TIMEOUT) &&
+		(intr != LPDDR4_INTR_DIMM) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
+		(intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
+		(intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
+		(intr != LPDDR4_INTR_MC_INIT_DONE) &&
+		(intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
+		(intr != LPDDR4_INTR_MRR_ERROR) &&
+		(intr != LPDDR4_INTR_MR_READ_DONE) &&
+		(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+		(intr != LPDDR4_INTR_PARITY_ERROR) &&
+		(intr != LPDDR4_INTR_LOR_BITS)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (irqstatus == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* LPDDR4_16BIT_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.c b/drivers/ram/k3-ddrss/lpddr4_32bit.c
new file mode 100644
index 0000000000..ab2e44891d
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <errno.h>
+
+#include "cps_drv_lpddr4.h"
+#include "lpddr4_ctl_regs.h"
+#include "lpddr4_if.h"
+#include "lpddr4.h"
+#include "lpddr4_structs_if.h"
+
+static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound);
+
+u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+	regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
+	regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
+	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
+	return result;
+}
+
+u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
+{
+	u32 result = 0U;
+	u32 lowermask = 0U;
+
+	result = lpddr4_getctlinterruptmasksf(pd, mask);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		lowermask = (u32)(CPS_FLD_READ(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG))));
+		*mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG))));
+		*mask = (u64)((*mask << WORD_SHIFT) | lowermask);
+	}
+	return result;
+}
+
+u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
+{
+	u32 result;
+	u32 regval = 0;
+	const u64 ui64one = 1ULL;
+	const u32 ui32irqcount = (u32)LPDDR4_INTR_LOR_BITS + 1U;
+
+	result = lpddr4_setctlinterruptmasksf(pd, mask);
+	if ((result == (u32)0) && (ui32irqcount < 64U)) {
+		if (*mask >= (ui64one << ui32irqcount))
+			result = (u32)EINVAL;
+	}
+
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		regval = (u32)(*mask & WORD_MASK);
+		regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)), regval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
+
+		regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK);
+		regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)), regval);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
+	}
+	return result;
+}
+
+u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
+{
+	u32 result;
+	u32 ctlirqstatus = 0;
+	u32 fieldshift = 0;
+
+	result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		if ((u32)intr >= (u32)WORD_SHIFT) {
+			ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG));
+			fieldshift = (u32)intr - ((u32)WORD_SHIFT);
+		} else {
+			ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG));
+			fieldshift = (u32)intr;
+		}
+
+		if (fieldshift < WORD_SHIFT) {
+			if (((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) > 0U)
+				*irqstatus = true;
+			else
+				*irqstatus = false;
+		}
+	}
+	return result;
+}
+
+u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
+{
+	u32 result = 0;
+	u32 regval = 0;
+	u32 localinterrupt = (u32)intr;
+
+	result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		if (localinterrupt > WORD_SHIFT) {
+			localinterrupt = (localinterrupt - (u32)WORD_SHIFT);
+			regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval);
+		} else {
+			regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
+			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval);
+		}
+	}
+
+	return result;
+}
+
+void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+	u32 regval;
+	u32 errbitmask = 0U;
+	u32 snum;
+	volatile u32 *regaddress;
+
+	regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
+	errbitmask = (LPDDR4_BIT_MASK << 1) | (LPDDR4_BIT_MASK);
+	for (snum = 0U; snum < DSLICE_NUM; snum++) {
+		regval = CPS_REG_READ(regaddress);
+		if ((regval & errbitmask) != 0U) {
+			debuginfo->wrlvlerror = CDN_TRUE;
+			*errfoundptr = true;
+		}
+		regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+	}
+}
+
+static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound)
+{
+	volatile u32 *regaddress;
+	u32 snum = 0U;
+	u32 errbitmask = 0U;
+	u32 regval = 0U;
+
+	if (*errorfound == (bool)false) {
+		regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
+		errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
+		for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+			regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress));
+			if ((regval & errbitmask) != RX_CAL_DONE) {
+				debuginfo->rxoffseterror = (u8)true;
+				*errorfound = true;
+			}
+			regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+		}
+	}
+}
+
+u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
+{
+	u32 result = 0U;
+	bool errorfound = false;
+
+	result = lpddr4_getdebuginitinfosf(pd, debuginfo);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
+		lpddr4_setsettings(ctlregbase, errorfound);
+		lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
+		errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
+	}
+
+	if (errorfound == (bool)true)
+		result = (u32)EPROTO;
+
+	return result;
+}
+
+u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
+{
+	u32 result = 0U;
+	u32 fldval = 0U;
+
+	result = lpddr4_geteccenablesf(pd, eccparam);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)));
+		switch (fldval) {
+		case 3:
+			*eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
+			break;
+		case 2:
+			*eccparam = LPDDR4_ECC_ERR_DETECT;
+			break;
+		case 1:
+			*eccparam = LPDDR4_ECC_ENABLED;
+			break;
+		default:
+			*eccparam = LPDDR4_ECC_DISABLED;
+			break;
+		}
+	}
+	return result;
+}
+
+u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	result = lpddr4_seteccenablesf(pd, eccparam);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+		regval = CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)), *eccparam);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
+	}
+	return result;
+}
+
+u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
+{
+	u32 result = 0U;
+
+	result = lpddr4_getreducmodesf(pd, mode);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U)
+			*mode = LPDDR4_REDUC_ON;
+		else
+			*mode = LPDDR4_REDUC_OFF;
+	}
+	return result;
+}
+u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+	u32 result = 0U;
+	u32 regval = 0U;
+
+	result = lpddr4_setreducmodesf(pd, mode);
+	if (result == (u32)0) {
+		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+		regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *mode);
+		CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
+	}
+	return result;
+}
+
+u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
+{
+	u32 lowerdata;
+	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+	u32 result = (u32)0;
+
+	if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
+		*mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
+		*mmrvalue = (u64)0;
+		result = (u32)EIO;
+	} else {
+		*mrrstatus = (u8)0;
+		lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
+		*mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
+		*mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
+		result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
+	}
+	return result;
+}
+
+#ifdef REG_WRITE_VERIF
+
+u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
+{
+	u32 rwmask = 0U;
+
+	switch (dslicenum) {
+	case 0:
+		if (arrayoffset < DSLICE0_REG_COUNT)
+			rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
+		break;
+	case 1:
+		if (arrayoffset < DSLICE1_REG_COUNT)
+			rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
+		break;
+	case 2:
+		if (arrayoffset < DSLICE2_REG_COUNT)
+			rwmask = g_lpddr4_data_slice_2_rw_mask[arrayoffset];
+		break;
+	default:
+		if (arrayoffset < DSLICE3_REG_COUNT)
+			rwmask = g_lpddr4_data_slice_3_rw_mask[arrayoffset];
+		break;
+	}
+	return rwmask;
+}
+#endif
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.h b/drivers/ram/k3-ddrss/lpddr4_32bit.h
new file mode 100644
index 0000000000..1f7fe658af
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_H
+#define LPDDR4_32BIT_H
+
+#define DSLICE_NUM (4U)
+#define ASLICE_NUM (1U)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DSLICE0_REG_COUNT  (140U)
+#define DSLICE1_REG_COUNT  (140U)
+#define DSLICE2_REG_COUNT  (140U)
+#define DSLICE3_REG_COUNT  (140U)
+#define ASLICE0_REG_COUNT  (52U)
+#define PHY_CORE_REG_COUNT (140U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* LPDDR4_32BIT_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
new file mode 100644
index 0000000000..70f0ef5942
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
@@ -0,0 +1,1548 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/types.h>
+#include "lpddr4_ctl_regs_rw_masks.h"
+
+u32 g_lpddr4_ddr_controller_rw_mask[] = {
+	0x00000F01U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x01FFFFFFU,
+	0x01010100U,
+	0x03013F01U,
+	0x1F1F1F03U,
+	0x00030303U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFF01U,
+	0x0001FFFFU,
+	0xFF0F7FFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7F7F0000U,
+	0x7F7F7F7FU,
+	0x00FF1F07U,
+	0x3FFF01FFU,
+	0xFF01FFFFU,
+	0x3FFF01FFU,
+	0xFF01FFFFU,
+	0x3FFF01FFU,
+	0x3F01FFFFU,
+	0x00FFFFFFU,
+	0x1F01FFFFU,
+	0xFFFFFFFFU,
+	0x1F01FFFFU,
+	0xFFFFFFFFU,
+	0x1F01FFFFU,
+	0x070707FFU,
+	0xFFFFFF01U,
+	0x0FFFFFFFU,
+	0x3F03FF1FU,
+	0x1F1F1F1FU,
+	0x0101011FU,
+	0x1FFFFFFFU,
+	0xFFFFFFFFU,
+	0x0301FFFFU,
+	0x0101017FU,
+	0x07010000U,
+	0x0003FF3FU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x03FF0101U,
+	0x03FFFFFFU,
+	0x03FFFFFFU,
+	0xFFFFFFFFU,
+	0x1F1F010FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x1F1F1FFFU,
+	0x1F010F1FU,
+	0x0F1F1F1FU,
+	0x1F1F1F01U,
+	0x00010F1FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFF1F1F1FU,
+	0x1F1F1F07U,
+	0xFF1F1F1FU,
+	0x1F1F1F07U,
+	0xFF1F1F1FU,
+	0x1F1F1F07U,
+	0x07010101U,
+	0x01010000U,
+	0x00010101U,
+	0xFFFFFFFFU,
+	0x0700FFFFU,
+	0xFFFFFF07U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x000FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x000FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x010FFFFFU,
+	0x00010100U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x01FFFFFFU,
+	0x01000107U,
+	0xFFFFFF03U,
+	0x00FFFFFFU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x3F0F0F0FU,
+	0x070FFF01U,
+	0x0F0F0000U,
+	0x000FFF07U,
+	0xFFFF0FFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x01010101U,
+	0x3F3F0101U,
+	0x01FF03FFU,
+	0xFFFF03FFU,
+	0xFFFF03FFU,
+	0xFFFF03FFU,
+	0x00000100U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00FFFF0FU,
+	0x07FFFFFFU,
+	0x01FFFF00U,
+	0x00000000U,
+	0x00000000U,
+	0x00010000U,
+	0x03FF0003U,
+	0x03FF03FFU,
+	0xFFFF1F1FU,
+	0x03FF03FFU,
+	0x1F1F03FFU,
+	0x03FFFFFFU,
+	0x03FF03FFU,
+	0xFFFF1F1FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF00FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFF00FFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00FFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFF00U,
+	0x010101FFU,
+	0x01000000U,
+	0x01010101U,
+	0x03030101U,
+	0x013F0000U,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0x00000007U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00000007U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0FFF0000U,
+	0x07030000U,
+	0x010F0101U,
+	0x01FFFF01U,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFF0000U,
+	0x7FFF7FFFU,
+	0x7FFF7FFFU,
+	0x00077FFFU,
+	0x010FFF00U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00000007U,
+	0xFFFFFFFFU,
+	0x1F1F1F07U,
+	0x000F1F1FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0007FFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FF00U,
+	0x00000000U,
+	0x0FFF0FFFU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0x007F0FFFU,
+	0x0FFF0FFFU,
+	0x0FFF0FFFU,
+	0x0000037FU,
+	0x0FFF0FFFU,
+	0x01010FFFU,
+	0x03030303U,
+	0x07070303U,
+	0xFFFF0F0FU,
+	0x0007FFFFU,
+	0xFFFFFFFFU,
+	0xFFFF0307U,
+	0x1F01FFFFU,
+	0xFFFF1F01U,
+	0x01010101U,
+	0x01010101U,
+	0x011F0301U,
+	0x01030301U,
+	0x0003FFFFU,
+	0x00000000U,
+	0x0103FFFFU,
+	0x01010103U,
+	0x01010101U,
+	0x01010101U,
+	0x01010101U,
+	0x0F0F0F07U,
+	0x0F0F070FU,
+	0x011F0F0FU,
+	0x01000003U,
+	0x03030301U,
+	0x00010101U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0xFFFFFFFFU,
+	0x00001FFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x03000000U,
+	0xFF030303U,
+	0x0FFF0F0FU,
+	0x0F0FFF0FU,
+	0x01010101U,
+	0x3F3F3F3FU,
+	0x1F1F3F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x0F1F1F1FU,
+	0x0F070F07U,
+	0x00000707U,
+	0x00000000U,
+	0x00010000U,
+	0x013F3F01U,
+	0x0F010101U,
+	0x00030101U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000FFFFU,
+	0x010F0F01U,
+	0x01010101U,
+	0x01010101U,
+	0x03030101U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00000100U,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x010FFFFFU,
+	0x0101030FU,
+	0x03010101U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0101FFFFU,
+	0x00000707U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00FFFFFFU,
+	0x7F7F7F00U,
+	0x00FF0300U,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x007FFFFFU,
+	0xFFFFFFFFU,
+	0x00007F7FU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x007FFFFFU,
+	0xFFFFFFFFU,
+	0x00007F7FU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x007FFFFFU,
+	0xFFFFFFFFU,
+	0x0F0F7F7FU,
+	0xFF0F0F0FU,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003FFFFU,
+	0xFFFFFFFFU,
+	0x000101FFU,
+	0xFFFFFFFFU,
+	0x00FF0000U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x07000101U,
+	0x7F7F0707U,
+	0x7F7F7F7FU,
+	0x010101FFU,
+	0x07070701U,
+	0x0F070707U,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0xFF0F0F0FU,
+	0xFFFF00FFU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x01010101U,
+	0x01010101U,
+	0x00010101U,
+	0x00000000U,
+	0x00000000U,
+	0x00000100U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x00000007U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000000FU
+};
+
+u32 g_lpddr4_pi_rw_mask[] = {
+	0x00000F01U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00010101U,
+	0x00FFFFFFU,
+	0x01010301U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0xFFFFFFFFU,
+	0x0101011FU,
+	0x0F011F0FU,
+	0x00010103U,
+	0x000FFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000007U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x01000000U,
+	0x00010101U,
+	0x003F3F03U,
+	0x0101FFFFU,
+	0x0F010F01U,
+	0x0000FF00U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0F0F0F1FU,
+	0x00030000U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0101010FU,
+	0x01010101U,
+	0x000F0F01U,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0x0000FF0FU,
+	0xFFFFFFFFU,
+	0x00FFFF00U,
+	0x0F0FFFFFU,
+	0x01011F1FU,
+	0x03000000U,
+	0x01030F01U,
+	0x0F010101U,
+	0x000000FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF0001U,
+	0x1F1F3F1FU,
+	0xFF0F0F01U,
+	0x7F1F0FFFU,
+	0x0101FFFFU,
+	0x00FFFF01U,
+	0x00000000U,
+	0x010F0701U,
+	0x011F1F0FU,
+	0x00FF0300U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0101FFFFU,
+	0x01010100U,
+	0x0F1F0703U,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x000F0F0FU,
+	0x00000000U,
+	0x00000000U,
+	0x0FFFFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x011F1F00U,
+	0x03030301U,
+	0x00FF0103U,
+	0x013F0001U,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0x0000FF07U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0FFF0000U,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0xFFFFFFFFU,
+	0x0303070FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x3FFFFFFFU,
+	0x0101010FU,
+	0x01010100U,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFF0101U,
+	0x000000FFU,
+	0x03FFFFFFU,
+	0x01FFFF00U,
+	0x01000000U,
+	0x0100000FU,
+	0x00010F07U,
+	0x0F00010FU,
+	0x010F0001U,
+	0x00010F00U,
+	0x0F00010FU,
+	0x010F0001U,
+	0x00000000U,
+	0x00000000U,
+	0x011F0000U,
+	0x01010103U,
+	0x01010101U,
+	0x01010101U,
+	0x01010101U,
+	0x01010101U,
+	0x0001FFFFU,
+	0x0000001FU,
+	0x0F011F01U,
+	0x01010101U,
+	0xFFFFFF01U,
+	0x000000FFU,
+	0x000000FFU,
+	0x000FFFFFU,
+	0x0FFF0FFFU,
+	0x7F7F7F7FU,
+	0x03FF7F7FU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x000FFFFFU,
+	0x000003FFU,
+	0x0F0FFFFFU,
+	0x03030F0FU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x01FF01FFU,
+	0x0F0F01FFU,
+	0x0F0F0F0FU,
+	0x03030303U,
+	0x03030303U,
+	0x03030303U,
+	0x03030303U,
+	0x7F7F0303U,
+	0x7F7F7F7FU,
+	0x00070707U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x1F030303U,
+	0x001F3FFFU,
+	0x001F3FFFU,
+	0x1F1F3FFFU,
+	0x03FF03FFU,
+	0x03FF1F1FU,
+	0x1F1F03FFU,
+	0x03FF03FFU,
+	0x7F7F7F7FU,
+	0x0F0F7F7FU,
+	0xFF1F0F0FU,
+	0xFF1F0F1FU,
+	0xFF1F0F1FU,
+	0x0003FF1FU,
+	0x03FFFFFFU,
+	0x03FFFFFFU,
+	0x003FFFFFU,
+	0x003F03FFU,
+	0x003F03FFU,
+	0x03FF03FFU,
+	0x7F7F03FFU,
+	0x0003030FU,
+	0x03FF03FFU,
+	0x030F7F7FU,
+	0x0003FF03U,
+	0x7F7F03FFU,
+	0xFF03030FU,
+	0xFF3FFFFFU,
+	0xFF01FFFFU,
+	0xFFFF3F0FU,
+	0xFFFFFFFFU,
+	0x0000FF3FU,
+	0xFF01FFFFU,
+	0xFFFF3F0FU,
+	0xFFFFFFFFU,
+	0x0000FF3FU,
+	0xFF01FFFFU,
+	0xFFFF3F0FU,
+	0x1FFFFFFFU,
+	0xFFFFFFFFU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0x001FFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x3F3FFFFFU,
+	0xFFFFFF3FU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x0000FFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x0000FFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x00FFFFFFU,
+	0x0FFFFFFFU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0x000FFF7FU,
+	0x0FFF0FFFU,
+	0xFF0F0F0FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0FFFFFFFU,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0xFF0F0F0FU,
+	0x0FFFFFFFU,
+	0x0F0F0F0FU,
+	0x000F0F0FU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x000007FFU
+};
+
+u32 g_lpddr4_data_slice_0_rw_mask[] = {
+	0x000F07FFU,
+	0x000703FFU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x0101FF7FU,
+	0x00003F01U,
+	0x000F03FFU,
+	0x070101FFU,
+	0x000301FFU,
+	0x00000000U,
+	0x00000301U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0xFF030001U,
+	0x00FF0F3FU,
+	0x0F3F03FFU,
+	0x1F030F3FU,
+	0x3FFFFFFFU,
+	0x0F07FF07U,
+	0x0000FF0FU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x010001FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0x00000000U,
+	0x017F7F01U,
+	0x07FF0FFFU,
+	0x03FFFF1FU,
+	0x01FFFF3FU,
+	0x07030101U,
+	0x01010101U,
+	0x000007FFU,
+	0x00003FFFU,
+	0x00001F00U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x003F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x000703FFU,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x03FFFF01U,
+	0x1F1F0103U,
+	0x3F07FF0FU,
+	0xFF0FFFFFU,
+	0x1F0F3F0FU,
+	0x03FF03FFU,
+	0x0F010FFFU,
+	0x000003FFU,
+	0x3F0103FFU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F3F7FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_1_rw_mask[] = {
+	0x000F07FFU,
+	0x000703FFU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x0101FF7FU,
+	0x00003F01U,
+	0x000F03FFU,
+	0x070101FFU,
+	0x000301FFU,
+	0x00000000U,
+	0x00000301U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0xFF030001U,
+	0x00FF0F3FU,
+	0x0F3F03FFU,
+	0x1F030F3FU,
+	0x3FFFFFFFU,
+	0x0F07FF07U,
+	0x0000FF0FU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x010001FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0x00000000U,
+	0x017F7F01U,
+	0x07FF0FFFU,
+	0x03FFFF1FU,
+	0x01FFFF3FU,
+	0x07030101U,
+	0x01010101U,
+	0x000007FFU,
+	0x00003FFFU,
+	0x00001F00U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x003F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x000703FFU,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x03FFFF01U,
+	0x1F1F0103U,
+	0x3F07FF0FU,
+	0xFF0FFFFFU,
+	0x1F0F3F0FU,
+	0x03FF03FFU,
+	0x0F010FFFU,
+	0x000003FFU,
+	0x3F0103FFU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F3F7FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_2_rw_mask[] = {
+	0x000F07FFU,
+	0x000703FFU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x0101FF7FU,
+	0x00003F01U,
+	0x000F03FFU,
+	0x070101FFU,
+	0x000301FFU,
+	0x00000000U,
+	0x00000301U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0xFF030001U,
+	0x00FF0F3FU,
+	0x0F3F03FFU,
+	0x1F030F3FU,
+	0x3FFFFFFFU,
+	0x0F07FF07U,
+	0x0000FF0FU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x010001FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0x00000000U,
+	0x017F7F01U,
+	0x07FF0FFFU,
+	0x03FFFF1FU,
+	0x01FFFF3FU,
+	0x07030101U,
+	0x01010101U,
+	0x000007FFU,
+	0x00003FFFU,
+	0x00001F00U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x003F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x000703FFU,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x03FFFF01U,
+	0x1F1F0103U,
+	0x3F07FF0FU,
+	0xFF0FFFFFU,
+	0x1F0F3F0FU,
+	0x03FF03FFU,
+	0x0F010FFFU,
+	0x000003FFU,
+	0x3F0103FFU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F3F7FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_3_rw_mask[] = {
+	0x000F07FFU,
+	0x000703FFU,
+	0x010303FFU,
+	0x3F3F3F3FU,
+	0x3F3F3F3FU,
+	0x01030F3FU,
+	0x1F1F0301U,
+	0x1F030F0FU,
+	0x0101FF03U,
+	0xFFFFFFFFU,
+	0x00000000U,
+	0x0101FF7FU,
+	0x00003F01U,
+	0x000F03FFU,
+	0x070101FFU,
+	0x000301FFU,
+	0x00000000U,
+	0x00000301U,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x070F0107U,
+	0x0F0F0F0FU,
+	0xFF030001U,
+	0x00FF0F3FU,
+	0x0F3F03FFU,
+	0x1F030F3FU,
+	0x3FFFFFFFU,
+	0x0F07FF07U,
+	0x0000FF0FU,
+	0x000001FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0001FFFFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x00000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7FFFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x010001FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x01FF01FFU,
+	0x000001FFU,
+	0x0003FFFFU,
+	0x01FF01FFU,
+	0x00000000U,
+	0x017F7F01U,
+	0x07FF0FFFU,
+	0x03FFFF1FU,
+	0x01FFFF3FU,
+	0x07030101U,
+	0x01010101U,
+	0x000007FFU,
+	0x00003FFFU,
+	0x00001F00U,
+	0x07FFFF07U,
+	0x7F03FFFFU,
+	0xFF01037FU,
+	0x07FF07FFU,
+	0x0103FFFFU,
+	0x1F1F0F3FU,
+	0x1F1F1F1FU,
+	0x1F1F1F1FU,
+	0x003F1F1FU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x000703FFU,
+	0xFFFFFFFFU,
+	0xFFFFFF0FU,
+	0x0FFFFFFFU,
+	0x03FFFF01U,
+	0x1F1F0103U,
+	0x3F07FF0FU,
+	0xFF0FFFFFU,
+	0x1F0F3F0FU,
+	0x03FF03FFU,
+	0x0F010FFFU,
+	0x000003FFU,
+	0x3F0103FFU,
+	0x00030703U,
+	0x07FF03FFU,
+	0xFFFF0101U,
+	0x001F3F7FU,
+	0xFFFFFFFFU,
+	0x0000000FU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x03FF07FFU,
+	0x0003FF03U,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF03FFU,
+	0x03FF070FU,
+	0x000103FFU,
+	0x000F03FFU,
+	0x010F07FFU,
+	0x000003FFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0xFFFFFFFFU,
+	0x0003033FU
+};
+
+u32 g_lpddr4_address_slice_0_rw_mask[] = {
+	0x000107FFU,
+	0x00000000U,
+	0x0F000000U,
+	0x00000000U,
+	0x01000707U,
+	0x011F7F7FU,
+	0x01000301U,
+	0x07FFFFFFU,
+	0x0000003FU,
+	0x00000000U,
+	0x00000000U,
+	0x07FF07FFU,
+	0x000007FFU,
+	0x00FFFFFFU,
+	0x03FFFFFFU,
+	0x01FF0F03U,
+	0x07000001U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x00FFFFFFU,
+	0x3F3F03FFU,
+	0x3F0F3F3FU,
+	0xFFFFFF03U,
+	0x01FFFFFFU,
+	0x3F03FFFFU,
+	0x0101FFFFU,
+	0x07FF3F01U,
+	0x01FF0000U,
+	0x01000000U,
+	0x00000000U,
+	0x07FF07FFU,
+	0x1F07FF1FU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x001F07FFU,
+	0x000F07FFU,
+	0xFF3F07FFU,
+	0x0103FFFFU,
+	0x0000000FU,
+	0x03FF010FU,
+	0x0000FF01U
+};
+
+u32 g_lpddr4_phy_core_rw_mask[] = {
+	0x00000003U,
+	0x1F030101U,
+	0x1F1F1F1FU,
+	0x001F1F1FU,
+	0x011F07FFU,
+	0x07FF0100U,
+	0x000107FFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x0101FF01U,
+	0x0007FF0FU,
+	0xFF0F07FFU,
+	0x01030007U,
+	0xFFFF0101U,
+	0xFF3F0103U,
+	0x010101FFU,
+	0x0F0F0100U,
+	0x010F0F01U,
+	0xFFFF0101U,
+	0x0001010FU,
+	0x00000000U,
+	0x0000FFFFU,
+	0x00000001U,
+	0x0F0F0F0FU,
+	0x0F0F0F0FU,
+	0x01FF0F0FU,
+	0x001FFFFFU,
+	0x0001FFFFU,
+	0x0007FFFFU,
+	0x000003FFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x01000000U,
+	0x0001FF0FU,
+	0x000103FFU,
+	0x0003FFFFU,
+	0x0001FFFFU,
+	0x0001FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x0003FFFFU,
+	0x1FFF03FFU,
+	0x00001FFFU,
+	0xFFFFFFFFU,
+	0x000007FFU,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x7F000000U,
+	0x01FFFFFFU,
+	0x00000000U,
+	0x00000000U,
+	0x0FFFFF7FU,
+	0x000FFFFFU,
+	0x01FFFFFFU,
+	0x3F7FFFFFU,
+	0x3F3F1F3FU,
+	0x1F3F3F1FU,
+	0x001F3F3FU,
+	0x07FFFFFFU,
+	0x03010000U,
+	0x0F7F01FFU,
+	0x00000000U,
+	0x003F0101U,
+	0x01010000U,
+	0x00000001U,
+	0xFFFFFFFFU,
+	0x031F01FFU,
+	0x00000003U,
+	0xFFFFFFFFU,
+	0x03FFFFFFU,
+	0x07FF073FU,
+	0x00000007U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000000U,
+	0x00000003U,
+	0x070F0101U,
+	0x00000000U,
+	0x0707FF01U,
+	0x00007F00U,
+	0x3FFF0000U,
+	0x3F000000U,
+	0x000FFF00U,
+	0x03000FFFU,
+	0x00000000U,
+	0x000001FFU,
+	0x03FF0000U,
+	0x03000000U,
+	0x007F0000U,
+	0x00003F00U,
+	0x000FFFFFU,
+	0x000FFFFFU,
+	0x0000FFFFU,
+	0xFFFFFFFFU,
+	0x1F0FFFFFU,
+	0x0FFFFFFFU,
+	0x0000FFFFU,
+	0x00003FFFU,
+	0x3FFF0000U,
+	0x00000000U,
+	0x00003FFFU,
+	0x0003FFFFU,
+	0x00003FFFU,
+	0x00000001U,
+	0x00011FFFU,
+	0x0F0F0FFFU,
+	0x010101FFU,
+	0x07FF07FFU,
+	0x07FF07FFU,
+	0x000007FFU,
+	0x000007FFU,
+	0x000007FFU,
+	0x000007FFU,
+	0x00000007U,
+	0x3FFFFFFFU,
+	0x0003FFFFU,
+	0x7FFFFFFFU,
+	0xFFFFFFFFU,
+	0x3FFFFFFFU,
+	0x07FFFFFFU,
+	0xFFFFFFFFU,
+	0x0003FFFFU,
+	0x3FFFFFFFU,
+	0x07FFFFFFU,
+	0x3FFFFFFFU,
+	0x07FFFFFFU,
+	0x3FFFFFFFU,
+	0x07FFFFFFU,
+	0x3FFFFFFFU,
+	0x07FFFFFFU,
+	0x7FFFFF07U
+};
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
new file mode 100644
index 0000000000..334eecc8aa
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_SANITY_H
+#define LPDDR4_32BIT_SANITY_H
+
+#include <errno.h>
+#include <linux/types.h>
+#include <lpddr4_if.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
+
+#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
+#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
+#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
+#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (irqstatus == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_RESET_DONE) &&
+		(intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
+		(intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
+		(intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
+		(intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
+		(intr != LPDDR4_INTR_MC_INIT_DONE) &&
+		(intr != LPDDR4_INTR_LP_DONE) &&
+		(intr != LPDDR4_INTR_BIST_DONE) &&
+		(intr != LPDDR4_INTR_WRAP_ERROR) &&
+		(intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
+		(intr != LPDDR4_INTR_RDLVL_ERROR) &&
+		(intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
+		(intr != LPDDR4_INTR_WRLVL_ERROR) &&
+		(intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+		(intr != LPDDR4_INTR_MRR_ERROR) &&
+		(intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
+		(intr != LPDDR4_INTR_WRLVL_REQ) &&
+		(intr != LPDDR4_INTR_RDLVL_REQ) &&
+		(intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
+		(intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
+		(intr != LPDDR4_INTR_LEVELING_DONE) &&
+		(intr != LPDDR4_INTR_PHY_ERROR) &&
+		(intr != LPDDR4_INTR_MR_READ_DONE) &&
+		(intr != LPDDR4_INTR_TEMP_CHANGE) &&
+		(intr != LPDDR4_INTR_TEMP_ALERT) &&
+		(intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
+		(intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
+		(intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
+		(intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
+		(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+		(intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
+		(intr != LPDDR4_INTR_DFI_INIT_STATE) &&
+		(intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
+		(intr != LPDDR4_INTR_TDFI_TO) &&
+		(intr != LPDDR4_INTR_DFS_DONE) &&
+		(intr != LPDDR4_INTR_DFS_STATUS) &&
+		(intr != LPDDR4_INTR_REFRESH_STATUS) &&
+		(intr != LPDDR4_INTR_ZQ_STATUS) &&
+		(intr != LPDDR4_INTR_SW_REQ_MODE) &&
+		(intr != LPDDR4_INTR_LOR_BITS)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_RESET_DONE) &&
+		(intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
+		(intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
+		(intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
+		(intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
+		(intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
+		(intr != LPDDR4_INTR_MC_INIT_DONE) &&
+		(intr != LPDDR4_INTR_LP_DONE) &&
+		(intr != LPDDR4_INTR_BIST_DONE) &&
+		(intr != LPDDR4_INTR_WRAP_ERROR) &&
+		(intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
+		(intr != LPDDR4_INTR_RDLVL_ERROR) &&
+		(intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
+		(intr != LPDDR4_INTR_WRLVL_ERROR) &&
+		(intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
+		(intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+		(intr != LPDDR4_INTR_MRR_ERROR) &&
+		(intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
+		(intr != LPDDR4_INTR_WRLVL_REQ) &&
+		(intr != LPDDR4_INTR_RDLVL_REQ) &&
+		(intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
+		(intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
+		(intr != LPDDR4_INTR_LEVELING_DONE) &&
+		(intr != LPDDR4_INTR_PHY_ERROR) &&
+		(intr != LPDDR4_INTR_MR_READ_DONE) &&
+		(intr != LPDDR4_INTR_TEMP_CHANGE) &&
+		(intr != LPDDR4_INTR_TEMP_ALERT) &&
+		(intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
+		(intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
+		(intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
+		(intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
+		(intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+		(intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
+		(intr != LPDDR4_INTR_DFI_INIT_STATE) &&
+		(intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
+		(intr != LPDDR4_INTR_TDFI_TO) &&
+		(intr != LPDDR4_INTR_DFS_DONE) &&
+		(intr != LPDDR4_INTR_DFS_STATUS) &&
+		(intr != LPDDR4_INTR_REFRESH_STATUS) &&
+		(intr != LPDDR4_INTR_ZQ_STATUS) &&
+		(intr != LPDDR4_INTR_SW_REQ_MODE) &&
+		(intr != LPDDR4_INTR_LOR_BITS)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (irqstatus == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
+{
+	u32 ret = 0;
+
+	if (pd == NULL) {
+		ret = EINVAL;
+	} else if (
+		(intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+		(intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* LPDDR4_32BIT_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_if.h b/drivers/ram/k3-ddrss/lpddr4_if.h
new file mode 100644
index 0000000000..7562989d99
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_if.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_IF_H
+#define LPDDR4_IF_H
+
+#include <linux/types.h>
+#ifdef CONFIG_K3_AM64_DDRSS
+#include <lpddr4_16bit_if.h>
+#else
+#include <lpddr4_32bit_if.h>
+#endif
+
+typedef struct lpddr4_config_s lpddr4_config;
+typedef struct lpddr4_privatedata_s lpddr4_privatedata;
+typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
+typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
+
+typedef enum {
+	LPDDR4_CTL_REGS		= 0U,
+	LPDDR4_PHY_REGS		= 1U,
+	LPDDR4_PHY_INDEP_REGS	= 2U
+} lpddr4_regblock;
+
+typedef enum {
+	LPDDR4_DRV_NONE			= 0U,
+	LPDDR4_DRV_SOC_PLL_UPDATE	= 1U
+} lpddr4_infotype;
+
+typedef enum {
+	LPDDR4_LPI_PD_WAKEUP_FN				= 0U,
+	LPDDR4_LPI_SR_SHORT_WAKEUP_FN			= 1U,
+	LPDDR4_LPI_SR_LONG_WAKEUP_FN			= 2U,
+	LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN		= 3U,
+	LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN			= 4U,
+	LPDDR4_LPI_SRPD_LONG_WAKEUP_FN			= 5U,
+	LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN	= 6U
+} lpddr4_lpiwakeupparam;
+
+typedef enum {
+	LPDDR4_REDUC_ON		= 0U,
+	LPDDR4_REDUC_OFF	= 1U
+} lpddr4_reducmode;
+
+typedef enum {
+	LPDDR4_ECC_DISABLED		= 0U,
+	LPDDR4_ECC_ENABLED		= 1U,
+	LPDDR4_ECC_ERR_DETECT		= 2U,
+	LPDDR4_ECC_ERR_DETECT_CORRECT	= 3U
+} lpddr4_eccenable;
+
+typedef enum {
+	LPDDR4_DBI_RD_ON	= 0U,
+	LPDDR4_DBI_RD_OFF	= 1U,
+	LPDDR4_DBI_WR_ON	= 2U,
+	LPDDR4_DBI_WR_OFF	= 3U
+} lpddr4_dbimode;
+
+typedef enum {
+	LPDDR4_FSP_0	= 0U,
+	LPDDR4_FSP_1	= 1U,
+	LPDDR4_FSP_2	= 2U
+} lpddr4_ctlfspnum;
+
+typedef void (*lpddr4_infocallback)(const lpddr4_privatedata *pd, lpddr4_infotype infotype);
+
+typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt ctlinterrupt, u8 chipselect);
+
+typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt phyindepinterrupt, u8 chipselect);
+
+u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize);
+
+u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg);
+
+u32 lpddr4_start(const lpddr4_privatedata *pd);
+
+u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
+
+u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
+
+u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
+
+u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
+
+u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask);
+
+u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask);
+
+u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
+
+u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
+
+u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask);
+
+u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask);
+
+u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
+
+u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
+
+u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
+
+u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
+
+u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+
+u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
+
+u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+
+u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
+
+u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+
+u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off);
+
+u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off);
+
+u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
+
+u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
+
+u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+
+u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval);
+
+#endif  /* LPDDR4_IF_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.c b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
new file mode 100644
index 0000000000..370242f5bd
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "lpddr4_obj_if.h"
+
+lpddr4_obj *lpddr4_getinstance(void)
+{
+	static lpddr4_obj driver = {
+		.probe				= lpddr4_probe,
+		.init				= lpddr4_init,
+		.start				= lpddr4_start,
+		.readreg			= lpddr4_readreg,
+		.writereg			= lpddr4_writereg,
+		.getmmrregister			= lpddr4_getmmrregister,
+		.setmmrregister			= lpddr4_setmmrregister,
+		.writectlconfig			= lpddr4_writectlconfig,
+		.writephyconfig			= lpddr4_writephyconfig,
+		.writephyindepconfig		= lpddr4_writephyindepconfig,
+		.readctlconfig			= lpddr4_readctlconfig,
+		.readphyconfig			= lpddr4_readphyconfig,
+		.readphyindepconfig		= lpddr4_readphyindepconfig,
+		.getctlinterruptmask		= lpddr4_getctlinterruptmask,
+		.setctlinterruptmask		= lpddr4_setctlinterruptmask,
+		.checkctlinterrupt		= lpddr4_checkctlinterrupt,
+		.ackctlinterrupt		= lpddr4_ackctlinterrupt,
+		.getphyindepinterruptmask	= lpddr4_getphyindepinterruptmask,
+		.setphyindepinterruptmask	= lpddr4_setphyindepinterruptmask,
+		.checkphyindepinterrupt		= lpddr4_checkphyindepinterrupt,
+		.ackphyindepinterrupt		= lpddr4_ackphyindepinterrupt,
+		.getdebuginitinfo		= lpddr4_getdebuginitinfo,
+		.getlpiwakeuptime		= lpddr4_getlpiwakeuptime,
+		.setlpiwakeuptime		= lpddr4_setlpiwakeuptime,
+		.geteccenable			= lpddr4_geteccenable,
+		.seteccenable			= lpddr4_seteccenable,
+		.getreducmode			= lpddr4_getreducmode,
+		.setreducmode			= lpddr4_setreducmode,
+		.getdbireadmode			= lpddr4_getdbireadmode,
+		.getdbiwritemode		= lpddr4_getdbiwritemode,
+		.setdbimode			= lpddr4_setdbimode,
+		.getrefreshrate			= lpddr4_getrefreshrate,
+		.setrefreshrate			= lpddr4_setrefreshrate,
+		.refreshperchipselect		= lpddr4_refreshperchipselect,
+	};
+
+	return &driver;
+}
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.h b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
new file mode 100644
index 0000000000..d538e61b74
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef lpddr4_obj_if_h
+#define lpddr4_obj_if_h
+
+#include "lpddr4_if.h"
+
+typedef struct lpddr4_obj_s {
+	u32 (*probe)(const lpddr4_config *config, u16 *configsize);
+
+	u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg);
+
+	u32 (*start)(const lpddr4_privatedata *pd);
+
+	u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
+
+	u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
+
+	u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
+
+	u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
+
+	u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+	u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+	u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+	u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+	u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+	u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+	u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask);
+
+	u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask);
+
+	u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
+
+	u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
+
+	u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask);
+
+	u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask);
+
+	u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
+
+	u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
+
+	u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
+
+	u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
+
+	u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+
+	u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
+
+	u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+
+	u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
+
+	u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+
+	u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off);
+
+	u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off);
+
+	u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
+
+	u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
+
+	u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+
+	u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
+} lpddr4_obj;
+
+extern lpddr4_obj *lpddr4_getinstance(void);
+
+#endif  /* lpddr4_obj_if_h */
diff --git a/drivers/ram/k3-j721e/lpddr4_private.h b/drivers/ram/k3-ddrss/lpddr4_private.h
index 3d5017ea47..3d5017ea47 100644
--- a/drivers/ram/k3-j721e/lpddr4_private.h
+++ b/drivers/ram/k3-ddrss/lpddr4_private.h
diff --git a/drivers/ram/k3-ddrss/lpddr4_sanity.h b/drivers/ram/k3-ddrss/lpddr4_sanity.h
new file mode 100644
index 0000000000..750e00d3f5
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_sanity.h
@@ -0,0 +1,445 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_SANITY_H
+#define LPDDR4_SANITY_H
+
+#include <errno.h>
+#include <linux/types.h>
+#include "lpddr4_if.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline u32 lpddr4_configsf(const lpddr4_config *obj);
+static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
+
+static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize);
+static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg);
+static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd);
+static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue);
+static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp);
+static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus);
+static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus);
+static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask);
+static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask);
+static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask);
+static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo);
+static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
+static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+
+#define lpddr4_probesf lpddr4_sanityfunction1
+#define lpddr4_initsf lpddr4_sanityfunction2
+#define lpddr4_startsf lpddr4_sanityfunction3
+#define lpddr4_readregsf lpddr4_sanityfunction4
+#define lpddr4_writeregsf lpddr4_sanityfunction5
+#define lpddr4_getmmrregistersf lpddr4_sanityfunction6
+#define lpddr4_setmmrregistersf lpddr4_sanityfunction7
+#define lpddr4_writectlconfigsf lpddr4_sanityfunction3
+#define lpddr4_writephyconfigsf lpddr4_sanityfunction3
+#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction3
+#define lpddr4_readctlconfigsf lpddr4_sanityfunction3
+#define lpddr4_readphyconfigsf lpddr4_sanityfunction3
+#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction3
+#define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
+#define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
+#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction16
+#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction16
+#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction18
+#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction19
+#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction19
+#define lpddr4_geteccenablesf lpddr4_sanityfunction21
+#define lpddr4_seteccenablesf lpddr4_sanityfunction22
+#define lpddr4_getreducmodesf lpddr4_sanityfunction23
+#define lpddr4_setreducmodesf lpddr4_sanityfunction24
+#define lpddr4_getdbireadmodesf lpddr4_sanityfunction25
+#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction25
+#define lpddr4_setdbimodesf lpddr4_sanityfunction27
+#define lpddr4_getrefreshratesf lpddr4_sanityfunction28
+#define lpddr4_setrefreshratesf lpddr4_sanityfunction29
+#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
+
+static inline u32 lpddr4_configsf(const lpddr4_config *obj)
+{
+	u32 ret = 0;
+
+	if (obj == NULL)
+		ret = EINVAL;
+
+	return ret;
+}
+
+static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj)
+{
+	u32 ret = 0;
+
+	if (obj == NULL)
+		ret = EINVAL;
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize)
+{
+	u32 ret = 0;
+
+	if (configsize == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_configsf(config) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg)
+{
+	u32 ret = 0;
+
+	if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (lpddr4_configsf(cfg) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd)
+{
+	u32 ret = 0;
+
+	if (lpddr4_privatedatasf(pd) == EINVAL)
+		ret = EINVAL;
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue)
+{
+	u32 ret = 0;
+
+	if (regvalue == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(cpp != LPDDR4_CTL_REGS) &&
+		(cpp != LPDDR4_PHY_REGS) &&
+		(cpp != LPDDR4_PHY_INDEP_REGS)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp)
+{
+	u32 ret = 0;
+
+	if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(cpp != LPDDR4_CTL_REGS) &&
+		(cpp != LPDDR4_PHY_REGS) &&
+		(cpp != LPDDR4_PHY_INDEP_REGS)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus)
+{
+	u32 ret = 0;
+
+	if (mmrvalue == NULL) {
+		ret = EINVAL;
+	} else if (mmrstatus == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus)
+{
+	u32 ret = 0;
+
+	if (mrwstatus == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask)
+{
+	u32 ret = 0;
+
+	if (mask == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask)
+{
+	u32 ret = 0;
+
+	if (mask == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask)
+{
+	u32 ret = 0;
+
+	if (mask == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo)
+{
+	u32 ret = 0;
+
+	if (debuginfo == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
+{
+	u32 ret = 0;
+
+	if (lpiwakeupparam == NULL) {
+		ret = EINVAL;
+	} else if (fspnum == NULL) {
+		ret = EINVAL;
+	} else if (cycles == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
+		(*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
+		(*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
+		(*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) &&
+		(*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
+		(*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
+		(*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
+		) {
+		ret = EINVAL;
+	} else if (
+		(*fspnum != LPDDR4_FSP_0) &&
+		(*fspnum != LPDDR4_FSP_1) &&
+		(*fspnum != LPDDR4_FSP_2)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+	u32 ret = 0;
+
+	if (eccparam == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+	u32 ret = 0;
+
+	if (eccparam == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(*eccparam != LPDDR4_ECC_DISABLED) &&
+		(*eccparam != LPDDR4_ECC_ENABLED) &&
+		(*eccparam != LPDDR4_ECC_ERR_DETECT) &&
+		(*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+	u32 ret = 0;
+
+	if (mode == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+	u32 ret = 0;
+
+	if (mode == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(*mode != LPDDR4_REDUC_ON) &&
+		(*mode != LPDDR4_REDUC_OFF)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off)
+{
+	u32 ret = 0;
+
+	if (on_off == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
+{
+	u32 ret = 0;
+
+	if (mode == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(*mode != LPDDR4_DBI_RD_ON) &&
+		(*mode != LPDDR4_DBI_RD_OFF) &&
+		(*mode != LPDDR4_DBI_WR_ON) &&
+		(*mode != LPDDR4_DBI_WR_OFF)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+{
+	u32 ret = 0;
+
+	if (fspnum == NULL) {
+		ret = EINVAL;
+	} else if (tref == NULL) {
+		ret = EINVAL;
+	} else if (tras_max == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(*fspnum != LPDDR4_FSP_0) &&
+		(*fspnum != LPDDR4_FSP_1) &&
+		(*fspnum != LPDDR4_FSP_2)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+{
+	u32 ret = 0;
+
+	if (fspnum == NULL) {
+		ret = EINVAL;
+	} else if (tref == NULL) {
+		ret = EINVAL;
+	} else if (tras_max == NULL) {
+		ret = EINVAL;
+	} else if (lpddr4_privatedatasf(pd) == EINVAL) {
+		ret = EINVAL;
+	} else if (
+		(*fspnum != LPDDR4_FSP_0) &&
+		(*fspnum != LPDDR4_FSP_1) &&
+		(*fspnum != LPDDR4_FSP_2)
+		) {
+		ret = EINVAL;
+	} else {
+	}
+
+	return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* LPDDR4_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
new file mode 100644
index 0000000000..e41cbb7ff4
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_STRUCTS_IF_H
+#define LPDDR4_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_if.h"
+
+struct lpddr4_config_s {
+	struct lpddr4_ctlregs_s *ctlbase;
+	lpddr4_infocallback infohandler;
+	lpddr4_ctlcallback ctlinterrupthandler;
+	lpddr4_phyindepcallback phyindepinterrupthandler;
+};
+
+struct lpddr4_privatedata_s {
+	struct lpddr4_ctlregs_s *ctlbase;
+	lpddr4_infocallback infohandler;
+	lpddr4_ctlcallback ctlinterrupthandler;
+	lpddr4_phyindepcallback phyindepinterrupthandler;
+};
+
+struct lpddr4_debuginfo_s {
+	u8 pllerror;
+	u8 iocaliberror;
+	u8 rxoffseterror;
+	u8 catraingerror;
+	u8 wrlvlerror;
+	u8 gatelvlerror;
+	u8 readlvlerror;
+	u8 dqtrainingerror;
+};
+
+struct lpddr4_fspmoderegs_s {
+	u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
+	u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
+	u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
+	u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
+	u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
+	u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
+	u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
+	u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
+};
+
+#endif  /* LPDDR4_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-j721e/Makefile b/drivers/ram/k3-j721e/Makefile
deleted file mode 100644
index d60cc626e0..0000000000
--- a/drivers/ram/k3-j721e/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
-#
-
-obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o
diff --git a/drivers/ram/k3-j721e/cps_drv_lpddr4.h b/drivers/ram/k3-j721e/cps_drv_lpddr4.h
deleted file mode 100644
index 706a5cde01..0000000000
--- a/drivers/ram/k3-j721e/cps_drv_lpddr4.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/******************************************************************************
- *
- * Copyright (C) 2017-2018 Cadence Design Systems, Inc.
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- * cps_drv_lpddr4.h
- * Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
- *****************************************************************************
- */
-
-#ifndef CPS_DRV_H_
-#define CPS_DRV_H_
-
-#include <stddef.h>
-#include <inttypes.h>
-#include <asm/io.h>
-
-/**
- *  \brief    Read a 32-bit value from memory.
- *  \param    reg   address of the memory mapped hardware register
- *  \return   the value at the given address
- */
-#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
-
-/**
- *  \brief   Write a 32-bit address value to memory.
- *  \param   reg     address of the memory mapped hardware register
- *  \param   value   unsigned 32-bit value to write
- */
-#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
-
-/**
- *  \brief    Subtitue the value of fld macro and concatinate with required string
- *  \param    fld         field name
- */
-#define CPS_FLD_MASK(fld)  (fld ## _MASK)
-#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
-#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
-#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
-#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
-
-/**
- *  \brief    Read a value of bit-field from the register value.
- *  \param    reg         register name
- *  \param    fld         field name
- *  \param    reg_value   register value
- *  \return   bit-field value
- */
-#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)),  \
-						(uint32_t)(CPS_FLD_SHIFT(fld)), \
-						(uint32_t)(reg_value)))
-
-/**
- *  \brief    Write a value of the bit-field into the register value.
- *  \param    reg         register name
- *  \param    fld         field name
- *  \param    reg_value   register value
- *  \param    value       value to be written to bit-field
- *  \return   modified register value
- */
-#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)),  \
-						(uint32_t)(CPS_FLD_SHIFT(fld)), \
-						(uint32_t)(reg_value), (uint32_t)(value)))
-
-/**
- *  \brief    Set bit within the register value.
- *  \param    reg         register name
- *  \param    fld         field name
- *  \param    reg_value   register value
- *  \return   modified register value
- */
-#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
-					(uint32_t)(CPS_FLD_MASK(fld)),  \
-					(uint32_t)(CPS_FLD_WOCLR(fld)), \
-					(uint32_t)(reg_value)))
-
-static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
-{
-	uint32_t result = (reg_value & mask) >> shift;
-
-	return (result);
-}
-
-/**
- *  \brief    Write a value of the bit-field into the register value.
- *  \param    mask        mask for the bit-field
- *  \param    shift       bit-field shift from LSB
- *  \param    reg_value   register value
- *  \param    value       value to be written to bit-field
- *  \return   modified register value
- */
-static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
-{
-	uint32_t new_value = (value << shift) & mask;
-
-	new_value = (reg_value & ~mask) | new_value;
-	return (new_value);
-}
-
-/**
- *  \brief    Set bit within the register value.
- *  \param    width       width of the bit-field
- *  \param    mask        mask for the bit-field
- *  \param    is_woclr    is bit-field has 'write one to clear' flag set
- *  \param    reg_value   register value
- *  \return   modified register value
- */
-static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
-{
-	uint32_t new_value = reg_value;
-	/* Confirm the field to be bit and not write to clear type */
-	if ((width == 1U) && (is_woclr == 0U)) {
-		new_value |= mask;
-	}
-
-	return (new_value);
-}
-#endif /* CPS_DRV_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c
deleted file mode 100644
index 68043d7cb6..0000000000
--- a/drivers/ram/k3-j721e/lpddr4.c
+++ /dev/null
@@ -1,2105 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/******************************************************************************
- * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- * lpddr4.c
- *
- *****************************************************************************
- */
-#include "cps_drv_lpddr4.h"
-#include "lpddr4_ctl_regs.h"
-#include "lpddr4_if.h"
-#include "lpddr4_private.h"
-#include "lpddr4_sanity.h"
-#include "lpddr4_structs_if.h"
-
-#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
-
-/**
- * Internal Function:Poll for status of interrupt received by the Controller.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] irqBit Interrupt status bit to be checked.
- * @param[in] delay time delay.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EIO on poll time out.
- * @return EINVAL checking status was not successful.
- */
-static uint32_t lpddr4_pollctlirq(const lpddr4_privatedata * pd,
-				  lpddr4_ctlinterrupt irqbit, uint32_t delay)
-{
-
-	uint32_t result = 0U;
-	uint32_t timeout = 0U;
-	bool irqstatus = false;
-
-	/* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
-	do {
-		if (++timeout == delay) {
-			result = EIO;
-			break;
-		}
-		/* cps_delayns(10000000U); */
-		result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
-	} while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
-
-	return result;
-}
-
-/**
- * Internal Function:Poll for status of interrupt received by the PHY Independent Module.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] irqBit Interrupt status bit to be checked.
- * @param[in] delay time delay.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EIO on poll time out.
- * @return EINVAL checking status was not successful.
- */
-static uint32_t lpddr4_pollphyindepirq(const lpddr4_privatedata * pd,
-				       lpddr4_phyindepinterrupt irqbit,
-				       uint32_t delay)
-{
-
-	uint32_t result = 0U;
-	uint32_t timeout = 0U;
-	bool irqstatus = false;
-
-	/* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
-	do {
-		if (++timeout == delay) {
-			result = EIO;
-			break;
-		}
-		/* cps_delayns(10000000U); */
-		result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
-	} while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
-
-	return result;
-}
-
-/**
- * Internal Function:Trigger function to poll and Ack IRQs
- * @param[in] pD Driver state info specific to this instance.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EIO on poll time out.
- * @return EINVAL checking status was not successful.
- */
-static uint32_t lpddr4_pollandackirq(const lpddr4_privatedata * pd)
-{
-	uint32_t result = 0U;
-
-	/* Wait for PhyIndependent module to finish up ctl init sequence */
-	result =
-	    lpddr4_pollphyindepirq(pd, LPDDR4_PHY_INDEP_INIT_DONE_BIT,
-				   LPDDR4_CUSTOM_TIMEOUT_DELAY);
-
-	/* Ack to clear the PhyIndependent interrupt bit */
-	if (result == (uint32_t) CDN_EOK) {
-		result =
-		    lpddr4_ackphyindepinterrupt(pd,
-						LPDDR4_PHY_INDEP_INIT_DONE_BIT);
-	}
-	/* Wait for the CTL end of initialization */
-	if (result == (uint32_t) CDN_EOK) {
-		result =
-		    lpddr4_pollctlirq(pd, LPDDR4_MC_INIT_DONE,
-				      LPDDR4_CUSTOM_TIMEOUT_DELAY);
-	}
-	/* Ack to clear the Ctl interrupt bit */
-	if (result == (uint32_t) CDN_EOK) {
-		result = lpddr4_ackctlinterrupt(pd, LPDDR4_MC_INIT_DONE);
-	}
-	return result;
-}
-
-/**
- * Internal Function: Controller start sequence.
- * @param[in] pD Driver state info specific to this instance.
- * @return CDN_EOK on success.
- * @return EINVAL starting controller was not successful.
- */
-static uint32_t lpddr4_startsequencecontroller(const lpddr4_privatedata * pd)
-{
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-	lpddr4_infotype infotype;
-
-	/* Set the PI_start to initiate leveling procedure */
-	regval =
-	    CPS_FLD_SET(LPDDR4__PI_START__FLD,
-			CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
-	CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
-
-	/* Set the Ctl_start  */
-	regval =
-	    CPS_FLD_SET(LPDDR4__START__FLD,
-			CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
-	CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
-
-	if (pd->infohandler != NULL) {
-		/* If a handler is registered, call it with the relevant information type */
-		infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
-		pd->infohandler(pd, infotype);
-	}
-
-	result = lpddr4_pollandackirq(pd);
-
-	return result;
-}
-
-/**
- * Internal Function: To add the offset to given address.
- * @param[in] addr Address to which the offset has to be added.
- * @param[in] regOffset The offset
- * @return regAddr The address value after the summation.
- */
-static volatile uint32_t *lpddr4_addoffset(volatile uint32_t * addr,
-					   uint32_t regoffset)
-{
-
-	volatile uint32_t *local_addr = addr;
-	/* Declaring as array to add the offset value. */
-	volatile uint32_t *regaddr = &local_addr[regoffset];
-	return regaddr;
-}
-
-/**
- * Checks configuration object.
- * @param[in] config Driver/hardware configuration required.
- * @param[out] configSize Size of memory allocations required.
- * @return CDN_EOK on success (requirements structure filled).
- * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
- */
-uint32_t lpddr4_probe(const lpddr4_config * config, uint16_t * configsize)
-{
-	uint32_t result;
-
-	result = (uint32_t) (lpddr4_probesf(config, configsize));
-	if (result == (uint32_t) CDN_EOK) {
-		*configsize = (uint16_t) (sizeof(lpddr4_privatedata));
-	}
-	return result;
-}
-
-/**
- * Init function to be called after LPDDR4_probe() to set up the driver configuration.
- * Memory should be allocated for drv_data (using the size determined using LPDDR4_probe) before
- * calling  this API, init_settings should be initialized with base addresses for PHY Independent Module,
- * Controller and PHY before calling this function.
- * If callbacks are required for interrupt handling, these should also be configured in init_settings.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cfg Specifies driver/hardware configuration.
- * @return CDN_EOK on success
- * @return EINVAL if illegal/inconsistent values in cfg.
- * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s)
- * required by 'config' parameters.
- */
-uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg)
-{
-	uint32_t result = 0U;
-	uint16_t productid = 0U;
-
-	result = lpddr4_initsf(pd, cfg);
-	if (result == (uint32_t) CDN_EOK) {
-		/* Validate Magic number */
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) cfg->ctlbase;
-		productid = (uint16_t) (CPS_FLD_READ(LPDDR4__CONTROLLER_ID__FLD,
-						     CPS_REG_READ(&
-								  (ctlregbase->
-								   LPDDR4__CONTROLLER_ID__REG))));
-		if (productid == PRODUCT_ID) {
-			/* Populating configuration data to pD */
-			pd->ctlbase = ctlregbase;
-			pd->infohandler =
-			    (lpddr4_infocallback) cfg->infohandler;
-			pd->ctlinterrupthandler =
-			    (lpddr4_ctlcallback) cfg->ctlinterrupthandler;
-			pd->phyindepinterrupthandler =
-			    (lpddr4_phyindepcallback) cfg->
-			    phyindepinterrupthandler;
-		} else {
-			/* Magic number validation failed - Driver doesn't support given IP version */
-			result = (uint32_t) EOPNOTSUPP;
-		}
-	}
-	return result;
-}
-
-/**
- * Start the driver.
- * @param[in] pD Driver state info specific to this instance.
- */
-uint32_t lpddr4_start(const lpddr4_privatedata * pd)
-{
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-
-	result = lpddr4_startsf(pd);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Enable PI as the initiator for DRAM */
-		regval =
-		    CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD,
-				CPS_REG_READ(&
-					     (ctlregbase->
-					      LPDDR4__PI_INIT_LVL_EN__REG)));
-		regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
-		CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)),
-			      regval);
-
-		/* Start PI init sequence. */
-		result = lpddr4_startsequencecontroller(pd);
-	}
-	return result;
-}
-
-/**
- * Read a register from the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[out] regValue Register value read
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset if out of range or regValue is NULL
- */
-uint32_t lpddr4_readreg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
-			uint32_t regoffset, uint32_t * regvalue)
-{
-	uint32_t result = 0U;
-
-	result = lpddr4_readregsf(pd, cpp, regvalue);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		if (cpp == LPDDR4_CTL_REGS) {
-			if (regoffset >= LPDDR4_CTL_REG_COUNT) {
-				/* Return if user provider invalid register number */
-				result = EINVAL;
-			} else {
-				*regvalue =
-				    CPS_REG_READ(lpddr4_addoffset
-						 (&(ctlregbase->DENALI_CTL_0),
-						  regoffset));
-			}
-		} else if (cpp == LPDDR4_PHY_REGS) {
-			if (regoffset >= LPDDR4_PHY_REG_COUNT) {
-				/* Return if user provider invalid register number */
-				result = EINVAL;
-			} else {
-				*regvalue =
-				    CPS_REG_READ(lpddr4_addoffset
-						 (&(ctlregbase->DENALI_PHY_0),
-						  regoffset));
-			}
-
-		} else {
-			if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
-				/* Return if user provider invalid register number */
-				result = EINVAL;
-			} else {
-				*regvalue =
-				    CPS_REG_READ(lpddr4_addoffset
-						 (&(ctlregbase->DENALI_PI_0),
-						  regoffset));
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_writereg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
-			 uint32_t regoffset, uint32_t regvalue)
-{
-	uint32_t result = 0U;
-
-	result = lpddr4_writeregsf(pd, cpp);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		if (cpp == LPDDR4_CTL_REGS) {
-			if (regoffset >= LPDDR4_CTL_REG_COUNT) {
-				/* Return if user provider invalid register number */
-				result = EINVAL;
-			} else {
-				CPS_REG_WRITE(lpddr4_addoffset
-					      (&(ctlregbase->DENALI_CTL_0),
-					       regoffset), regvalue);
-			}
-		} else if (cpp == LPDDR4_PHY_REGS) {
-			if (regoffset >= LPDDR4_PHY_REG_COUNT) {
-				/* Return if user provider invalid register number */
-				result = EINVAL;
-			} else {
-				CPS_REG_WRITE(lpddr4_addoffset
-					      (&(ctlregbase->DENALI_PHY_0),
-					       regoffset), regvalue);
-			}
-		} else {
-			if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
-				/* Return if user provider invalid register number */
-				result = EINVAL;
-			} else {
-				CPS_REG_WRITE(lpddr4_addoffset
-					      (&(ctlregbase->DENALI_PI_0),
-					       regoffset), regvalue);
-			}
-		}
-	}
-
-	return result;
-}
-
-static uint32_t lpddr4_checkmmrreaderror(const lpddr4_privatedata * pd,
-					 uint64_t * mmrvalue,
-					 uint8_t * mrrstatus)
-{
-
-	uint64_t lowerdata;
-	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-	uint32_t result = (uint32_t) CDN_EOK;
-
-	/* Check if mode register read error interrupt occurred */
-	if (lpddr4_pollctlirq(pd, LPDDR4_MRR_ERROR, 100) == 0U) {
-		/* Mode register read error interrupt, read MRR status register and return. */
-		*mrrstatus =
-		    (uint8_t) CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD,
-					   CPS_REG_READ(&
-							(ctlregbase->
-							 LPDDR4__MRR_ERROR_STATUS__REG)));
-		*mmrvalue = 0;
-		result = EIO;
-	} else {
-		*mrrstatus = 0;
-		/* Mode register read was successful, read DATA */
-		lowerdata =
-		    CPS_REG_READ(&
-				 (ctlregbase->
-				  LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
-		*mmrvalue =
-		    CPS_REG_READ(&
-				 (ctlregbase->
-				  LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
-		*mmrvalue = (uint64_t) ((*mmrvalue << WORD_SHIFT) | lowerdata);
-		/* Acknowledge MR_READ_DONE interrupt to clear it */
-		result = lpddr4_ackctlinterrupt(pd, LPDDR4_MR_READ_DONE);
-	}
-	return result;
-}
-
-uint32_t lpddr4_getmmrregister(const lpddr4_privatedata * pd,
-			       uint32_t readmoderegval, uint64_t * mmrvalue,
-			       uint8_t * mmrstatus)
-{
-
-	uint32_t result = 0U;
-	uint32_t tdelay = 1000U;
-	uint32_t regval = 0U;
-
-	result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
-	if (result == (uint32_t) CDN_EOK) {
-
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Populate the calculated value to the register  */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__READ_MODEREG__REG)),
-				  readmoderegval);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
-
-		/* Wait until the Read is done */
-		result = lpddr4_pollctlirq(pd, LPDDR4_MR_READ_DONE, tdelay);
-	}
-	if (result == (uint32_t) CDN_EOK) {
-		result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
-	}
-	return result;
-}
-
-static uint32_t lpddr4_writemmrregister(const lpddr4_privatedata * pd,
-					uint32_t writemoderegval)
-{
-
-	uint32_t result = (uint32_t) CDN_EOK;
-	uint32_t tdelay = 1000U;
-	uint32_t regval = 0U;
-	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-	/* Populate the calculated value to the register  */
-	regval =
-	    CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD,
-			  CPS_REG_READ(&
-				       (ctlregbase->
-					LPDDR4__WRITE_MODEREG__REG)),
-			  writemoderegval);
-	CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
-
-	result = lpddr4_pollctlirq(pd, LPDDR4_MR_WRITE_DONE, tdelay);
-
-	return result;
-}
-
-uint32_t lpddr4_setmmrregister(const lpddr4_privatedata * pd,
-			       uint32_t writemoderegval, uint8_t * mrwstatus)
-{
-	uint32_t result = 0U;
-
-	result = lpddr4_setmmrregistersf(pd, mrwstatus);
-	if (result == (uint32_t) CDN_EOK) {
-
-		/* Function call to trigger Mode register write */
-		result = lpddr4_writemmrregister(pd, writemoderegval);
-
-		if (result == (uint32_t) CDN_EOK) {
-			result =
-			    lpddr4_ackctlinterrupt(pd, LPDDR4_MR_WRITE_DONE);
-		}
-		/* Read the status of mode register write */
-		if (result == (uint32_t) CDN_EOK) {
-			lpddr4_ctlregs *ctlregbase =
-			    (lpddr4_ctlregs *) pd->ctlbase;
-			*mrwstatus =
-			    (uint8_t) CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD,
-						   CPS_REG_READ(&
-								(ctlregbase->
-								 LPDDR4__MRW_STATUS__REG)));
-			if ((*mrwstatus) != 0U) {
-				result = EIO;
-			}
-		}
-	}
-
-	return result;
-}
-
-uint32_t lpddr4_writectlconfig(const lpddr4_privatedata * pd,
-			       const lpddr4_reginitdata * regvalues)
-{
-	uint32_t result;
-	uint32_t regnum;
-
-	result = lpddr4_writectlconfigsf(pd, regvalues);
-	if (result == (uint32_t) CDN_EOK) {
-
-		/* Iterate through CTL register numbers. */
-		for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
-			/* Check if the user has requested update */
-			if (regvalues->updatectlreg[regnum]) {
-				result =
-				    lpddr4_writereg(pd, LPDDR4_CTL_REGS, regnum,
-						    (uint32_t) (regvalues->
-								denalictlreg
-								[regnum]));
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata * pd,
-				    const lpddr4_reginitdata * regvalues)
-{
-	uint32_t result;
-	uint32_t regnum;
-
-	result = lpddr4_writephyindepconfigsf(pd, regvalues);
-	if (result == (uint32_t) CDN_EOK) {
-
-		/* Iterate through PHY Independent module register numbers. */
-		for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
-			/* Check if the user has requested update */
-			if (regvalues->updatephyindepreg[regnum]) {
-				result =
-				    lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS,
-						    regnum,
-						    (uint32_t) (regvalues->
-								denaliphyindepreg
-								[regnum]));
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_writephyconfig(const lpddr4_privatedata * pd,
-			       const lpddr4_reginitdata * regvalues)
-{
-	uint32_t result;
-	uint32_t regnum;
-
-	result = lpddr4_writephyconfigsf(pd, regvalues);
-	if (result == (uint32_t) CDN_EOK) {
-
-		/* Iterate through PHY register numbers. */
-		for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
-			/* Check if the user has requested update */
-			if (regvalues->updatephyreg[regnum]) {
-				result =
-				    lpddr4_writereg(pd, LPDDR4_PHY_REGS, regnum,
-						    (uint32_t) (regvalues->
-								denaliphyreg
-								[regnum]));
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_readctlconfig(const lpddr4_privatedata * pd,
-			      lpddr4_reginitdata * regvalues)
-{
-	uint32_t result;
-	uint32_t regnum;
-	result = lpddr4_readctlconfigsf(pd, regvalues);
-	if (result == (uint32_t) CDN_EOK) {
-		/* Iterate through CTL register numbers. */
-		for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
-			/* Check if the user has requested read (updateCtlReg=1) */
-			if (regvalues->updatectlreg[regnum]) {
-				result =
-				    lpddr4_readreg(pd, LPDDR4_CTL_REGS, regnum,
-						   (uint32_t *) (&regvalues->
-								 denalictlreg
-								 [regnum]));
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata * pd,
-				   lpddr4_reginitdata * regvalues)
-{
-	uint32_t result;
-	uint32_t regnum;
-
-	result = lpddr4_readphyindepconfigsf(pd, regvalues);
-	if (result == (uint32_t) CDN_EOK) {
-		/* Iterate through PHY Independent module register numbers. */
-		for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
-			/* Check if the user has requested read (updateCtlReg=1) */
-			if (regvalues->updatephyindepreg[regnum]) {
-				result =
-				    lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS,
-						   regnum,
-						   (uint32_t *) (&regvalues->
-								 denaliphyindepreg
-								 [regnum]));
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_readphyconfig(const lpddr4_privatedata * pd,
-			      lpddr4_reginitdata * regvalues)
-{
-	uint32_t result;
-	uint32_t regnum;
-
-	result = lpddr4_readphyconfigsf(pd, regvalues);
-	if (result == (uint32_t) CDN_EOK) {
-		/* Iterate through PHY register numbers. */
-		for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
-			/* Check if the user has requested read (updateCtlReg=1) */
-			if (regvalues->updatephyreg[regnum]) {
-				result =
-				    lpddr4_readreg(pd, LPDDR4_PHY_REGS, regnum,
-						   (uint32_t *) (&regvalues->
-								 denaliphyreg
-								 [regnum]));
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata * pd,
-				    uint64_t * mask)
-{
-	uint32_t result = 0U;
-	uint64_t lowermask = 0U;
-
-	result = lpddr4_getctlinterruptmasksf(pd, mask);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		/* Reading the lower mask register */
-		lowermask =
-		    (uint64_t) (CPS_FLD_READ
-				(LPDDR4__INT_MASK_0__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__INT_MASK_0__REG))));
-		/* Reading the upper mask register */
-		*mask =
-		    (uint64_t) (CPS_FLD_READ
-				(LPDDR4__INT_MASK_1__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__INT_MASK_1__REG))));
-		/* Concatenate both register informations */
-		*mask = (uint64_t) ((*mask << WORD_SHIFT) | lowermask);
-	}
-	return result;
-}
-
-uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata * pd,
-				    const uint64_t * mask)
-{
-	uint32_t result;
-	uint32_t regval = 0;
-	const uint64_t ui64one = 1ULL;
-	const uint32_t ui32irqcount = (uint32_t) LPDDR4_LOR_BITS + 1U;
-
-	result = lpddr4_setctlinterruptmasksf(pd, mask);
-	if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < 64U)) {
-		/* Return if the user given value is higher than the field width */
-		if (*mask >= (ui64one << ui32irqcount)) {
-			result = EINVAL;
-		}
-	}
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Extracting the lower 32 bits and writing to lower mask register */
-		regval = (uint32_t) (*mask & WORD_MASK);
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__INT_MASK_0__REG)),
-				  regval);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
-
-		/* Extracting the upper 32 bits and writing to upper mask register */
-		regval = (uint32_t) ((*mask >> WORD_SHIFT) & WORD_MASK);
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__INT_MASK_1__REG)),
-				  regval);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
-	}
-	return result;
-}
-
-uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,
-				  lpddr4_ctlinterrupt intr, bool * irqstatus)
-{
-	uint32_t result;
-	uint32_t ctlirqstatus = 0;
-	uint32_t fieldshift = 0;
-
-	/* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
-	 * Value of 'interrupt' should be less than 64 */
-	result = lpddr4_checkctlinterruptsf(pd, intr, irqstatus);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		if ((uint32_t) intr >= WORD_SHIFT) {
-			ctlirqstatus =
-			    CPS_REG_READ(&
-					 (ctlregbase->
-					  LPDDR4__INT_STATUS_1__REG));
-			/* Reduce the shift value as we are considering upper register */
-			fieldshift = (uint32_t) intr - ((uint32_t) WORD_SHIFT);
-		} else {
-			ctlirqstatus =
-			    CPS_REG_READ(&
-					 (ctlregbase->
-					  LPDDR4__INT_STATUS_0__REG));
-			/* The shift value remains same for lower interrupt register */
-			fieldshift = (uint32_t) intr;
-		}
-
-		/* MISRA compliance (Shifting operation) check */
-		if (fieldshift < WORD_SHIFT) {
-			if ((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) {
-				*irqstatus = true;
-			} else {
-				*irqstatus = false;
-			}
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,
-				lpddr4_ctlinterrupt intr)
-{
-	uint32_t result = 0;
-	uint32_t regval = 0;
-	uint32_t localinterrupt = (uint32_t) intr;
-
-	/* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
-	 * Value of 'interrupt' should be less than 64 */
-	result = lpddr4_ackctlinterruptsf(pd, intr);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Check if the requested bit is in upper register */
-		if (localinterrupt > WORD_SHIFT) {
-			localinterrupt =
-			    (localinterrupt - (uint32_t) WORD_SHIFT);
-			regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
-			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG),
-				      regval);
-		} else {
-			regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
-			CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG),
-				      regval);
-		}
-	}
-
-	return result;
-}
-
-uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata * pd,
-					 uint32_t * mask)
-{
-	uint32_t result;
-
-	result = lpddr4_getphyindepinterruptmsf(pd, mask);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		/* Reading mask register */
-		*mask =
-		    CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__PI_INT_MASK__REG)));
-	}
-	return result;
-}
-
-uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata * pd,
-					 const uint32_t * mask)
-{
-	uint32_t result;
-	uint32_t regval = 0;
-	const uint32_t ui32irqcount =
-	    (uint32_t) LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
-
-	result = lpddr4_setphyindepinterruptmsf(pd, mask);
-	if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < WORD_SHIFT)) {
-		/* Return if the user given value is higher than the field width */
-		if (*mask >= (1U << ui32irqcount)) {
-			result = EINVAL;
-		}
-	}
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Writing to the user requested interrupt mask */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__PI_INT_MASK__REG)),
-				  *mask);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
-	}
-	return result;
-}
-
-uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,
-				       lpddr4_phyindepinterrupt intr,
-				       bool * irqstatus)
-{
-	uint32_t result = 0;
-	uint32_t phyindepirqstatus = 0;
-
-	result = lpddr4_checkphyindepinterrupsf(pd, intr, irqstatus);
-	/* Confirming that the value of interrupt is less than register width */
-	if ((result == (uint32_t) CDN_EOK) && ((uint32_t) intr < WORD_SHIFT)) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Reading the requested bit to check interrupt status */
-		phyindepirqstatus =
-		    CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
-		*irqstatus =
-		    !!((phyindepirqstatus >> (uint32_t)intr) & LPDDR4_BIT_MASK);
-	}
-	return result;
-}
-
-uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,
-				     lpddr4_phyindepinterrupt intr)
-{
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-	uint32_t ui32shiftinterrupt = (uint32_t) intr;
-
-	result = lpddr4_ackphyindepinterruptsf(pd, intr);
-	/* Confirming that the value of interrupt is less than register width */
-	if ((result == (uint32_t) CDN_EOK) && (ui32shiftinterrupt < WORD_SHIFT)) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Write 1 to the requested bit to ACk the interrupt */
-		regval = (uint32_t)LPDDR4_BIT_MASK << ui32shiftinterrupt;
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
-	}
-
-	return result;
-}
-
-/* Check for caTrainingError */
-static void lpddr4_checkcatrainingerror(lpddr4_ctlregs * ctlregbase,
-					lpddr4_debuginfo * debuginfo,
-					bool * errfoundptr)
-{
-
-	uint32_t regval;
-	uint32_t errbitmask = 0U;
-	uint32_t snum;
-	volatile uint32_t *regaddress;
-
-	regaddress =
-	    (volatile uint32_t
-	     *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
-	errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
-	/* PHY_ADR_CALVL_OBS1[4] – Right found
-	   PHY_ADR_CALVL_OBS1[5] – left found
-	   both the above fields should be high and below field should be zero.
-	   PHY_ADR_CALVL_OBS1[3:0] – calvl_state
-	 */
-	for (snum = 0U; snum < ASLICE_NUM; snum++) {
-		regval = CPS_REG_READ(regaddress);
-		if ((regval & errbitmask) != CA_TRAIN_RL) {
-			debuginfo->catraingerror = true;
-			*errfoundptr = true;
-		}
-		regaddress =
-		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
-	}
-}
-
-/* Check for  wrLvlError */
-static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,
-				   lpddr4_debuginfo * debuginfo,
-				   bool * errfoundptr)
-{
-
-	uint32_t regval;
-	uint32_t errbitmask = 0U;
-	uint32_t snum;
-	volatile uint32_t *regaddress;
-
-	regaddress =
-	    (volatile uint32_t
-	     *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
-	/* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */
-	errbitmask = (LPDDR4_BIT_MASK << 1) | LPDDR4_BIT_MASK;
-	for (snum = 0U; snum < DSLICE_NUM; snum++) {
-		regval = CPS_REG_READ(regaddress);
-		if ((regval & errbitmask) != 0U) {
-			debuginfo->wrlvlerror = true;
-			*errfoundptr = true;
-		}
-		regaddress =
-		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
-	}
-}
-
-/* Check for  GateLvlError */
-static void lpddr4_checkgatelvlerror(lpddr4_ctlregs * ctlregbase,
-				     lpddr4_debuginfo * debuginfo,
-				     bool * errfoundptr)
-{
-
-	uint32_t regval;
-	uint32_t errbitmask = 0U;
-	uint32_t snum;
-	volatile uint32_t *regaddress;
-
-	regaddress =
-	    (volatile uint32_t
-	     *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
-	/* PHY_GTLVL_STATUS_OBS[6] – gate_level min error
-	 * PHY_GTLVL_STATUS_OBS[7] – gate_level max error
-	 * All the above bit fields should be zero */
-	errbitmask = GATE_LVL_ERROR_FIELDS;
-	for (snum = 0U; snum < DSLICE_NUM; snum++) {
-		regval = CPS_REG_READ(regaddress);
-		if ((regval & errbitmask) != 0U) {
-			debuginfo->gatelvlerror = true;
-			*errfoundptr = true;
-		}
-		regaddress =
-		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
-	}
-}
-
-/* Check for  ReadLvlError */
-static void lpddr4_checkreadlvlerror(lpddr4_ctlregs * ctlregbase,
-				     lpddr4_debuginfo * debuginfo,
-				     bool * errfoundptr)
-{
-
-	uint32_t regval;
-	uint32_t errbitmask = 0U;
-	uint32_t snum;
-	volatile uint32_t *regaddress;
-
-	regaddress =
-	    (volatile uint32_t
-	     *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
-	/* PHY_RDLVL_STATUS_OBS[23:16] – failed bits : should be zero.
-	   PHY_RDLVL_STATUS_OBS[31:28] – rdlvl_state : should be zero */
-	errbitmask = READ_LVL_ERROR_FIELDS;
-	for (snum = 0U; snum < DSLICE_NUM; snum++) {
-		regval = CPS_REG_READ(regaddress);
-		if ((regval & errbitmask) != 0U) {
-			debuginfo->readlvlerror = true;
-			*errfoundptr = true;
-		}
-		regaddress =
-		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
-	}
-}
-
-/* Check for  DqTrainingError */
-static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs * ctlregbase,
-					lpddr4_debuginfo * debuginfo,
-					bool * errfoundptr)
-{
-
-	uint32_t regval;
-	uint32_t errbitmask = 0U;
-	uint32_t snum;
-	volatile uint32_t *regaddress;
-
-	regaddress =
-	    (volatile uint32_t
-	     *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
-	/* PHY_WDQLVL_STATUS_OBS[26:18] should all be zero. */
-	errbitmask = DQ_LVL_STATUS;
-	for (snum = 0U; snum < DSLICE_NUM; snum++) {
-		regval = CPS_REG_READ(regaddress);
-		if ((regval & errbitmask) != 0U) {
-			debuginfo->dqtrainingerror = true;
-			*errfoundptr = true;
-		}
-		regaddress =
-		    lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
-	}
-}
-
-/**
- * Internal Function:For checking errors in training/levelling sequence.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] debugInfo pointer to debug information.
- * @param[out] errFoundPtr pointer to return if error found.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EINVAL checking or unmasking was not successful.
- */
-static bool lpddr4_checklvlerrors(const lpddr4_privatedata * pd,
-				  lpddr4_debuginfo * debuginfo, bool errfound)
-{
-
-	bool localerrfound = errfound;
-
-	lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-	if (localerrfound == false) {
-		/* Check for ca training error */
-		lpddr4_checkcatrainingerror(ctlregbase, debuginfo,
-					    &localerrfound);
-	}
-
-	if (localerrfound == false) {
-		/* Check for Write leveling error */
-		lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
-	}
-
-	if (localerrfound == false) {
-		/* Check for Gate leveling error */
-		lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
-	}
-
-	if (localerrfound == false) {
-		/* Check for Read leveling error */
-		lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
-	}
-
-	if (localerrfound == false) {
-		/* Check for DQ training error */
-		lpddr4_checkdqtrainingerror(ctlregbase, debuginfo,
-					    &localerrfound);
-	}
-	return localerrfound;
-}
-
-static bool lpddr4_seterror(volatile uint32_t * reg, uint32_t errbitmask,
-			    bool * errfoundptr, const uint32_t errorinfobits)
-{
-
-	uint32_t regval = 0U;
-
-	/* Read the respective observation register */
-	regval = CPS_REG_READ(reg);
-	/* Compare the error bit values */
-	if ((regval & errbitmask) != errorinfobits) {
-		*errfoundptr = true;
-	}
-	return *errfoundptr;
-}
-
-static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,
-			     lpddr4_debuginfo * debuginfo, bool * errfoundptr)
-{
-
-	uint32_t errbitmask = (LPDDR4_BIT_MASK << 0x1U) | LPDDR4_BIT_MASK;
-	/* Check PLL observation registers for PLL lock errors */
-
-	debuginfo->pllerror =
-	    lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
-			    errbitmask, errfoundptr, PLL_READY);
-	if (*errfoundptr == false) {
-		debuginfo->pllerror =
-		    lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
-				    errbitmask, errfoundptr, PLL_READY);
-	}
-
-	/* Check for IO Calibration errors */
-	if (*errfoundptr == false) {
-		debuginfo->iocaliberror =
-		    lpddr4_seterror(&
-				    (ctlregbase->
-				     LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
-				    IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
-	}
-	if (*errfoundptr == false) {
-		debuginfo->iocaliberror =
-		    lpddr4_seterror(&
-				    (ctlregbase->
-				     LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
-				    IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
-	}
-	if (*errfoundptr == false) {
-		debuginfo->iocaliberror =
-		    lpddr4_seterror(&
-				    (ctlregbase->
-				     LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
-				    IO_CALIB_FIELD, errfoundptr,
-				    IO_CALIB_STATE);
-	}
-}
-
-static void lpddr4_setphysnapsettings(lpddr4_ctlregs * ctlregbase,
-				      const bool errorfound)
-{
-
-	uint32_t snum = 0U;
-	volatile uint32_t *regaddress;
-	uint32_t regval = 0U;
-
-	/* Setting SC_PHY_SNAP_OBS_REGS_x to get a snapshot */
-	if (errorfound == false) {
-		regaddress =
-		    (volatile uint32_t
-		     *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
-		/* Iterate through each PHY Data Slice */
-		for (snum = 0U; snum < DSLICE_NUM; snum++) {
-			regval =
-			    CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD,
-					CPS_REG_READ(regaddress));
-			CPS_REG_WRITE(regaddress, regval);
-			regaddress =
-			    lpddr4_addoffset(regaddress,
-					     (uint32_t) SLICE_WIDTH);
-		}
-	}
-}
-
-static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs * ctlregbase,
-					 const bool errorfound)
-{
-
-	uint32_t snum = 0U;
-	volatile uint32_t *regaddress;
-	uint32_t regval = 0U;
-
-	/* Setting SC_PHY ADR_SNAP_OBS_REGS_x to get a snapshot */
-	if (errorfound == false) {
-		regaddress =
-		    (volatile uint32_t
-		     *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
-		/* Iterate through each PHY Address Slice */
-		for (snum = 0U; snum < ASLICE_NUM; snum++) {
-			regval =
-			    CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD,
-					CPS_REG_READ(regaddress));
-			CPS_REG_WRITE(regaddress, regval);
-			regaddress =
-			    lpddr4_addoffset(regaddress,
-					     (uint32_t) SLICE_WIDTH);
-		}
-	}
-}
-
-static void lpddr4_setsettings(lpddr4_ctlregs * ctlregbase,
-			       const bool errorfound)
-{
-
-	/* Calling functions to enable snap shots of OBS registers */
-	lpddr4_setphysnapsettings(ctlregbase, errorfound);
-	lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
-}
-
-static void lpddr4_setrxoffseterror(lpddr4_ctlregs * ctlregbase,
-				    lpddr4_debuginfo * debuginfo,
-				    bool * errorfound)
-{
-
-	volatile uint32_t *regaddress;
-	uint32_t snum = 0U;
-	uint32_t errbitmask = 0U;
-	uint32_t regval = 0U;
-
-	/* Check for rxOffsetError */
-	if (*errorfound == false) {
-		regaddress =
-		    (volatile uint32_t
-		     *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
-		errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
-		/* PHY_RX_CAL_LOCK_OBS_x[4] – RX_CAL_DONE : should be high
-		   phy_rx_cal_lock_obs_x[3:0] – RX_CAL_STATE : should be zero. */
-		for (snum = 0U; snum < DSLICE_NUM; snum++) {
-			regval =
-			    CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD,
-					 CPS_REG_READ(regaddress));
-			if ((regval & errbitmask) != RX_CAL_DONE) {
-				debuginfo->rxoffseterror = true;
-				*errorfound = true;
-			}
-			regaddress =
-			    lpddr4_addoffset(regaddress,
-					     (uint32_t) SLICE_WIDTH);
-		}
-	}
-}
-
-uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata * pd,
-				 lpddr4_debuginfo * debuginfo)
-{
-
-	uint32_t result = 0U;
-	bool errorfound = false;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_getdebuginitinfosf(pd, debuginfo);
-	if (result == (uint32_t) CDN_EOK) {
-
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		lpddr4_seterrors(ctlregbase, debuginfo, &errorfound);
-		/* Function to setup Snap for OBS registers */
-		lpddr4_setsettings(ctlregbase, errorfound);
-		/* Function to check for Rx offset error */
-		lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
-		/* Function Check various levelling errors */
-		errorfound = lpddr4_checklvlerrors(pd, debuginfo, errorfound);
-	}
-
-	if (errorfound == true) {
-		result = (uint32_t) EPROTO;
-	}
-
-	return result;
-}
-
-static void readpdwakeup(const lpddr4_ctlfspnum * fspnum,
-			 lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
-	/* Read the appropriate register, based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_PD_WAKEUP_F0__REG)));
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_PD_WAKEUP_F1__REG)));
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_PD_WAKEUP_F2__REG)));
-	}
-}
-
-static void readsrshortwakeup(const lpddr4_ctlfspnum * fspnum,
-			      lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
-	/* Read the appropriate register, based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
-	}
-}
-
-static void readsrlongwakeup(const lpddr4_ctlfspnum * fspnum,
-			     lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
-	/* Read the appropriate register, based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
-	}
-}
-
-static void readsrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
-				 lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
-	/* Read the appropriate register, based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
-	}
-}
-
-static void readsrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
-				lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
-	/* Read the appropriate register, based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
-	}
-}
-
-static void readsrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
-			       lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
-	/* Read the appropriate register, based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		*cycles =
-		    CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
-	}
-}
-
-static void readsrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
-				   lpddr4_ctlregs * ctlregbase,
-				   uint32_t * cycles)
-{
-
-	/* Read the appropriate register, based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		*cycles =
-		    CPS_FLD_READ
-		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
-		     CPS_REG_READ(&
-				  (ctlregbase->
-				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		*cycles =
-		    CPS_FLD_READ
-		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
-		     CPS_REG_READ(&
-				  (ctlregbase->
-				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		*cycles =
-		    CPS_FLD_READ
-		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
-		     CPS_REG_READ(&
-				  (ctlregbase->
-				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
-	}
-
-}
-
-static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs * ctlregbase,
-				     const lpddr4_lpiwakeupparam *
-				     lpiwakeupparam,
-				     const lpddr4_ctlfspnum * fspnum,
-				     uint32_t * cycles)
-{
-
-	/* Iterate through each of the Wake up parameter type */
-	if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
-		/* Calling appropriate function for register read */
-		readpdwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
-		readsrshortwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
-		readsrlongwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
-		readsrlonggatewakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
-		readsrdpshortwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
-		readsrdplongwakeup(fspnum, ctlregbase, cycles);
-	} else {
-		/* Default function (sanity function already confirmed the variable value) */
-		readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
-	}
-}
-
-uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata * pd,
-				 const lpddr4_lpiwakeupparam * lpiwakeupparam,
-				 const lpddr4_ctlfspnum * fspnum,
-				 uint32_t * cycles)
-{
-
-	uint32_t result = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
-					 cycles);
-	}
-	return result;
-}
-
-static void writepdwakeup(const lpddr4_ctlfspnum * fspnum,
-			  lpddr4_ctlregs * ctlregbase, const uint32_t * cycles)
-{
-
-	uint32_t regval = 0U;
-	/* Write to appropriate register ,based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_PD_WAKEUP_F0__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG),
-			      regval);
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_PD_WAKEUP_F1__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG),
-			      regval);
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_PD_WAKEUP_F2__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG),
-			      regval);
-	}
-}
-
-static void writesrshortwakeup(const lpddr4_ctlfspnum * fspnum,
-			       lpddr4_ctlregs * ctlregbase,
-			       const uint32_t * cycles)
-{
-
-	uint32_t regval = 0U;
-	/* Write to appropriate register ,based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG),
-			      regval);
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG),
-			      regval);
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG),
-			      regval);
-	}
-}
-
-static void writesrlongwakeup(const lpddr4_ctlfspnum * fspnum,
-			      lpddr4_ctlregs * ctlregbase,
-			      const uint32_t * cycles)
-{
-
-	uint32_t regval = 0U;
-	/* Write to appropriate register ,based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG),
-			      regval);
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG),
-			      regval);
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG),
-			      regval);
-	}
-}
-
-static void writesrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
-				  lpddr4_ctlregs * ctlregbase,
-				  const uint32_t * cycles)
-{
-
-	uint32_t regval = 0U;
-	/* Write to appropriate register ,based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG),
-			      regval);
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG),
-			      regval);
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG),
-			      regval);
-	}
-}
-
-static void writesrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
-				 lpddr4_ctlregs * ctlregbase,
-				 const uint32_t * cycles)
-{
-
-	uint32_t regval = 0U;
-	/* Write to appropriate register ,based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
-	}
-}
-
-static void writesrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
-				lpddr4_ctlregs * ctlregbase,
-				const uint32_t * cycles)
-{
-
-	uint32_t regval = 0U;
-	/* Write to appropriate register ,based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)),
-				  *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
-	}
-}
-
-static void writesrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
-				    lpddr4_ctlregs * ctlregbase,
-				    const uint32_t * cycles)
-{
-
-	uint32_t regval = 0U;
-	/* Write to appropriate register ,based on user given frequency. */
-	if (*fspnum == LPDDR4_FSP_0) {
-		regval =
-		    CPS_FLD_WRITE
-		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
-		     CPS_REG_READ(&
-				  (ctlregbase->
-				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
-		     *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG),
-			      regval);
-	} else if (*fspnum == LPDDR4_FSP_1) {
-		regval =
-		    CPS_FLD_WRITE
-		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
-		     CPS_REG_READ(&
-				  (ctlregbase->
-				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
-		     *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG),
-			      regval);
-	} else {
-		/* Default register (sanity function already confirmed the variable value) */
-		regval =
-		    CPS_FLD_WRITE
-		    (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
-		     CPS_REG_READ(&
-				  (ctlregbase->
-				   LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
-		     *cycles);
-		CPS_REG_WRITE(&
-			      (ctlregbase->
-			       LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG),
-			      regval);
-	}
-}
-
-static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs * ctlregbase,
-				      const lpddr4_lpiwakeupparam *
-				      lpiwakeupparam,
-				      const lpddr4_ctlfspnum * fspnum,
-				      const uint32_t * cycles)
-{
-
-	/* Iterate through each of the Wake up parameter type */
-	if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
-		/* Calling appropriate function for register write */
-		writepdwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
-		writesrshortwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
-		writesrlongwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
-		writesrlonggatewakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
-		writesrdpshortwakeup(fspnum, ctlregbase, cycles);
-	} else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
-		writesrdplongwakeup(fspnum, ctlregbase, cycles);
-	} else {
-		/* Default function (sanity function already confirmed the variable value) */
-		writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
-	}
-}
-
-uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata * pd,
-				 const lpddr4_lpiwakeupparam * lpiwakeupparam,
-				 const lpddr4_ctlfspnum * fspnum,
-				 const uint32_t * cycles)
-{
-	uint32_t result = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
-	if (result == (uint32_t) CDN_EOK) {
-		/* Return if the user given value is higher than the field width */
-		if (*cycles > NIBBLE_MASK) {
-			result = EINVAL;
-		}
-	}
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
-					  cycles);
-	}
-	return result;
-}
-
-uint32_t lpddr4_geteccenable(const lpddr4_privatedata * pd,
-			     lpddr4_eccenable * eccparam)
-{
-	uint32_t result = 0U;
-	uint32_t fldval = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_geteccenablesf(pd, eccparam);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Reading the ECC_Enable field  from the register. */
-		fldval =
-		    CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD,
-				 CPS_REG_READ(&
-					      (ctlregbase->
-					       LPDDR4__ECC_ENABLE__REG)));
-		switch (fldval) {
-		case 3:
-			*eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
-			break;
-		case 2:
-			*eccparam = LPDDR4_ECC_ERR_DETECT;
-			break;
-		case 1:
-			*eccparam = LPDDR4_ECC_ENABLED;
-			break;
-		default:
-			/* Default ECC (Sanity function already confirmed the value to be in expected range.) */
-			*eccparam = LPDDR4_ECC_DISABLED;
-			break;
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_seteccenable(const lpddr4_privatedata * pd,
-			     const lpddr4_eccenable * eccparam)
-{
-
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_seteccenablesf(pd, eccparam);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Updating the ECC_Enable field based on the user given value. */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__ECC_ENABLE__REG)),
-				  *eccparam);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
-	}
-	return result;
-}
-
-uint32_t lpddr4_getreducmode(const lpddr4_privatedata * pd,
-			     lpddr4_reducmode * mode)
-{
-	uint32_t result = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_getreducmodesf(pd, mode);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		/* Read the value of reduc parameter. */
-		if (CPS_FLD_READ
-		    (LPDDR4__REDUC__FLD,
-		     CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) {
-			*mode = LPDDR4_REDUC_ON;
-		} else {
-			*mode = LPDDR4_REDUC_OFF;
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_setreducmode(const lpddr4_privatedata * pd,
-			     const lpddr4_reducmode * mode)
-{
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_setreducmodesf(pd, mode);
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		/* Setting to enable Half data path. */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__REDUC__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__REDUC__REG)), *mode);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
-	}
-	return result;
-}
-
-uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata * pd, bool * on_off)
-{
-
-	uint32_t result = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_getdbireadmodesf(pd, on_off);
-
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		/* Reading the field value from the register. */
-		if (CPS_FLD_READ
-		    (LPDDR4__RD_DBI_EN__FLD,
-		     CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) ==
-		    0U) {
-			*on_off = false;
-		} else {
-			*on_off = true;
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata * pd, bool * on_off)
-{
-
-	uint32_t result = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_getdbireadmodesf(pd, on_off);
-
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		/* Reading the field value from the register. */
-		if (CPS_FLD_READ
-		    (LPDDR4__WR_DBI_EN__FLD,
-		     CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) ==
-		    0U) {
-			*on_off = false;
-		} else {
-			*on_off = true;
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_setdbimode(const lpddr4_privatedata * pd,
-			   const lpddr4_dbimode * mode)
-{
-
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_setdbimodesf(pd, mode);
-
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Updating the appropriate field value based on the user given mode */
-		if (*mode == LPDDR4_DBI_RD_ON) {
-			regval =
-			    CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
-					  CPS_REG_READ(&
-						       (ctlregbase->
-							LPDDR4__RD_DBI_EN__REG)),
-					  1U);
-		} else if (*mode == LPDDR4_DBI_RD_OFF) {
-			regval =
-			    CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
-					  CPS_REG_READ(&
-						       (ctlregbase->
-							LPDDR4__RD_DBI_EN__REG)),
-					  0U);
-		} else if (*mode == LPDDR4_DBI_WR_ON) {
-			regval =
-			    CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
-					  CPS_REG_READ(&
-						       (ctlregbase->
-							LPDDR4__WR_DBI_EN__REG)),
-					  1U);
-		} else {
-			/* Default field (Sanity function already confirmed the value to be in expected range.) */
-			regval =
-			    CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
-					  CPS_REG_READ(&
-						       (ctlregbase->
-							LPDDR4__WR_DBI_EN__REG)),
-					  0U);
-		}
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
-	}
-	return result;
-}
-
-uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata * pd,
-			       const lpddr4_ctlfspnum * fspnum,
-			       uint32_t * cycles)
-{
-	uint32_t result = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_getrefreshratesf(pd, fspnum, cycles);
-
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Selecting the appropriate register for the user requested Frequency */
-		switch (*fspnum) {
-		case LPDDR4_FSP_2:
-			*cycles =
-			    CPS_FLD_READ(LPDDR4__TREF_F2__FLD,
-					 CPS_REG_READ(&
-						      (ctlregbase->
-						       LPDDR4__TREF_F2__REG)));
-			break;
-		case LPDDR4_FSP_1:
-			*cycles =
-			    CPS_FLD_READ(LPDDR4__TREF_F1__FLD,
-					 CPS_REG_READ(&
-						      (ctlregbase->
-						       LPDDR4__TREF_F1__REG)));
-			break;
-		default:
-			/* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
-			*cycles =
-			    CPS_FLD_READ(LPDDR4__TREF_F0__FLD,
-					 CPS_REG_READ(&
-						      (ctlregbase->
-						       LPDDR4__TREF_F0__REG)));
-			break;
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata * pd,
-			       const lpddr4_ctlfspnum * fspnum,
-			       const uint32_t * cycles)
-{
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_setrefreshratesf(pd, fspnum, cycles);
-
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
-		/* Selecting the appropriate register for the user requested Frequency */
-		switch (*fspnum) {
-		case LPDDR4_FSP_2:
-			regval =
-			    CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD,
-					  CPS_REG_READ(&
-						       (ctlregbase->
-							LPDDR4__TREF_F2__REG)),
-					  *cycles);
-			CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG),
-				      regval);
-			break;
-		case LPDDR4_FSP_1:
-			regval =
-			    CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD,
-					  CPS_REG_READ(&
-						       (ctlregbase->
-							LPDDR4__TREF_F1__REG)),
-					  *cycles);
-			CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG),
-				      regval);
-			break;
-		default:
-			/* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
-			regval =
-			    CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD,
-					  CPS_REG_READ(&
-						       (ctlregbase->
-							LPDDR4__TREF_F0__REG)),
-					  *cycles);
-			CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG),
-				      regval);
-			break;
-		}
-	}
-	return result;
-}
-
-uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata * pd,
-				     const uint32_t trefinterval)
-{
-	uint32_t result = 0U;
-	uint32_t regval = 0U;
-
-	/* Calling Sanity Function to verify the input variables */
-	result = lpddr4_refreshperchipselectsf(pd);
-
-	if (result == (uint32_t) CDN_EOK) {
-		lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-		/* Setting tref_interval parameter to enable/disable Refresh per chip select. */
-		regval =
-		    CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD,
-				  CPS_REG_READ(&
-					       (ctlregbase->
-						LPDDR4__TREF_INTERVAL__REG)),
-				  trefinterval);
-		CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG),
-			      regval);
-	}
-	return result;
-}
diff --git a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
deleted file mode 100644
index 213e569488..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
+++ /dev/null
@@ -1,1546 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
- */
-
-#ifndef REG_LPDDR4_CTL_REGS_H_
-#define REG_LPDDR4_CTL_REGS_H_
-
-#include "lpddr4_ddr_controller_macros.h"
-#include "lpddr4_pi_macros.h"
-#include "lpddr4_data_slice_0_macros.h"
-#include "lpddr4_data_slice_1_macros.h"
-#include "lpddr4_data_slice_2_macros.h"
-#include "lpddr4_data_slice_3_macros.h"
-#include "lpddr4_address_slice_0_macros.h"
-#include "lpddr4_phy_core_macros.h"
-
-typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
-	volatile uint32_t DENALI_CTL_0;
-	volatile uint32_t DENALI_CTL_1;
-	volatile uint32_t DENALI_CTL_2;
-	volatile uint32_t DENALI_CTL_3;
-	volatile uint32_t DENALI_CTL_4;
-	volatile uint32_t DENALI_CTL_5;
-	volatile uint32_t DENALI_CTL_6;
-	volatile uint32_t DENALI_CTL_7;
-	volatile uint32_t DENALI_CTL_8;
-	volatile uint32_t DENALI_CTL_9;
-	volatile uint32_t DENALI_CTL_10;
-	volatile uint32_t DENALI_CTL_11;
-	volatile uint32_t DENALI_CTL_12;
-	volatile uint32_t DENALI_CTL_13;
-	volatile uint32_t DENALI_CTL_14;
-	volatile uint32_t DENALI_CTL_15;
-	volatile uint32_t DENALI_CTL_16;
-	volatile uint32_t DENALI_CTL_17;
-	volatile uint32_t DENALI_CTL_18;
-	volatile uint32_t DENALI_CTL_19;
-	volatile uint32_t DENALI_CTL_20;
-	volatile uint32_t DENALI_CTL_21;
-	volatile uint32_t DENALI_CTL_22;
-	volatile uint32_t DENALI_CTL_23;
-	volatile uint32_t DENALI_CTL_24;
-	volatile uint32_t DENALI_CTL_25;
-	volatile uint32_t DENALI_CTL_26;
-	volatile uint32_t DENALI_CTL_27;
-	volatile uint32_t DENALI_CTL_28;
-	volatile uint32_t DENALI_CTL_29;
-	volatile uint32_t DENALI_CTL_30;
-	volatile uint32_t DENALI_CTL_31;
-	volatile uint32_t DENALI_CTL_32;
-	volatile uint32_t DENALI_CTL_33;
-	volatile uint32_t DENALI_CTL_34;
-	volatile uint32_t DENALI_CTL_35;
-	volatile uint32_t DENALI_CTL_36;
-	volatile uint32_t DENALI_CTL_37;
-	volatile uint32_t DENALI_CTL_38;
-	volatile uint32_t DENALI_CTL_39;
-	volatile uint32_t DENALI_CTL_40;
-	volatile uint32_t DENALI_CTL_41;
-	volatile uint32_t DENALI_CTL_42;
-	volatile uint32_t DENALI_CTL_43;
-	volatile uint32_t DENALI_CTL_44;
-	volatile uint32_t DENALI_CTL_45;
-	volatile uint32_t DENALI_CTL_46;
-	volatile uint32_t DENALI_CTL_47;
-	volatile uint32_t DENALI_CTL_48;
-	volatile uint32_t DENALI_CTL_49;
-	volatile uint32_t DENALI_CTL_50;
-	volatile uint32_t DENALI_CTL_51;
-	volatile uint32_t DENALI_CTL_52;
-	volatile uint32_t DENALI_CTL_53;
-	volatile uint32_t DENALI_CTL_54;
-	volatile uint32_t DENALI_CTL_55;
-	volatile uint32_t DENALI_CTL_56;
-	volatile uint32_t DENALI_CTL_57;
-	volatile uint32_t DENALI_CTL_58;
-	volatile uint32_t DENALI_CTL_59;
-	volatile uint32_t DENALI_CTL_60;
-	volatile uint32_t DENALI_CTL_61;
-	volatile uint32_t DENALI_CTL_62;
-	volatile uint32_t DENALI_CTL_63;
-	volatile uint32_t DENALI_CTL_64;
-	volatile uint32_t DENALI_CTL_65;
-	volatile uint32_t DENALI_CTL_66;
-	volatile uint32_t DENALI_CTL_67;
-	volatile uint32_t DENALI_CTL_68;
-	volatile uint32_t DENALI_CTL_69;
-	volatile uint32_t DENALI_CTL_70;
-	volatile uint32_t DENALI_CTL_71;
-	volatile uint32_t DENALI_CTL_72;
-	volatile uint32_t DENALI_CTL_73;
-	volatile uint32_t DENALI_CTL_74;
-	volatile uint32_t DENALI_CTL_75;
-	volatile uint32_t DENALI_CTL_76;
-	volatile uint32_t DENALI_CTL_77;
-	volatile uint32_t DENALI_CTL_78;
-	volatile uint32_t DENALI_CTL_79;
-	volatile uint32_t DENALI_CTL_80;
-	volatile uint32_t DENALI_CTL_81;
-	volatile uint32_t DENALI_CTL_82;
-	volatile uint32_t DENALI_CTL_83;
-	volatile uint32_t DENALI_CTL_84;
-	volatile uint32_t DENALI_CTL_85;
-	volatile uint32_t DENALI_CTL_86;
-	volatile uint32_t DENALI_CTL_87;
-	volatile uint32_t DENALI_CTL_88;
-	volatile uint32_t DENALI_CTL_89;
-	volatile uint32_t DENALI_CTL_90;
-	volatile uint32_t DENALI_CTL_91;
-	volatile uint32_t DENALI_CTL_92;
-	volatile uint32_t DENALI_CTL_93;
-	volatile uint32_t DENALI_CTL_94;
-	volatile uint32_t DENALI_CTL_95;
-	volatile uint32_t DENALI_CTL_96;
-	volatile uint32_t DENALI_CTL_97;
-	volatile uint32_t DENALI_CTL_98;
-	volatile uint32_t DENALI_CTL_99;
-	volatile uint32_t DENALI_CTL_100;
-	volatile uint32_t DENALI_CTL_101;
-	volatile uint32_t DENALI_CTL_102;
-	volatile uint32_t DENALI_CTL_103;
-	volatile uint32_t DENALI_CTL_104;
-	volatile uint32_t DENALI_CTL_105;
-	volatile uint32_t DENALI_CTL_106;
-	volatile uint32_t DENALI_CTL_107;
-	volatile uint32_t DENALI_CTL_108;
-	volatile uint32_t DENALI_CTL_109;
-	volatile uint32_t DENALI_CTL_110;
-	volatile uint32_t DENALI_CTL_111;
-	volatile uint32_t DENALI_CTL_112;
-	volatile uint32_t DENALI_CTL_113;
-	volatile uint32_t DENALI_CTL_114;
-	volatile uint32_t DENALI_CTL_115;
-	volatile uint32_t DENALI_CTL_116;
-	volatile uint32_t DENALI_CTL_117;
-	volatile uint32_t DENALI_CTL_118;
-	volatile uint32_t DENALI_CTL_119;
-	volatile uint32_t DENALI_CTL_120;
-	volatile uint32_t DENALI_CTL_121;
-	volatile uint32_t DENALI_CTL_122;
-	volatile uint32_t DENALI_CTL_123;
-	volatile uint32_t DENALI_CTL_124;
-	volatile uint32_t DENALI_CTL_125;
-	volatile uint32_t DENALI_CTL_126;
-	volatile uint32_t DENALI_CTL_127;
-	volatile uint32_t DENALI_CTL_128;
-	volatile uint32_t DENALI_CTL_129;
-	volatile uint32_t DENALI_CTL_130;
-	volatile uint32_t DENALI_CTL_131;
-	volatile uint32_t DENALI_CTL_132;
-	volatile uint32_t DENALI_CTL_133;
-	volatile uint32_t DENALI_CTL_134;
-	volatile uint32_t DENALI_CTL_135;
-	volatile uint32_t DENALI_CTL_136;
-	volatile uint32_t DENALI_CTL_137;
-	volatile uint32_t DENALI_CTL_138;
-	volatile uint32_t DENALI_CTL_139;
-	volatile uint32_t DENALI_CTL_140;
-	volatile uint32_t DENALI_CTL_141;
-	volatile uint32_t DENALI_CTL_142;
-	volatile uint32_t DENALI_CTL_143;
-	volatile uint32_t DENALI_CTL_144;
-	volatile uint32_t DENALI_CTL_145;
-	volatile uint32_t DENALI_CTL_146;
-	volatile uint32_t DENALI_CTL_147;
-	volatile uint32_t DENALI_CTL_148;
-	volatile uint32_t DENALI_CTL_149;
-	volatile uint32_t DENALI_CTL_150;
-	volatile uint32_t DENALI_CTL_151;
-	volatile uint32_t DENALI_CTL_152;
-	volatile uint32_t DENALI_CTL_153;
-	volatile uint32_t DENALI_CTL_154;
-	volatile uint32_t DENALI_CTL_155;
-	volatile uint32_t DENALI_CTL_156;
-	volatile uint32_t DENALI_CTL_157;
-	volatile uint32_t DENALI_CTL_158;
-	volatile uint32_t DENALI_CTL_159;
-	volatile uint32_t DENALI_CTL_160;
-	volatile uint32_t DENALI_CTL_161;
-	volatile uint32_t DENALI_CTL_162;
-	volatile uint32_t DENALI_CTL_163;
-	volatile uint32_t DENALI_CTL_164;
-	volatile uint32_t DENALI_CTL_165;
-	volatile uint32_t DENALI_CTL_166;
-	volatile uint32_t DENALI_CTL_167;
-	volatile uint32_t DENALI_CTL_168;
-	volatile uint32_t DENALI_CTL_169;
-	volatile uint32_t DENALI_CTL_170;
-	volatile uint32_t DENALI_CTL_171;
-	volatile uint32_t DENALI_CTL_172;
-	volatile uint32_t DENALI_CTL_173;
-	volatile uint32_t DENALI_CTL_174;
-	volatile uint32_t DENALI_CTL_175;
-	volatile uint32_t DENALI_CTL_176;
-	volatile uint32_t DENALI_CTL_177;
-	volatile uint32_t DENALI_CTL_178;
-	volatile uint32_t DENALI_CTL_179;
-	volatile uint32_t DENALI_CTL_180;
-	volatile uint32_t DENALI_CTL_181;
-	volatile uint32_t DENALI_CTL_182;
-	volatile uint32_t DENALI_CTL_183;
-	volatile uint32_t DENALI_CTL_184;
-	volatile uint32_t DENALI_CTL_185;
-	volatile uint32_t DENALI_CTL_186;
-	volatile uint32_t DENALI_CTL_187;
-	volatile uint32_t DENALI_CTL_188;
-	volatile uint32_t DENALI_CTL_189;
-	volatile uint32_t DENALI_CTL_190;
-	volatile uint32_t DENALI_CTL_191;
-	volatile uint32_t DENALI_CTL_192;
-	volatile uint32_t DENALI_CTL_193;
-	volatile uint32_t DENALI_CTL_194;
-	volatile uint32_t DENALI_CTL_195;
-	volatile uint32_t DENALI_CTL_196;
-	volatile uint32_t DENALI_CTL_197;
-	volatile uint32_t DENALI_CTL_198;
-	volatile uint32_t DENALI_CTL_199;
-	volatile uint32_t DENALI_CTL_200;
-	volatile uint32_t DENALI_CTL_201;
-	volatile uint32_t DENALI_CTL_202;
-	volatile uint32_t DENALI_CTL_203;
-	volatile uint32_t DENALI_CTL_204;
-	volatile uint32_t DENALI_CTL_205;
-	volatile uint32_t DENALI_CTL_206;
-	volatile uint32_t DENALI_CTL_207;
-	volatile uint32_t DENALI_CTL_208;
-	volatile uint32_t DENALI_CTL_209;
-	volatile uint32_t DENALI_CTL_210;
-	volatile uint32_t DENALI_CTL_211;
-	volatile uint32_t DENALI_CTL_212;
-	volatile uint32_t DENALI_CTL_213;
-	volatile uint32_t DENALI_CTL_214;
-	volatile uint32_t DENALI_CTL_215;
-	volatile uint32_t DENALI_CTL_216;
-	volatile uint32_t DENALI_CTL_217;
-	volatile uint32_t DENALI_CTL_218;
-	volatile uint32_t DENALI_CTL_219;
-	volatile uint32_t DENALI_CTL_220;
-	volatile uint32_t DENALI_CTL_221;
-	volatile uint32_t DENALI_CTL_222;
-	volatile uint32_t DENALI_CTL_223;
-	volatile uint32_t DENALI_CTL_224;
-	volatile uint32_t DENALI_CTL_225;
-	volatile uint32_t DENALI_CTL_226;
-	volatile uint32_t DENALI_CTL_227;
-	volatile uint32_t DENALI_CTL_228;
-	volatile uint32_t DENALI_CTL_229;
-	volatile uint32_t DENALI_CTL_230;
-	volatile uint32_t DENALI_CTL_231;
-	volatile uint32_t DENALI_CTL_232;
-	volatile uint32_t DENALI_CTL_233;
-	volatile uint32_t DENALI_CTL_234;
-	volatile uint32_t DENALI_CTL_235;
-	volatile uint32_t DENALI_CTL_236;
-	volatile uint32_t DENALI_CTL_237;
-	volatile uint32_t DENALI_CTL_238;
-	volatile uint32_t DENALI_CTL_239;
-	volatile uint32_t DENALI_CTL_240;
-	volatile uint32_t DENALI_CTL_241;
-	volatile uint32_t DENALI_CTL_242;
-	volatile uint32_t DENALI_CTL_243;
-	volatile uint32_t DENALI_CTL_244;
-	volatile uint32_t DENALI_CTL_245;
-	volatile uint32_t DENALI_CTL_246;
-	volatile uint32_t DENALI_CTL_247;
-	volatile uint32_t DENALI_CTL_248;
-	volatile uint32_t DENALI_CTL_249;
-	volatile uint32_t DENALI_CTL_250;
-	volatile uint32_t DENALI_CTL_251;
-	volatile uint32_t DENALI_CTL_252;
-	volatile uint32_t DENALI_CTL_253;
-	volatile uint32_t DENALI_CTL_254;
-	volatile uint32_t DENALI_CTL_255;
-	volatile uint32_t DENALI_CTL_256;
-	volatile uint32_t DENALI_CTL_257;
-	volatile uint32_t DENALI_CTL_258;
-	volatile uint32_t DENALI_CTL_259;
-	volatile uint32_t DENALI_CTL_260;
-	volatile uint32_t DENALI_CTL_261;
-	volatile uint32_t DENALI_CTL_262;
-	volatile uint32_t DENALI_CTL_263;
-	volatile uint32_t DENALI_CTL_264;
-	volatile uint32_t DENALI_CTL_265;
-	volatile uint32_t DENALI_CTL_266;
-	volatile uint32_t DENALI_CTL_267;
-	volatile uint32_t DENALI_CTL_268;
-	volatile uint32_t DENALI_CTL_269;
-	volatile uint32_t DENALI_CTL_270;
-	volatile uint32_t DENALI_CTL_271;
-	volatile uint32_t DENALI_CTL_272;
-	volatile uint32_t DENALI_CTL_273;
-	volatile uint32_t DENALI_CTL_274;
-	volatile uint32_t DENALI_CTL_275;
-	volatile uint32_t DENALI_CTL_276;
-	volatile uint32_t DENALI_CTL_277;
-	volatile uint32_t DENALI_CTL_278;
-	volatile uint32_t DENALI_CTL_279;
-	volatile uint32_t DENALI_CTL_280;
-	volatile uint32_t DENALI_CTL_281;
-	volatile uint32_t DENALI_CTL_282;
-	volatile uint32_t DENALI_CTL_283;
-	volatile uint32_t DENALI_CTL_284;
-	volatile uint32_t DENALI_CTL_285;
-	volatile uint32_t DENALI_CTL_286;
-	volatile uint32_t DENALI_CTL_287;
-	volatile uint32_t DENALI_CTL_288;
-	volatile uint32_t DENALI_CTL_289;
-	volatile uint32_t DENALI_CTL_290;
-	volatile uint32_t DENALI_CTL_291;
-	volatile uint32_t DENALI_CTL_292;
-	volatile uint32_t DENALI_CTL_293;
-	volatile uint32_t DENALI_CTL_294;
-	volatile uint32_t DENALI_CTL_295;
-	volatile uint32_t DENALI_CTL_296;
-	volatile uint32_t DENALI_CTL_297;
-	volatile uint32_t DENALI_CTL_298;
-	volatile uint32_t DENALI_CTL_299;
-	volatile uint32_t DENALI_CTL_300;
-	volatile uint32_t DENALI_CTL_301;
-	volatile uint32_t DENALI_CTL_302;
-	volatile uint32_t DENALI_CTL_303;
-	volatile uint32_t DENALI_CTL_304;
-	volatile uint32_t DENALI_CTL_305;
-	volatile uint32_t DENALI_CTL_306;
-	volatile uint32_t DENALI_CTL_307;
-	volatile uint32_t DENALI_CTL_308;
-	volatile uint32_t DENALI_CTL_309;
-	volatile uint32_t DENALI_CTL_310;
-	volatile uint32_t DENALI_CTL_311;
-	volatile uint32_t DENALI_CTL_312;
-	volatile uint32_t DENALI_CTL_313;
-	volatile uint32_t DENALI_CTL_314;
-	volatile uint32_t DENALI_CTL_315;
-	volatile uint32_t DENALI_CTL_316;
-	volatile uint32_t DENALI_CTL_317;
-	volatile uint32_t DENALI_CTL_318;
-	volatile uint32_t DENALI_CTL_319;
-	volatile uint32_t DENALI_CTL_320;
-	volatile uint32_t DENALI_CTL_321;
-	volatile uint32_t DENALI_CTL_322;
-	volatile uint32_t DENALI_CTL_323;
-	volatile uint32_t DENALI_CTL_324;
-	volatile uint32_t DENALI_CTL_325;
-	volatile uint32_t DENALI_CTL_326;
-	volatile uint32_t DENALI_CTL_327;
-	volatile uint32_t DENALI_CTL_328;
-	volatile uint32_t DENALI_CTL_329;
-	volatile uint32_t DENALI_CTL_330;
-	volatile uint32_t DENALI_CTL_331;
-	volatile uint32_t DENALI_CTL_332;
-	volatile uint32_t DENALI_CTL_333;
-	volatile uint32_t DENALI_CTL_334;
-	volatile uint32_t DENALI_CTL_335;
-	volatile uint32_t DENALI_CTL_336;
-	volatile uint32_t DENALI_CTL_337;
-	volatile uint32_t DENALI_CTL_338;
-	volatile uint32_t DENALI_CTL_339;
-	volatile uint32_t DENALI_CTL_340;
-	volatile uint32_t DENALI_CTL_341;
-	volatile uint32_t DENALI_CTL_342;
-	volatile uint32_t DENALI_CTL_343;
-	volatile uint32_t DENALI_CTL_344;
-	volatile uint32_t DENALI_CTL_345;
-	volatile uint32_t DENALI_CTL_346;
-	volatile uint32_t DENALI_CTL_347;
-	volatile uint32_t DENALI_CTL_348;
-	volatile uint32_t DENALI_CTL_349;
-	volatile uint32_t DENALI_CTL_350;
-	volatile uint32_t DENALI_CTL_351;
-	volatile uint32_t DENALI_CTL_352;
-	volatile uint32_t DENALI_CTL_353;
-	volatile uint32_t DENALI_CTL_354;
-	volatile uint32_t DENALI_CTL_355;
-	volatile uint32_t DENALI_CTL_356;
-	volatile uint32_t DENALI_CTL_357;
-	volatile uint32_t DENALI_CTL_358;
-	volatile uint32_t DENALI_CTL_359;
-	volatile uint32_t DENALI_CTL_360;
-	volatile uint32_t DENALI_CTL_361;
-	volatile uint32_t DENALI_CTL_362;
-	volatile uint32_t DENALI_CTL_363;
-	volatile uint32_t DENALI_CTL_364;
-	volatile uint32_t DENALI_CTL_365;
-	volatile uint32_t DENALI_CTL_366;
-	volatile uint32_t DENALI_CTL_367;
-	volatile uint32_t DENALI_CTL_368;
-	volatile uint32_t DENALI_CTL_369;
-	volatile uint32_t DENALI_CTL_370;
-	volatile uint32_t DENALI_CTL_371;
-	volatile uint32_t DENALI_CTL_372;
-	volatile uint32_t DENALI_CTL_373;
-	volatile uint32_t DENALI_CTL_374;
-	volatile uint32_t DENALI_CTL_375;
-	volatile uint32_t DENALI_CTL_376;
-	volatile uint32_t DENALI_CTL_377;
-	volatile uint32_t DENALI_CTL_378;
-	volatile uint32_t DENALI_CTL_379;
-	volatile uint32_t DENALI_CTL_380;
-	volatile uint32_t DENALI_CTL_381;
-	volatile uint32_t DENALI_CTL_382;
-	volatile uint32_t DENALI_CTL_383;
-	volatile uint32_t DENALI_CTL_384;
-	volatile uint32_t DENALI_CTL_385;
-	volatile uint32_t DENALI_CTL_386;
-	volatile uint32_t DENALI_CTL_387;
-	volatile uint32_t DENALI_CTL_388;
-	volatile uint32_t DENALI_CTL_389;
-	volatile uint32_t DENALI_CTL_390;
-	volatile uint32_t DENALI_CTL_391;
-	volatile uint32_t DENALI_CTL_392;
-	volatile uint32_t DENALI_CTL_393;
-	volatile uint32_t DENALI_CTL_394;
-	volatile uint32_t DENALI_CTL_395;
-	volatile uint32_t DENALI_CTL_396;
-	volatile uint32_t DENALI_CTL_397;
-	volatile uint32_t DENALI_CTL_398;
-	volatile uint32_t DENALI_CTL_399;
-	volatile uint32_t DENALI_CTL_400;
-	volatile uint32_t DENALI_CTL_401;
-	volatile uint32_t DENALI_CTL_402;
-	volatile uint32_t DENALI_CTL_403;
-	volatile uint32_t DENALI_CTL_404;
-	volatile uint32_t DENALI_CTL_405;
-	volatile uint32_t DENALI_CTL_406;
-	volatile uint32_t DENALI_CTL_407;
-	volatile uint32_t DENALI_CTL_408;
-	volatile uint32_t DENALI_CTL_409;
-	volatile uint32_t DENALI_CTL_410;
-	volatile uint32_t DENALI_CTL_411;
-	volatile uint32_t DENALI_CTL_412;
-	volatile uint32_t DENALI_CTL_413;
-	volatile uint32_t DENALI_CTL_414;
-	volatile uint32_t DENALI_CTL_415;
-	volatile uint32_t DENALI_CTL_416;
-	volatile uint32_t DENALI_CTL_417;
-	volatile uint32_t DENALI_CTL_418;
-	volatile uint32_t DENALI_CTL_419;
-	volatile uint32_t DENALI_CTL_420;
-	volatile uint32_t DENALI_CTL_421;
-	volatile uint32_t DENALI_CTL_422;
-	volatile uint32_t DENALI_CTL_423;
-	volatile uint32_t DENALI_CTL_424;
-	volatile uint32_t DENALI_CTL_425;
-	volatile uint32_t DENALI_CTL_426;
-	volatile uint32_t DENALI_CTL_427;
-	volatile uint32_t DENALI_CTL_428;
-	volatile uint32_t DENALI_CTL_429;
-	volatile uint32_t DENALI_CTL_430;
-	volatile uint32_t DENALI_CTL_431;
-	volatile uint32_t DENALI_CTL_432;
-	volatile uint32_t DENALI_CTL_433;
-	volatile uint32_t DENALI_CTL_434;
-	volatile uint32_t DENALI_CTL_435;
-	volatile uint32_t DENALI_CTL_436;
-	volatile uint32_t DENALI_CTL_437;
-	volatile uint32_t DENALI_CTL_438;
-	volatile uint32_t DENALI_CTL_439;
-	volatile uint32_t DENALI_CTL_440;
-	volatile uint32_t DENALI_CTL_441;
-	volatile uint32_t DENALI_CTL_442;
-	volatile uint32_t DENALI_CTL_443;
-	volatile uint32_t DENALI_CTL_444;
-	volatile uint32_t DENALI_CTL_445;
-	volatile uint32_t DENALI_CTL_446;
-	volatile uint32_t DENALI_CTL_447;
-	volatile uint32_t DENALI_CTL_448;
-	volatile uint32_t DENALI_CTL_449;
-	volatile uint32_t DENALI_CTL_450;
-	volatile uint32_t DENALI_CTL_451;
-	volatile uint32_t DENALI_CTL_452;
-	volatile uint32_t DENALI_CTL_453;
-	volatile uint32_t DENALI_CTL_454;
-	volatile uint32_t DENALI_CTL_455;
-	volatile uint32_t DENALI_CTL_456;
-	volatile uint32_t DENALI_CTL_457;
-	volatile uint32_t DENALI_CTL_458;
-	volatile char pad__0[0x18D4U];
-	volatile uint32_t DENALI_PI_0;
-	volatile uint32_t DENALI_PI_1;
-	volatile uint32_t DENALI_PI_2;
-	volatile uint32_t DENALI_PI_3;
-	volatile uint32_t DENALI_PI_4;
-	volatile uint32_t DENALI_PI_5;
-	volatile uint32_t DENALI_PI_6;
-	volatile uint32_t DENALI_PI_7;
-	volatile uint32_t DENALI_PI_8;
-	volatile uint32_t DENALI_PI_9;
-	volatile uint32_t DENALI_PI_10;
-	volatile uint32_t DENALI_PI_11;
-	volatile uint32_t DENALI_PI_12;
-	volatile uint32_t DENALI_PI_13;
-	volatile uint32_t DENALI_PI_14;
-	volatile uint32_t DENALI_PI_15;
-	volatile uint32_t DENALI_PI_16;
-	volatile uint32_t DENALI_PI_17;
-	volatile uint32_t DENALI_PI_18;
-	volatile uint32_t DENALI_PI_19;
-	volatile uint32_t DENALI_PI_20;
-	volatile uint32_t DENALI_PI_21;
-	volatile uint32_t DENALI_PI_22;
-	volatile uint32_t DENALI_PI_23;
-	volatile uint32_t DENALI_PI_24;
-	volatile uint32_t DENALI_PI_25;
-	volatile uint32_t DENALI_PI_26;
-	volatile uint32_t DENALI_PI_27;
-	volatile uint32_t DENALI_PI_28;
-	volatile uint32_t DENALI_PI_29;
-	volatile uint32_t DENALI_PI_30;
-	volatile uint32_t DENALI_PI_31;
-	volatile uint32_t DENALI_PI_32;
-	volatile uint32_t DENALI_PI_33;
-	volatile uint32_t DENALI_PI_34;
-	volatile uint32_t DENALI_PI_35;
-	volatile uint32_t DENALI_PI_36;
-	volatile uint32_t DENALI_PI_37;
-	volatile uint32_t DENALI_PI_38;
-	volatile uint32_t DENALI_PI_39;
-	volatile uint32_t DENALI_PI_40;
-	volatile uint32_t DENALI_PI_41;
-	volatile uint32_t DENALI_PI_42;
-	volatile uint32_t DENALI_PI_43;
-	volatile uint32_t DENALI_PI_44;
-	volatile uint32_t DENALI_PI_45;
-	volatile uint32_t DENALI_PI_46;
-	volatile uint32_t DENALI_PI_47;
-	volatile uint32_t DENALI_PI_48;
-	volatile uint32_t DENALI_PI_49;
-	volatile uint32_t DENALI_PI_50;
-	volatile uint32_t DENALI_PI_51;
-	volatile uint32_t DENALI_PI_52;
-	volatile uint32_t DENALI_PI_53;
-	volatile uint32_t DENALI_PI_54;
-	volatile uint32_t DENALI_PI_55;
-	volatile uint32_t DENALI_PI_56;
-	volatile uint32_t DENALI_PI_57;
-	volatile uint32_t DENALI_PI_58;
-	volatile uint32_t DENALI_PI_59;
-	volatile uint32_t DENALI_PI_60;
-	volatile uint32_t DENALI_PI_61;
-	volatile uint32_t DENALI_PI_62;
-	volatile uint32_t DENALI_PI_63;
-	volatile uint32_t DENALI_PI_64;
-	volatile uint32_t DENALI_PI_65;
-	volatile uint32_t DENALI_PI_66;
-	volatile uint32_t DENALI_PI_67;
-	volatile uint32_t DENALI_PI_68;
-	volatile uint32_t DENALI_PI_69;
-	volatile uint32_t DENALI_PI_70;
-	volatile uint32_t DENALI_PI_71;
-	volatile uint32_t DENALI_PI_72;
-	volatile uint32_t DENALI_PI_73;
-	volatile uint32_t DENALI_PI_74;
-	volatile uint32_t DENALI_PI_75;
-	volatile uint32_t DENALI_PI_76;
-	volatile uint32_t DENALI_PI_77;
-	volatile uint32_t DENALI_PI_78;
-	volatile uint32_t DENALI_PI_79;
-	volatile uint32_t DENALI_PI_80;
-	volatile uint32_t DENALI_PI_81;
-	volatile uint32_t DENALI_PI_82;
-	volatile uint32_t DENALI_PI_83;
-	volatile uint32_t DENALI_PI_84;
-	volatile uint32_t DENALI_PI_85;
-	volatile uint32_t DENALI_PI_86;
-	volatile uint32_t DENALI_PI_87;
-	volatile uint32_t DENALI_PI_88;
-	volatile uint32_t DENALI_PI_89;
-	volatile uint32_t DENALI_PI_90;
-	volatile uint32_t DENALI_PI_91;
-	volatile uint32_t DENALI_PI_92;
-	volatile uint32_t DENALI_PI_93;
-	volatile uint32_t DENALI_PI_94;
-	volatile uint32_t DENALI_PI_95;
-	volatile uint32_t DENALI_PI_96;
-	volatile uint32_t DENALI_PI_97;
-	volatile uint32_t DENALI_PI_98;
-	volatile uint32_t DENALI_PI_99;
-	volatile uint32_t DENALI_PI_100;
-	volatile uint32_t DENALI_PI_101;
-	volatile uint32_t DENALI_PI_102;
-	volatile uint32_t DENALI_PI_103;
-	volatile uint32_t DENALI_PI_104;
-	volatile uint32_t DENALI_PI_105;
-	volatile uint32_t DENALI_PI_106;
-	volatile uint32_t DENALI_PI_107;
-	volatile uint32_t DENALI_PI_108;
-	volatile uint32_t DENALI_PI_109;
-	volatile uint32_t DENALI_PI_110;
-	volatile uint32_t DENALI_PI_111;
-	volatile uint32_t DENALI_PI_112;
-	volatile uint32_t DENALI_PI_113;
-	volatile uint32_t DENALI_PI_114;
-	volatile uint32_t DENALI_PI_115;
-	volatile uint32_t DENALI_PI_116;
-	volatile uint32_t DENALI_PI_117;
-	volatile uint32_t DENALI_PI_118;
-	volatile uint32_t DENALI_PI_119;
-	volatile uint32_t DENALI_PI_120;
-	volatile uint32_t DENALI_PI_121;
-	volatile uint32_t DENALI_PI_122;
-	volatile uint32_t DENALI_PI_123;
-	volatile uint32_t DENALI_PI_124;
-	volatile uint32_t DENALI_PI_125;
-	volatile uint32_t DENALI_PI_126;
-	volatile uint32_t DENALI_PI_127;
-	volatile uint32_t DENALI_PI_128;
-	volatile uint32_t DENALI_PI_129;
-	volatile uint32_t DENALI_PI_130;
-	volatile uint32_t DENALI_PI_131;
-	volatile uint32_t DENALI_PI_132;
-	volatile uint32_t DENALI_PI_133;
-	volatile uint32_t DENALI_PI_134;
-	volatile uint32_t DENALI_PI_135;
-	volatile uint32_t DENALI_PI_136;
-	volatile uint32_t DENALI_PI_137;
-	volatile uint32_t DENALI_PI_138;
-	volatile uint32_t DENALI_PI_139;
-	volatile uint32_t DENALI_PI_140;
-	volatile uint32_t DENALI_PI_141;
-	volatile uint32_t DENALI_PI_142;
-	volatile uint32_t DENALI_PI_143;
-	volatile uint32_t DENALI_PI_144;
-	volatile uint32_t DENALI_PI_145;
-	volatile uint32_t DENALI_PI_146;
-	volatile uint32_t DENALI_PI_147;
-	volatile uint32_t DENALI_PI_148;
-	volatile uint32_t DENALI_PI_149;
-	volatile uint32_t DENALI_PI_150;
-	volatile uint32_t DENALI_PI_151;
-	volatile uint32_t DENALI_PI_152;
-	volatile uint32_t DENALI_PI_153;
-	volatile uint32_t DENALI_PI_154;
-	volatile uint32_t DENALI_PI_155;
-	volatile uint32_t DENALI_PI_156;
-	volatile uint32_t DENALI_PI_157;
-	volatile uint32_t DENALI_PI_158;
-	volatile uint32_t DENALI_PI_159;
-	volatile uint32_t DENALI_PI_160;
-	volatile uint32_t DENALI_PI_161;
-	volatile uint32_t DENALI_PI_162;
-	volatile uint32_t DENALI_PI_163;
-	volatile uint32_t DENALI_PI_164;
-	volatile uint32_t DENALI_PI_165;
-	volatile uint32_t DENALI_PI_166;
-	volatile uint32_t DENALI_PI_167;
-	volatile uint32_t DENALI_PI_168;
-	volatile uint32_t DENALI_PI_169;
-	volatile uint32_t DENALI_PI_170;
-	volatile uint32_t DENALI_PI_171;
-	volatile uint32_t DENALI_PI_172;
-	volatile uint32_t DENALI_PI_173;
-	volatile uint32_t DENALI_PI_174;
-	volatile uint32_t DENALI_PI_175;
-	volatile uint32_t DENALI_PI_176;
-	volatile uint32_t DENALI_PI_177;
-	volatile uint32_t DENALI_PI_178;
-	volatile uint32_t DENALI_PI_179;
-	volatile uint32_t DENALI_PI_180;
-	volatile uint32_t DENALI_PI_181;
-	volatile uint32_t DENALI_PI_182;
-	volatile uint32_t DENALI_PI_183;
-	volatile uint32_t DENALI_PI_184;
-	volatile uint32_t DENALI_PI_185;
-	volatile uint32_t DENALI_PI_186;
-	volatile uint32_t DENALI_PI_187;
-	volatile uint32_t DENALI_PI_188;
-	volatile uint32_t DENALI_PI_189;
-	volatile uint32_t DENALI_PI_190;
-	volatile uint32_t DENALI_PI_191;
-	volatile uint32_t DENALI_PI_192;
-	volatile uint32_t DENALI_PI_193;
-	volatile uint32_t DENALI_PI_194;
-	volatile uint32_t DENALI_PI_195;
-	volatile uint32_t DENALI_PI_196;
-	volatile uint32_t DENALI_PI_197;
-	volatile uint32_t DENALI_PI_198;
-	volatile uint32_t DENALI_PI_199;
-	volatile uint32_t DENALI_PI_200;
-	volatile uint32_t DENALI_PI_201;
-	volatile uint32_t DENALI_PI_202;
-	volatile uint32_t DENALI_PI_203;
-	volatile uint32_t DENALI_PI_204;
-	volatile uint32_t DENALI_PI_205;
-	volatile uint32_t DENALI_PI_206;
-	volatile uint32_t DENALI_PI_207;
-	volatile uint32_t DENALI_PI_208;
-	volatile uint32_t DENALI_PI_209;
-	volatile uint32_t DENALI_PI_210;
-	volatile uint32_t DENALI_PI_211;
-	volatile uint32_t DENALI_PI_212;
-	volatile uint32_t DENALI_PI_213;
-	volatile uint32_t DENALI_PI_214;
-	volatile uint32_t DENALI_PI_215;
-	volatile uint32_t DENALI_PI_216;
-	volatile uint32_t DENALI_PI_217;
-	volatile uint32_t DENALI_PI_218;
-	volatile uint32_t DENALI_PI_219;
-	volatile uint32_t DENALI_PI_220;
-	volatile uint32_t DENALI_PI_221;
-	volatile uint32_t DENALI_PI_222;
-	volatile uint32_t DENALI_PI_223;
-	volatile uint32_t DENALI_PI_224;
-	volatile uint32_t DENALI_PI_225;
-	volatile uint32_t DENALI_PI_226;
-	volatile uint32_t DENALI_PI_227;
-	volatile uint32_t DENALI_PI_228;
-	volatile uint32_t DENALI_PI_229;
-	volatile uint32_t DENALI_PI_230;
-	volatile uint32_t DENALI_PI_231;
-	volatile uint32_t DENALI_PI_232;
-	volatile uint32_t DENALI_PI_233;
-	volatile uint32_t DENALI_PI_234;
-	volatile uint32_t DENALI_PI_235;
-	volatile uint32_t DENALI_PI_236;
-	volatile uint32_t DENALI_PI_237;
-	volatile uint32_t DENALI_PI_238;
-	volatile uint32_t DENALI_PI_239;
-	volatile uint32_t DENALI_PI_240;
-	volatile uint32_t DENALI_PI_241;
-	volatile uint32_t DENALI_PI_242;
-	volatile uint32_t DENALI_PI_243;
-	volatile uint32_t DENALI_PI_244;
-	volatile uint32_t DENALI_PI_245;
-	volatile uint32_t DENALI_PI_246;
-	volatile uint32_t DENALI_PI_247;
-	volatile uint32_t DENALI_PI_248;
-	volatile uint32_t DENALI_PI_249;
-	volatile uint32_t DENALI_PI_250;
-	volatile uint32_t DENALI_PI_251;
-	volatile uint32_t DENALI_PI_252;
-	volatile uint32_t DENALI_PI_253;
-	volatile uint32_t DENALI_PI_254;
-	volatile uint32_t DENALI_PI_255;
-	volatile uint32_t DENALI_PI_256;
-	volatile uint32_t DENALI_PI_257;
-	volatile uint32_t DENALI_PI_258;
-	volatile uint32_t DENALI_PI_259;
-	volatile uint32_t DENALI_PI_260;
-	volatile uint32_t DENALI_PI_261;
-	volatile uint32_t DENALI_PI_262;
-	volatile uint32_t DENALI_PI_263;
-	volatile uint32_t DENALI_PI_264;
-	volatile uint32_t DENALI_PI_265;
-	volatile uint32_t DENALI_PI_266;
-	volatile uint32_t DENALI_PI_267;
-	volatile uint32_t DENALI_PI_268;
-	volatile uint32_t DENALI_PI_269;
-	volatile uint32_t DENALI_PI_270;
-	volatile uint32_t DENALI_PI_271;
-	volatile uint32_t DENALI_PI_272;
-	volatile uint32_t DENALI_PI_273;
-	volatile uint32_t DENALI_PI_274;
-	volatile uint32_t DENALI_PI_275;
-	volatile uint32_t DENALI_PI_276;
-	volatile uint32_t DENALI_PI_277;
-	volatile uint32_t DENALI_PI_278;
-	volatile uint32_t DENALI_PI_279;
-	volatile uint32_t DENALI_PI_280;
-	volatile uint32_t DENALI_PI_281;
-	volatile uint32_t DENALI_PI_282;
-	volatile uint32_t DENALI_PI_283;
-	volatile uint32_t DENALI_PI_284;
-	volatile uint32_t DENALI_PI_285;
-	volatile uint32_t DENALI_PI_286;
-	volatile uint32_t DENALI_PI_287;
-	volatile uint32_t DENALI_PI_288;
-	volatile uint32_t DENALI_PI_289;
-	volatile uint32_t DENALI_PI_290;
-	volatile uint32_t DENALI_PI_291;
-	volatile uint32_t DENALI_PI_292;
-	volatile uint32_t DENALI_PI_293;
-	volatile uint32_t DENALI_PI_294;
-	volatile uint32_t DENALI_PI_295;
-	volatile uint32_t DENALI_PI_296;
-	volatile uint32_t DENALI_PI_297;
-	volatile uint32_t DENALI_PI_298;
-	volatile uint32_t DENALI_PI_299;
-	volatile char pad__1[0x1B50U];
-	volatile uint32_t DENALI_PHY_0;
-	volatile uint32_t DENALI_PHY_1;
-	volatile uint32_t DENALI_PHY_2;
-	volatile uint32_t DENALI_PHY_3;
-	volatile uint32_t DENALI_PHY_4;
-	volatile uint32_t DENALI_PHY_5;
-	volatile uint32_t DENALI_PHY_6;
-	volatile uint32_t DENALI_PHY_7;
-	volatile uint32_t DENALI_PHY_8;
-	volatile uint32_t DENALI_PHY_9;
-	volatile uint32_t DENALI_PHY_10;
-	volatile uint32_t DENALI_PHY_11;
-	volatile uint32_t DENALI_PHY_12;
-	volatile uint32_t DENALI_PHY_13;
-	volatile uint32_t DENALI_PHY_14;
-	volatile uint32_t DENALI_PHY_15;
-	volatile uint32_t DENALI_PHY_16;
-	volatile uint32_t DENALI_PHY_17;
-	volatile uint32_t DENALI_PHY_18;
-	volatile uint32_t DENALI_PHY_19;
-	volatile uint32_t DENALI_PHY_20;
-	volatile uint32_t DENALI_PHY_21;
-	volatile uint32_t DENALI_PHY_22;
-	volatile uint32_t DENALI_PHY_23;
-	volatile uint32_t DENALI_PHY_24;
-	volatile uint32_t DENALI_PHY_25;
-	volatile uint32_t DENALI_PHY_26;
-	volatile uint32_t DENALI_PHY_27;
-	volatile uint32_t DENALI_PHY_28;
-	volatile uint32_t DENALI_PHY_29;
-	volatile uint32_t DENALI_PHY_30;
-	volatile uint32_t DENALI_PHY_31;
-	volatile uint32_t DENALI_PHY_32;
-	volatile uint32_t DENALI_PHY_33;
-	volatile uint32_t DENALI_PHY_34;
-	volatile uint32_t DENALI_PHY_35;
-	volatile uint32_t DENALI_PHY_36;
-	volatile uint32_t DENALI_PHY_37;
-	volatile uint32_t DENALI_PHY_38;
-	volatile uint32_t DENALI_PHY_39;
-	volatile uint32_t DENALI_PHY_40;
-	volatile uint32_t DENALI_PHY_41;
-	volatile uint32_t DENALI_PHY_42;
-	volatile uint32_t DENALI_PHY_43;
-	volatile uint32_t DENALI_PHY_44;
-	volatile uint32_t DENALI_PHY_45;
-	volatile uint32_t DENALI_PHY_46;
-	volatile uint32_t DENALI_PHY_47;
-	volatile uint32_t DENALI_PHY_48;
-	volatile uint32_t DENALI_PHY_49;
-	volatile uint32_t DENALI_PHY_50;
-	volatile uint32_t DENALI_PHY_51;
-	volatile uint32_t DENALI_PHY_52;
-	volatile uint32_t DENALI_PHY_53;
-	volatile uint32_t DENALI_PHY_54;
-	volatile uint32_t DENALI_PHY_55;
-	volatile uint32_t DENALI_PHY_56;
-	volatile uint32_t DENALI_PHY_57;
-	volatile uint32_t DENALI_PHY_58;
-	volatile uint32_t DENALI_PHY_59;
-	volatile uint32_t DENALI_PHY_60;
-	volatile uint32_t DENALI_PHY_61;
-	volatile uint32_t DENALI_PHY_62;
-	volatile uint32_t DENALI_PHY_63;
-	volatile uint32_t DENALI_PHY_64;
-	volatile uint32_t DENALI_PHY_65;
-	volatile uint32_t DENALI_PHY_66;
-	volatile uint32_t DENALI_PHY_67;
-	volatile uint32_t DENALI_PHY_68;
-	volatile uint32_t DENALI_PHY_69;
-	volatile uint32_t DENALI_PHY_70;
-	volatile uint32_t DENALI_PHY_71;
-	volatile uint32_t DENALI_PHY_72;
-	volatile uint32_t DENALI_PHY_73;
-	volatile uint32_t DENALI_PHY_74;
-	volatile uint32_t DENALI_PHY_75;
-	volatile uint32_t DENALI_PHY_76;
-	volatile uint32_t DENALI_PHY_77;
-	volatile uint32_t DENALI_PHY_78;
-	volatile uint32_t DENALI_PHY_79;
-	volatile uint32_t DENALI_PHY_80;
-	volatile uint32_t DENALI_PHY_81;
-	volatile uint32_t DENALI_PHY_82;
-	volatile uint32_t DENALI_PHY_83;
-	volatile uint32_t DENALI_PHY_84;
-	volatile uint32_t DENALI_PHY_85;
-	volatile uint32_t DENALI_PHY_86;
-	volatile uint32_t DENALI_PHY_87;
-	volatile uint32_t DENALI_PHY_88;
-	volatile uint32_t DENALI_PHY_89;
-	volatile uint32_t DENALI_PHY_90;
-	volatile uint32_t DENALI_PHY_91;
-	volatile uint32_t DENALI_PHY_92;
-	volatile uint32_t DENALI_PHY_93;
-	volatile uint32_t DENALI_PHY_94;
-	volatile uint32_t DENALI_PHY_95;
-	volatile uint32_t DENALI_PHY_96;
-	volatile uint32_t DENALI_PHY_97;
-	volatile uint32_t DENALI_PHY_98;
-	volatile uint32_t DENALI_PHY_99;
-	volatile uint32_t DENALI_PHY_100;
-	volatile uint32_t DENALI_PHY_101;
-	volatile uint32_t DENALI_PHY_102;
-	volatile uint32_t DENALI_PHY_103;
-	volatile uint32_t DENALI_PHY_104;
-	volatile uint32_t DENALI_PHY_105;
-	volatile uint32_t DENALI_PHY_106;
-	volatile uint32_t DENALI_PHY_107;
-	volatile uint32_t DENALI_PHY_108;
-	volatile uint32_t DENALI_PHY_109;
-	volatile uint32_t DENALI_PHY_110;
-	volatile uint32_t DENALI_PHY_111;
-	volatile uint32_t DENALI_PHY_112;
-	volatile uint32_t DENALI_PHY_113;
-	volatile uint32_t DENALI_PHY_114;
-	volatile uint32_t DENALI_PHY_115;
-	volatile uint32_t DENALI_PHY_116;
-	volatile uint32_t DENALI_PHY_117;
-	volatile uint32_t DENALI_PHY_118;
-	volatile uint32_t DENALI_PHY_119;
-	volatile uint32_t DENALI_PHY_120;
-	volatile uint32_t DENALI_PHY_121;
-	volatile uint32_t DENALI_PHY_122;
-	volatile uint32_t DENALI_PHY_123;
-	volatile uint32_t DENALI_PHY_124;
-	volatile uint32_t DENALI_PHY_125;
-	volatile uint32_t DENALI_PHY_126;
-	volatile uint32_t DENALI_PHY_127;
-	volatile uint32_t DENALI_PHY_128;
-	volatile uint32_t DENALI_PHY_129;
-	volatile uint32_t DENALI_PHY_130;
-	volatile uint32_t DENALI_PHY_131;
-	volatile uint32_t DENALI_PHY_132;
-	volatile uint32_t DENALI_PHY_133;
-	volatile uint32_t DENALI_PHY_134;
-	volatile uint32_t DENALI_PHY_135;
-	volatile uint32_t DENALI_PHY_136;
-	volatile uint32_t DENALI_PHY_137;
-	volatile uint32_t DENALI_PHY_138;
-	volatile uint32_t DENALI_PHY_139;
-	volatile char pad__2[0x1D0U];
-	volatile uint32_t DENALI_PHY_256;
-	volatile uint32_t DENALI_PHY_257;
-	volatile uint32_t DENALI_PHY_258;
-	volatile uint32_t DENALI_PHY_259;
-	volatile uint32_t DENALI_PHY_260;
-	volatile uint32_t DENALI_PHY_261;
-	volatile uint32_t DENALI_PHY_262;
-	volatile uint32_t DENALI_PHY_263;
-	volatile uint32_t DENALI_PHY_264;
-	volatile uint32_t DENALI_PHY_265;
-	volatile uint32_t DENALI_PHY_266;
-	volatile uint32_t DENALI_PHY_267;
-	volatile uint32_t DENALI_PHY_268;
-	volatile uint32_t DENALI_PHY_269;
-	volatile uint32_t DENALI_PHY_270;
-	volatile uint32_t DENALI_PHY_271;
-	volatile uint32_t DENALI_PHY_272;
-	volatile uint32_t DENALI_PHY_273;
-	volatile uint32_t DENALI_PHY_274;
-	volatile uint32_t DENALI_PHY_275;
-	volatile uint32_t DENALI_PHY_276;
-	volatile uint32_t DENALI_PHY_277;
-	volatile uint32_t DENALI_PHY_278;
-	volatile uint32_t DENALI_PHY_279;
-	volatile uint32_t DENALI_PHY_280;
-	volatile uint32_t DENALI_PHY_281;
-	volatile uint32_t DENALI_PHY_282;
-	volatile uint32_t DENALI_PHY_283;
-	volatile uint32_t DENALI_PHY_284;
-	volatile uint32_t DENALI_PHY_285;
-	volatile uint32_t DENALI_PHY_286;
-	volatile uint32_t DENALI_PHY_287;
-	volatile uint32_t DENALI_PHY_288;
-	volatile uint32_t DENALI_PHY_289;
-	volatile uint32_t DENALI_PHY_290;
-	volatile uint32_t DENALI_PHY_291;
-	volatile uint32_t DENALI_PHY_292;
-	volatile uint32_t DENALI_PHY_293;
-	volatile uint32_t DENALI_PHY_294;
-	volatile uint32_t DENALI_PHY_295;
-	volatile uint32_t DENALI_PHY_296;
-	volatile uint32_t DENALI_PHY_297;
-	volatile uint32_t DENALI_PHY_298;
-	volatile uint32_t DENALI_PHY_299;
-	volatile uint32_t DENALI_PHY_300;
-	volatile uint32_t DENALI_PHY_301;
-	volatile uint32_t DENALI_PHY_302;
-	volatile uint32_t DENALI_PHY_303;
-	volatile uint32_t DENALI_PHY_304;
-	volatile uint32_t DENALI_PHY_305;
-	volatile uint32_t DENALI_PHY_306;
-	volatile uint32_t DENALI_PHY_307;
-	volatile uint32_t DENALI_PHY_308;
-	volatile uint32_t DENALI_PHY_309;
-	volatile uint32_t DENALI_PHY_310;
-	volatile uint32_t DENALI_PHY_311;
-	volatile uint32_t DENALI_PHY_312;
-	volatile uint32_t DENALI_PHY_313;
-	volatile uint32_t DENALI_PHY_314;
-	volatile uint32_t DENALI_PHY_315;
-	volatile uint32_t DENALI_PHY_316;
-	volatile uint32_t DENALI_PHY_317;
-	volatile uint32_t DENALI_PHY_318;
-	volatile uint32_t DENALI_PHY_319;
-	volatile uint32_t DENALI_PHY_320;
-	volatile uint32_t DENALI_PHY_321;
-	volatile uint32_t DENALI_PHY_322;
-	volatile uint32_t DENALI_PHY_323;
-	volatile uint32_t DENALI_PHY_324;
-	volatile uint32_t DENALI_PHY_325;
-	volatile uint32_t DENALI_PHY_326;
-	volatile uint32_t DENALI_PHY_327;
-	volatile uint32_t DENALI_PHY_328;
-	volatile uint32_t DENALI_PHY_329;
-	volatile uint32_t DENALI_PHY_330;
-	volatile uint32_t DENALI_PHY_331;
-	volatile uint32_t DENALI_PHY_332;
-	volatile uint32_t DENALI_PHY_333;
-	volatile uint32_t DENALI_PHY_334;
-	volatile uint32_t DENALI_PHY_335;
-	volatile uint32_t DENALI_PHY_336;
-	volatile uint32_t DENALI_PHY_337;
-	volatile uint32_t DENALI_PHY_338;
-	volatile uint32_t DENALI_PHY_339;
-	volatile uint32_t DENALI_PHY_340;
-	volatile uint32_t DENALI_PHY_341;
-	volatile uint32_t DENALI_PHY_342;
-	volatile uint32_t DENALI_PHY_343;
-	volatile uint32_t DENALI_PHY_344;
-	volatile uint32_t DENALI_PHY_345;
-	volatile uint32_t DENALI_PHY_346;
-	volatile uint32_t DENALI_PHY_347;
-	volatile uint32_t DENALI_PHY_348;
-	volatile uint32_t DENALI_PHY_349;
-	volatile uint32_t DENALI_PHY_350;
-	volatile uint32_t DENALI_PHY_351;
-	volatile uint32_t DENALI_PHY_352;
-	volatile uint32_t DENALI_PHY_353;
-	volatile uint32_t DENALI_PHY_354;
-	volatile uint32_t DENALI_PHY_355;
-	volatile uint32_t DENALI_PHY_356;
-	volatile uint32_t DENALI_PHY_357;
-	volatile uint32_t DENALI_PHY_358;
-	volatile uint32_t DENALI_PHY_359;
-	volatile uint32_t DENALI_PHY_360;
-	volatile uint32_t DENALI_PHY_361;
-	volatile uint32_t DENALI_PHY_362;
-	volatile uint32_t DENALI_PHY_363;
-	volatile uint32_t DENALI_PHY_364;
-	volatile uint32_t DENALI_PHY_365;
-	volatile uint32_t DENALI_PHY_366;
-	volatile uint32_t DENALI_PHY_367;
-	volatile uint32_t DENALI_PHY_368;
-	volatile uint32_t DENALI_PHY_369;
-	volatile uint32_t DENALI_PHY_370;
-	volatile uint32_t DENALI_PHY_371;
-	volatile uint32_t DENALI_PHY_372;
-	volatile uint32_t DENALI_PHY_373;
-	volatile uint32_t DENALI_PHY_374;
-	volatile uint32_t DENALI_PHY_375;
-	volatile uint32_t DENALI_PHY_376;
-	volatile uint32_t DENALI_PHY_377;
-	volatile uint32_t DENALI_PHY_378;
-	volatile uint32_t DENALI_PHY_379;
-	volatile uint32_t DENALI_PHY_380;
-	volatile uint32_t DENALI_PHY_381;
-	volatile uint32_t DENALI_PHY_382;
-	volatile uint32_t DENALI_PHY_383;
-	volatile uint32_t DENALI_PHY_384;
-	volatile uint32_t DENALI_PHY_385;
-	volatile uint32_t DENALI_PHY_386;
-	volatile uint32_t DENALI_PHY_387;
-	volatile uint32_t DENALI_PHY_388;
-	volatile uint32_t DENALI_PHY_389;
-	volatile uint32_t DENALI_PHY_390;
-	volatile uint32_t DENALI_PHY_391;
-	volatile uint32_t DENALI_PHY_392;
-	volatile uint32_t DENALI_PHY_393;
-	volatile uint32_t DENALI_PHY_394;
-	volatile uint32_t DENALI_PHY_395;
-	volatile char pad__3[0x1D0U];
-	volatile uint32_t DENALI_PHY_512;
-	volatile uint32_t DENALI_PHY_513;
-	volatile uint32_t DENALI_PHY_514;
-	volatile uint32_t DENALI_PHY_515;
-	volatile uint32_t DENALI_PHY_516;
-	volatile uint32_t DENALI_PHY_517;
-	volatile uint32_t DENALI_PHY_518;
-	volatile uint32_t DENALI_PHY_519;
-	volatile uint32_t DENALI_PHY_520;
-	volatile uint32_t DENALI_PHY_521;
-	volatile uint32_t DENALI_PHY_522;
-	volatile uint32_t DENALI_PHY_523;
-	volatile uint32_t DENALI_PHY_524;
-	volatile uint32_t DENALI_PHY_525;
-	volatile uint32_t DENALI_PHY_526;
-	volatile uint32_t DENALI_PHY_527;
-	volatile uint32_t DENALI_PHY_528;
-	volatile uint32_t DENALI_PHY_529;
-	volatile uint32_t DENALI_PHY_530;
-	volatile uint32_t DENALI_PHY_531;
-	volatile uint32_t DENALI_PHY_532;
-	volatile uint32_t DENALI_PHY_533;
-	volatile uint32_t DENALI_PHY_534;
-	volatile uint32_t DENALI_PHY_535;
-	volatile uint32_t DENALI_PHY_536;
-	volatile uint32_t DENALI_PHY_537;
-	volatile uint32_t DENALI_PHY_538;
-	volatile uint32_t DENALI_PHY_539;
-	volatile uint32_t DENALI_PHY_540;
-	volatile uint32_t DENALI_PHY_541;
-	volatile uint32_t DENALI_PHY_542;
-	volatile uint32_t DENALI_PHY_543;
-	volatile uint32_t DENALI_PHY_544;
-	volatile uint32_t DENALI_PHY_545;
-	volatile uint32_t DENALI_PHY_546;
-	volatile uint32_t DENALI_PHY_547;
-	volatile uint32_t DENALI_PHY_548;
-	volatile uint32_t DENALI_PHY_549;
-	volatile uint32_t DENALI_PHY_550;
-	volatile uint32_t DENALI_PHY_551;
-	volatile uint32_t DENALI_PHY_552;
-	volatile uint32_t DENALI_PHY_553;
-	volatile uint32_t DENALI_PHY_554;
-	volatile uint32_t DENALI_PHY_555;
-	volatile uint32_t DENALI_PHY_556;
-	volatile uint32_t DENALI_PHY_557;
-	volatile uint32_t DENALI_PHY_558;
-	volatile uint32_t DENALI_PHY_559;
-	volatile uint32_t DENALI_PHY_560;
-	volatile uint32_t DENALI_PHY_561;
-	volatile uint32_t DENALI_PHY_562;
-	volatile uint32_t DENALI_PHY_563;
-	volatile uint32_t DENALI_PHY_564;
-	volatile uint32_t DENALI_PHY_565;
-	volatile uint32_t DENALI_PHY_566;
-	volatile uint32_t DENALI_PHY_567;
-	volatile uint32_t DENALI_PHY_568;
-	volatile uint32_t DENALI_PHY_569;
-	volatile uint32_t DENALI_PHY_570;
-	volatile uint32_t DENALI_PHY_571;
-	volatile uint32_t DENALI_PHY_572;
-	volatile uint32_t DENALI_PHY_573;
-	volatile uint32_t DENALI_PHY_574;
-	volatile uint32_t DENALI_PHY_575;
-	volatile uint32_t DENALI_PHY_576;
-	volatile uint32_t DENALI_PHY_577;
-	volatile uint32_t DENALI_PHY_578;
-	volatile uint32_t DENALI_PHY_579;
-	volatile uint32_t DENALI_PHY_580;
-	volatile uint32_t DENALI_PHY_581;
-	volatile uint32_t DENALI_PHY_582;
-	volatile uint32_t DENALI_PHY_583;
-	volatile uint32_t DENALI_PHY_584;
-	volatile uint32_t DENALI_PHY_585;
-	volatile uint32_t DENALI_PHY_586;
-	volatile uint32_t DENALI_PHY_587;
-	volatile uint32_t DENALI_PHY_588;
-	volatile uint32_t DENALI_PHY_589;
-	volatile uint32_t DENALI_PHY_590;
-	volatile uint32_t DENALI_PHY_591;
-	volatile uint32_t DENALI_PHY_592;
-	volatile uint32_t DENALI_PHY_593;
-	volatile uint32_t DENALI_PHY_594;
-	volatile uint32_t DENALI_PHY_595;
-	volatile uint32_t DENALI_PHY_596;
-	volatile uint32_t DENALI_PHY_597;
-	volatile uint32_t DENALI_PHY_598;
-	volatile uint32_t DENALI_PHY_599;
-	volatile uint32_t DENALI_PHY_600;
-	volatile uint32_t DENALI_PHY_601;
-	volatile uint32_t DENALI_PHY_602;
-	volatile uint32_t DENALI_PHY_603;
-	volatile uint32_t DENALI_PHY_604;
-	volatile uint32_t DENALI_PHY_605;
-	volatile uint32_t DENALI_PHY_606;
-	volatile uint32_t DENALI_PHY_607;
-	volatile uint32_t DENALI_PHY_608;
-	volatile uint32_t DENALI_PHY_609;
-	volatile uint32_t DENALI_PHY_610;
-	volatile uint32_t DENALI_PHY_611;
-	volatile uint32_t DENALI_PHY_612;
-	volatile uint32_t DENALI_PHY_613;
-	volatile uint32_t DENALI_PHY_614;
-	volatile uint32_t DENALI_PHY_615;
-	volatile uint32_t DENALI_PHY_616;
-	volatile uint32_t DENALI_PHY_617;
-	volatile uint32_t DENALI_PHY_618;
-	volatile uint32_t DENALI_PHY_619;
-	volatile uint32_t DENALI_PHY_620;
-	volatile uint32_t DENALI_PHY_621;
-	volatile uint32_t DENALI_PHY_622;
-	volatile uint32_t DENALI_PHY_623;
-	volatile uint32_t DENALI_PHY_624;
-	volatile uint32_t DENALI_PHY_625;
-	volatile uint32_t DENALI_PHY_626;
-	volatile uint32_t DENALI_PHY_627;
-	volatile uint32_t DENALI_PHY_628;
-	volatile uint32_t DENALI_PHY_629;
-	volatile uint32_t DENALI_PHY_630;
-	volatile uint32_t DENALI_PHY_631;
-	volatile uint32_t DENALI_PHY_632;
-	volatile uint32_t DENALI_PHY_633;
-	volatile uint32_t DENALI_PHY_634;
-	volatile uint32_t DENALI_PHY_635;
-	volatile uint32_t DENALI_PHY_636;
-	volatile uint32_t DENALI_PHY_637;
-	volatile uint32_t DENALI_PHY_638;
-	volatile uint32_t DENALI_PHY_639;
-	volatile uint32_t DENALI_PHY_640;
-	volatile uint32_t DENALI_PHY_641;
-	volatile uint32_t DENALI_PHY_642;
-	volatile uint32_t DENALI_PHY_643;
-	volatile uint32_t DENALI_PHY_644;
-	volatile uint32_t DENALI_PHY_645;
-	volatile uint32_t DENALI_PHY_646;
-	volatile uint32_t DENALI_PHY_647;
-	volatile uint32_t DENALI_PHY_648;
-	volatile uint32_t DENALI_PHY_649;
-	volatile uint32_t DENALI_PHY_650;
-	volatile uint32_t DENALI_PHY_651;
-	volatile char pad__4[0x1D0U];
-	volatile uint32_t DENALI_PHY_768;
-	volatile uint32_t DENALI_PHY_769;
-	volatile uint32_t DENALI_PHY_770;
-	volatile uint32_t DENALI_PHY_771;
-	volatile uint32_t DENALI_PHY_772;
-	volatile uint32_t DENALI_PHY_773;
-	volatile uint32_t DENALI_PHY_774;
-	volatile uint32_t DENALI_PHY_775;
-	volatile uint32_t DENALI_PHY_776;
-	volatile uint32_t DENALI_PHY_777;
-	volatile uint32_t DENALI_PHY_778;
-	volatile uint32_t DENALI_PHY_779;
-	volatile uint32_t DENALI_PHY_780;
-	volatile uint32_t DENALI_PHY_781;
-	volatile uint32_t DENALI_PHY_782;
-	volatile uint32_t DENALI_PHY_783;
-	volatile uint32_t DENALI_PHY_784;
-	volatile uint32_t DENALI_PHY_785;
-	volatile uint32_t DENALI_PHY_786;
-	volatile uint32_t DENALI_PHY_787;
-	volatile uint32_t DENALI_PHY_788;
-	volatile uint32_t DENALI_PHY_789;
-	volatile uint32_t DENALI_PHY_790;
-	volatile uint32_t DENALI_PHY_791;
-	volatile uint32_t DENALI_PHY_792;
-	volatile uint32_t DENALI_PHY_793;
-	volatile uint32_t DENALI_PHY_794;
-	volatile uint32_t DENALI_PHY_795;
-	volatile uint32_t DENALI_PHY_796;
-	volatile uint32_t DENALI_PHY_797;
-	volatile uint32_t DENALI_PHY_798;
-	volatile uint32_t DENALI_PHY_799;
-	volatile uint32_t DENALI_PHY_800;
-	volatile uint32_t DENALI_PHY_801;
-	volatile uint32_t DENALI_PHY_802;
-	volatile uint32_t DENALI_PHY_803;
-	volatile uint32_t DENALI_PHY_804;
-	volatile uint32_t DENALI_PHY_805;
-	volatile uint32_t DENALI_PHY_806;
-	volatile uint32_t DENALI_PHY_807;
-	volatile uint32_t DENALI_PHY_808;
-	volatile uint32_t DENALI_PHY_809;
-	volatile uint32_t DENALI_PHY_810;
-	volatile uint32_t DENALI_PHY_811;
-	volatile uint32_t DENALI_PHY_812;
-	volatile uint32_t DENALI_PHY_813;
-	volatile uint32_t DENALI_PHY_814;
-	volatile uint32_t DENALI_PHY_815;
-	volatile uint32_t DENALI_PHY_816;
-	volatile uint32_t DENALI_PHY_817;
-	volatile uint32_t DENALI_PHY_818;
-	volatile uint32_t DENALI_PHY_819;
-	volatile uint32_t DENALI_PHY_820;
-	volatile uint32_t DENALI_PHY_821;
-	volatile uint32_t DENALI_PHY_822;
-	volatile uint32_t DENALI_PHY_823;
-	volatile uint32_t DENALI_PHY_824;
-	volatile uint32_t DENALI_PHY_825;
-	volatile uint32_t DENALI_PHY_826;
-	volatile uint32_t DENALI_PHY_827;
-	volatile uint32_t DENALI_PHY_828;
-	volatile uint32_t DENALI_PHY_829;
-	volatile uint32_t DENALI_PHY_830;
-	volatile uint32_t DENALI_PHY_831;
-	volatile uint32_t DENALI_PHY_832;
-	volatile uint32_t DENALI_PHY_833;
-	volatile uint32_t DENALI_PHY_834;
-	volatile uint32_t DENALI_PHY_835;
-	volatile uint32_t DENALI_PHY_836;
-	volatile uint32_t DENALI_PHY_837;
-	volatile uint32_t DENALI_PHY_838;
-	volatile uint32_t DENALI_PHY_839;
-	volatile uint32_t DENALI_PHY_840;
-	volatile uint32_t DENALI_PHY_841;
-	volatile uint32_t DENALI_PHY_842;
-	volatile uint32_t DENALI_PHY_843;
-	volatile uint32_t DENALI_PHY_844;
-	volatile uint32_t DENALI_PHY_845;
-	volatile uint32_t DENALI_PHY_846;
-	volatile uint32_t DENALI_PHY_847;
-	volatile uint32_t DENALI_PHY_848;
-	volatile uint32_t DENALI_PHY_849;
-	volatile uint32_t DENALI_PHY_850;
-	volatile uint32_t DENALI_PHY_851;
-	volatile uint32_t DENALI_PHY_852;
-	volatile uint32_t DENALI_PHY_853;
-	volatile uint32_t DENALI_PHY_854;
-	volatile uint32_t DENALI_PHY_855;
-	volatile uint32_t DENALI_PHY_856;
-	volatile uint32_t DENALI_PHY_857;
-	volatile uint32_t DENALI_PHY_858;
-	volatile uint32_t DENALI_PHY_859;
-	volatile uint32_t DENALI_PHY_860;
-	volatile uint32_t DENALI_PHY_861;
-	volatile uint32_t DENALI_PHY_862;
-	volatile uint32_t DENALI_PHY_863;
-	volatile uint32_t DENALI_PHY_864;
-	volatile uint32_t DENALI_PHY_865;
-	volatile uint32_t DENALI_PHY_866;
-	volatile uint32_t DENALI_PHY_867;
-	volatile uint32_t DENALI_PHY_868;
-	volatile uint32_t DENALI_PHY_869;
-	volatile uint32_t DENALI_PHY_870;
-	volatile uint32_t DENALI_PHY_871;
-	volatile uint32_t DENALI_PHY_872;
-	volatile uint32_t DENALI_PHY_873;
-	volatile uint32_t DENALI_PHY_874;
-	volatile uint32_t DENALI_PHY_875;
-	volatile uint32_t DENALI_PHY_876;
-	volatile uint32_t DENALI_PHY_877;
-	volatile uint32_t DENALI_PHY_878;
-	volatile uint32_t DENALI_PHY_879;
-	volatile uint32_t DENALI_PHY_880;
-	volatile uint32_t DENALI_PHY_881;
-	volatile uint32_t DENALI_PHY_882;
-	volatile uint32_t DENALI_PHY_883;
-	volatile uint32_t DENALI_PHY_884;
-	volatile uint32_t DENALI_PHY_885;
-	volatile uint32_t DENALI_PHY_886;
-	volatile uint32_t DENALI_PHY_887;
-	volatile uint32_t DENALI_PHY_888;
-	volatile uint32_t DENALI_PHY_889;
-	volatile uint32_t DENALI_PHY_890;
-	volatile uint32_t DENALI_PHY_891;
-	volatile uint32_t DENALI_PHY_892;
-	volatile uint32_t DENALI_PHY_893;
-	volatile uint32_t DENALI_PHY_894;
-	volatile uint32_t DENALI_PHY_895;
-	volatile uint32_t DENALI_PHY_896;
-	volatile uint32_t DENALI_PHY_897;
-	volatile uint32_t DENALI_PHY_898;
-	volatile uint32_t DENALI_PHY_899;
-	volatile uint32_t DENALI_PHY_900;
-	volatile uint32_t DENALI_PHY_901;
-	volatile uint32_t DENALI_PHY_902;
-	volatile uint32_t DENALI_PHY_903;
-	volatile uint32_t DENALI_PHY_904;
-	volatile uint32_t DENALI_PHY_905;
-	volatile uint32_t DENALI_PHY_906;
-	volatile uint32_t DENALI_PHY_907;
-	volatile char pad__5[0x1D0U];
-	volatile uint32_t DENALI_PHY_1024;
-	volatile uint32_t DENALI_PHY_1025;
-	volatile uint32_t DENALI_PHY_1026;
-	volatile uint32_t DENALI_PHY_1027;
-	volatile uint32_t DENALI_PHY_1028;
-	volatile uint32_t DENALI_PHY_1029;
-	volatile uint32_t DENALI_PHY_1030;
-	volatile uint32_t DENALI_PHY_1031;
-	volatile uint32_t DENALI_PHY_1032;
-	volatile uint32_t DENALI_PHY_1033;
-	volatile uint32_t DENALI_PHY_1034;
-	volatile uint32_t DENALI_PHY_1035;
-	volatile uint32_t DENALI_PHY_1036;
-	volatile uint32_t DENALI_PHY_1037;
-	volatile uint32_t DENALI_PHY_1038;
-	volatile uint32_t DENALI_PHY_1039;
-	volatile uint32_t DENALI_PHY_1040;
-	volatile uint32_t DENALI_PHY_1041;
-	volatile uint32_t DENALI_PHY_1042;
-	volatile uint32_t DENALI_PHY_1043;
-	volatile uint32_t DENALI_PHY_1044;
-	volatile uint32_t DENALI_PHY_1045;
-	volatile uint32_t DENALI_PHY_1046;
-	volatile uint32_t DENALI_PHY_1047;
-	volatile uint32_t DENALI_PHY_1048;
-	volatile uint32_t DENALI_PHY_1049;
-	volatile uint32_t DENALI_PHY_1050;
-	volatile uint32_t DENALI_PHY_1051;
-	volatile uint32_t DENALI_PHY_1052;
-	volatile uint32_t DENALI_PHY_1053;
-	volatile uint32_t DENALI_PHY_1054;
-	volatile uint32_t DENALI_PHY_1055;
-	volatile uint32_t DENALI_PHY_1056;
-	volatile uint32_t DENALI_PHY_1057;
-	volatile uint32_t DENALI_PHY_1058;
-	volatile uint32_t DENALI_PHY_1059;
-	volatile uint32_t DENALI_PHY_1060;
-	volatile uint32_t DENALI_PHY_1061;
-	volatile uint32_t DENALI_PHY_1062;
-	volatile uint32_t DENALI_PHY_1063;
-	volatile uint32_t DENALI_PHY_1064;
-	volatile uint32_t DENALI_PHY_1065;
-	volatile uint32_t DENALI_PHY_1066;
-	volatile uint32_t DENALI_PHY_1067;
-	volatile uint32_t DENALI_PHY_1068;
-	volatile uint32_t DENALI_PHY_1069;
-	volatile uint32_t DENALI_PHY_1070;
-	volatile uint32_t DENALI_PHY_1071;
-	volatile uint32_t DENALI_PHY_1072;
-	volatile uint32_t DENALI_PHY_1073;
-	volatile uint32_t DENALI_PHY_1074;
-	volatile uint32_t DENALI_PHY_1075;
-	volatile char pad__6[0x330U];
-	volatile uint32_t DENALI_PHY_1280;
-	volatile uint32_t DENALI_PHY_1281;
-	volatile uint32_t DENALI_PHY_1282;
-	volatile uint32_t DENALI_PHY_1283;
-	volatile uint32_t DENALI_PHY_1284;
-	volatile uint32_t DENALI_PHY_1285;
-	volatile uint32_t DENALI_PHY_1286;
-	volatile uint32_t DENALI_PHY_1287;
-	volatile uint32_t DENALI_PHY_1288;
-	volatile uint32_t DENALI_PHY_1289;
-	volatile uint32_t DENALI_PHY_1290;
-	volatile uint32_t DENALI_PHY_1291;
-	volatile uint32_t DENALI_PHY_1292;
-	volatile uint32_t DENALI_PHY_1293;
-	volatile uint32_t DENALI_PHY_1294;
-	volatile uint32_t DENALI_PHY_1295;
-	volatile uint32_t DENALI_PHY_1296;
-	volatile uint32_t DENALI_PHY_1297;
-	volatile uint32_t DENALI_PHY_1298;
-	volatile uint32_t DENALI_PHY_1299;
-	volatile uint32_t DENALI_PHY_1300;
-	volatile uint32_t DENALI_PHY_1301;
-	volatile uint32_t DENALI_PHY_1302;
-	volatile uint32_t DENALI_PHY_1303;
-	volatile uint32_t DENALI_PHY_1304;
-	volatile uint32_t DENALI_PHY_1305;
-	volatile uint32_t DENALI_PHY_1306;
-	volatile uint32_t DENALI_PHY_1307;
-	volatile uint32_t DENALI_PHY_1308;
-	volatile uint32_t DENALI_PHY_1309;
-	volatile uint32_t DENALI_PHY_1310;
-	volatile uint32_t DENALI_PHY_1311;
-	volatile uint32_t DENALI_PHY_1312;
-	volatile uint32_t DENALI_PHY_1313;
-	volatile uint32_t DENALI_PHY_1314;
-	volatile uint32_t DENALI_PHY_1315;
-	volatile uint32_t DENALI_PHY_1316;
-	volatile uint32_t DENALI_PHY_1317;
-	volatile uint32_t DENALI_PHY_1318;
-	volatile uint32_t DENALI_PHY_1319;
-	volatile uint32_t DENALI_PHY_1320;
-	volatile uint32_t DENALI_PHY_1321;
-	volatile uint32_t DENALI_PHY_1322;
-	volatile uint32_t DENALI_PHY_1323;
-	volatile uint32_t DENALI_PHY_1324;
-	volatile uint32_t DENALI_PHY_1325;
-	volatile uint32_t DENALI_PHY_1326;
-	volatile uint32_t DENALI_PHY_1327;
-	volatile uint32_t DENALI_PHY_1328;
-	volatile uint32_t DENALI_PHY_1329;
-	volatile uint32_t DENALI_PHY_1330;
-	volatile uint32_t DENALI_PHY_1331;
-	volatile uint32_t DENALI_PHY_1332;
-	volatile uint32_t DENALI_PHY_1333;
-	volatile uint32_t DENALI_PHY_1334;
-	volatile uint32_t DENALI_PHY_1335;
-	volatile uint32_t DENALI_PHY_1336;
-	volatile uint32_t DENALI_PHY_1337;
-	volatile uint32_t DENALI_PHY_1338;
-	volatile uint32_t DENALI_PHY_1339;
-	volatile uint32_t DENALI_PHY_1340;
-	volatile uint32_t DENALI_PHY_1341;
-	volatile uint32_t DENALI_PHY_1342;
-	volatile uint32_t DENALI_PHY_1343;
-	volatile uint32_t DENALI_PHY_1344;
-	volatile uint32_t DENALI_PHY_1345;
-	volatile uint32_t DENALI_PHY_1346;
-	volatile uint32_t DENALI_PHY_1347;
-	volatile uint32_t DENALI_PHY_1348;
-	volatile uint32_t DENALI_PHY_1349;
-	volatile uint32_t DENALI_PHY_1350;
-	volatile uint32_t DENALI_PHY_1351;
-	volatile uint32_t DENALI_PHY_1352;
-	volatile uint32_t DENALI_PHY_1353;
-	volatile uint32_t DENALI_PHY_1354;
-	volatile uint32_t DENALI_PHY_1355;
-	volatile uint32_t DENALI_PHY_1356;
-	volatile uint32_t DENALI_PHY_1357;
-	volatile uint32_t DENALI_PHY_1358;
-	volatile uint32_t DENALI_PHY_1359;
-	volatile uint32_t DENALI_PHY_1360;
-	volatile uint32_t DENALI_PHY_1361;
-	volatile uint32_t DENALI_PHY_1362;
-	volatile uint32_t DENALI_PHY_1363;
-	volatile uint32_t DENALI_PHY_1364;
-	volatile uint32_t DENALI_PHY_1365;
-	volatile uint32_t DENALI_PHY_1366;
-	volatile uint32_t DENALI_PHY_1367;
-	volatile uint32_t DENALI_PHY_1368;
-	volatile uint32_t DENALI_PHY_1369;
-	volatile uint32_t DENALI_PHY_1370;
-	volatile uint32_t DENALI_PHY_1371;
-	volatile uint32_t DENALI_PHY_1372;
-	volatile uint32_t DENALI_PHY_1373;
-	volatile uint32_t DENALI_PHY_1374;
-	volatile uint32_t DENALI_PHY_1375;
-	volatile uint32_t DENALI_PHY_1376;
-	volatile uint32_t DENALI_PHY_1377;
-	volatile uint32_t DENALI_PHY_1378;
-	volatile uint32_t DENALI_PHY_1379;
-	volatile uint32_t DENALI_PHY_1380;
-	volatile uint32_t DENALI_PHY_1381;
-	volatile uint32_t DENALI_PHY_1382;
-	volatile uint32_t DENALI_PHY_1383;
-	volatile uint32_t DENALI_PHY_1384;
-	volatile uint32_t DENALI_PHY_1385;
-	volatile uint32_t DENALI_PHY_1386;
-	volatile uint32_t DENALI_PHY_1387;
-	volatile uint32_t DENALI_PHY_1388;
-	volatile uint32_t DENALI_PHY_1389;
-	volatile uint32_t DENALI_PHY_1390;
-	volatile uint32_t DENALI_PHY_1391;
-	volatile uint32_t DENALI_PHY_1392;
-	volatile uint32_t DENALI_PHY_1393;
-	volatile uint32_t DENALI_PHY_1394;
-	volatile uint32_t DENALI_PHY_1395;
-	volatile uint32_t DENALI_PHY_1396;
-	volatile uint32_t DENALI_PHY_1397;
-	volatile uint32_t DENALI_PHY_1398;
-	volatile uint32_t DENALI_PHY_1399;
-	volatile uint32_t DENALI_PHY_1400;
-	volatile uint32_t DENALI_PHY_1401;
-	volatile uint32_t DENALI_PHY_1402;
-	volatile uint32_t DENALI_PHY_1403;
-	volatile uint32_t DENALI_PHY_1404;
-	volatile uint32_t DENALI_PHY_1405;
-	volatile uint32_t DENALI_PHY_1406;
-	volatile uint32_t DENALI_PHY_1407;
-	volatile uint32_t DENALI_PHY_1408;
-	volatile uint32_t DENALI_PHY_1409;
-	volatile uint32_t DENALI_PHY_1410;
-	volatile uint32_t DENALI_PHY_1411;
-	volatile uint32_t DENALI_PHY_1412;
-	volatile uint32_t DENALI_PHY_1413;
-	volatile uint32_t DENALI_PHY_1414;
-	volatile uint32_t DENALI_PHY_1415;
-	volatile uint32_t DENALI_PHY_1416;
-	volatile uint32_t DENALI_PHY_1417;
-	volatile uint32_t DENALI_PHY_1418;
-	volatile uint32_t DENALI_PHY_1419;
-	volatile uint32_t DENALI_PHY_1420;
-	volatile uint32_t DENALI_PHY_1421;
-	volatile uint32_t DENALI_PHY_1422;
-} lpddr4_ctlregs;
-
-#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
deleted file mode 100644
index 274a976ef9..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
+++ /dev/null
@@ -1,7793 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
- */
-
-#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
-#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
-
-#define LPDDR4__DENALI_CTL_0_READ_MASK				               0xFFFF0F01U
-#define LPDDR4__DENALI_CTL_0_WRITE_MASK				              0xFFFF0F01U
-#define LPDDR4__DENALI_CTL_0__START_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_0__START_SHIFT								     0U
-#define LPDDR4__DENALI_CTL_0__START_WIDTH								     1U
-#define LPDDR4__DENALI_CTL_0__START_WOCLR								     0U
-#define LPDDR4__DENALI_CTL_0__START_WOSET								     0U
-#define LPDDR4__START__REG DENALI_CTL_0
-#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
-
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK				        0x00000F00U
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT								8U
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH								4U
-#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
-#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
-
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK				     0xFFFF0000U
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH				            16U
-#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
-#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
-
-#define LPDDR4__DENALI_CTL_1_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH				     32U
-#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
-#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
-
-#define LPDDR4__DENALI_CTL_2_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH				     32U
-#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
-#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
-
-#define LPDDR4__DENALI_CTL_3_READ_MASK				               0xFF030F1FU
-#define LPDDR4__DENALI_CTL_3_WRITE_MASK				              0xFF030F1FU
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK				       0x0000001FU
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH				               5U
-#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
-#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
-
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK				       0x00000F00U
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH				               4U
-#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
-#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
-
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK				        0x00030000U
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH								2U
-#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
-#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
-
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK              0xFF000000U
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH				      8U
-#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
-#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
-
-#define LPDDR4__DENALI_CTL_4_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_4_WRITE_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK          0x000000FFU
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH				  8U
-#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
-#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
-
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK             0x0000FF00U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH				     8U
-#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
-#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
-
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK         0x00FF0000U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT				16U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH				 8U
-#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
-#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
-
-#define LPDDR4__DENALI_CTL_5_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_5_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK            0x0000FFFFU
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH				   16U
-#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
-#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
-
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK        0x00FF0000U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT               16U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH				8U
-#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
-#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
-
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH				          8U
-#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
-#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
-
-#define LPDDR4__DENALI_CTL_6_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_6_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK           0x000000FFU
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH				   8U
-#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK            0x0000FF00U
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT				    8U
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH				    8U
-#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK          0x00FF0000U
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH				  8U
-#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK   0xFF000000U
-#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT          24U
-#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH           8U
-#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_7_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7_WRITE_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK				          0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH								 24U
-#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
-#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
-
-#define LPDDR4__DENALI_CTL_8_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8_WRITE_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH								24U
-#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
-#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
-
-#define LPDDR4__DENALI_CTL_9_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9_WRITE_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH								24U
-#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
-#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
-
-#define LPDDR4__DENALI_CTL_10_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT								0U
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH				               24U
-#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
-#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
-
-#define LPDDR4__DENALI_CTL_11_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH								24U
-#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
-#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
-
-#define LPDDR4__DENALI_CTL_12_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH				               24U
-#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
-#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
-
-#define LPDDR4__DENALI_CTL_13_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH				               24U
-#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
-#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
-
-#define LPDDR4__DENALI_CTL_14_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH				               24U
-#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
-#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
-
-#define LPDDR4__DENALI_CTL_15_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH								24U
-#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
-#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
-
-#define LPDDR4__DENALI_CTL_16_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH				               24U
-#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
-#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
-
-#define LPDDR4__DENALI_CTL_17_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH				               24U
-#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
-#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
-
-#define LPDDR4__DENALI_CTL_18_READ_MASK				              0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_18_WRITE_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH				               24U
-#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
-#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
-
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET				         0U
-#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
-#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
-
-#define LPDDR4__DENALI_CTL_19_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_CTL_19_WRITE_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET				         0U
-#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
-#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET				          0U
-#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19
-#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS
-
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET				              0U
-#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19
-#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT
-
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK				        0x01000000U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH								1U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR								0U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET								0U
-#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19
-#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE
-
-#define LPDDR4__DENALI_CTL_20_READ_MASK				              0x03013F01U
-#define LPDDR4__DENALI_CTL_20_WRITE_MASK				             0x03013F01U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK             0x00000001U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET				     0U
-#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
-#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
-
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK				    0x00003F00U
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH				            6U
-#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20
-#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR
-
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET				      0U
-#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20
-#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE
-
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK				 0x03000000U
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH				         2U
-#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20
-#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT
-
-#define LPDDR4__DENALI_CTL_21_READ_MASK				              0x1F1F1F03U
-#define LPDDR4__DENALI_CTL_21_WRITE_MASK				             0x1F1F1F03U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK				 0x00000003U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH				         2U
-#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ
-
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK				   0x00001F00U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH				           5U
-#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
-
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK				   0x001F0000U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH				           5U
-#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
-
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK				   0x1F000000U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH				           5U
-#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2
-
-#define LPDDR4__DENALI_CTL_22_READ_MASK				              0x00030303U
-#define LPDDR4__DENALI_CTL_22_WRITE_MASK				             0x00030303U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK              0x00000003U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH				      2U
-#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
-#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
-
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK              0x00000300U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH				      2U
-#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
-#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
-
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK              0x00030000U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH				      2U
-#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
-#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
-
-#define LPDDR4__DENALI_CTL_23_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK				       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH				              32U
-#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
-#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
-
-#define LPDDR4__DENALI_CTL_24_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK				     0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH				            32U
-#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
-#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
-
-#define LPDDR4__DENALI_CTL_25_READ_MASK				              0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_25_WRITE_MASK				             0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET				             0U
-#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
-#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0
-
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK				     0xFFFFFF00U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH				            24U
-#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
-#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1
-
-#define LPDDR4__DENALI_CTL_26_READ_MASK				              0x0001FFFFU
-#define LPDDR4__DENALI_CTL_26_WRITE_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH				             8U
-#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26
-#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2
-
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK				     0x0000FF00U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH				             8U
-#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26
-#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3
-
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET				           0U
-#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26
-#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE
-
-#define LPDDR4__DENALI_CTL_27_READ_MASK				              0xFF0F7FFFU
-#define LPDDR4__DENALI_CTL_27_WRITE_MASK				             0xFF0F7FFFU
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK				   0x00007FFFU
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH				          15U
-#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27
-#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD
-
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK				0x000F0000U
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH				        4U
-#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27
-#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES
-
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK				         0xFF000000U
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT								24U
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH								 8U
-#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27
-#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0
-
-#define LPDDR4__DENALI_CTL_28_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_28_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK				         0x000000FFU
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH								 8U
-#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28
-#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1
-
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK				         0x0000FF00U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH								 8U
-#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28
-#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2
-
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK           0x00FF0000U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH				   8U
-#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28
-#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK           0xFF000000U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT				  24U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH				   8U
-#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28
-#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_29_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_29_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH				          8U
-#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29
-#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT
-
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK        0x0000FF00U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT				8U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH				8U
-#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29
-#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK               0xFFFF0000U
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH				      16U
-#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29
-#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT
-
-#define LPDDR4__DENALI_CTL_30_READ_MASK				              0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30_WRITE_MASK				             0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK				  0x00000001U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET				          0U
-#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30
-#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST
-
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK             0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30
-#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0
-
-#define LPDDR4__DENALI_CTL_31_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_31_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31
-#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0
-
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK             0xFFFF0000U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31
-#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0
-
-#define LPDDR4__DENALI_CTL_32_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_32_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32
-#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0
-
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK             0xFFFF0000U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32
-#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1
-
-#define LPDDR4__DENALI_CTL_33_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_33_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33
-#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1
-
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK             0xFFFF0000U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33
-#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1
-
-#define LPDDR4__DENALI_CTL_34_READ_MASK				              0x7F7FFFFFU
-#define LPDDR4__DENALI_CTL_34_WRITE_MASK				             0x7F7FFFFFU
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH				    16U
-#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34
-#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1
-
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK				    0x007F0000U
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH				            7U
-#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34
-#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0
-
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK				         0x7F000000U
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT								24U
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH								 7U
-#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34
-#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0
-
-#define LPDDR4__DENALI_CTL_35_READ_MASK				              0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_35_WRITE_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH				            7U
-#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35
-#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1
-
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK				         0x00007F00U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH								 7U
-#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35
-#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1
-
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK				    0x007F0000U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH				            7U
-#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35
-#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2
-
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK				         0x7F000000U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT								24U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH								 7U
-#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35
-#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2
-
-#define LPDDR4__DENALI_CTL_36_READ_MASK				              0x00FF1F07U
-#define LPDDR4__DENALI_CTL_36_WRITE_MASK				             0x00FF1F07U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK				0x00000007U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH				        3U
-#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36
-#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL
-
-#define LPDDR4__DENALI_CTL_36__TCCD_MASK				             0x00001F00U
-#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT								     8U
-#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH								     5U
-#define LPDDR4__TCCD__REG DENALI_CTL_36
-#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD
-
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH								  8U
-#define LPDDR4__TRRD_F0__REG DENALI_CTL_36
-#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0
-
-#define LPDDR4__DENALI_CTL_37_READ_MASK				              0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_37_WRITE_MASK				             0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK				           0x000001FFU
-#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH								   9U
-#define LPDDR4__TRC_F0__REG DENALI_CTL_37
-#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0
-
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH				              8U
-#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37
-#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0
-
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK				          0x3F000000U
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH								  6U
-#define LPDDR4__TWTR_F0__REG DENALI_CTL_37
-#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0
-
-#define LPDDR4__DENALI_CTL_38_READ_MASK				              0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_38_WRITE_MASK				             0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH								   8U
-#define LPDDR4__TRP_F0__REG DENALI_CTL_38
-#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0
-
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK				          0x0001FF00U
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH								  9U
-#define LPDDR4__TFAW_F0__REG DENALI_CTL_38
-#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0
-
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH								  8U
-#define LPDDR4__TRRD_F1__REG DENALI_CTL_38
-#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1
-
-#define LPDDR4__DENALI_CTL_39_READ_MASK				              0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_39_WRITE_MASK				             0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK				           0x000001FFU
-#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH								   9U
-#define LPDDR4__TRC_F1__REG DENALI_CTL_39
-#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1
-
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH				              8U
-#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39
-#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1
-
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK				          0x3F000000U
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH								  6U
-#define LPDDR4__TWTR_F1__REG DENALI_CTL_39
-#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1
-
-#define LPDDR4__DENALI_CTL_40_READ_MASK				              0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_40_WRITE_MASK				             0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH								   8U
-#define LPDDR4__TRP_F1__REG DENALI_CTL_40
-#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1
-
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK				          0x0001FF00U
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH								  9U
-#define LPDDR4__TFAW_F1__REG DENALI_CTL_40
-#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1
-
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH								  8U
-#define LPDDR4__TRRD_F2__REG DENALI_CTL_40
-#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2
-
-#define LPDDR4__DENALI_CTL_41_READ_MASK				              0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_41_WRITE_MASK				             0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK				           0x000001FFU
-#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH								   9U
-#define LPDDR4__TRC_F2__REG DENALI_CTL_41
-#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2
-
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH				              8U
-#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41
-#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2
-
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK				          0x3F000000U
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH								  6U
-#define LPDDR4__TWTR_F2__REG DENALI_CTL_41
-#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2
-
-#define LPDDR4__DENALI_CTL_42_READ_MASK				              0x3F01FFFFU
-#define LPDDR4__DENALI_CTL_42_WRITE_MASK				             0x3F01FFFFU
-#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH								   8U
-#define LPDDR4__TRP_F2__REG DENALI_CTL_42
-#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2
-
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK				          0x0001FF00U
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH								  9U
-#define LPDDR4__TFAW_F2__REG DENALI_CTL_42
-#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2
-
-#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK				           0x3F000000U
-#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH								   6U
-#define LPDDR4__TCCDMW__REG DENALI_CTL_42
-#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW
-
-#define LPDDR4__DENALI_CTL_43_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_43_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK				          0x000000FFU
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH								  8U
-#define LPDDR4__TRTP_F0__REG DENALI_CTL_43
-#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0
-
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH								  8U
-#define LPDDR4__TMRD_F0__REG DENALI_CTL_43
-#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0
-
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH								  8U
-#define LPDDR4__TMOD_F0__REG DENALI_CTL_43
-#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0
-
-#define LPDDR4__DENALI_CTL_44_READ_MASK				              0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_44_WRITE_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK				      0x0001FFFFU
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH				             17U
-#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44
-#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0
-
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH								  5U
-#define LPDDR4__TCKE_F0__REG DENALI_CTL_44
-#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0
-
-#define LPDDR4__DENALI_CTL_45_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_45_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT								0U
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH								8U
-#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45
-#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0
-
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH								  8U
-#define LPDDR4__TRTP_F1__REG DENALI_CTL_45
-#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1
-
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH								  8U
-#define LPDDR4__TMRD_F1__REG DENALI_CTL_45
-#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1
-
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH								  8U
-#define LPDDR4__TMOD_F1__REG DENALI_CTL_45
-#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1
-
-#define LPDDR4__DENALI_CTL_46_READ_MASK				              0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_46_WRITE_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK				      0x0001FFFFU
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH				             17U
-#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46
-#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1
-
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH								  5U
-#define LPDDR4__TCKE_F1__REG DENALI_CTL_46
-#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1
-
-#define LPDDR4__DENALI_CTL_47_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_47_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH								8U
-#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47
-#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1
-
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH								  8U
-#define LPDDR4__TRTP_F2__REG DENALI_CTL_47
-#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2
-
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH								  8U
-#define LPDDR4__TMRD_F2__REG DENALI_CTL_47
-#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2
-
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH								  8U
-#define LPDDR4__TMOD_F2__REG DENALI_CTL_47
-#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2
-
-#define LPDDR4__DENALI_CTL_48_READ_MASK				              0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_48_WRITE_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK				      0x0001FFFFU
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH				             17U
-#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48
-#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2
-
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH								  5U
-#define LPDDR4__TCKE_F2__REG DENALI_CTL_48
-#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2
-
-#define LPDDR4__DENALI_CTL_49_READ_MASK				              0x070707FFU
-#define LPDDR4__DENALI_CTL_49_WRITE_MASK				             0x070707FFU
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH								8U
-#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49
-#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2
-
-#define LPDDR4__DENALI_CTL_49__TPPD_MASK				             0x00000700U
-#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT								     8U
-#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH								     3U
-#define LPDDR4__TPPD__REG DENALI_CTL_49
-#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD
-
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK				     0x00070000U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH				             3U
-#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49
-#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4
-
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK				     0x07000000U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH				             3U
-#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49
-#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5
-
-#define LPDDR4__DENALI_CTL_50_READ_MASK				              0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_50_WRITE_MASK				             0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK				      0x00000001U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET				              0U
-#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50
-#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP
-
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH								  8U
-#define LPDDR4__TRCD_F0__REG DENALI_CTL_50
-#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0
-
-#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK				           0x00FF0000U
-#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT								  16U
-#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH								   8U
-#define LPDDR4__TWR_F0__REG DENALI_CTL_50
-#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0
-
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH								  8U
-#define LPDDR4__TRCD_F1__REG DENALI_CTL_50
-#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1
-
-#define LPDDR4__DENALI_CTL_51_READ_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_CTL_51_WRITE_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH								   8U
-#define LPDDR4__TWR_F1__REG DENALI_CTL_51
-#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1
-
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH								  8U
-#define LPDDR4__TRCD_F2__REG DENALI_CTL_51
-#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2
-
-#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK				           0x00FF0000U
-#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT								  16U
-#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH								   8U
-#define LPDDR4__TWR_F2__REG DENALI_CTL_51
-#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2
-
-#define LPDDR4__DENALI_CTL_51__TMRR_MASK				             0x0F000000U
-#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT								    24U
-#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH								     4U
-#define LPDDR4__TMRR__REG DENALI_CTL_51
-#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR
-
-#define LPDDR4__DENALI_CTL_52_READ_MASK				              0x3F03FF1FU
-#define LPDDR4__DENALI_CTL_52_WRITE_MASK				             0x3F03FF1FU
-#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK				          0x0000001FU
-#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH								  5U
-#define LPDDR4__TCACKEL__REG DENALI_CTL_52
-#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL
-
-#define LPDDR4__DENALI_CTL_52__TCAENT_MASK				           0x0003FF00U
-#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT								   8U
-#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH								  10U
-#define LPDDR4__TCAENT__REG DENALI_CTL_52
-#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT
-
-#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK				           0x3F000000U
-#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH								   6U
-#define LPDDR4__TCAMRD__REG DENALI_CTL_52
-#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD
-
-#define LPDDR4__DENALI_CTL_53_READ_MASK				              0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_53_WRITE_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK				           0x0000001FU
-#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH								   5U
-#define LPDDR4__TCAEXT__REG DENALI_CTL_53
-#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT
-
-#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK				          0x00001F00U
-#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH								  5U
-#define LPDDR4__TCACKEH__REG DENALI_CTL_53
-#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH
-
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK				          0x001F0000U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH								  5U
-#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53
-#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0
-
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH								  5U
-#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53
-#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1
-
-#define LPDDR4__DENALI_CTL_54_READ_MASK				              0x0101011FU
-#define LPDDR4__DENALI_CTL_54_WRITE_MASK				             0x0101011FU
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK				          0x0000001FU
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH								  5U
-#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54
-#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2
-
-#define LPDDR4__DENALI_CTL_54__AP_MASK				               0x00000100U
-#define LPDDR4__DENALI_CTL_54__AP_SHIFT								       8U
-#define LPDDR4__DENALI_CTL_54__AP_WIDTH								       1U
-#define LPDDR4__DENALI_CTL_54__AP_WOCLR								       0U
-#define LPDDR4__DENALI_CTL_54__AP_WOSET								       0U
-#define LPDDR4__AP__REG DENALI_CTL_54
-#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP
-
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET				             0U
-#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54
-#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP
-
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET				             0U
-#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54
-#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT
-
-#define LPDDR4__DENALI_CTL_55_READ_MASK				              0x1FFFFFFFU
-#define LPDDR4__DENALI_CTL_55_WRITE_MASK				             0x1FFFFFFFU
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK				          0x000000FFU
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH								  8U
-#define LPDDR4__TDAL_F0__REG DENALI_CTL_55
-#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0
-
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH								  8U
-#define LPDDR4__TDAL_F1__REG DENALI_CTL_55
-#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1
-
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH								  8U
-#define LPDDR4__TDAL_F2__REG DENALI_CTL_55
-#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2
-
-#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK				           0x1F000000U
-#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH								   5U
-#define LPDDR4__BSTLEN__REG DENALI_CTL_55
-#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN
-
-#define LPDDR4__DENALI_CTL_56_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_56_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK				      0x000000FFU
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH				              8U
-#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0
-
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH				              8U
-#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0
-
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH				              8U
-#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0
-
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK				      0xFF000000U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH				              8U
-#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1
-
-#define LPDDR4__DENALI_CTL_57_READ_MASK				              0x0301FFFFU
-#define LPDDR4__DENALI_CTL_57_WRITE_MASK				             0x0301FFFFU
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK				      0x000000FFU
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH				              8U
-#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57
-#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1
-
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH				              8U
-#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57
-#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1
-
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK				  0x00010000U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET				          0U
-#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57
-#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE
-
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK				     0x03000000U
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH				             2U
-#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57
-#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6
-
-#define LPDDR4__DENALI_CTL_58_READ_MASK				              0x0101017FU
-#define LPDDR4__DENALI_CTL_58_WRITE_MASK				             0x0101017FU
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK				     0x0000007FU
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH				             7U
-#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58
-#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7
-
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK				 0x00000100U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET				         0U
-#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58
-#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN
-
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET				             0U
-#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58
-#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8
-
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET				             0U
-#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58
-#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM
-
-#define LPDDR4__DENALI_CTL_59_READ_MASK				              0x07010100U
-#define LPDDR4__DENALI_CTL_59_WRITE_MASK				             0x07010100U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK				         0x00000001U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH								 1U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR								 0U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET								 0U
-#define LPDDR4__AREFRESH__REG DENALI_CTL_59
-#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH
-
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK				      0x00000100U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET				              0U
-#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59
-#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS
-
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET				              0U
-#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59
-#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE
-
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK				     0x07000000U
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH				             3U
-#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59
-#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9
-
-#define LPDDR4__DENALI_CTL_60_READ_MASK				              0x0003FF3FU
-#define LPDDR4__DENALI_CTL_60_WRITE_MASK				             0x0003FF3FU
-#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK  0x0000003FU
-#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT          0U
-#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH          6U
-#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60
-#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH
-
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK				          0x0003FF00U
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH								 10U
-#define LPDDR4__TRFC_F0__REG DENALI_CTL_60
-#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0
-
-#define LPDDR4__DENALI_CTL_61_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK				          0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH								 20U
-#define LPDDR4__TREF_F0__REG DENALI_CTL_61
-#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0
-
-#define LPDDR4__DENALI_CTL_62_READ_MASK				              0x000003FFU
-#define LPDDR4__DENALI_CTL_62_WRITE_MASK				             0x000003FFU
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK				          0x000003FFU
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH								 10U
-#define LPDDR4__TRFC_F1__REG DENALI_CTL_62
-#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1
-
-#define LPDDR4__DENALI_CTL_63_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK				          0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH								 20U
-#define LPDDR4__TREF_F1__REG DENALI_CTL_63
-#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1
-
-#define LPDDR4__DENALI_CTL_64_READ_MASK				              0x000003FFU
-#define LPDDR4__DENALI_CTL_64_WRITE_MASK				             0x000003FFU
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK				          0x000003FFU
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH								 10U
-#define LPDDR4__TRFC_F2__REG DENALI_CTL_64
-#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2
-
-#define LPDDR4__DENALI_CTL_65_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK				          0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH								 20U
-#define LPDDR4__TREF_F2__REG DENALI_CTL_65
-#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2
-
-#define LPDDR4__DENALI_CTL_66_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK				    0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH				           20U
-#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66
-#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL
-
-#define LPDDR4__DENALI_CTL_67_READ_MASK				              0x03FF0101U
-#define LPDDR4__DENALI_CTL_67_WRITE_MASK				             0x03FF0101U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK				           0x00000001U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH								   1U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR								   0U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET								   0U
-#define LPDDR4__PBR_EN__REG DENALI_CTL_67
-#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN
-
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK				0x00000100U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET				        0U
-#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67
-#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER
-
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK				       0x03FF0000U
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH				              10U
-#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67
-#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0
-
-#define LPDDR4__DENALI_CTL_68_READ_MASK				              0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_68_WRITE_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH				             16U
-#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68
-#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0
-
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK				       0x03FF0000U
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH				              10U
-#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68
-#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1
-
-#define LPDDR4__DENALI_CTL_69_READ_MASK				              0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_69_WRITE_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH				             16U
-#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69
-#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1
-
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK				       0x03FF0000U
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH				              10U
-#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69
-#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2
-
-#define LPDDR4__DENALI_CTL_70_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_70_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH				             16U
-#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70
-#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2
-
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH				       16U
-#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70
-#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT
-
-#define LPDDR4__DENALI_CTL_71_READ_MASK				              0x1F1F010FU
-#define LPDDR4__DENALI_CTL_71_WRITE_MASK				             0x1F1F010FU
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK            0x0000000FU
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH				    4U
-#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71
-#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY
-
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET				          0U
-#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71
-#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN
-
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK       0x001F0000U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT              16U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH               5U
-#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71
-#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK      0x1F000000U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT             24U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH              5U
-#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71
-#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_72_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_72_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK				         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH								16U
-#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72
-#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0
-
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT								16U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH								16U
-#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72
-#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1
-
-#define LPDDR4__DENALI_CTL_73_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_73_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK				         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH								16U
-#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73
-#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2
-
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK				         0x00FF0000U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT								16U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH								 8U
-#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73
-#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0
-
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK				         0xFF000000U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT								24U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH								 8U
-#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73
-#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1
-
-#define LPDDR4__DENALI_CTL_74_READ_MASK				              0x1F1F1FFFU
-#define LPDDR4__DENALI_CTL_74_WRITE_MASK				             0x1F1F1FFFU
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK				         0x000000FFU
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH								 8U
-#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74
-#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2
-
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK				        0x00001F00U
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT								8U
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH								5U
-#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74
-#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0
-
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH				               5U
-#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74
-#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0
-
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH				               5U
-#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74
-#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0
-
-#define LPDDR4__DENALI_CTL_75_READ_MASK				              0x1F010F1FU
-#define LPDDR4__DENALI_CTL_75_WRITE_MASK				             0x1F010F1FU
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH				              5U
-#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75
-#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0
-
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK				        0x00000F00U
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT								8U
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH								4U
-#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75
-#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0
-
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET				        0U
-#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75
-#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0
-
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK				        0x1F000000U
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH								5U
-#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75
-#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1
-
-#define LPDDR4__DENALI_CTL_76_READ_MASK				              0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_76_WRITE_MASK				             0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK				       0x0000001FU
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH				               5U
-#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76
-#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1
-
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH				               5U
-#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76
-#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1
-
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK				      0x001F0000U
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH				              5U
-#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76
-#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1
-
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK				        0x0F000000U
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH								4U
-#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76
-#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1
-
-#define LPDDR4__DENALI_CTL_77_READ_MASK				              0x1F1F1F01U
-#define LPDDR4__DENALI_CTL_77_WRITE_MASK				             0x1F1F1F01U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK				0x00000001U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET				        0U
-#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77
-#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1
-
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK				        0x00001F00U
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT								8U
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH								5U
-#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77
-#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2
-
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH				               5U
-#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77
-#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2
-
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH				               5U
-#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77
-#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2
-
-#define LPDDR4__DENALI_CTL_78_READ_MASK				              0x00010F1FU
-#define LPDDR4__DENALI_CTL_78_WRITE_MASK				             0x00010F1FU
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH				              5U
-#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78
-#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2
-
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK				        0x00000F00U
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT								8U
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH								4U
-#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78
-#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2
-
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET				        0U
-#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78
-#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2
-
-#define LPDDR4__DENALI_CTL_79_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_79_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK				          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH								 16U
-#define LPDDR4__TXSR_F0__REG DENALI_CTL_79
-#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0
-
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT								16U
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH								16U
-#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79
-#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0
-
-#define LPDDR4__DENALI_CTL_80_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_80_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK				          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH								 16U
-#define LPDDR4__TXSR_F1__REG DENALI_CTL_80
-#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1
-
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT								16U
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH								16U
-#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80
-#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1
-
-#define LPDDR4__DENALI_CTL_81_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_81_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK				          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH								 16U
-#define LPDDR4__TXSR_F2__REG DENALI_CTL_81
-#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2
-
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT								16U
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH								16U
-#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81
-#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2
-
-#define LPDDR4__DENALI_CTL_82_READ_MASK				              0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_82_WRITE_MASK				             0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH				              5U
-#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82
-#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0
-
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH				              5U
-#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82
-#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0
-
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH				               5U
-#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82
-#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0
-
-#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK				           0xFF000000U
-#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH								   8U
-#define LPDDR4__TSR_F0__REG DENALI_CTL_82
-#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0
-
-#define LPDDR4__DENALI_CTL_83_READ_MASK				              0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_83_WRITE_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK				        0x00000007U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT								0U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH								3U
-#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83
-#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0
-
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH				               5U
-#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83
-#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0
-
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH				               5U
-#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83
-#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0
-
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH				               5U
-#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83
-#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0
-
-#define LPDDR4__DENALI_CTL_84_READ_MASK				              0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_84_WRITE_MASK				             0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH				              5U
-#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84
-#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1
-
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH				              5U
-#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84
-#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1
-
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH				               5U
-#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84
-#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1
-
-#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK				           0xFF000000U
-#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH								   8U
-#define LPDDR4__TSR_F1__REG DENALI_CTL_84
-#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1
-
-#define LPDDR4__DENALI_CTL_85_READ_MASK				              0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_85_WRITE_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK				        0x00000007U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH								3U
-#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85
-#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1
-
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH				               5U
-#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85
-#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1
-
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH				               5U
-#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85
-#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1
-
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH				               5U
-#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85
-#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1
-
-#define LPDDR4__DENALI_CTL_86_READ_MASK				              0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_86_WRITE_MASK				             0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH				              5U
-#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86
-#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2
-
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH				              5U
-#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86
-#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2
-
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH				               5U
-#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86
-#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2
-
-#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK				           0xFF000000U
-#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH								   8U
-#define LPDDR4__TSR_F2__REG DENALI_CTL_86
-#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2
-
-#define LPDDR4__DENALI_CTL_87_READ_MASK				              0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_87_WRITE_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK				        0x00000007U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH								3U
-#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87
-#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2
-
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH				               5U
-#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87
-#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2
-
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH				               5U
-#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87
-#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2
-
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH				               5U
-#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87
-#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2
-
-#define LPDDR4__DENALI_CTL_88_READ_MASK				              0x07010101U
-#define LPDDR4__DENALI_CTL_88_WRITE_MASK				             0x07010101U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK              0x00000001U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET				      0U
-#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88
-#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT
-
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET				            0U
-#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88
-#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10
-
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK            0x00010000U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET				    0U
-#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88
-#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH
-
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK				        0x07000000U
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH								3U
-#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88
-#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY
-
-#define LPDDR4__DENALI_CTL_89_READ_MASK				              0x01010300U
-#define LPDDR4__DENALI_CTL_89_WRITE_MASK				             0x01010300U
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK				    0x0000001FU
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH				            5U
-#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89
-#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11
-
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK				       0x00000300U
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH				               2U
-#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89
-#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS
-
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK				        0x00010000U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET								0U
-#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89
-#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN
-
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET				             0U
-#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89
-#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN
-
-#define LPDDR4__DENALI_CTL_90_READ_MASK				              0x00010101U
-#define LPDDR4__DENALI_CTL_90_WRITE_MASK				             0x00010101U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET				             0U
-#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90
-#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN
-
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK				     0x00000100U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET				             0U
-#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90
-#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN
-
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET				        0U
-#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90
-#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN
-
-#define LPDDR4__DENALI_CTL_91_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_91_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_92_READ_MASK				              0x0707FFFFU
-#define LPDDR4__DENALI_CTL_92_WRITE_MASK				             0x0707FFFFU
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK				    0x00070000U
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH				            3U
-#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92
-#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG
-
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK				    0x07000000U
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH				            3U
-#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92
-#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12
-
-#define LPDDR4__DENALI_CTL_93_READ_MASK				              0xFFFFFF07U
-#define LPDDR4__DENALI_CTL_93_WRITE_MASK				             0xFFFFFF07U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK				    0x00000007U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH				            3U
-#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13
-
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK				    0x0000FF00U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH				            8U
-#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14
-
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK				    0x00FF0000U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH				            8U
-#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15
-
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK				    0xFF000000U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH				            8U
-#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16
-
-#define LPDDR4__DENALI_CTL_94_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_94_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK    0x0000FFFFU
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT            0U
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH           16U
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK    0xFFFF0000U
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT           16U
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH           16U
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_95_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_95_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH				  16U
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT     16U
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH     16U
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_96_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_96_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT      0U
-#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH     16U
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK    0xFFFF0000U
-#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT           16U
-#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH           16U
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_97_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_97_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK    0x0000FFFFU
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT            0U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH           16U
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH				  16U
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_98_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_98_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT      0U
-#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH     16U
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT     16U
-#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH     16U
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_99_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_99_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK    0x0000FFFFU
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT            0U
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH           16U
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK    0xFFFF0000U
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT           16U
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH           16U
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_100_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_100_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH				 16U
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT    16U
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH    16U
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_101_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_101_WRITE_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT     0U
-#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_102_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH				    32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102
-#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0
-
-#define LPDDR4__DENALI_CTL_103_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_103_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT               0U
-#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0
-
-#define LPDDR4__DENALI_CTL_104_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_104_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT               0U
-#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0
-
-#define LPDDR4__DENALI_CTL_105_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_105_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT               0U
-#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0
-
-#define LPDDR4__DENALI_CTL_106_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_106_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT               0U
-#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0
-
-#define LPDDR4__DENALI_CTL_107_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_107_WRITE_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT       0U
-#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH      16U
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_108_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH				   20U
-#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108
-#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0
-
-#define LPDDR4__DENALI_CTL_109_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH				    32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109
-#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1
-
-#define LPDDR4__DENALI_CTL_110_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_110_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT               0U
-#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1
-
-#define LPDDR4__DENALI_CTL_111_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_111_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT               0U
-#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1
-
-#define LPDDR4__DENALI_CTL_112_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_112_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT               0U
-#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1
-
-#define LPDDR4__DENALI_CTL_113_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_113_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT               0U
-#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1
-
-#define LPDDR4__DENALI_CTL_114_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_114_WRITE_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT       0U
-#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH      16U
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_115_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH				   20U
-#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115
-#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1
-
-#define LPDDR4__DENALI_CTL_116_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH				    32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116
-#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2
-
-#define LPDDR4__DENALI_CTL_117_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_117_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT               0U
-#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2
-
-#define LPDDR4__DENALI_CTL_118_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_118_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT               0U
-#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2
-
-#define LPDDR4__DENALI_CTL_119_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_119_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT               0U
-#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2
-
-#define LPDDR4__DENALI_CTL_120_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_120_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT               0U
-#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH              32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2
-
-#define LPDDR4__DENALI_CTL_121_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_121_WRITE_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT       0U
-#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH      16U
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_122_READ_MASK				             0x010FFFFFU
-#define LPDDR4__DENALI_CTL_122_WRITE_MASK				            0x010FFFFFU
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH				   20U
-#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122
-#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2
-
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET				         0U
-#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122
-#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF
-
-#define LPDDR4__DENALI_CTL_123_READ_MASK				             0x00010103U
-#define LPDDR4__DENALI_CTL_123_WRITE_MASK				            0x00010103U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK            0x00000003U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH				    2U
-#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123
-#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK       0x00000100U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT               8U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH               1U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR               0U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET               0U
-#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123
-#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1
-
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT      16U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH       1U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR       0U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET       0U
-#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123
-#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
-
-#define LPDDR4__DENALI_CTL_124_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_124_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT           0U
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT          16U
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_125_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_125_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH				 16U
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT          16U
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_126_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_126_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT           0U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH				 16U
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_127_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_127_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT           0U
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT          16U
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_128_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_CTL_128_WRITE_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH				 16U
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET				             0U
-#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128
-#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL
-
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK				     0x07000000U
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH				             3U
-#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128
-#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND
-
-#define LPDDR4__DENALI_CTL_129_READ_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_129_WRITE_MASK				            0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH				         8U
-#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129
-#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW
-
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK				 0x01FFFF00U
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH				        17U
-#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129
-#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS
-
-#define LPDDR4__DENALI_CTL_130_READ_MASK				             0x01030107U
-#define LPDDR4__DENALI_CTL_130_WRITE_MASK				            0x01030107U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK				0x00000007U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH				        3U
-#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130
-#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS
-
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET				          0U
-#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130
-#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS
-
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK				      0x00030000U
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH				              2U
-#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130
-#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS
-
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK               0x01000000U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET				       0U
-#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130
-#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL
-
-#define LPDDR4__DENALI_CTL_131_READ_MASK				             0xFFFFFF03U
-#define LPDDR4__DENALI_CTL_131_WRITE_MASK				            0xFFFFFF03U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK         0x00000003U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH				 2U
-#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131
-#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE
-
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK				        0x0000FF00U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT								8U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH								8U
-#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131
-#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0
-
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH								8U
-#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131
-#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0
-
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK				        0xFF000000U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH								8U
-#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131
-#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1
-
-#define LPDDR4__DENALI_CTL_132_READ_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_132_WRITE_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH								8U
-#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132
-#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1
-
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK				        0x0000FF00U
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT								8U
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH								8U
-#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132
-#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2
-
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH								8U
-#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132
-#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2
-
-#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK				          0x7F000000U
-#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH								  7U
-#define LPDDR4__LP_CMD__REG DENALI_CTL_132
-#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD
-
-#define LPDDR4__DENALI_CTL_133_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_133_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK         0x0000000FU
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH				 4U
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK          0x00000F00U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH				  4U
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK           0x000F0000U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH				   4U
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT       24U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH        4U
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_134_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK				0x0000000FU
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH				        4U
-#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK        0x00000F00U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT				8U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH				4U
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK         0x000F0000U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH				 4U
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT     24U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH      4U
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_135_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_135_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK             0x0000000FU
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH				     4U
-#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135
-#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK         0x00000F00U
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT				 8U
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH				 4U
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK          0x000F0000U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH				  4U
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK           0x0F000000U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT				  24U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH				   4U
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_136_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT        0U
-#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH        4U
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK				0x00000F00U
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH				        4U
-#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK        0x000F0000U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT               16U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH				4U
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK         0x0F000000U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT				24U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH				 4U
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_137_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_137_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT      0U
-#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH      4U
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK             0x00000F00U
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH				     4U
-#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137
-#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK         0x000F0000U
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH				 4U
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK          0x0F000000U
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT				 24U
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH				  4U
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_138_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK           0x0000000FU
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH				   4U
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT        8U
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH        4U
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK				0x000F0000U
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH				        4U
-#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK        0x0F000000U
-#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT               24U
-#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH				4U
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139_READ_MASK				             0x3F0F0F0FU
-#define LPDDR4__DENALI_CTL_139_WRITE_MASK				            0x3F0F0F0FU
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK         0x0000000FU
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH				 4U
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT      8U
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH      4U
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK             0x000F0000U
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH				     4U
-#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139
-#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK				   0x3F000000U
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH				           6U
-#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139
-#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN
-
-#define LPDDR4__DENALI_CTL_140_READ_MASK				             0x070FFF01U
-#define LPDDR4__DENALI_CTL_140_WRITE_MASK				            0x070FFF01U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET				         0U
-#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140
-#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN
-
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK              0x000FFF00U
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH				     12U
-#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140
-#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT
-
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK				    0x07000000U
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH				            3U
-#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140
-#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP
-
-#define LPDDR4__DENALI_CTL_141_READ_MASK				             0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_141_WRITE_MASK				            0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH				            7U
-#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141
-#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0
-
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH				            7U
-#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141
-#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1
-
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK				0x000F0000U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH				        4U
-#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141
-#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN
-
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK				 0x0F000000U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH				         4U
-#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141
-#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN
-
-#define LPDDR4__DENALI_CTL_142_READ_MASK				             0x000FFF07U
-#define LPDDR4__DENALI_CTL_142_WRITE_MASK				            0x000FFF07U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK             0x00000007U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH				     3U
-#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142
-#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN
-
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK				 0x000FFF00U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH				        12U
-#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142
-#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE
-
-#define LPDDR4__DENALI_CTL_143_READ_MASK				             0xFFFF0FFFU
-#define LPDDR4__DENALI_CTL_143_WRITE_MASK				            0xFFFF0FFFU
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK           0x00000FFFU
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH				  12U
-#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143
-#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE
-
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK            0x00FF0000U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH				    8U
-#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143
-#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE
-
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK    0xFF000000U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT           24U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH            8U
-#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143
-#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE
-
-#define LPDDR4__DENALI_CTL_144_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_144_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_145_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_145_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
-#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT               16U
-#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH               16U
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_146_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_146_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT				0U
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH               16U
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT               16U
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH               16U
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_147_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_147_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK               0x00000001U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET				       0U
-#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147
-#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN
-
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK				0x00000100U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET				        0U
-#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147
-#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN
-
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK               0x00010000U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET				       0U
-#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147
-#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN
-
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET				           0U
-#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147
-#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17
-
-#define LPDDR4__DENALI_CTL_148_READ_MASK				             0x3F3F0101U
-#define LPDDR4__DENALI_CTL_148_WRITE_MASK				            0x3F3F0101U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET				            0U
-#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148
-#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN
-
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK				     0x00000100U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET				             0U
-#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148
-#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN
-
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK            0x003F0000U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH				    6U
-#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148
-#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH
-
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK             0x3F000000U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH				     6U
-#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148
-#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH
-
-#define LPDDR4__DENALI_CTL_149_READ_MASK				             0x01FF03FFU
-#define LPDDR4__DENALI_CTL_149_WRITE_MASK				            0x01FF03FFU
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK            0x000000FFU
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH				    8U
-#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149
-#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER
-
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK				   0x00000300U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH				           2U
-#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149
-#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK
-
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH				           8U
-#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149
-#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18
-
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK				      0x01000000U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET				              0U
-#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149
-#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE
-
-#define LPDDR4__DENALI_CTL_150_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_150_WRITE_MASK				            0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK              0x000003FFU
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH				     10U
-#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150
-#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0
-
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH				  16U
-#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150
-#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0
-
-#define LPDDR4__DENALI_CTL_151_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_151_WRITE_MASK				            0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK              0x000003FFU
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH				     10U
-#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151
-#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1
-
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH				  16U
-#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151
-#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1
-
-#define LPDDR4__DENALI_CTL_152_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_152_WRITE_MASK				            0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK              0x000003FFU
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH				     10U
-#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152
-#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2
-
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH				  16U
-#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152
-#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2
-
-#define LPDDR4__DENALI_CTL_153_READ_MASK				             0x00000103U
-#define LPDDR4__DENALI_CTL_153_WRITE_MASK				            0x00000103U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK				0x00000003U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH				        2U
-#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153
-#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY
-
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK            0x00000100U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT				    8U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET				    0U
-#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153
-#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN
-
-#define LPDDR4__DENALI_CTL_154_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH				 32U
-#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154
-#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR
-
-#define LPDDR4__DENALI_CTL_155_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_155_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT               0U
-#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH              32U
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0
-
-#define LPDDR4__DENALI_CTL_156_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_156_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT               0U
-#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH              32U
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1
-
-#define LPDDR4__DENALI_CTL_157_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_157_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT               0U
-#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH              32U
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2
-
-#define LPDDR4__DENALI_CTL_158_READ_MASK				             0x00FFFF0FU
-#define LPDDR4__DENALI_CTL_158_WRITE_MASK				            0x00FFFF0FU
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK          0x0000000FU
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH				  4U
-#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158
-#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK
-
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK          0x00FFFF00U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH				 16U
-#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158
-#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT
-
-#define LPDDR4__DENALI_CTL_159_READ_MASK				             0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159_WRITE_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK				   0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH				          27U
-#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159
-#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG
-
-#define LPDDR4__DENALI_CTL_160_READ_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_160_WRITE_MASK				            0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK				      0x000000FFU
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH				              8U
-#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160
-#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS
-
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK				    0x01FFFF00U
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH				           17U
-#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160
-#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG
-
-#define LPDDR4__DENALI_CTL_161_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH				  32U
-#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161
-#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0
-
-#define LPDDR4__DENALI_CTL_162_READ_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_162_WRITE_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK           0x000000FFU
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH				   8U
-#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162
-#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1
-
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK              0x00FFFF00U
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH				     16U
-#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162
-#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0
-
-#define LPDDR4__DENALI_CTL_163_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_CTL_163_WRITE_MASK				            0x0001FFFFU
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK              0x0000FFFFU
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH				     16U
-#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163
-#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1
-
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK            0x00010000U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET				    0U
-#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163
-#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG
-
-#define LPDDR4__DENALI_CTL_164_READ_MASK				             0x03FF0003U
-#define LPDDR4__DENALI_CTL_164_WRITE_MASK				            0x03FF0003U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK              0x00000003U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH				      2U
-#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164
-#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC
-
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK				 0x03FF0000U
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH				        10U
-#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164
-#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0
-
-#define LPDDR4__DENALI_CTL_165_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_165_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH				       10U
-#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165
-#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0
-
-#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK				          0x03FF0000U
-#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH								 10U
-#define LPDDR4__TFC_F0__REG DENALI_CTL_165
-#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0
-
-#define LPDDR4__DENALI_CTL_166_READ_MASK				             0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_166_WRITE_MASK				            0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH				              5U
-#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166
-#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0
-
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH				              5U
-#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166
-#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0
-
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK				   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH				          16U
-#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166
-#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0
-
-#define LPDDR4__DENALI_CTL_167_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_167_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK				 0x000003FFU
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH				        10U
-#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167
-#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1
-
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK				0x03FF0000U
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH				       10U
-#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167
-#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1
-
-#define LPDDR4__DENALI_CTL_168_READ_MASK				             0x1F1F03FFU
-#define LPDDR4__DENALI_CTL_168_WRITE_MASK				            0x1F1F03FFU
-#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK				          0x000003FFU
-#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH								 10U
-#define LPDDR4__TFC_F1__REG DENALI_CTL_168
-#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1
-
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK				      0x001F0000U
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH				              5U
-#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168
-#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1
-
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK				      0x1F000000U
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH				              5U
-#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168
-#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1
-
-#define LPDDR4__DENALI_CTL_169_READ_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_169_WRITE_MASK				            0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK				   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH				          16U
-#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169
-#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1
-
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK				 0x03FF0000U
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH				        10U
-#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169
-#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2
-
-#define LPDDR4__DENALI_CTL_170_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_170_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH				       10U
-#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170
-#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2
-
-#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK				          0x03FF0000U
-#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH								 10U
-#define LPDDR4__TFC_F2__REG DENALI_CTL_170
-#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2
-
-#define LPDDR4__DENALI_CTL_171_READ_MASK				             0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_171_WRITE_MASK				            0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH				              5U
-#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171
-#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2
-
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH				              5U
-#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171
-#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2
-
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK				   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH				          16U
-#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171
-#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2
-
-#define LPDDR4__DENALI_CTL_172_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_172_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT				0U
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH               16U
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT               16U
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH               16U
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_173_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_173_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT				0U
-#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH               16U
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
-#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT               16U
-#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH               16U
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_174_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_174_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT				0U
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH               16U
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT               16U
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH               16U
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_175_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_175_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH				           8U
-#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175
-#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH				           8U
-#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175
-#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH				           8U
-#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175
-#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH				           8U
-#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175
-#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_176_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_176_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH				           8U
-#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176
-#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH				           8U
-#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176
-#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH				         8U
-#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176
-#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0
-
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH				           8U
-#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176
-#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_177_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_177_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH				           8U
-#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177
-#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH				           8U
-#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177
-#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH				           8U
-#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177
-#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH				           8U
-#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177
-#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_178_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_178_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH				           8U
-#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178
-#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH				              8U
-#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178
-#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0
-
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH				          8U
-#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178
-#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH				          8U
-#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178
-#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_179_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_179_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH				          8U
-#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179
-#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH				          8U
-#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179
-#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH				          8U
-#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179
-#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH				          8U
-#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179
-#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_180_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_180_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH				             8U
-#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180
-#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0
-
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH				          8U
-#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180
-#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH				          8U
-#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180
-#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH				          8U
-#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180
-#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_181_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_181_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH				             8U
-#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181
-#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0
-
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK				     0x0000FF00U
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH				             8U
-#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181
-#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0
-
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH				             8U
-#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181
-#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0
-
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH				          8U
-#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181
-#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_182_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_182_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH				          8U
-#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182
-#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH				          8U
-#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182
-#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH				           8U
-#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182
-#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH				           8U
-#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182
-#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_183_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_183_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH				           8U
-#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183
-#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH				           8U
-#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183
-#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH				           8U
-#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183
-#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH				           8U
-#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183
-#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_184_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_184_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH				         8U
-#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184
-#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1
-
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH				           8U
-#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184
-#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH				           8U
-#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184
-#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH				           8U
-#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184
-#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_185_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_185_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH				           8U
-#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185
-#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH				           8U
-#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185
-#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH				           8U
-#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185
-#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK				      0xFF000000U
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH				              8U
-#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185
-#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1
-
-#define LPDDR4__DENALI_CTL_186_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_186_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH				          8U
-#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186
-#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH				          8U
-#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186
-#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH				          8U
-#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186
-#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH				          8U
-#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186
-#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_187_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_187_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH				          8U
-#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187
-#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH				          8U
-#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187
-#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH				             8U
-#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187
-#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1
-
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH				          8U
-#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187
-#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_188_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_188_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH				          8U
-#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188
-#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH				          8U
-#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188
-#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH				             8U
-#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188
-#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1
-
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK				     0xFF000000U
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH				             8U
-#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188
-#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1
-
-#define LPDDR4__DENALI_CTL_189_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_189_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH				             8U
-#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189
-#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1
-
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH				          8U
-#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189
-#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH				          8U
-#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189
-#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH				          8U
-#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189
-#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_190_READ_MASK				             0x010101FFU
-#define LPDDR4__DENALI_CTL_190_WRITE_MASK				            0x010101FFU
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK				       0x000000FFU
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH				               8U
-#define LPDDR4__MR23_DATA__REG DENALI_CTL_190
-#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA
-
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK            0x00000100U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT				    8U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET				    0U
-#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190
-#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0
-
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK            0x00010000U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET				    0U
-#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190
-#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1
-
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK            0x01000000U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT				   24U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET				    0U
-#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190
-#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2
-
-#define LPDDR4__DENALI_CTL_191_READ_MASK				             0x01010103U
-#define LPDDR4__DENALI_CTL_191_WRITE_MASK				            0x01010103U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK				  0x00000003U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH				          2U
-#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191
-#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN
-
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET				           0U
-#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191
-#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19
-
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET				           0U
-#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191
-#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20
-
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK              0x01000000U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET				      0U
-#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191
-#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW
-
-#define LPDDR4__DENALI_CTL_192_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_192_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK            0x00000001U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET				    0U
-#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192
-#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP
-
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK				      0x00000100U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET				              0U
-#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192
-#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS
-
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK				  0x00010000U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET				          0U
-#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192
-#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT
-
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET				          0U
-#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192
-#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT
-
-#define LPDDR4__DENALI_CTL_193_READ_MASK				             0x03030101U
-#define LPDDR4__DENALI_CTL_193_WRITE_MASK				            0x03030101U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK				  0x00000001U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET				          0U
-#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193
-#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID
-
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET				          0U
-#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193
-#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID
-
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK				        0x00030000U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH								2U
-#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193
-#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC
-
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK				        0x03000000U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH								2U
-#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193
-#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC
-
-#define LPDDR4__DENALI_CTL_194_READ_MASK				             0x013F0300U
-#define LPDDR4__DENALI_CTL_194_WRITE_MASK				            0x013F0300U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK				         0x00000001U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH								 1U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR								 0U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET								 0U
-#define LPDDR4__BIST_GO__REG DENALI_CTL_194
-#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO
-
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK				     0x00000300U
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH				             2U
-#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194
-#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT
-
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK				      0x003F0000U
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH				              6U
-#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194
-#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE
-
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET				         0U
-#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194
-#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK
-
-#define LPDDR4__DENALI_CTL_195_READ_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_195_WRITE_MASK				            0x00000001U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET				         0U
-#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195
-#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK
-
-#define LPDDR4__DENALI_CTL_196_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH				   32U
-#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196
-#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0
-
-#define LPDDR4__DENALI_CTL_197_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_197_WRITE_MASK				            0x00000007U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK            0x00000007U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH				    3U
-#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197
-#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1
-
-#define LPDDR4__DENALI_CTL_198_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH				       32U
-#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198
-#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0
-
-#define LPDDR4__DENALI_CTL_199_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH				       32U
-#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199
-#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1
-
-#define LPDDR4__DENALI_CTL_200_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_200_WRITE_MASK				            0x00000007U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK				  0x00000007U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH				          3U
-#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200
-#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE
-
-#define LPDDR4__DENALI_CTL_201_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH				    32U
-#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201
-#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0
-
-#define LPDDR4__DENALI_CTL_202_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH				    32U
-#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202
-#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1
-
-#define LPDDR4__DENALI_CTL_203_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH				    32U
-#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203
-#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2
-
-#define LPDDR4__DENALI_CTL_204_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH				    32U
-#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204
-#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3
-
-#define LPDDR4__DENALI_CTL_205_READ_MASK				             0x0FFF0100U
-#define LPDDR4__DENALI_CTL_205_WRITE_MASK				            0x0FFF0100U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK             0x00000001U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET				     0U
-#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205
-#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT
-
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET				          0U
-#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205
-#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE
-
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK				   0x0FFF0000U
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH				          12U
-#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205
-#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP
-
-#define LPDDR4__DENALI_CTL_206_READ_MASK				             0x07030FFFU
-#define LPDDR4__DENALI_CTL_206_WRITE_MASK				            0x07030FFFU
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK				  0x00000FFFU
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH				         12U
-#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206
-#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT
-
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK				      0x00030000U
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH				              2U
-#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206
-#define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE
-
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK          0x07000000U
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT				 24U
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH				  3U
-#define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206
-#define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET
-
-#define LPDDR4__DENALI_CTL_207_READ_MASK				             0x010F0101U
-#define LPDDR4__DENALI_CTL_207_WRITE_MASK				            0x010F0101U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK             0x00000001U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET				     0U
-#define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207
-#define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN
-
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK          0x00000100U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH				  1U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR				  0U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET				  0U
-#define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207
-#define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN
-
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH				           4U
-#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207
-#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21
-
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET				           0U
-#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207
-#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22
-
-#define LPDDR4__DENALI_CTL_208_READ_MASK				             0x01FFFF01U
-#define LPDDR4__DENALI_CTL_208_WRITE_MASK				            0x01FFFF01U
-#define LPDDR4__DENALI_CTL_208__FWC_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_208__FWC_SHIFT								     0U
-#define LPDDR4__DENALI_CTL_208__FWC_WIDTH								     1U
-#define LPDDR4__DENALI_CTL_208__FWC_WOCLR								     0U
-#define LPDDR4__DENALI_CTL_208__FWC_WOSET								     0U
-#define LPDDR4__FWC__REG DENALI_CTL_208
-#define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC
-
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK				  0x00FFFF00U
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH				         16U
-#define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208
-#define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS
-
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK				0x01000000U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT				       24U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET				        0U
-#define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208
-#define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN
-
-#define LPDDR4__DENALI_CTL_209_READ_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_209_WRITE_MASK				            0x00000001U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK            0x00000001U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET				    0U
-#define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209
-#define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR
-
-#define LPDDR4__DENALI_CTL_210_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH				           32U
-#define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210
-#define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0
-
-#define LPDDR4__DENALI_CTL_211_READ_MASK				             0x0000FF07U
-#define LPDDR4__DENALI_CTL_211_WRITE_MASK				            0x0000FF07U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK				    0x00000007U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH				            3U
-#define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211
-#define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1
-
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH				              8U
-#define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211
-#define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND
-
-#define LPDDR4__DENALI_CTL_212_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH				           32U
-#define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212
-#define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0
-
-#define LPDDR4__DENALI_CTL_213_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH				           32U
-#define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213
-#define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1
-
-#define LPDDR4__DENALI_CTL_214_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH				           32U
-#define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214
-#define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0
-
-#define LPDDR4__DENALI_CTL_215_READ_MASK				             0x0000FF07U
-#define LPDDR4__DENALI_CTL_215_WRITE_MASK				            0x0000FF07U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK				    0x00000007U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH				            3U
-#define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215
-#define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1
-
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH				              8U
-#define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215
-#define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND
-
-#define LPDDR4__DENALI_CTL_216_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH				           32U
-#define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216
-#define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0
-
-#define LPDDR4__DENALI_CTL_217_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH				           32U
-#define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217
-#define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1
-
-#define LPDDR4__DENALI_CTL_218_READ_MASK				             0x7FFF3F3FU
-#define LPDDR4__DENALI_CTL_218_WRITE_MASK				            0x7FFF3F3FU
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK				        0x0000003FU
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT								0U
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH								6U
-#define LPDDR4__ECC_U_ID__REG DENALI_CTL_218
-#define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID
-
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK				        0x00003F00U
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT								8U
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH								6U
-#define LPDDR4__ECC_C_ID__REG DENALI_CTL_218
-#define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID
-
-#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK     0x7FFF0000U
-#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT            16U
-#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH            15U
-#define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218
-#define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0
-
-#define LPDDR4__DENALI_CTL_219_READ_MASK				             0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_219_WRITE_MASK				            0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK       0x00007FFFU
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT               0U
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH              15U
-#define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219
-#define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0
-
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK     0x7FFF0000U
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT            16U
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH            15U
-#define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219
-#define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1
-
-#define LPDDR4__DENALI_CTL_220_READ_MASK				             0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_220_WRITE_MASK				            0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK       0x00007FFFU
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT               0U
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH              15U
-#define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220
-#define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1
-
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK     0x7FFF0000U
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT            16U
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH            15U
-#define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220
-#define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2
-
-#define LPDDR4__DENALI_CTL_221_READ_MASK				             0x00077FFFU
-#define LPDDR4__DENALI_CTL_221_WRITE_MASK				            0x00077FFFU
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK       0x00007FFFU
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT               0U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH              15U
-#define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221
-#define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2
-
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK           0x00070000U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH				   3U
-#define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221
-#define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE
-
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET				         0U
-#define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221
-#define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START
-
-#define LPDDR4__DENALI_CTL_222_READ_MASK				             0x010FFF01U
-#define LPDDR4__DENALI_CTL_222_WRITE_MASK				            0x010FFF01U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK           0x00000001U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH				   1U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR				   0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET				   0U
-#define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222
-#define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS
-
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK				   0x000FFF00U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH				          12U
-#define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222
-#define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN
-
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET				          0U
-#define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222
-#define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE
-
-#define LPDDR4__DENALI_CTL_223_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_223_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK              0x0000FFFFU
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH				     16U
-#define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223
-#define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL
-
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK              0xFFFF0000U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH				     16U
-#define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223
-#define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT
-
-#define LPDDR4__DENALI_CTL_224_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH				 32U
-#define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224
-#define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0
-
-#define LPDDR4__DENALI_CTL_225_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_225_WRITE_MASK				            0x00000007U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK          0x00000007U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH				  3U
-#define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225
-#define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1
-
-#define LPDDR4__DENALI_CTL_226_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH				   32U
-#define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226
-#define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0
-
-#define LPDDR4__DENALI_CTL_227_READ_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_227_WRITE_MASK				            0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK            0x00000007U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH				    3U
-#define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227
-#define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1
-
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK				 0x00001F00U
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH				         5U
-#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227
-#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK
-
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK             0x001F0000U
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH				     5U
-#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227
-#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK             0x1F000000U
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH				     5U
-#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227
-#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_228_READ_MASK				             0x000F1F1FU
-#define LPDDR4__DENALI_CTL_228_WRITE_MASK				            0x000F1F1FU
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK				0x0000001FU
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH				        5U
-#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228
-#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT
-
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK				 0x00001F00U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH				         5U
-#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228
-#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT
-
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK          0x000F0000U
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH				  4U
-#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228
-#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI
-
-#define LPDDR4__DENALI_CTL_229_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_229_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT           0U
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT          16U
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_230_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_230_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT           0U
-#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_231_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_231_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH				 16U
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_232_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_232_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH				 16U
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH				       16U
-#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232
-#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_233_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_233_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT          16U
-#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_234_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_234_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT           0U
-#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT          16U
-#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_235_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_235_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_236_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_236_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH				 16U
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH				 16U
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_237_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_237_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH				       16U
-#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237
-#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_238_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_238_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT           0U
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT          16U
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_239_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_239_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT           0U
-#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_240_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_240_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH				 16U
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_241_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_241_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH				 16U
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH				       16U
-#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241
-#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_242_READ_MASK				             0x0007FFFFU
-#define LPDDR4__DENALI_CTL_242_WRITE_MASK				            0x0007FFFFU
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH				           3U
-#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242
-#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23
-
-#define LPDDR4__DENALI_CTL_243_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_243_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT          0U
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH         16U
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0
-
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT          16U
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH          16U
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0
-
-#define LPDDR4__DENALI_CTL_244_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_244_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT     0U
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH    16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0
-
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK     0xFFFF0000U
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT            16U
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH            16U
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0
-
-#define LPDDR4__DENALI_CTL_245_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_245_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT          0U
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH         16U
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0
-
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0
-
-#define LPDDR4__DENALI_CTL_246_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_246_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT   0U
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH  16U
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0
-
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT  16U
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH  16U
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0
-
-#define LPDDR4__DENALI_CTL_247_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_247_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT          0U
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH         16U
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1
-
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT          16U
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH          16U
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1
-
-#define LPDDR4__DENALI_CTL_248_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_248_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT     0U
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH    16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1
-
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK     0xFFFF0000U
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT            16U
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH            16U
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1
-
-#define LPDDR4__DENALI_CTL_249_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_249_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT          0U
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH         16U
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1
-
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1
-
-#define LPDDR4__DENALI_CTL_250_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_250_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT   0U
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH  16U
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1
-
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT  16U
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH  16U
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1
-
-#define LPDDR4__DENALI_CTL_251_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_251_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT          0U
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH         16U
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2
-
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT          16U
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH          16U
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2
-
-#define LPDDR4__DENALI_CTL_252_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_252_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT     0U
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH    16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2
-
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK     0xFFFF0000U
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT            16U
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH            16U
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2
-
-#define LPDDR4__DENALI_CTL_253_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_253_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT          0U
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH         16U
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2
-
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2
-
-#define LPDDR4__DENALI_CTL_254_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_254_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT   0U
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH  16U
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2
-
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT  16U
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH  16U
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2
-
-#define LPDDR4__DENALI_CTL_255_READ_MASK				             0x0000FF00U
-#define LPDDR4__DENALI_CTL_255_WRITE_MASK				            0x0000FF00U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH				         8U
-#define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255
-#define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD
-
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK        0x0000FF00U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT				8U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH				8U
-#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255
-#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE
-
-#define LPDDR4__DENALI_CTL_256_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK               0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH				      20U
-#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256
-#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG
-
-#define LPDDR4__DENALI_CTL_257_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_257_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH				              12U
-#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257
-#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0
-
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK				         0x0FFF0000U
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT								16U
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH								12U
-#define LPDDR4__ZQCL_F0__REG DENALI_CTL_257
-#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0
-
-#define LPDDR4__DENALI_CTL_258_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_258_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK				         0x00000FFFU
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH								12U
-#define LPDDR4__ZQCS_F0__REG DENALI_CTL_258
-#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0
-
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK				       0x0FFF0000U
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH				              12U
-#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258
-#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0
-
-#define LPDDR4__DENALI_CTL_259_READ_MASK				             0x000FFF7FU
-#define LPDDR4__DENALI_CTL_259_WRITE_MASK				            0x000FFF7FU
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK				       0x0000007FU
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH				               7U
-#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259
-#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0
-
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK				       0x000FFF00U
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH				              12U
-#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259
-#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1
-
-#define LPDDR4__DENALI_CTL_260_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_260_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK				         0x00000FFFU
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH								12U
-#define LPDDR4__ZQCL_F1__REG DENALI_CTL_260
-#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1
-
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK				         0x0FFF0000U
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT								16U
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH								12U
-#define LPDDR4__ZQCS_F1__REG DENALI_CTL_260
-#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1
-
-#define LPDDR4__DENALI_CTL_261_READ_MASK				             0x007F0FFFU
-#define LPDDR4__DENALI_CTL_261_WRITE_MASK				            0x007F0FFFU
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH				              12U
-#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261
-#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1
-
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK				       0x007F0000U
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH				               7U
-#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261
-#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1
-
-#define LPDDR4__DENALI_CTL_262_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_262_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH				              12U
-#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262
-#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2
-
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK				         0x0FFF0000U
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT								16U
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH								12U
-#define LPDDR4__ZQCL_F2__REG DENALI_CTL_262
-#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2
-
-#define LPDDR4__DENALI_CTL_263_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_263_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK				         0x00000FFFU
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH								12U
-#define LPDDR4__ZQCS_F2__REG DENALI_CTL_263
-#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2
-
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK				       0x0FFF0000U
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH				              12U
-#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263
-#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2
-
-#define LPDDR4__DENALI_CTL_264_READ_MASK				             0x0100037FU
-#define LPDDR4__DENALI_CTL_264_WRITE_MASK				            0x0100037FU
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK				       0x0000007FU
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH				               7U
-#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264
-#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2
-
-#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK       0x00000300U
-#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT               8U
-#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH               2U
-#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264
-#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP
-
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK				          0x000F0000U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH								  4U
-#define LPDDR4__ZQ_REQ__REG DENALI_CTL_264
-#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ
-
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET				          0U
-#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264
-#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING
-
-#define LPDDR4__DENALI_CTL_265_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_265_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK				      0x00000FFFU
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH				             12U
-#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265
-#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0
-
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK				      0x0FFF0000U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH				             12U
-#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265
-#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1
-
-#define LPDDR4__DENALI_CTL_266_READ_MASK				             0x01010FFFU
-#define LPDDR4__DENALI_CTL_266_WRITE_MASK				            0x01010FFFU
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK				      0x00000FFFU
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH				             12U
-#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266
-#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2
-
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET				              0U
-#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266
-#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT
-
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET				             0U
-#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266
-#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE
-
-#define LPDDR4__DENALI_CTL_267_READ_MASK				             0x03030303U
-#define LPDDR4__DENALI_CTL_267_WRITE_MASK				            0x03030303U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK              0x00000003U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH				      2U
-#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0
-
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK              0x00000300U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH				      2U
-#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0
-
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK              0x00030000U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH				      2U
-#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1
-
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK              0x03000000U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH				      2U
-#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1
-
-#define LPDDR4__DENALI_CTL_268_READ_MASK				             0x07070303U
-#define LPDDR4__DENALI_CTL_268_WRITE_MASK				            0x07070303U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK				     0x00000003U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH				             2U
-#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268
-#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0
-
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK				     0x00000300U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH				             2U
-#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268
-#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1
-
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK				      0x00070000U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH				              3U
-#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268
-#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0
-
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK				      0x07000000U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH				              3U
-#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268
-#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1
-
-#define LPDDR4__DENALI_CTL_269_READ_MASK				             0xFFFF0F0FU
-#define LPDDR4__DENALI_CTL_269_WRITE_MASK				            0xFFFF0F0FU
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK				      0x0000000FU
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH				              4U
-#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269
-#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0
-
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK				      0x00000F00U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH				              4U
-#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269
-#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1
-
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK				  0xFFFF0000U
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH				         16U
-#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269
-#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0
-
-#define LPDDR4__DENALI_CTL_270_READ_MASK				             0x0007FFFFU
-#define LPDDR4__DENALI_CTL_270_WRITE_MASK				            0x0007FFFFU
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK				  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH				         16U
-#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270
-#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0
-
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK				 0x00070000U
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH				         3U
-#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270
-#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0
-
-#define LPDDR4__DENALI_CTL_271_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_271_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK				  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH				         16U
-#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271
-#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1
-
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK				  0xFFFF0000U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH				         16U
-#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271
-#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1
-
-#define LPDDR4__DENALI_CTL_272_READ_MASK				             0xFFFF0307U
-#define LPDDR4__DENALI_CTL_272_WRITE_MASK				            0xFFFF0307U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH				         3U
-#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272
-#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1
-
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK				 0x00000300U
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH				         2U
-#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272
-#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2
-
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK				        0xFFFF0000U
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH				               16U
-#define LPDDR4__CS_MSK_0__REG DENALI_CTL_272
-#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0
-
-#define LPDDR4__DENALI_CTL_273_READ_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_273_WRITE_MASK				            0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK				        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH				               16U
-#define LPDDR4__CS_MSK_1__REG DENALI_CTL_273
-#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1
-
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET				        0U
-#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273
-#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN
-
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK				   0x1F000000U
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH				           5U
-#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273
-#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24
-
-#define LPDDR4__DENALI_CTL_274_READ_MASK				             0xFFFF1F01U
-#define LPDDR4__DENALI_CTL_274_WRITE_MASK				            0xFFFF1F01U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET				           0U
-#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274
-#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25
-
-#define LPDDR4__DENALI_CTL_274__APREBIT_MASK				         0x00001F00U
-#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH								 5U
-#define LPDDR4__APREBIT__REG DENALI_CTL_274
-#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT
-
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK				       0x00FF0000U
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH				               8U
-#define LPDDR4__AGE_COUNT__REG DENALI_CTL_274
-#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT
-
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK               0xFF000000U
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH				       8U
-#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274
-#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT
-
-#define LPDDR4__DENALI_CTL_275_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_275_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET				             0U
-#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275
-#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN
-
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK          0x00000100U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH				  1U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR				  0U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET				  0U
-#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275
-#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS
-
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET				           0U
-#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275
-#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN
-
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK				    0x01000000U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET				            0U
-#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275
-#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN
-
-#define LPDDR4__DENALI_CTL_276_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_276_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET				             0U
-#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276
-#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN
-
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK				      0x00000100U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET				              0U
-#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276
-#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN
-
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK				 0x00010000U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET				         0U
-#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276
-#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN
-
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK				      0x01000000U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET				              0U
-#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276
-#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN
-
-#define LPDDR4__DENALI_CTL_277_READ_MASK				             0x011F0301U
-#define LPDDR4__DENALI_CTL_277_WRITE_MASK				            0x011F0301U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET				            0U
-#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277
-#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN
-
-#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT         8U
-#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH         2U
-#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277
-#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT
-
-#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK       0x001F0000U
-#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT              16U
-#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH               5U
-#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277
-#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE
-
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK				         0x01000000U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT								24U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH								 1U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR								 0U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET								 0U
-#define LPDDR4__SWAP_EN__REG DENALI_CTL_277
-#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN
-
-#define LPDDR4__DENALI_CTL_278_READ_MASK				             0x01030301U
-#define LPDDR4__DENALI_CTL_278_WRITE_MASK				            0x01030301U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK           0x00000001U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH				   1U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR				   0U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET				   0U
-#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278
-#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE
-
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK				0x00000300U
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH				        2U
-#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278
-#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD
-
-#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK				          0x00030000U
-#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH								  2U
-#define LPDDR4__CS_MAP__REG DENALI_CTL_278
-#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP
-
-#define LPDDR4__DENALI_CTL_278__REDUC_MASK				           0x01000000U
-#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH								   1U
-#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR								   0U
-#define LPDDR4__DENALI_CTL_278__REDUC_WOSET								   0U
-#define LPDDR4__REDUC__REG DENALI_CTL_278
-#define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC
-
-#define LPDDR4__DENALI_CTL_279_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279_WRITE_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK        0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT				0U
-#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH               18U
-#define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279
-#define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_280_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_CTL_280_WRITE_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK    0x0003FFFFU
-#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT            0U
-#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH           18U
-#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280
-#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS
-
-#define LPDDR4__DENALI_CTL_281_READ_MASK				             0x0103FFFFU
-#define LPDDR4__DENALI_CTL_281_WRITE_MASK				            0x0103FFFFU
-#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT      0U
-#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH     18U
-#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281
-#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK       0x01000000U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT              24U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH               1U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR               0U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET               0U
-#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281
-#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282_READ_MASK				             0x01010103U
-#define LPDDR4__DENALI_CTL_282_WRITE_MASK				            0x01010103U
-#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK       0x00000003U
-#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT               0U
-#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH               2U
-#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK       0x00000100U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT               8U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH               1U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR               0U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET               0U
-#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK        0x00010000U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT               16U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH				1U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR				0U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET				0U
-#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK        0x01000000U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT               24U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH				1U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR				0U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET				0U
-#define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_283_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_283_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET				           0U
-#define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283
-#define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26
-
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET				           0U
-#define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283
-#define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27
-
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK       0x00010000U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT              16U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH               1U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR               0U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET               0U
-#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283
-#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN
-
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK        0x01000000U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT               24U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH				1U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR				0U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET				0U
-#define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283
-#define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN
-
-#define LPDDR4__DENALI_CTL_284_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_284_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT       0U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH       1U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR       0U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET       0U
-#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT       8U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH       1U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR       0U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET       0U
-#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT      16U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH       1U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR       0U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET       0U
-#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT       24U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH        1U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR        0U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET        0U
-#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_285_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_285_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT        0U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH        1U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR        0U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET        0U
-#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285
-#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK  0x00000100U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT          8U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH          1U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR          0U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET          0U
-#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285
-#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT
-
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT        16U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH         1U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR         0U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET         0U
-#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285
-#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN
-
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK   0x01000000U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT          24U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH           1U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR           0U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET           0U
-#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285
-#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_286_READ_MASK				             0x0F0F0F07U
-#define LPDDR4__DENALI_CTL_286_WRITE_MASK				            0x0F0F0F07U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH				         3U
-#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286
-#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0
-
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK               0x00000F00U
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH				       4U
-#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286
-#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK               0x000F0000U
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH				       4U
-#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286
-#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK               0x0F000000U
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH				       4U
-#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286
-#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_287_READ_MASK				             0x0F0F070FU
-#define LPDDR4__DENALI_CTL_287_WRITE_MASK				            0x0F0F070FU
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK               0x0000000FU
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH				       4U
-#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287
-#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK				 0x00000700U
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH				         3U
-#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287
-#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1
-
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK               0x000F0000U
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH				       4U
-#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287
-#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK               0x0F000000U
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH				       4U
-#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287
-#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_288_READ_MASK				             0x011F0F0FU
-#define LPDDR4__DENALI_CTL_288_WRITE_MASK				            0x011F0F0FU
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK               0x0000000FU
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH				       4U
-#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288
-#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK               0x00000F00U
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH				       4U
-#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288
-#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK				      0x001F0000U
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH				              5U
-#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288
-#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS
-
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET				         0U
-#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288
-#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT
-
-#define LPDDR4__DENALI_CTL_289_READ_MASK				             0x01000103U
-#define LPDDR4__DENALI_CTL_289_WRITE_MASK				            0x01000103U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK				    0x00000003U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH				            2U
-#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289
-#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ
-
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK				 0x00000100U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET				         0U
-#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289
-#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY
-
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET				             0U
-#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289
-#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ
-
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK         0x01000000U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT				24U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET				 0U
-#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289
-#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN
-
-#define LPDDR4__DENALI_CTL_290_READ_MASK				             0x03030301U
-#define LPDDR4__DENALI_CTL_290_WRITE_MASK				            0x03030301U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK          0x00000001U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH				  1U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR				  0U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET				  0U
-#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290
-#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE
-
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK             0x00000300U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH				     2U
-#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290
-#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0
-
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK             0x00030000U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH				     2U
-#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290
-#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1
-
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK             0x03000000U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH				     2U
-#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290
-#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2
-
-#define LPDDR4__DENALI_CTL_291_READ_MASK				             0x1F010101U
-#define LPDDR4__DENALI_CTL_291_WRITE_MASK				            0x1F010101U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK         0x00000001U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET				 0U
-#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291
-#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN
-
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK				       0x00000100U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET				               0U
-#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291
-#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN
-
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK				       0x00010000U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET				               0U
-#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291
-#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN
-
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH				               5U
-#define LPDDR4__DFI_ERROR__REG DENALI_CTL_291
-#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR
-
-#define LPDDR4__DENALI_CTL_292_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH				         20U
-#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292
-#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO
-
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET				           0U
-#define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292
-#define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28
-
-#define LPDDR4__DENALI_CTL_293_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH				           32U
-#define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293
-#define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0
-
-#define LPDDR4__DENALI_CTL_294_READ_MASK				             0x00001FFFU
-#define LPDDR4__DENALI_CTL_294_WRITE_MASK				            0x00001FFFU
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK				    0x00001FFFU
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH				           13U
-#define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294
-#define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1
-
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK				       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH				              32U
-#define LPDDR4__INT_ACK_0__REG DENALI_CTL_295
-#define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0
-
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH				              12U
-#define LPDDR4__INT_ACK_1__REG DENALI_CTL_296
-#define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1
-
-#define LPDDR4__DENALI_CTL_297_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK				      0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH				             32U
-#define LPDDR4__INT_MASK_0__REG DENALI_CTL_297
-#define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0
-
-#define LPDDR4__DENALI_CTL_298_READ_MASK				             0x00001FFFU
-#define LPDDR4__DENALI_CTL_298_WRITE_MASK				            0x00001FFFU
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK				      0x00001FFFU
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH				             13U
-#define LPDDR4__INT_MASK_1__REG DENALI_CTL_298
-#define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1
-
-#define LPDDR4__DENALI_CTL_299_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH				    32U
-#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299
-#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0
-
-#define LPDDR4__DENALI_CTL_300_READ_MASK				             0x7F0FFF07U
-#define LPDDR4__DENALI_CTL_300_WRITE_MASK				            0x7F0FFF07U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK             0x00000007U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH				     3U
-#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300
-#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1
-
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK             0x000FFF00U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH				    12U
-#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300
-#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH
-
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK               0x7F000000U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH				       7U
-#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300
-#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE
-
-#define LPDDR4__DENALI_CTL_301_READ_MASK				             0x0000003FU
-#define LPDDR4__DENALI_CTL_301_WRITE_MASK				            0x0000003FU
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK          0x0000003FU
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH				  6U
-#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301
-#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID
-
-#define LPDDR4__DENALI_CTL_302_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH				        32U
-#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302
-#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0
-
-#define LPDDR4__DENALI_CTL_303_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH				        32U
-#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303
-#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1
-
-#define LPDDR4__DENALI_CTL_304_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH				        32U
-#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304
-#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2
-
-#define LPDDR4__DENALI_CTL_305_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH				        32U
-#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305
-#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3
-
-#define LPDDR4__DENALI_CTL_306_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH				       32U
-#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306
-#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0
-
-#define LPDDR4__DENALI_CTL_307_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH				       32U
-#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307
-#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1
-
-#define LPDDR4__DENALI_CTL_308_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH				       32U
-#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308
-#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2
-
-#define LPDDR4__DENALI_CTL_309_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH				       32U
-#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309
-#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3
-
-#define LPDDR4__DENALI_CTL_310_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH				       32U
-#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310
-#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0
-
-#define LPDDR4__DENALI_CTL_311_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_311_WRITE_MASK				            0x00000007U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK				0x00000007U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH				        3U
-#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311
-#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1
-
-#define LPDDR4__DENALI_CTL_312_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH				  32U
-#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312
-#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0
-
-#define LPDDR4__DENALI_CTL_313_READ_MASK				             0x03033F07U
-#define LPDDR4__DENALI_CTL_313_WRITE_MASK				            0x03033F07U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK           0x00000007U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH				   3U
-#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313
-#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1
-
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK               0x00003F00U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH				       6U
-#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313
-#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID
-
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK             0x00030000U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH				     2U
-#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313
-#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE
-
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK				  0x03000000U
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH				          2U
-#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313
-#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0
-
-#define LPDDR4__DENALI_CTL_314_READ_MASK				             0xFF030303U
-#define LPDDR4__DENALI_CTL_314_WRITE_MASK				            0xFF030303U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK				  0x00000003U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH				          2U
-#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314
-#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0
-
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK				  0x00000300U
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH				          2U
-#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314
-#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1
-
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK				  0x00030000U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH				          2U
-#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314
-#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1
-
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH				           8U
-#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314
-#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0
-
-#define LPDDR4__DENALI_CTL_315_READ_MASK				             0x0FFF0F0FU
-#define LPDDR4__DENALI_CTL_315_WRITE_MASK				            0x0FFF0F0FU
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK				     0x0000000FU
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH				             4U
-#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315
-#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0
-
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK				     0x00000F00U
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH				             4U
-#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315
-#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0
-
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH				           8U
-#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315
-#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1
-
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK				     0x0F000000U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH				             4U
-#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315
-#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1
-
-#define LPDDR4__DENALI_CTL_316_READ_MASK				             0x0F0FFF0FU
-#define LPDDR4__DENALI_CTL_316_WRITE_MASK				            0x0F0FFF0FU
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK				     0x0000000FU
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH				             4U
-#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316
-#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1
-
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH				           8U
-#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316
-#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2
-
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK				     0x000F0000U
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH				             4U
-#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316
-#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2
-
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK				     0x0F000000U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH				             4U
-#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316
-#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2
-
-#define LPDDR4__DENALI_CTL_317_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_317_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK				       0x00000001U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET				               0U
-#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317
-#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0
-
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK				       0x00000100U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET				               0U
-#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317
-#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1
-
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK				       0x00010000U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET				               0U
-#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317
-#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2
-
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK         0x01000000U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT				24U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET				 0U
-#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317
-#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD
-
-#define LPDDR4__DENALI_CTL_318_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_CTL_318_WRITE_MASK				            0x3F3F3F3FU
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK				   0x0000003FU
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH				           6U
-#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318
-#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0
-
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK				   0x00003F00U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH				           6U
-#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318
-#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1
-
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK				   0x003F0000U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH				           6U
-#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318
-#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2
-
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK				   0x3F000000U
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH				           6U
-#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318
-#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0
-
-#define LPDDR4__DENALI_CTL_319_READ_MASK				             0x1F1F3F3FU
-#define LPDDR4__DENALI_CTL_319_WRITE_MASK				            0x1F1F3F3FU
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK				   0x0000003FU
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH				           6U
-#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319
-#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1
-
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK				   0x00003F00U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH				           6U
-#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319
-#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2
-
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK				   0x001F0000U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH				           5U
-#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319
-#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0
-
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK				   0x1F000000U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH				           5U
-#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319
-#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1
-
-#define LPDDR4__DENALI_CTL_320_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_320_WRITE_MASK				            0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK				   0x0000001FU
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH				           5U
-#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320
-#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2
-
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK               0x00001F00U
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH				       5U
-#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
-#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH				       5U
-#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320
-#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH				       5U
-#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
-#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_321_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_321_WRITE_MASK				            0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH				       5U
-#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321
-#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK               0x00001F00U
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH				       5U
-#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
-#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH				       5U
-#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321
-#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH				       5U
-#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
-#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_322_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_322_WRITE_MASK				            0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH				       5U
-#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322
-#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK               0x00001F00U
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH				       5U
-#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
-#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH				       5U
-#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322
-#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH				       5U
-#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
-#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_323_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_323_WRITE_MASK				            0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH				       5U
-#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323
-#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK				  0x00001F00U
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH				          5U
-#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323
-#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY
-
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH				       5U
-#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323
-#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH				       5U
-#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323
-#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_324_READ_MASK				             0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_324_WRITE_MASK				            0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH				       5U
-#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324
-#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK				  0x00001F00U
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH				          5U
-#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324
-#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY
-
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK				  0x001F0000U
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH				          5U
-#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324
-#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY
-
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH				           4U
-#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324
-#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0
-
-#define LPDDR4__DENALI_CTL_325_READ_MASK				             0x0F070F07U
-#define LPDDR4__DENALI_CTL_325_WRITE_MASK				            0x0F070F07U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK				   0x00000007U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH				           3U
-#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0
-
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH				           4U
-#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1
-
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH				           3U
-#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1
-
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH				           4U
-#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2
-
-#define LPDDR4__DENALI_CTL_326_READ_MASK				             0x00000707U
-#define LPDDR4__DENALI_CTL_326_WRITE_MASK				            0x00000707U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK				   0x00000007U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH				           3U
-#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326
-#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2
-
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK				0x00000700U
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH				        3U
-#define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326
-#define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE
-
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET				              0U
-#define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326
-#define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD
-
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET				             0U
-#define LPDDR4__SWLVL_START__REG DENALI_CTL_326
-#define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START
-
-#define LPDDR4__DENALI_CTL_327_READ_MASK				             0x01010100U
-#define LPDDR4__DENALI_CTL_327_WRITE_MASK				            0x01010100U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK				      0x00000001U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET				              0U
-#define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT
-
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET				           0U
-#define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE
-
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK				    0x00010000U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET				            0U
-#define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0
-
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK				    0x01000000U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET				            0U
-#define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1
-
-#define LPDDR4__DENALI_CTL_328_READ_MASK				             0x00010101U
-#define LPDDR4__DENALI_CTL_328_WRITE_MASK				            0x00010101U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET				            0U
-#define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328
-#define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2
-
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET				            0U
-#define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328
-#define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3
-
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET				        0U
-#define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328
-#define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN
-
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK				       0x01000000U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET				               0U
-#define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328
-#define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ
-
-#define LPDDR4__DENALI_CTL_329_READ_MASK				             0x013F3F01U
-#define LPDDR4__DENALI_CTL_329_WRITE_MASK				            0x013F3F01U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK				        0x00000001U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT								0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH								1U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR								0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET								0U
-#define LPDDR4__WRLVL_CS__REG DENALI_CTL_329
-#define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS
-
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK				         0x00003F00U
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH								 6U
-#define LPDDR4__WLDQSEN__REG DENALI_CTL_329
-#define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN
-
-#define LPDDR4__DENALI_CTL_329__WLMRD_MASK				           0x003F0000U
-#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT								  16U
-#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH								   6U
-#define LPDDR4__WLMRD__REG DENALI_CTL_329
-#define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD
-
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK				        0x01000000U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET								0U
-#define LPDDR4__WRLVL_EN__REG DENALI_CTL_329
-#define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN
-
-#define LPDDR4__DENALI_CTL_330_READ_MASK				             0x0F010101U
-#define LPDDR4__DENALI_CTL_330_WRITE_MASK				            0x0F010101U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK              0x00000001U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET				      0U
-#define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330
-#define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE
-
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET				          0U
-#define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330
-#define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC
-
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET				      0U
-#define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330
-#define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK				 0x0F000000U
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH				         4U
-#define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330
-#define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK
-
-#define LPDDR4__DENALI_CTL_331_READ_MASK				             0x07030101U
-#define LPDDR4__DENALI_CTL_331_WRITE_MASK				            0x07030101U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET				           0U
-#define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN
-
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET				            0U
-#define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE
-
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK				    0x00030000U
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH				            2U
-#define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP
-
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK              0x07000000U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH				      3U
-#define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_332_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_332_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_333_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_333_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH				       16U
-#define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333
-#define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT          16U
-#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_334_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_334_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
-#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_335_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_335_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH				       16U
-#define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335
-#define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_336_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_336_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT           0U
-#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK  0xFFFF0000U
-#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT         16U
-#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH         16U
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_337_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_337_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_338_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_338_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH				       16U
-#define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338
-#define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT          16U
-#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_339_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_339_WRITE_MASK				            0x0000FFFFU
-#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
-#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK				       0x00010000U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET				               0U
-#define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339
-#define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ
-
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET				          0U
-#define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339
-#define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ
-
-#define LPDDR4__DENALI_CTL_340_READ_MASK				             0x010F0F01U
-#define LPDDR4__DENALI_CTL_340_WRITE_MASK				            0x010F0F01U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK				        0x00000001U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT								0U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH								1U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR								0U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET								0U
-#define LPDDR4__RDLVL_CS__REG DENALI_CTL_340
-#define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS
-
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK				    0x00000F00U
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH				            4U
-#define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340
-#define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN
-
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK               0x000F0000U
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH				       4U
-#define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340
-#define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN
-
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK              0x01000000U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET				      0U
-#define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340
-#define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE
-
-#define LPDDR4__DENALI_CTL_341_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_341_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK         0x00000001U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET				 0U
-#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341
-#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE
-
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET				          0U
-#define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341
-#define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC
-
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET				      0U
-#define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341
-#define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK             0x01000000U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET				     0U
-#define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341
-#define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC
-
-#define LPDDR4__DENALI_CTL_342_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_342_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK         0x00000001U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET				 0U
-#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342
-#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET				           0U
-#define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342
-#define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN
-
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET				      0U
-#define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342
-#define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN
-
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET				           0U
-#define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342
-#define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29
-
-#define LPDDR4__DENALI_CTL_343_READ_MASK				             0x03030101U
-#define LPDDR4__DENALI_CTL_343_WRITE_MASK				            0x03030101U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET				            0U
-#define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE
-
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK               0x00000100U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET				       0U
-#define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE
-
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK				    0x00030000U
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH				            2U
-#define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP
-
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK               0x03000000U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH				       2U
-#define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP
-
-#define LPDDR4__DENALI_CTL_344_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_344_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_345_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_345_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH				       16U
-#define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345
-#define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT          16U
-#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_346_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_346_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
-#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK    0xFFFF0000U
-#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT           16U
-#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH           16U
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_347_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_347_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK    0x0000FFFFU
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT            0U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH           16U
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH				  16U
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_348_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_348_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT      0U
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH     16U
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT    16U
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH    16U
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_349_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_349_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_350_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_350_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH				       16U
-#define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350
-#define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT          16U
-#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_351_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_351_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT          0U
-#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH         16U
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK    0xFFFF0000U
-#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT           16U
-#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH           16U
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_352_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_352_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK    0x0000FFFFU
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT            0U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH           16U
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH				  16U
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_353_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_353_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT      0U
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH     16U
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT    16U
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH    16U
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_354_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_354_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_355_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_355_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH				       16U
-#define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355
-#define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT          16U
-#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_356_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_356_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
-#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK    0xFFFF0000U
-#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT           16U
-#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH           16U
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_357_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_357_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK    0x0000FFFFU
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT            0U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH           16U
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH				  16U
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_358_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_358_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT      0U
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH     16U
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT    16U
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_359_READ_MASK				             0x00000100U
-#define LPDDR4__DENALI_CTL_359_WRITE_MASK				            0x00000100U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK				       0x00000001U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET				               0U
-#define LPDDR4__CALVL_REQ__REG DENALI_CTL_359
-#define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ
-
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK				        0x00000100U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT								8U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH								1U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR								0U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET								0U
-#define LPDDR4__CALVL_CS__REG DENALI_CTL_359
-#define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS
-
-#define LPDDR4__DENALI_CTL_360_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH				            20U
-#define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360
-#define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0
-
-#define LPDDR4__DENALI_CTL_361_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH				         20U
-#define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361
-#define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0
-
-#define LPDDR4__DENALI_CTL_362_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH				            20U
-#define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362
-#define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1
-
-#define LPDDR4__DENALI_CTL_363_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH				         20U
-#define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363
-#define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1
-
-#define LPDDR4__DENALI_CTL_364_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH				            20U
-#define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364
-#define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2
-
-#define LPDDR4__DENALI_CTL_365_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH				         20U
-#define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365
-#define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2
-
-#define LPDDR4__DENALI_CTL_366_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH				            20U
-#define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366
-#define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3
-
-#define LPDDR4__DENALI_CTL_367_READ_MASK				             0x010FFFFFU
-#define LPDDR4__DENALI_CTL_367_WRITE_MASK				            0x010FFFFFU
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH				         20U
-#define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367
-#define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3
-
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET				           0U
-#define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367
-#define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30
-
-#define LPDDR4__DENALI_CTL_368_READ_MASK				             0x0101030FU
-#define LPDDR4__DENALI_CTL_368_WRITE_MASK				            0x0101030FU
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH				           4U
-#define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368
-#define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31
-
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK				    0x00000300U
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH				            2U
-#define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368
-#define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN
-
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET				      0U
-#define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368
-#define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE
-
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET				          0U
-#define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368
-#define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC
-
-#define LPDDR4__DENALI_CTL_369_READ_MASK				             0x03010101U
-#define LPDDR4__DENALI_CTL_369_WRITE_MASK				            0x03010101U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK              0x00000001U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET				      0U
-#define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369
-#define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET				           0U
-#define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369
-#define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN
-
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK				    0x00010000U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET				            0U
-#define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369
-#define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE
-
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK				    0x03000000U
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH				            2U
-#define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369
-#define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP
-
-#define LPDDR4__DENALI_CTL_370_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_370_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370
-#define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH				16U
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_371_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_371_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH				       16U
-#define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371
-#define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT          16U
-#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH          16U
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_372_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_372_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
-#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372
-#define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_373_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_373_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH				16U
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH				       16U
-#define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373
-#define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_374_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_374_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT           0U
-#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK  0xFFFF0000U
-#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT         16U
-#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH         16U
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_375_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_375_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375
-#define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH				16U
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_376_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_376_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH				       16U
-#define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376
-#define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT          16U
-#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH          16U
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_377_READ_MASK				             0x0101FFFFU
-#define LPDDR4__DENALI_CTL_377_WRITE_MASK				            0x0101FFFFU
-#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
-#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK    0x00010000U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT           16U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH            1U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR            0U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET            0U
-#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377
-#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE
-
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT        24U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH         1U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR         0U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET         0U
-#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377
-#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE
-
-#define LPDDR4__DENALI_CTL_378_READ_MASK				             0x00000707U
-#define LPDDR4__DENALI_CTL_378_WRITE_MASK				            0x00000707U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH				         3U
-#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378
-#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY
-
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK				 0x00000700U
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH				         3U
-#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378
-#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY
-
-#define LPDDR4__DENALI_CTL_379_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH				 32U
-#define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379
-#define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0
-
-#define LPDDR4__DENALI_CTL_380_READ_MASK				             0x1FFF3F07U
-#define LPDDR4__DENALI_CTL_380_WRITE_MASK				            0x1FFF3F07U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK          0x00000007U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH				  3U
-#define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380
-#define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1
-
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK          0x00003F00U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH				  6U
-#define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380
-#define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID
-
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK        0x1FFF0000U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT               16U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH               13U
-#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380
-#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL
-
-#define LPDDR4__DENALI_CTL_381_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_381_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT               0U
-#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH              32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0
-
-#define LPDDR4__DENALI_CTL_382_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_382_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT               0U
-#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH              32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1
-
-#define LPDDR4__DENALI_CTL_383_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_383_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT               0U
-#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH              32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2
-
-#define LPDDR4__DENALI_CTL_384_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_384_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT               0U
-#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH              32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3
-
-#define LPDDR4__DENALI_CTL_385_READ_MASK				             0x0103FFFFU
-#define LPDDR4__DENALI_CTL_385_WRITE_MASK				            0x0103FFFFU
-#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT   0U
-#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH  16U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
-
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK				      0x00030000U
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH				              2U
-#define LPDDR4__CKE_STATUS__REG DENALI_CTL_385
-#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS
-
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET				           0U
-#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385
-#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID
-
-#define LPDDR4__DENALI_CTL_386_READ_MASK				             0x7FFFFFFFU
-#define LPDDR4__DENALI_CTL_386_WRITE_MASK				            0x7FFFFFFFU
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK				   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH				          16U
-#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386
-#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY
-
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH				         8U
-#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386
-#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY
-
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK				  0x7F000000U
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH				          7U
-#define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386
-#define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT
-
-#define LPDDR4__DENALI_CTL_387_READ_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_387_WRITE_MASK				            0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK             0x0000007FU
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH				     7U
-#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387
-#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK               0x00007F00U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH				       7U
-#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387
-#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0
-
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK               0x007F0000U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH				       7U
-#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387
-#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1
-
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK               0x7F000000U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH				       7U
-#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387
-#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2
-
-#define LPDDR4__DENALI_CTL_388_READ_MASK				             0x00FF037FU
-#define LPDDR4__DENALI_CTL_388_WRITE_MASK				            0x00FF037FU
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK				  0x0000007FU
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH				          7U
-#define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388
-#define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN
-
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK				0x00000300U
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH				        2U
-#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388
-#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE
-
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK				0x00FF0000U
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH				        8U
-#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388
-#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN
-
-#define LPDDR4__DENALI_CTL_389_READ_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389_WRITE_MASK				            0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH				    21U
-#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389
-#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0
-
-#define LPDDR4__DENALI_CTL_390_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0
-
-#define LPDDR4__DENALI_CTL_391_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0
-
-#define LPDDR4__DENALI_CTL_392_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0
-
-#define LPDDR4__DENALI_CTL_393_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0
-
-#define LPDDR4__DENALI_CTL_394_READ_MASK				             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394_WRITE_MASK				            0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH				    23U
-#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394
-#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0
-
-#define LPDDR4__DENALI_CTL_395_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT				0U
-#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH               32U
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0
-
-#define LPDDR4__DENALI_CTL_396_READ_MASK				             0x00007F7FU
-#define LPDDR4__DENALI_CTL_396_WRITE_MASK				            0x00007F7FU
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH				            7U
-#define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396
-#define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0
-
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH				            7U
-#define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396
-#define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0
-
-#define LPDDR4__DENALI_CTL_397_READ_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397_WRITE_MASK				            0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH				    21U
-#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397
-#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1
-
-#define LPDDR4__DENALI_CTL_398_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1
-
-#define LPDDR4__DENALI_CTL_399_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1
-
-#define LPDDR4__DENALI_CTL_400_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1
-
-#define LPDDR4__DENALI_CTL_401_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1
-
-#define LPDDR4__DENALI_CTL_402_READ_MASK				             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402_WRITE_MASK				            0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH				    23U
-#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402
-#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1
-
-#define LPDDR4__DENALI_CTL_403_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT				0U
-#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH               32U
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1
-
-#define LPDDR4__DENALI_CTL_404_READ_MASK				             0x00007F7FU
-#define LPDDR4__DENALI_CTL_404_WRITE_MASK				            0x00007F7FU
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH				            7U
-#define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404
-#define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1
-
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH				            7U
-#define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404
-#define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1
-
-#define LPDDR4__DENALI_CTL_405_READ_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405_WRITE_MASK				            0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH				    21U
-#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405
-#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2
-
-#define LPDDR4__DENALI_CTL_406_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2
-
-#define LPDDR4__DENALI_CTL_407_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2
-
-#define LPDDR4__DENALI_CTL_408_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2
-
-#define LPDDR4__DENALI_CTL_409_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH				   32U
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2
-
-#define LPDDR4__DENALI_CTL_410_READ_MASK				             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410_WRITE_MASK				            0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH				    23U
-#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410
-#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2
-
-#define LPDDR4__DENALI_CTL_411_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT				0U
-#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH               32U
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2
-
-#define LPDDR4__DENALI_CTL_412_READ_MASK				             0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_412_WRITE_MASK				            0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH				            7U
-#define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412
-#define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2
-
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH				            7U
-#define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412
-#define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2
-
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK              0x000F0000U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH				      4U
-#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412
-#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0
-
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK              0x0F000000U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH				      4U
-#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412
-#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1
-
-#define LPDDR4__DENALI_CTL_413_READ_MASK				             0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_413_WRITE_MASK				            0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK              0x0000000FU
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH				      4U
-#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413
-#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2
-
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK           0x00000F00U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT				   8U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH				   4U
-#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
-#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
-
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK            0x000F0000U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH				    4U
-#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
-#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
-
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH				           8U
-#define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413
-#define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN
-
-#define LPDDR4__DENALI_CTL_414_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_CTL_414_WRITE_MASK				            0x000003FFU
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK				   0x000003FFU
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH				          10U
-#define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414
-#define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW
-
-#define LPDDR4__DENALI_CTL_415_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH				        32U
-#define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415
-#define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP
-
-#define LPDDR4__DENALI_CTL_416_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK				  0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH				         32U
-#define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416
-#define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX
-
-#define LPDDR4__DENALI_CTL_417_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_CTL_417_WRITE_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH				           8U
-#define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417
-#define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN
-
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK				   0x0003FF00U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH				          10U
-#define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417
-#define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR
-
-#define LPDDR4__DENALI_CTL_418_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH				        32U
-#define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418
-#define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP
-
-#define LPDDR4__DENALI_CTL_419_READ_MASK				             0x000101FFU
-#define LPDDR4__DENALI_CTL_419_WRITE_MASK				            0x000101FFU
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH				         8U
-#define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419
-#define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK
-
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK				        0x00000100U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT								8U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET								0U
-#define LPDDR4__RDLVL_EN__REG DENALI_CTL_419
-#define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN
-
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET				           0U
-#define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419
-#define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN
-
-#define LPDDR4__DENALI_CTL_420_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK				  0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH				         32U
-#define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420
-#define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX
-
-#define LPDDR4__DENALI_CTL_421_READ_MASK				             0x00FF0707U
-#define LPDDR4__DENALI_CTL_421_WRITE_MASK				            0x00FF0707U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK              0x00000007U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH				      3U
-#define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421
-#define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK         0x00000700U
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT				 8U
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH				 3U
-#define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421
-#define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH				           8U
-#define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421
-#define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN
-
-#define LPDDR4__DENALI_CTL_422_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_422_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH				       10U
-#define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422
-#define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0
-
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK           0x03FF0000U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH				  10U
-#define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422
-#define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0
-
-#define LPDDR4__DENALI_CTL_423_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_423_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH				       10U
-#define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423
-#define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1
-
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK           0x03FF0000U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH				  10U
-#define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423
-#define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1
-
-#define LPDDR4__DENALI_CTL_424_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_424_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH				       10U
-#define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424
-#define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2
-
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK           0x03FF0000U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH				  10U
-#define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424
-#define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2
-
-#define LPDDR4__DENALI_CTL_425_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH				        32U
-#define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425
-#define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP
-
-#define LPDDR4__DENALI_CTL_426_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK				  0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH				         32U
-#define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426
-#define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX
-
-#define LPDDR4__DENALI_CTL_427_READ_MASK				             0x070F0101U
-#define LPDDR4__DENALI_CTL_427_WRITE_MASK				            0x070F0101U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET				         0U
-#define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427
-#define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK
-
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK				        0x00000100U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT								8U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET								0U
-#define LPDDR4__CALVL_EN__REG DENALI_CTL_427
-#define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN
-
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK              0x000F0000U
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH				      4U
-#define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427
-#define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK              0x07000000U
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH				      3U
-#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427
-#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0
-
-#define LPDDR4__DENALI_CTL_428_READ_MASK				             0x7F7F0707U
-#define LPDDR4__DENALI_CTL_428_WRITE_MASK				            0x7F7F0707U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK              0x00000007U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH				      3U
-#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428
-#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1
-
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK              0x00000700U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH				      3U
-#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428
-#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2
-
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK				 0x007F0000U
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH				         7U
-#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428
-#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0
-
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK				 0x7F000000U
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH				         7U
-#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428
-#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0
-
-#define LPDDR4__DENALI_CTL_429_READ_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_429_WRITE_MASK				            0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK				 0x0000007FU
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH				         7U
-#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429
-#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1
-
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK				 0x00007F00U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH				         7U
-#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429
-#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1
-
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK				 0x007F0000U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH				         7U
-#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429
-#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2
-
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK				 0x7F000000U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH				         7U
-#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429
-#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2
-
-#define LPDDR4__DENALI_CTL_430_READ_MASK				             0x010101FFU
-#define LPDDR4__DENALI_CTL_430_WRITE_MASK				            0x010101FFU
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK               0x000000FFU
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH				       8U
-#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430
-#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY
-
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET				            0U
-#define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430
-#define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING
-
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK     0x00010000U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT            16U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH             1U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR             0U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET             0U
-#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430
-#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE
-
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK				0x01000000U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT				       24U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET				        0U
-#define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430
-#define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE
-
-#define LPDDR4__DENALI_CTL_431_READ_MASK				             0x07070701U
-#define LPDDR4__DENALI_CTL_431_WRITE_MASK				            0x07070701U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET				           0U
-#define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32
-
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK				   0x00000700U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH				           3U
-#define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33
-
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH				           3U
-#define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34
-
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK				   0x07000000U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH				           3U
-#define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35
-
-#define LPDDR4__DENALI_CTL_432_READ_MASK				             0x0F070707U
-#define LPDDR4__DENALI_CTL_432_WRITE_MASK				            0x0F070707U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK				   0x00000007U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH				           3U
-#define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36
-
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK				   0x00000700U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH				           3U
-#define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37
-
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH				           3U
-#define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38
-
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH				           4U
-#define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39
-
-#define LPDDR4__DENALI_CTL_433_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_433_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH				           4U
-#define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40
-
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH				           4U
-#define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41
-
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH				           4U
-#define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42
-
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH				           4U
-#define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43
-
-#define LPDDR4__DENALI_CTL_434_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_434_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH				           4U
-#define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44
-
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH				           4U
-#define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45
-
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH				           4U
-#define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46
-
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH				           4U
-#define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47
-
-#define LPDDR4__DENALI_CTL_435_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_435_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH				           4U
-#define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48
-
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH				           4U
-#define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49
-
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH				           4U
-#define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50
-
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH				           4U
-#define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51
-
-#define LPDDR4__DENALI_CTL_436_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_436_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH				           4U
-#define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52
-
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH				           4U
-#define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53
-
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH				           4U
-#define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54
-
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH				           4U
-#define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55
-
-#define LPDDR4__DENALI_CTL_437_READ_MASK				             0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_437_WRITE_MASK				            0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH				           4U
-#define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437
-#define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56
-
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH				           4U
-#define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437
-#define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57
-
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH				           4U
-#define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437
-#define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58
-
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK               0xFF000000U
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH				       8U
-#define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437
-#define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO
-
-#define LPDDR4__DENALI_CTL_438_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_438_WRITE_MASK				            0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK               0x000000FFU
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH				       8U
-#define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438
-#define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK
-
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK         0x00000300U
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT				 8U
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH				 2U
-#define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438
-#define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH								  8U
-#define LPDDR4__NWR_F0__REG DENALI_CTL_438
-#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0
-
-#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH								  8U
-#define LPDDR4__NWR_F1__REG DENALI_CTL_438
-#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1
-
-#define LPDDR4__DENALI_CTL_439_READ_MASK				             0x001F01FFU
-#define LPDDR4__DENALI_CTL_439_WRITE_MASK				            0x001F01FFU
-#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK				          0x000000FFU
-#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH								  8U
-#define LPDDR4__NWR_F2__REG DENALI_CTL_439
-#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2
-
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET				           0U
-#define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439
-#define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59
-
-#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U
-#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH  5U
-#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439
-#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS
-
-#define LPDDR4__DENALI_CTL_440_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_440_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT       0U
-#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH      32U
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0
-
-#define LPDDR4__DENALI_CTL_441_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_441_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT       0U
-#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH      32U
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1
-
-#define LPDDR4__DENALI_CTL_442_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_442_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK            0x00000001U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET				    0U
-#define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442
-#define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE
-
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT       8U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH       1U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR       0U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET       0U
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH  1U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR  0U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET  0U
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT     24U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH      1U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR      0U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET      0U
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_443_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_443_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT       0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH       1U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR       0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET       0U
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK   0x00000100U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT           8U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH           1U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR           0U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET           0U
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_444_READ_MASK				             0x00010101U
-#define LPDDR4__DENALI_CTL_444_WRITE_MASK				            0x00010101U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_445_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH				        32U
-#define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445
-#define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0
-
-#define LPDDR4__DENALI_CTL_446_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH				        32U
-#define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446
-#define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1
-
-#define LPDDR4__DENALI_CTL_447_READ_MASK				             0x00000107U
-#define LPDDR4__DENALI_CTL_447_WRITE_MASK				            0x00000107U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH				         3U
-#define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447
-#define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2
-
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK      0x00000100U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT              8U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH              1U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR              0U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET              0U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447
-#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_448_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_448_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT  0U
-#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0
-
-#define LPDDR4__DENALI_CTL_449_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_449_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT  0U
-#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1
-
-#define LPDDR4__DENALI_CTL_450_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_450_WRITE_MASK				            0x00000007U
-#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT  0U
-#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH  3U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2
-
-#define LPDDR4__DENALI_CTL_451_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH				        32U
-#define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451
-#define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0
-
-#define LPDDR4__DENALI_CTL_452_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH				        32U
-#define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452
-#define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1
-
-#define LPDDR4__DENALI_CTL_453_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH				        32U
-#define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453
-#define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2
-
-#define LPDDR4__DENALI_CTL_454_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_CTL_454_WRITE_MASK				            0x0000000FU
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK				 0x0000000FU
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH				         4U
-#define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454
-#define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3
-
-#define LPDDR4__DENALI_CTL_455_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_455_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT            0U
-#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH           32U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0
-
-#define LPDDR4__DENALI_CTL_456_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_456_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT            0U
-#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH           32U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1
-
-#define LPDDR4__DENALI_CTL_457_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_457_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT            0U
-#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH           32U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2
-
-#define LPDDR4__DENALI_CTL_458_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_CTL_458_WRITE_MASK				            0x0000000FU
-#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK    0x0000000FU
-#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT            0U
-#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH            4U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3
-
-#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_if.h b/drivers/ram/k3-j721e/lpddr4_if.h
deleted file mode 100644
index 66ec3c5a27..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_if.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- *          api-generator: 12.02.13bb8d5
- *          Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-#ifndef LPDDR4_IF_H
-#define LPDDR4_IF_H
-
-#include <linux/types.h>
-
-/** @defgroup ConfigInfo  Configuration and Hardware Operation Information
- *  The following definitions specify the driver operation environment that
- *  is defined by hardware configuration or client code. These defines are
- *  located in the header file of the core driver.
- *  @{
- */
-
-/**********************************************************************
-* Defines
-**********************************************************************/
-/** Number of chip-selects */
-#define LPDDR4_MAX_CS (2U)
-
-/** Number of accessible registers for controller. */
-#define LPDDR4_CTL_REG_COUNT (459U)
-
-/** Number of accessible registers for PHY Independent Module. */
-#define LPDDR4_PHY_INDEP_REG_COUNT (300U)
-
-/** Number of accessible registers for PHY. */
-#define LPDDR4_PHY_REG_COUNT (1423U)
-
-/**
- *  @}
- */
-
-/** @defgroup DataStructure Dynamic Data Structures
- *  This section defines the data structures used by the driver to provide
- *  hardware information, modification and dynamic operation of the driver.
- *  These data structures are defined in the header file of the core driver
- *  and utilized by the API.
- *  @{
- */
-
-/**********************************************************************
-* Forward declarations
-**********************************************************************/
-typedef struct lpddr4_config_s lpddr4_config;
-typedef struct lpddr4_privatedata_s lpddr4_privatedata;
-typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
-typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
-typedef struct lpddr4_reginitdata_s lpddr4_reginitdata;
-
-/**********************************************************************
-* Enumerations
-**********************************************************************/
-/** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */
-typedef enum
-{
-	LPDDR4_CTL_REGS = 0U,
-	LPDDR4_PHY_REGS = 1U,
-	LPDDR4_PHY_INDEP_REGS = 2U
-} lpddr4_regblock;
-
-/** Controller status or error interrupts. */
-typedef enum
-{
-	LPDDR4_RESET_DONE = 0U,
-	LPDDR4_BUS_ACCESS_ERROR = 1U,
-	LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U,
-	LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U,
-	LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U,
-	LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U,
-	LPDDR4_ECC_SCRUB_DONE = 6U,
-	LPDDR4_ECC_SCRUB_ERROR = 7U,
-	LPDDR4_PORT_COMMAND_ERROR = 8U,
-	LPDDR4_MC_INIT_DONE = 9U,
-	LPDDR4_LP_DONE = 10U,
-	LPDDR4_BIST_DONE = 11U,
-	LPDDR4_WRAP_ERROR = 12U,
-	LPDDR4_INVALID_BURST_ERROR = 13U,
-	LPDDR4_RDLVL_ERROR = 14U,
-	LPDDR4_RDLVL_GATE_ERROR = 15U,
-	LPDDR4_WRLVL_ERROR = 16U,
-	LPDDR4_CA_TRAINING_ERROR = 17U,
-	LPDDR4_DFI_UPDATE_ERROR = 18U,
-	LPDDR4_MRR_ERROR = 19U,
-	LPDDR4_PHY_MASTER_ERROR = 20U,
-	LPDDR4_WRLVL_REQ = 21U,
-	LPDDR4_RDLVL_REQ = 22U,
-	LPDDR4_RDLVL_GATE_REQ = 23U,
-	LPDDR4_CA_TRAINING_REQ = 24U,
-	LPDDR4_LEVELING_DONE = 25U,
-	LPDDR4_PHY_ERROR = 26U,
-	LPDDR4_MR_READ_DONE = 27U,
-	LPDDR4_TEMP_CHANGE = 28U,
-	LPDDR4_TEMP_ALERT = 29U,
-	LPDDR4_SW_DQS_COMPLETE = 30U,
-	LPDDR4_DQS_OSC_BV_UPDATED = 31U,
-	LPDDR4_DQS_OSC_OVERFLOW = 32U,
-	LPDDR4_DQS_OSC_VAR_OUT = 33U,
-	LPDDR4_MR_WRITE_DONE = 34U,
-	LPDDR4_INHIBIT_DRAM_DONE = 35U,
-	LPDDR4_DFI_INIT_STATE = 36U,
-	LPDDR4_DLL_RESYNC_DONE = 37U,
-	LPDDR4_TDFI_TO = 38U,
-	LPDDR4_DFS_DONE = 39U,
-	LPDDR4_DFS_STATUS = 40U,
-	LPDDR4_REFRESH_STATUS = 41U,
-	LPDDR4_ZQ_STATUS = 42U,
-	LPDDR4_SW_REQ_MODE = 43U,
-	LPDDR4_LOR_BITS = 44U
-} lpddr4_ctlinterrupt;
-
-/** PHY Independent Module status or error interrupts. */
-typedef enum
-{
-	LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U,
-	LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
-	LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
-	LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
-	LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U,
-	LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
-	LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U,
-	LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
-	LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
-	LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U,
-	LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
-	LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U,
-	LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U,
-	LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
-	LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U,
-	LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U,
-	LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
-	LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
-} lpddr4_phyindepinterrupt;
-
-/** List of informations and warnings from driver. */
-typedef enum
-{
-	LPDDR4_DRV_NONE = 0U,
-	LPDDR4_DRV_SOC_PLL_UPDATE = 1U
-} lpddr4_infotype;
-
-/** Low power interface wake up timing parameters */
-typedef enum
-{
-	LPDDR4_LPI_PD_WAKEUP_FN = 0U,
-	LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
-	LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
-	LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
-	LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
-	LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
-	LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
-} lpddr4_lpiwakeupparam;
-
-/** Half Datapath mode setting */
-typedef enum
-{
-	LPDDR4_REDUC_ON = 0U,
-	LPDDR4_REDUC_OFF = 1U
-} lpddr4_reducmode;
-
-/** ECC Control parameter setting */
-typedef enum
-{
-	LPDDR4_ECC_DISABLED = 0U,
-	LPDDR4_ECC_ENABLED = 1U,
-	LPDDR4_ECC_ERR_DETECT = 2U,
-	LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
-} lpddr4_eccenable;
-
-/** Data Byte Inversion mode setting */
-typedef enum
-{
-	LPDDR4_DBI_RD_ON = 0U,
-	LPDDR4_DBI_RD_OFF = 1U,
-	LPDDR4_DBI_WR_ON = 2U,
-	LPDDR4_DBI_WR_OFF = 3U
-} lpddr4_dbimode;
-
-/** Controller Frequency Set Point number  */
-typedef enum
-{
-	LPDDR4_FSP_0 = 0U,
-	LPDDR4_FSP_1 = 1U,
-	LPDDR4_FSP_2 = 2U
-} lpddr4_ctlfspnum;
-
-/**********************************************************************
-* Callbacks
-**********************************************************************/
-/**
- * Reports informations and warnings that need to be communicated.
- * Params:
- * pD - driver state info specific to this instance.
- * infoType - Type of information.
- */
-typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype);
-
-/**
- * Reports interrupts received by the controller.
- * Params:
- * pD - driver state info specific to this instance.
- * ctlInterrupt - Interrupt raised
- * chipSelect - Chip for which interrupt raised
- */
-typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect);
-
-/**
- * Reports interrupts received by the PHY Independent Module.
- * Params:
- * privateData - driver state info specific to this instance.
- * phyIndepInterrupt - Interrupt raised
- * chipSelect - Chip for which interrupt raised
- */
-typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect);
-
-/**
- *  @}
- */
-
-/** @defgroup DriverFunctionAPI Driver Function API
- *  Prototypes for the driver API functions. The user application can link statically to the
- *  necessary API functions and call them directly.
- *  @{
- */
-
-/**********************************************************************
-* API methods
-**********************************************************************/
-
-/**
- * Checks configuration object.
- * @param[in] config Driver/hardware configuration required.
- * @param[out] configSize Size of memory allocations required.
- * @return CDN_EOK on success (requirements structure filled).
- * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
- */
-uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize);
-
-/**
- * Init function to be called after LPDDR4_probe() to set up the
- * driver configuration.  Memory should be allocated for drv_data
- * (using the size determined using LPDDR4_probe)  before calling this
- * API.  init_settings should be initialised with base addresses for
- * PHY Indepenent Module, Controller and PHY before calling this
- * function.  If callbacks are required for interrupt handling, these
- * should also be configured in init_settings.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cfg Specifies driver/hardware configuration.
- * @return CDN_EOK on success
- * @return EINVAL if illegal/inconsistent values in cfg.
- * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
- */
-uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg);
-
-/**
- * Start the driver.
- * @param[in] pD Driver state info specific to this instance.
- */
-uint32_t lpddr4_start(const lpddr4_privatedata* pd);
-
-/**
- * Read a register from the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[out] regValue Register value read
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset if out of range or regValue is NULL
- */
-uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
-
-/**
- * Write a register in the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[in] regValue Register value to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset is out of range or regValue is NULL
- */
-uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
-
-/**
- * Read a memory mode register from DRAM
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
- * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
- * @param[out] mmrStatus Status of mode register read(mrr) instruction.
- * @return CDN_EOK on success.
- * @return EINVAL if regNumber is out of range or regValue is NULL
- */
-uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
-
-/**
- * Write a memory mode register in DRAM
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
- * @param[out] mrwStatus Status of mode register write(mrw) instruction.
- * @return CDN_EOK on success.
- * @return EINVAL if regNumber is out of range or regValue is NULL
- */
-uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
-
-/**
- * Write a set of initialisation values to the controller registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-/**
- * Write a set of initialisation values to the PHY registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-/**
- * Write a set of initialisation values to the PHY Independent Module
- * registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-/**
- * Read values of the controller registers in bulk (Set 'updateCtlReg'
- * to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-/**
- * Read the values of the PHY module registers in bulk (Set
- * 'updatePhyReg' to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-/**
- * Read the values of the PHY Independent module registers in bulk(Set
- * 'updatePhyIndepReg' to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-/**
- * Read the current interrupt mask for the controller
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask);
-
-/**
- * Sets the interrupt mask for the controller
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask);
-
-/**
- * Check whether a specific controller interrupt is active
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
-
-/**
- * Acknowledge  a specific controller interrupt
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
-
-/**
- * Read the current interrupt mask for the PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask);
-
-/**
- * Sets the interrupt mask for the PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask);
-
-/**
- * Check whether a specific PHY Independent Module interrupt is active
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
-
-/**
- * Acknowledge  a specific PHY Independent Module interrupt
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
-
-/**
- * Retrieve status information after a failed init.  The
- * DebugStructInfo will be filled  in with error codes which can be
- * referenced against the driver documentation for further details.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] debugInfo status
- * @return CDN_EOK on success.
- * @return EINVAL if debugInfo is NULL
- */
-uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
-
-/**
- * Get the current value of Low power Interface wake up time.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[out] cycles Timing value(in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if powerMode is NULL
- */
-uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
-/**
- * Set the current value of Low power Interface wake up time.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[in] cycles Timing value(in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if powerMode is NULL
- */
-uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-/**
- * Get the current value for ECC auto correction
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] eccParam ECC parameter setting
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
-
-/**
- * Set the value for ECC auto correction.  This API must be called
- * before startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] eccParam ECC control parameter setting
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-
-/**
- * Get the current value for the Half Datapath option
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mode Half Datapath setting
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
-uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
-
-/**
- * Set the value for the Half Datapath option.  This API must be
- * called before startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode Half Datapath setting
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
-uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-
-/**
- * Get the current value for Data Bus Inversion setting.  This will be
- * compared with the   current DRAM setting using the MR3 register.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI read value
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off);
-
-/**
- * Get the current value for Data Bus Inversion setting.  This will be
- * compared with the   current DRAM setting using the MR3 register.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI write value
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off);
-
-/**
- * Set the mode for Data Bus Inversion. This will also be set in DRAM
- * using the MR3   controller register. This API must be called before
- * startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode status
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
-uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
-
-/**
- * Get the current value for the refresh rate (reading Refresh per
- * command timing).
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[out] cycles Refresh rate (in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if rate is NULL
- */
-uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
-/**
- * Set the refresh rate (writing Refresh per command timing).
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[in] cycles Refresh rate (in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if rate is NULL
- */
-uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-/**
- * Handle Refreshing per chip select
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] trefInterval status
- * @return CDN_EOK on success.
- * @return EINVAL if chipSelect is invalid
- */
-uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval);
-
-#endif  /* LPDDR4_IF_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_obj_if.c b/drivers/ram/k3-j721e/lpddr4_obj_if.c
deleted file mode 100644
index 35b3db6707..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_obj_if.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- *          api-generator: 12.02.13bb8d5
- *          Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-#include "lpddr4_obj_if.h"
-
-LPDDR4_OBJ *lpddr4_getinstance(void)
-{
-	static LPDDR4_OBJ driver = {
-		.probe = lpddr4_probe,
-		.init = lpddr4_init,
-		.start = lpddr4_start,
-		.readreg = lpddr4_readreg,
-		.writereg = lpddr4_writereg,
-		.getmmrregister = lpddr4_getmmrregister,
-		.setmmrregister = lpddr4_setmmrregister,
-		.writectlconfig = lpddr4_writectlconfig,
-		.writephyconfig = lpddr4_writephyconfig,
-		.writephyindepconfig = lpddr4_writephyindepconfig,
-		.readctlconfig = lpddr4_readctlconfig,
-		.readphyconfig = lpddr4_readphyconfig,
-		.readphyindepconfig = lpddr4_readphyindepconfig,
-		.getctlinterruptmask = lpddr4_getctlinterruptmask,
-		.setctlinterruptmask = lpddr4_setctlinterruptmask,
-		.checkctlinterrupt = lpddr4_checkctlinterrupt,
-		.ackctlinterrupt = lpddr4_ackctlinterrupt,
-		.getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
-		.setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
-		.checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
-		.ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
-		.getdebuginitinfo = lpddr4_getdebuginitinfo,
-		.getlpiwakeuptime = lpddr4_getlpiwakeuptime,
-		.setlpiwakeuptime = lpddr4_setlpiwakeuptime,
-		.geteccenable = lpddr4_geteccenable,
-		.seteccenable = lpddr4_seteccenable,
-		.getreducmode = lpddr4_getreducmode,
-		.setreducmode = lpddr4_setreducmode,
-		.getdbireadmode = lpddr4_getdbireadmode,
-		.getdbiwritemode = lpddr4_getdbiwritemode,
-		.setdbimode = lpddr4_setdbimode,
-		.getrefreshrate = lpddr4_getrefreshrate,
-		.setrefreshrate = lpddr4_setrefreshrate,
-		.refreshperchipselect = lpddr4_refreshperchipselect,
-	};
-
-	return &driver;
-}
diff --git a/drivers/ram/k3-j721e/lpddr4_obj_if.h b/drivers/ram/k3-j721e/lpddr4_obj_if.h
deleted file mode 100644
index 33dae6f7ed..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_obj_if.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- *          api-generator: 12.02.13bb8d5
- *          Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-#ifndef LPDDR4_OBJ_IF_H
-#define LPDDR4_OBJ_IF_H
-
-#include "lpddr4_if.h"
-
-/** @defgroup DriverObject Driver API Object
- *  API listing for the driver. The API is contained in the object as
- *  function pointers in the object structure. As the actual functions
- *  resides in the Driver Object, the client software must first use the
- *  global GetInstance function to obtain the Driver Object Pointer.
- *  The actual APIs then can be invoked using obj->(api_name)() syntax.
- *  These functions are defined in the header file of the core driver
- *  and utilized by the API.
- *  @{
- */
-
-/**********************************************************************
-* API methods
-**********************************************************************/
-typedef struct lpddr4_obj_s
-{
-	/**
-	 * Checks configuration object.
-	 * @param[in] config Driver/hardware configuration required.
-	 * @param[out] configSize Size of memory allocations required.
-	 * @return CDN_EOK on success (requirements structure filled).
-	 * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
-	 */
-	uint32_t (*probe)(const lpddr4_config* config, uint16_t* configsize);
-
-	/**
-	 * Init function to be called after LPDDR4_probe() to set up the
-	 * driver configuration.  Memory should be allocated for drv_data
-	 * (using the size determined using LPDDR4_probe)  before calling
-	 * this API.  init_settings should be initialised with base addresses
-	 * for  PHY Indepenent Module, Controller and PHY before calling this
-	 * function.  If callbacks are required for interrupt handling, these
-	 * should also be configured in init_settings.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] cfg Specifies driver/hardware configuration.
-	 * @return CDN_EOK on success
-	 * @return EINVAL if illegal/inconsistent values in cfg.
-	 * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
-	 */
-	uint32_t (*init)(lpddr4_privatedata* pd, const lpddr4_config* cfg);
-
-	/**
-	 * Start the driver.
-	 * @param[in] pD Driver state info specific to this instance.
-	 */
-	uint32_t (*start)(const lpddr4_privatedata* pd);
-
-	/**
-	 * Read a register from the controller, PHY or PHY Independent Module
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
-	 * @param[in] regOffset Register offset
-	 * @param[out] regValue Register value read
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regOffset if out of range or regValue is NULL
-	 */
-	uint32_t (*readreg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
-
-	/**
-	 * Write a register in the controller, PHY or PHY Independent Module
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
-	 * @param[in] regOffset Register offset
-	 * @param[in] regValue Register value to be written
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regOffset is out of range or regValue is NULL
-	 */
-	uint32_t (*writereg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
-
-	/**
-	 * Read a memory mode register from DRAM
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
-	 * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
-	 * @param[out] mmrStatus Status of mode register read(mrr) instruction.
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regNumber is out of range or regValue is NULL
-	 */
-	uint32_t (*getmmrregister)(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
-
-	/**
-	 * Write a memory mode register in DRAM
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
-	 * @param[out] mrwStatus Status of mode register write(mrw) instruction.
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regNumber is out of range or regValue is NULL
-	 */
-	uint32_t (*setmmrregister)(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
-
-	/**
-	 * Write a set of initialisation values to the controller registers
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] regValues Register values to be written
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regValues is NULL
-	 */
-	uint32_t (*writectlconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-	/**
-	 * Write a set of initialisation values to the PHY registers
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] regValues Register values to be written
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regValues is NULL
-	 */
-	uint32_t (*writephyconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-	/**
-	 * Write a set of initialisation values to the PHY Independent Module
-	 * registers
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] regValues Register values to be written
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regValues is NULL
-	 */
-	uint32_t (*writephyindepconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-	/**
-	 * Read values of the controller registers in bulk (Set
-	 * 'updateCtlReg' to read) and store in memory.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] regValues Register values which are read
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regValues is NULL
-	 */
-	uint32_t (*readctlconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-	/**
-	 * Read the values of the PHY module registers in bulk (Set
-	 * 'updatePhyReg' to read) and store in memory.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] regValues Register values which are read
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regValues is NULL
-	 */
-	uint32_t (*readphyconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-	/**
-	 * Read the values of the PHY Independent module registers in
-	 * bulk(Set 'updatePhyIndepReg' to read) and store in memory.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] regValues Register values which are read
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if regValues is NULL
-	 */
-	uint32_t (*readphyindepconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-	/**
-	 * Read the current interrupt mask for the controller
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] mask Value of interrupt mask
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if mask pointer is NULL
-	 */
-	uint32_t (*getctlinterruptmask)(const lpddr4_privatedata* pd, uint64_t* mask);
-
-	/**
-	 * Sets the interrupt mask for the controller
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] mask Value of interrupt mask to be written
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if mask pointer is NULL
-	 */
-	uint32_t (*setctlinterruptmask)(const lpddr4_privatedata* pd, const uint64_t* mask);
-
-	/**
-	 * Check whether a specific controller interrupt is active
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] intr Interrupt to be checked
-	 * @param[out] irqStatus Status of the interrupt, TRUE if active
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if intr is not valid
-	 */
-	uint32_t (*checkctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
-
-	/**
-	 * Acknowledge  a specific controller interrupt
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] intr Interrupt to be acknowledged
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if intr is not valid
-	 */
-	uint32_t (*ackctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
-
-	/**
-	 * Read the current interrupt mask for the PHY Independent Module
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] mask Value of interrupt mask
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if mask pointer is NULL
-	 */
-	uint32_t (*getphyindepinterruptmask)(const lpddr4_privatedata* pd, uint32_t* mask);
-
-	/**
-	 * Sets the interrupt mask for the PHY Independent Module
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] mask Value of interrupt mask to be written
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if mask pointer is NULL
-	 */
-	uint32_t (*setphyindepinterruptmask)(const lpddr4_privatedata* pd, const uint32_t* mask);
-
-	/**
-	 * Check whether a specific PHY Independent Module interrupt is
-	 * active
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] intr Interrupt to be checked
-	 * @param[out] irqStatus Status of the interrupt, TRUE if active
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if intr is not valid
-	 */
-	uint32_t (*checkphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
-
-	/**
-	 * Acknowledge  a specific PHY Independent Module interrupt
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] intr Interrupt to be acknowledged
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if intr is not valid
-	 */
-	uint32_t (*ackphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
-
-	/**
-	 * Retrieve status information after a failed init.  The
-	 * DebugStructInfo will be filled  in with error codes which can be
-	 * referenced against the driver documentation for further details.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] debugInfo status
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if debugInfo is NULL
-	 */
-	uint32_t (*getdebuginitinfo)(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
-
-	/**
-	 * Get the current value of Low power Interface wake up time.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] lpiWakeUpParam LPI timing parameter
-	 * @param[in] fspNum Frequency copy
-	 * @param[out] cycles Timing value(in cycles)
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if powerMode is NULL
-	 */
-	uint32_t (*getlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
-	/**
-	 * Set the current value of Low power Interface wake up time.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] lpiWakeUpParam LPI timing parameter
-	 * @param[in] fspNum Frequency copy
-	 * @param[in] cycles Timing value(in cycles)
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if powerMode is NULL
-	 */
-	uint32_t (*setlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-	/**
-	 * Get the current value for ECC auto correction
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] eccParam ECC parameter setting
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if on_off is NULL
-	 */
-	uint32_t (*geteccenable)(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
-
-	/**
-	 * Set the value for ECC auto correction.  This API must be called
-	 * before startup of memory.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] eccParam ECC control parameter setting
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if on_off is NULL
-	 */
-	uint32_t (*seteccenable)(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-
-	/**
-	 * Get the current value for the Half Datapath option
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] mode Half Datapath setting
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if mode is NULL
-	 */
-	uint32_t (*getreducmode)(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
-
-	/**
-	 * Set the value for the Half Datapath option.  This API must be
-	 * called before startup of memory.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] mode Half Datapath setting
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if mode is NULL
-	 */
-	uint32_t (*setreducmode)(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-
-	/**
-	 * Get the current value for Data Bus Inversion setting.  This will
-	 * be compared with the   current DRAM setting using the MR3
-	 * register.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] on_off DBI read value
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if on_off is NULL
-	 */
-	uint32_t (*getdbireadmode)(const lpddr4_privatedata* pd, bool* on_off);
-
-	/**
-	 * Get the current value for Data Bus Inversion setting.  This will
-	 * be compared with the   current DRAM setting using the MR3
-	 * register.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[out] on_off DBI write value
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if on_off is NULL
-	 */
-	uint32_t (*getdbiwritemode)(const lpddr4_privatedata* pd, bool* on_off);
-
-	/**
-	 * Set the mode for Data Bus Inversion. This will also be set in DRAM
-	 * using the MR3   controller register. This API must be called
-	 * before startup of memory.
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] mode status
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if mode is NULL
-	 */
-	uint32_t (*setdbimode)(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
-
-	/**
-	 * Get the current value for the refresh rate (reading Refresh per
-	 * command timing).
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] fspNum Frequency set number
-	 * @param[out] cycles Refresh rate (in cycles)
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if rate is NULL
-	 */
-	uint32_t (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
-	/**
-	 * Set the refresh rate (writing Refresh per command timing).
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] fspNum Frequency set number
-	 * @param[in] cycles Refresh rate (in cycles)
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if rate is NULL
-	 */
-	uint32_t (*setrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-	/**
-	 * Handle Refreshing per chip select
-	 * @param[in] pD Driver state info specific to this instance.
-	 * @param[in] trefInterval status
-	 * @return CDN_EOK on success.
-	 * @return EINVAL if chipSelect is invalid
-	 */
-	uint32_t (*refreshperchipselect)(const lpddr4_privatedata* pd, const uint32_t trefinterval);
-
-} LPDDR4_OBJ;
-
-/**
- * In order to access the LPDDR4 APIs, the upper layer software must call
- * this global function to obtain the pointer to the driver object.
- * @return LPDDR4_OBJ* Driver Object Pointer
- */
-extern LPDDR4_OBJ *lpddr4_getinstance(void);
-
-#endif  /* LPDDR4_OBJ_IF_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_pi_macros.h b/drivers/ram/k3-j721e/lpddr4_pi_macros.h
deleted file mode 100644
index 23b31f2f51..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_pi_macros.h
+++ /dev/null
@@ -1,5397 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
- */
-
-#ifndef REG_LPDDR4_PI_MACROS_H_
-#define REG_LPDDR4_PI_MACROS_H_
-
-#define LPDDR4__DENALI_PI_0_READ_MASK								0x00000F01U
-#define LPDDR4__DENALI_PI_0_WRITE_MASK				               0x00000F01U
-#define LPDDR4__DENALI_PI_0__PI_START_MASK				           0x00000001U
-#define LPDDR4__DENALI_PI_0__PI_START_SHIFT								   0U
-#define LPDDR4__DENALI_PI_0__PI_START_WIDTH								   1U
-#define LPDDR4__DENALI_PI_0__PI_START_WOCLR								   0U
-#define LPDDR4__DENALI_PI_0__PI_START_WOSET								   0U
-#define LPDDR4__PI_START__REG DENALI_PI_0
-#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
-
-#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK				      0x00000F00U
-#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT				              8U
-#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH				              4U
-#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
-#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
-
-#define LPDDR4__DENALI_PI_1_READ_MASK								0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_1_WRITE_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK				       0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT				               0U
-#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH				              32U
-#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
-#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
-
-#define LPDDR4__DENALI_PI_2_READ_MASK								0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_2_WRITE_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK				       0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT				               0U
-#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH				              32U
-#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
-#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
-
-#define LPDDR4__DENALI_PI_3_READ_MASK								0x0000FFFFU
-#define LPDDR4__DENALI_PI_3_WRITE_MASK				               0x0000FFFFU
-#define LPDDR4__DENALI_PI_3__PI_ID_MASK				              0x0000FFFFU
-#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT								      0U
-#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH								     16U
-#define LPDDR4__PI_ID__REG DENALI_PI_3
-#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
-
-#define LPDDR4__DENALI_PI_4_READ_MASK								0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_4_WRITE_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT				     0U
-#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH				    32U
-#define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4
-#define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0
-
-#define LPDDR4__DENALI_PI_5_READ_MASK								0x00010101U
-#define LPDDR4__DENALI_PI_5_WRITE_MASK				               0x00010101U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK				  0x00000001U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT				          0U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH				          1U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR				          0U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET				          0U
-#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5
-#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ
-
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK				     0x00000100U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT				             8U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH				             1U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR				             0U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET				             0U
-#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5
-#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN
-
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK				  0x00010000U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT				         16U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH				          1U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR				          0U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET				          0U
-#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5
-#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD
-
-#define LPDDR4__DENALI_PI_6_READ_MASK								0x00FFFFFFU
-#define LPDDR4__DENALI_PI_6_WRITE_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK				        0x0000FFFFU
-#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT								0U
-#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH				               16U
-#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6
-#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP
-
-#define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK				       0x00FF0000U
-#define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT				              16U
-#define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH				               8U
-#define LPDDR4__PI_RESERVED0__REG DENALI_PI_6
-#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0
-
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK              0x01000000U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT				     24U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH				      1U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR				      0U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET				      0U
-#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6
-#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ
-
-#define LPDDR4__DENALI_PI_7_READ_MASK								0x01010301U
-#define LPDDR4__DENALI_PI_7_WRITE_MASK				               0x01010301U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK				     0x00000001U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT				             0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH				             1U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR				             0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET				             0U
-#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION
-
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK				0x00000300U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT				        8U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH				        2U
-#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE
-
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK          0x00010000U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT				 16U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH				  1U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR				  0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET				  0U
-#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R
-
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK         0x01000000U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT				24U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH				 1U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR				 0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET				 0U
-#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R
-
-#define LPDDR4__DENALI_PI_8_READ_MASK								0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_8_WRITE_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT				        0U
-#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH				       32U
-#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8
-#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX
-
-#define LPDDR4__DENALI_PI_9_READ_MASK								0x000FFFFFU
-#define LPDDR4__DENALI_PI_9_WRITE_MASK				               0x000FFFFFU
-#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK               0x000FFFFFU
-#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT				       0U
-#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH				      20U
-#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9
-#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP
-
-#define LPDDR4__DENALI_PI_10_READ_MASK				               0x000FFFFFU
-#define LPDDR4__DENALI_PI_10_WRITE_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK               0x000FFFFFU
-#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT				       0U
-#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH				      20U
-#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10
-#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP
-
-#define LPDDR4__DENALI_PI_11_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_11_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT				        0U
-#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH				       32U
-#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11
-#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX
-
-#define LPDDR4__DENALI_PI_12_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_12_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK				       0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT				               0U
-#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH				              32U
-#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
-#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
-
-#define LPDDR4__DENALI_PI_13_READ_MASK				               0x0101011FU
-#define LPDDR4__DENALI_PI_13_WRITE_MASK				              0x0101011FU
-#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK				 0x0000001FU
-#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT				         0U
-#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH				         5U
-#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13
-#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ
-
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK            0x00000100U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT				    8U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH				    1U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR				    0U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET				    0U
-#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13
-#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY
-
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK				       0x00010000U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT				              16U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH				               1U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR				               0U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET				               0U
-#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
-#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
-
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK				      0x01000000U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT				             24U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH				              1U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR				              0U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET				              0U
-#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
-#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
-
-#define LPDDR4__DENALI_PI_14_READ_MASK				               0x0F011F0FU
-#define LPDDR4__DENALI_PI_14_WRITE_MASK				              0x0F011F0FU
-#define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK				         0x0000000FU
-#define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT								 0U
-#define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH								 4U
-#define LPDDR4__PI_CS_MAP__REG DENALI_PI_14
-#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP
-
-#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK               0x00001F00U
-#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT				       8U
-#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH				       5U
-#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
-#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
-
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK           0x00010000U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT				  16U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH				   1U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR				   0U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET				   0U
-#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
-#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
-
-#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK				           0x0F000000U
-#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT								  24U
-#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH								   4U
-#define LPDDR4__PI_TMRR__REG DENALI_PI_14
-#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
-
-#define LPDDR4__DENALI_PI_15_READ_MASK				               0x00010103U
-#define LPDDR4__DENALI_PI_15_WRITE_MASK				              0x00010103U
-#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK               0x00000003U
-#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT				       0U
-#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH				       2U
-#define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15
-#define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT
-
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK            0x00000100U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT				    8U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH				    1U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR				    0U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET				    0U
-#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
-#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
-
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK				      0x00010000U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT				             16U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH				              1U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR				              0U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET				              0U
-#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
-#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
-
-#define LPDDR4__DENALI_PI_16_READ_MASK				               0x010FFFFFU
-#define LPDDR4__DENALI_PI_16_WRITE_MASK				              0x010FFFFFU
-#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT				          0U
-#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH				         20U
-#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
-#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
-
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK				      0x01000000U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT				             24U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH				              1U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR				              0U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET				              0U
-#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
-#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
-
-#define LPDDR4__DENALI_PI_17_READ_MASK				               0x01010001U
-#define LPDDR4__DENALI_PI_17_WRITE_MASK				              0x01010001U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK				 0x00000001U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT				         0U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH				         1U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR				         0U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET				         0U
-#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
-#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
-
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK				     0x00000100U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT				             8U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH				             1U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR				             0U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET				             0U
-#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
-#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
-
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK				  0x00010000U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT				         16U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH				          1U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR				          0U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET				          0U
-#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
-#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
-
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK				0x01000000U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH				        1U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR				        0U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET				        0U
-#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
-#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
-
-#define LPDDR4__DENALI_PI_18_READ_MASK				               0x03010101U
-#define LPDDR4__DENALI_PI_18_WRITE_MASK				              0x03010101U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK				0x00000001U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT				        0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH				        1U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR				        0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET				        0U
-#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
-#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
-
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK				0x00000100U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT				        8U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH				        1U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR				        0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET				        0U
-#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18
-#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2
-
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK				0x00010000U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT				       16U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH				        1U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR				        0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET				        0U
-#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18
-#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3
-
-#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK				0x03000000U
-#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH				        2U
-#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
-#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
-
-#define LPDDR4__DENALI_PI_19_READ_MASK				               0x03030303U
-#define LPDDR4__DENALI_PI_19_WRITE_MASK				              0x03030303U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK				0x00000003U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT				        0U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH				        2U
-#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19
-#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1
-
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK				0x00000300U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT				        8U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH				        2U
-#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19
-#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2
-
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK				0x00030000U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT				       16U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH				        2U
-#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19
-#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3
-
-#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK				0x03000000U
-#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH				        2U
-#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19
-#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0
-
-#define LPDDR4__DENALI_PI_20_READ_MASK				               0x00000007U
-#define LPDDR4__DENALI_PI_20_WRITE_MASK				              0x00000007U
-#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK               0x00000007U
-#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT				       0U
-#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH				       3U
-#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20
-#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE
-
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK				    0x00000100U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT				            8U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH				            1U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR				            0U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET				            0U
-#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20
-#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START
-
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK				     0x00010000U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT				            16U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH				             1U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR				             0U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET				             0U
-#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20
-#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT
-
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK               0x01000000U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT				      24U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH				       1U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR				       0U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET				       0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20
-#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0
-
-#define LPDDR4__DENALI_PI_21_READ_MASK				               0x00030000U
-#define LPDDR4__DENALI_PI_21_WRITE_MASK				              0x00030000U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK               0x00000001U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT				       0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH				       1U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR				       0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET				       0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21
-#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0
-
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK      0x00000100U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT              8U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH              1U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR              0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET              0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0
-
-#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK               0x00030000U
-#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT				      16U
-#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH				       2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21
-#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0
-
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK               0x01000000U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT				      24U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH				       1U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR				       0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET				       0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21
-#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1
-
-#define LPDDR4__DENALI_PI_22_READ_MASK				               0x00030000U
-#define LPDDR4__DENALI_PI_22_WRITE_MASK				              0x00030000U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK               0x00000001U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH				       1U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR				       0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET				       0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22
-#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1
-
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK      0x00000100U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT              8U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH              1U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR              0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET              0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1
-
-#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK               0x00030000U
-#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT				      16U
-#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH				       2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22
-#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1
-
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK               0x01000000U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT				      24U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH				       1U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR				       0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET				       0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22
-#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2
-
-#define LPDDR4__DENALI_PI_23_READ_MASK				               0x00030000U
-#define LPDDR4__DENALI_PI_23_WRITE_MASK				              0x00030000U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK               0x00000001U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT				       0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH				       1U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR				       0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET				       0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23
-#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2
-
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK      0x00000100U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT              8U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH              1U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR              0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET              0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2
-
-#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK               0x00030000U
-#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT				      16U
-#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH				       2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23
-#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2
-
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK               0x01000000U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT				      24U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH				       1U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR				       0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET				       0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23
-#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3
-
-#define LPDDR4__DENALI_PI_24_READ_MASK				               0x00030000U
-#define LPDDR4__DENALI_PI_24_WRITE_MASK				              0x00030000U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK               0x00000001U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT				       0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH				       1U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR				       0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET				       0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24
-#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3
-
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK      0x00000100U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT              8U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH              1U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR              0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET              0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3
-
-#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK               0x00030000U
-#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT				      16U
-#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH				       2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24
-#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3
-
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK				0x01000000U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT				       24U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH				        1U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR				        0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET				        0U
-#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24
-#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START
-
-#define LPDDR4__DENALI_PI_25_READ_MASK				               0x01000000U
-#define LPDDR4__DENALI_PI_25_WRITE_MASK				              0x01000000U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK				   0x00000001U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT				           0U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH				           1U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR				           0U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET				           0U
-#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25
-#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR
-
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK				   0x00000100U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT				           8U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH				           1U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR				           0U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET				           0U
-#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25
-#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD
-
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK             0x00010000U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT				    16U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH				     1U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR				     0U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET				     0U
-#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25
-#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ
-
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK				  0x01000000U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT				         24U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH				          1U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR				          0U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET				          0U
-#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25
-#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN
-
-#define LPDDR4__DENALI_PI_26_READ_MASK				               0x00010101U
-#define LPDDR4__DENALI_PI_26_WRITE_MASK				              0x00010101U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK				  0x00000001U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT				          0U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH				          1U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR				          0U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET				          0U
-#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26
-#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN
-
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK				 0x00000100U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT				         8U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH				         1U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR				         0U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET				         0U
-#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26
-#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY
-
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK             0x00010000U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT				    16U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH				     1U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR				     0U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET				     0U
-#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26
-#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT
-
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK				      0x01000000U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT				             24U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH				              1U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR				              0U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET				              0U
-#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26
-#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ
-
-#define LPDDR4__DENALI_PI_27_READ_MASK				               0x003F3F03U
-#define LPDDR4__DENALI_PI_27_WRITE_MASK				              0x003F3F03U
-#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK				       0x00000003U
-#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT				               0U
-#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH				               2U
-#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27
-#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS
-
-#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK				        0x00003F00U
-#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT								8U
-#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH								6U
-#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27
-#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN
-
-#define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK				          0x003F0000U
-#define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT								 16U
-#define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH								  6U
-#define LPDDR4__PI_WLMRD__REG DENALI_PI_27
-#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD
-
-#define LPDDR4__DENALI_PI_28_READ_MASK				               0x0101FFFFU
-#define LPDDR4__DENALI_PI_28_WRITE_MASK				              0x0101FFFFU
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK				 0x0000FFFFU
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT				         0U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH				        16U
-#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28
-#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK				 0x00010000U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT				        16U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH				         1U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR				         0U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET				         0U
-#define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28
-#define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK             0x01000000U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT				    24U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH				     1U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR				     0U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET				     0U
-#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28
-#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_29_READ_MASK				               0x0F010F01U
-#define LPDDR4__DENALI_PI_29_WRITE_MASK				              0x0F010F01U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK              0x00000001U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT				      0U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH				      1U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR				      0U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET				      0U
-#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK				0x00000F00U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT				        8U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH				        4U
-#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK				   0x00010000U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT				          16U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH				           1U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR				           0U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET				           0U
-#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE
-
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK				   0x0F000000U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT				          24U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH				           4U
-#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_30_READ_MASK				               0x0000FF01U
-#define LPDDR4__DENALI_PI_30_WRITE_MASK				              0x0000FF01U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK             0x00000001U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT				     0U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH				     1U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR				     0U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET				     0U
-#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30
-#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT				          8U
-#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH				          8U
-#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30
-#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN
-
-#define LPDDR4__DENALI_PI_31_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_31_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT				        0U
-#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH				       32U
-#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31
-#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP
-
-#define LPDDR4__DENALI_PI_32_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_32_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT				         0U
-#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH				        32U
-#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32
-#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX
-
-#define LPDDR4__DENALI_PI_33_READ_MASK				               0x0F0F0F1FU
-#define LPDDR4__DENALI_PI_33_WRITE_MASK				              0x0F0F0F1FU
-#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK               0x0000001FU
-#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT				       0U
-#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH				       5U
-#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33
-#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK				       0x00000F00U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT				               8U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH				               4U
-#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33
-#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR
-
-#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK				       0x000F0000U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT				              16U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH				               4U
-#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33
-#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD
-
-#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK				      0x0F000000U
-#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT				             24U
-#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH				              4U
-#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33
-#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE
-
-#define LPDDR4__DENALI_PI_34_READ_MASK				               0x00030000U
-#define LPDDR4__DENALI_PI_34_WRITE_MASK				              0x00030000U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK				      0x00000001U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT				              0U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH				              1U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR				              0U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET				              0U
-#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34
-#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ
-
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK				 0x00000100U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT				         8U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH				         1U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR				         0U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET				         0U
-#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34
-#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ
-
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK				       0x00030000U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT				              16U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH				               2U
-#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34
-#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS
-
-#define LPDDR4__DENALI_PI_35_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_35_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT				            0U
-#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35
-#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0
-
-#define LPDDR4__DENALI_PI_36_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_36_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT				            0U
-#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36
-#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1
-
-#define LPDDR4__DENALI_PI_37_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_37_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT				            0U
-#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37
-#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2
-
-#define LPDDR4__DENALI_PI_38_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_38_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT				            0U
-#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38
-#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3
-
-#define LPDDR4__DENALI_PI_39_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_39_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT				            0U
-#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39
-#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4
-
-#define LPDDR4__DENALI_PI_40_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_40_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT				            0U
-#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40
-#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5
-
-#define LPDDR4__DENALI_PI_41_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_41_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT				            0U
-#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41
-#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6
-
-#define LPDDR4__DENALI_PI_42_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_42_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT				            0U
-#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH				           32U
-#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42
-#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7
-
-#define LPDDR4__DENALI_PI_43_READ_MASK				               0x0101010FU
-#define LPDDR4__DENALI_PI_43_WRITE_MASK				              0x0101010FU
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK				   0x0000000FU
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT				           0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH				           4U
-#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN
-
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK				 0x00000100U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT				         8U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH				         1U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR				         0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET				         0U
-#define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK             0x00010000U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT				    16U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH				     1U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR				     0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET				     0U
-#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK              0x01000000U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT				     24U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH				      1U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR				      0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET				      0U
-#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_44_READ_MASK				               0x01010101U
-#define LPDDR4__DENALI_PI_44_WRITE_MASK				              0x01010101U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK            0x00000001U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT				    0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH				    1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR				    0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET				    0U
-#define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC
-
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK        0x00000100U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT				8U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH				1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR				0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET				0U
-#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK         0x00010000U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT				16U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH				 1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR				 0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET				 0U
-#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK				   0x01000000U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT				          24U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH				           1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR				           0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET				           0U
-#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE
-
-#define LPDDR4__DENALI_PI_45_READ_MASK				               0x000F0F01U
-#define LPDDR4__DENALI_PI_45_WRITE_MASK				              0x000F0F01U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK              0x00000001U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT				      0U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH				      1U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR				      0U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET				      0U
-#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45
-#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE
-
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK				   0x00000F00U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT				           8U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH				           4U
-#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45
-#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK              0x000F0000U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT				     16U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH				      4U
-#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45
-#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP
-
-#define LPDDR4__DENALI_PI_46_READ_MASK				               0x000003FFU
-#define LPDDR4__DENALI_PI_46_WRITE_MASK				              0x000003FFU
-#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK				  0x000003FFU
-#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT				          0U
-#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH				         10U
-#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46
-#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR
-
-#define LPDDR4__DENALI_PI_47_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_47_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT				        0U
-#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH				       32U
-#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47
-#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP
-
-#define LPDDR4__DENALI_PI_48_READ_MASK				               0x0000FF0FU
-#define LPDDR4__DENALI_PI_48_WRITE_MASK				              0x0000FF0FU
-#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK				0x0000000FU
-#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT				        0U
-#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH				        4U
-#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48
-#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT				          8U
-#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH				          8U
-#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48
-#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN
-
-#define LPDDR4__DENALI_PI_49_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_49_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT				         0U
-#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH				        32U
-#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49
-#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX
-
-#define LPDDR4__DENALI_PI_50_READ_MASK				               0x00FFFF01U
-#define LPDDR4__DENALI_PI_50_WRITE_MASK				              0x00FFFF01U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK             0x00000001U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT				     0U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH				     1U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR				     0U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET				     0U
-#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50
-#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK				 0x00FFFF00U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT				         8U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH				        16U
-#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50
-#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_51_READ_MASK				               0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_51_WRITE_MASK				              0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK            0x0000FFFFU
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT				    0U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH				   16U
-#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51
-#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL
-
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK            0x000F0000U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT				   16U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH				    4U
-#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51
-#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START
-
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK              0x0F000000U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT				     24U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH				      4U
-#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51
-#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM
-
-#define LPDDR4__DENALI_PI_52_READ_MASK				               0x01011F1FU
-#define LPDDR4__DENALI_PI_52_WRITE_MASK				              0x01011F1FU
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK               0x0000001FU
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT				       0U
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH				       5U
-#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52
-#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK          0x00001F00U
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT				  8U
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH				  5U
-#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52
-#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK        0x00010000U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT               16U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH				1U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR				0U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET				0U
-#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52
-#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN
-
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK				0x01000000U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT				       24U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH				        1U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR				        0U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET				        0U
-#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52
-#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE
-
-#define LPDDR4__DENALI_PI_53_READ_MASK				               0x03007F7FU
-#define LPDDR4__DENALI_PI_53_WRITE_MASK				              0x03007F7FU
-#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK				 0x0000007FU
-#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT				         0U
-#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH				         7U
-#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53
-#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN
-
-#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK				 0x00007F00U
-#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT				         8U
-#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH				         7U
-#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53
-#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT
-
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK				      0x00010000U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT				             16U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH				              1U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR				              0U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET				              0U
-#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53
-#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ
-
-#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK				       0x03000000U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT				              24U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH				               2U
-#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53
-#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS
-
-#define LPDDR4__DENALI_PI_54_READ_MASK				               0x01030F01U
-#define LPDDR4__DENALI_PI_54_WRITE_MASK				              0x01030F01U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK				      0x00000001U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT				              0U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH				              1U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR				              0U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET				              0U
-#define LPDDR4__PI_RESERVED3__REG DENALI_PI_54
-#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3
-
-#define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK				      0x00000F00U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT				              8U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH				              4U
-#define LPDDR4__PI_RESERVED4__REG DENALI_PI_54
-#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4
-
-#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK				   0x00030000U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT				          16U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH				           2U
-#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54
-#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN
-
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK				 0x01000000U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT				        24U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH				         1U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR				         0U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET				         0U
-#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54
-#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_55_READ_MASK				               0x0F010101U
-#define LPDDR4__DENALI_PI_55_WRITE_MASK				              0x0F010101U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK             0x00000001U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT				     0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH				     1U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR				     0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET				     0U
-#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK              0x00000100U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT				      8U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH				      1U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR				      0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET				      0U
-#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK				   0x00010000U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT				          16U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH				           1U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR				           0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET				           0U
-#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE
-
-#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK				   0x0F000000U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT				          24U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH				           4U
-#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_56_READ_MASK				               0x000000FFU
-#define LPDDR4__DENALI_PI_56_WRITE_MASK				              0x000000FFU
-#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK				  0x000000FFU
-#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT				          0U
-#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH				          8U
-#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56
-#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN
-
-#define LPDDR4__DENALI_PI_57_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_57_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT				        0U
-#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH				       32U
-#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57
-#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP
-
-#define LPDDR4__DENALI_PI_58_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_58_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT				         0U
-#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH				        32U
-#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58
-#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX
-
-#define LPDDR4__DENALI_PI_59_READ_MASK				               0xFFFF0301U
-#define LPDDR4__DENALI_PI_59_WRITE_MASK				              0xFFFF0301U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK				0x00000001U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT				        0U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH				        1U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR				        0U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET				        0U
-#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59
-#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK             0x00000300U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT				     8U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH				     2U
-#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59
-#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK				 0xFFFF0000U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT				        16U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH				        16U
-#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59
-#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_60_READ_MASK				               0x1F1F3F1FU
-#define LPDDR4__DENALI_PI_60_WRITE_MASK				              0x1F1F3F1FU
-#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK				        0x0000001FU
-#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT								0U
-#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH								5U
-#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60
-#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL
-
-#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK				         0x00003F00U
-#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT								 8U
-#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH								 6U
-#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60
-#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD
-
-#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK				        0x001F0000U
-#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT				               16U
-#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH								5U
-#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60
-#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH
-
-#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK				         0x1F000000U
-#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT								24U
-#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH								 5U
-#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60
-#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT
-
-#define LPDDR4__DENALI_PI_61_READ_MASK				               0xFF0F0F01U
-#define LPDDR4__DENALI_PI_61_WRITE_MASK				              0xFF0F0F01U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK               0x00000001U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT				       0U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH				       1U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR				       0U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET				       0U
-#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61
-#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN
-
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK    0x00000F00U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT            8U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH            4U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK     0x000F0000U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT            16U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH             4U
-#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61
-#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK            0xFF000000U
-#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT				   24U
-#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH				    8U
-#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61
-#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN
-
-#define LPDDR4__DENALI_PI_62_READ_MASK				               0x7F1F0FFFU
-#define LPDDR4__DENALI_PI_62_WRITE_MASK				              0x7F1F0FFFU
-#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK         0x000000FFU
-#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT				 0U
-#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH				 8U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN
-
-#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK				        0x00000F00U
-#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT								8U
-#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH								4U
-#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62
-#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH
-
-#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK               0x001F0000U
-#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT				      16U
-#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH				       5U
-#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62
-#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK               0x7F000000U
-#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT				      24U
-#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH				       7U
-#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62
-#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF
-
-#define LPDDR4__DENALI_PI_63_READ_MASK				               0x0101FFFFU
-#define LPDDR4__DENALI_PI_63_WRITE_MASK				              0x0101FFFFU
-#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK        0x000000FFU
-#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT				0U
-#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH				8U
-#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63
-#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START
-
-#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT      8U
-#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH      8U
-#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63
-#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
-
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK  0x00010000U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT         16U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH          1U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR          0U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET          0U
-#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63
-#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
-
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT       24U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH        1U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR        0U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET        0U
-#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63
-#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
-
-#define LPDDR4__DENALI_PI_64_READ_MASK				               0x00FFFF01U
-#define LPDDR4__DENALI_PI_64_WRITE_MASK				              0x00FFFF01U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK      0x00000001U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT              0U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH              1U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR              0U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET              0U
-#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64
-#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE
-
-#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK            0x00FFFF00U
-#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT				    8U
-#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH				   16U
-#define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64
-#define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK
-
-#define LPDDR4__DENALI_PI_65_READ_MASK				               0xFFFF0000U
-#define LPDDR4__DENALI_PI_65_WRITE_MASK				              0xFFFF0000U
-#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT				0U
-#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH               16U
-#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65
-#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR
-
-#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK				 0xFFFF0000U
-#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT				        16U
-#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH				        16U
-#define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65
-#define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO
-
-#define LPDDR4__DENALI_PI_66_READ_MASK				               0x010F0701U
-#define LPDDR4__DENALI_PI_66_WRITE_MASK				              0x010F0701U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK				 0x00000001U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT				         0U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH				         1U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR				         0U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET				         0U
-#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN
-
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK				 0x00000700U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT				         8U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH				         3U
-#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM
-
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK               0x000F0000U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT				      16U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH				       4U
-#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK				  0x01000000U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT				         24U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH				          1U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR				          0U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET				          0U
-#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE
-
-#define LPDDR4__DENALI_PI_67_READ_MASK				               0x011F1F0FU
-#define LPDDR4__DENALI_PI_67_WRITE_MASK				              0x011F1F0FU
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK				  0x0000000FU
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT				          0U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH				          4U
-#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK   0x00001F00U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT           8U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH           5U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK    0x001F0000U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT           16U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH            5U
-#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK				0x01000000U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT				       24U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH				        1U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR				        0U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET				        0U
-#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_68_READ_MASK				               0x00FF0300U
-#define LPDDR4__DENALI_PI_68_WRITE_MASK				              0x00FF0300U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK				     0x00000001U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT				             0U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH				             1U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR				             0U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET				             0U
-#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68
-#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ
-
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK				      0x00000300U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT				              8U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH				              2U
-#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68
-#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS
-
-#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT				        16U
-#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH				         8U
-#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68
-#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN
-
-#define LPDDR4__DENALI_PI_69_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_69_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT				       0U
-#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH				      32U
-#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69
-#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP
-
-#define LPDDR4__DENALI_PI_70_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_70_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT				        0U
-#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH				       32U
-#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70
-#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX
-
-#define LPDDR4__DENALI_PI_71_READ_MASK				               0x0101FFFFU
-#define LPDDR4__DENALI_PI_71_WRITE_MASK				              0x0101FFFFU
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT				        0U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH				       16U
-#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71
-#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK            0x00010000U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT				   16U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH				    1U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR				    0U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET				    0U
-#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71
-#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK             0x01000000U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT				    24U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH				     1U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR				     0U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET				     0U
-#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71
-#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_72_READ_MASK				               0x01010103U
-#define LPDDR4__DENALI_PI_72_WRITE_MASK				              0x01010103U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK            0x00000003U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT				    0U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH				    2U
-#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72
-#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK				  0x00000100U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT				          8U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH				          1U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR				          0U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET				          0U
-#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72
-#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN
-
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK              0x00010000U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT				     16U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH				      1U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR				      0U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET				      0U
-#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72
-#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN
-
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK             0x01000000U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT				    24U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH				     1U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR				     0U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET				     0U
-#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72
-#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN
-
-#define LPDDR4__DENALI_PI_73_READ_MASK				               0x0F1F0703U
-#define LPDDR4__DENALI_PI_73_WRITE_MASK				              0x0F1F0703U
-#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK				      0x00000003U
-#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT				              0U
-#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH				              2U
-#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73
-#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF
-
-#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK				       0x00000700U
-#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT				               8U
-#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH				               3U
-#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73
-#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF
-
-#define LPDDR4__DENALI_PI_73__PI_TCCD_MASK				           0x001F0000U
-#define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT								  16U
-#define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH								   5U
-#define LPDDR4__PI_TCCD__REG DENALI_PI_73
-#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD
-
-#define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK				      0x0F000000U
-#define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT				             24U
-#define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH				              4U
-#define LPDDR4__PI_RESERVED5__REG DENALI_PI_73
-#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5
-
-#define LPDDR4__DENALI_PI_74_READ_MASK				               0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_74_WRITE_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK				      0x0000000FU
-#define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT				              0U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH				              4U
-#define LPDDR4__PI_RESERVED6__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6
-
-#define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK				      0x00000F00U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT				              8U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH				              4U
-#define LPDDR4__PI_RESERVED7__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7
-
-#define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK				      0x000F0000U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT				             16U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH				              4U
-#define LPDDR4__PI_RESERVED8__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8
-
-#define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK				      0x0F000000U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT				             24U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH				              4U
-#define LPDDR4__PI_RESERVED9__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9
-
-#define LPDDR4__DENALI_PI_75_READ_MASK				               0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_75_WRITE_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK				     0x0000000FU
-#define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT				             0U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH				             4U
-#define LPDDR4__PI_RESERVED10__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10
-
-#define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK				     0x00000F00U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT				             8U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH				             4U
-#define LPDDR4__PI_RESERVED11__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11
-
-#define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK				     0x000F0000U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT				            16U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH				             4U
-#define LPDDR4__PI_RESERVED12__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12
-
-#define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK				     0x0F000000U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT				            24U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH				             4U
-#define LPDDR4__PI_RESERVED13__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13
-
-#define LPDDR4__DENALI_PI_76_READ_MASK				               0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_76_WRITE_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK				     0x0000000FU
-#define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT				             0U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH				             4U
-#define LPDDR4__PI_RESERVED14__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14
-
-#define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK				     0x00000F00U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT				             8U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH				             4U
-#define LPDDR4__PI_RESERVED15__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15
-
-#define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK				     0x000F0000U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT				            16U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH				             4U
-#define LPDDR4__PI_RESERVED16__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16
-
-#define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK				     0x0F000000U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT				            24U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH				             4U
-#define LPDDR4__PI_RESERVED17__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17
-
-#define LPDDR4__DENALI_PI_77_READ_MASK				               0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_77_WRITE_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK				     0x0000000FU
-#define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT				             0U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH				             4U
-#define LPDDR4__PI_RESERVED18__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18
-
-#define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK				     0x00000F00U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT				             8U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH				             4U
-#define LPDDR4__PI_RESERVED19__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19
-
-#define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK				     0x000F0000U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT				            16U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH				             4U
-#define LPDDR4__PI_RESERVED20__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20
-
-#define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK				     0x0F000000U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT				            24U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH				             4U
-#define LPDDR4__PI_RESERVED21__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21
-
-#define LPDDR4__DENALI_PI_78_READ_MASK				               0x000F0F0FU
-#define LPDDR4__DENALI_PI_78_WRITE_MASK				              0x000F0F0FU
-#define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK				     0x0000000FU
-#define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT				             0U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH				             4U
-#define LPDDR4__PI_RESERVED22__REG DENALI_PI_78
-#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22
-
-#define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK				     0x00000F00U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT				             8U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH				             4U
-#define LPDDR4__PI_RESERVED23__REG DENALI_PI_78
-#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23
-
-#define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK				     0x000F0000U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT				            16U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH				             4U
-#define LPDDR4__PI_RESERVED24__REG DENALI_PI_78
-#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24
-
-#define LPDDR4__DENALI_PI_79_READ_MASK				               0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_79_WRITE_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK				     0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT				             0U
-#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH				            28U
-#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79
-#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS
-
-#define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK				        0x07FFFFFFU
-#define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT								0U
-#define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH				               27U
-#define LPDDR4__PI_INT_ACK__REG DENALI_PI_80
-#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK
-
-#define LPDDR4__DENALI_PI_81_READ_MASK				               0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_81_WRITE_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK				       0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT				               0U
-#define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH				              28U
-#define LPDDR4__PI_INT_MASK__REG DENALI_PI_81
-#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK
-
-#define LPDDR4__DENALI_PI_82_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_82_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT				        0U
-#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH				       32U
-#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82
-#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0
-
-#define LPDDR4__DENALI_PI_83_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_83_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT				        0U
-#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH				       32U
-#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83
-#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1
-
-#define LPDDR4__DENALI_PI_84_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_84_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT				        0U
-#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH				       32U
-#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84
-#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2
-
-#define LPDDR4__DENALI_PI_85_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_85_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT				        0U
-#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH				       32U
-#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85
-#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3
-
-#define LPDDR4__DENALI_PI_86_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_86_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT				       0U
-#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH				      32U
-#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86
-#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0
-
-#define LPDDR4__DENALI_PI_87_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_87_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH				      32U
-#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87
-#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1
-
-#define LPDDR4__DENALI_PI_88_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_88_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT				       0U
-#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH				      32U
-#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88
-#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2
-
-#define LPDDR4__DENALI_PI_89_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_89_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT				       0U
-#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH				      32U
-#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89
-#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3
-
-#define LPDDR4__DENALI_PI_90_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_90_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT				       0U
-#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH				      32U
-#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90
-#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0
-
-#define LPDDR4__DENALI_PI_91_READ_MASK				               0x011F1F07U
-#define LPDDR4__DENALI_PI_91_WRITE_MASK				              0x011F1F07U
-#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK               0x00000007U
-#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH				       3U
-#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91
-#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1
-
-#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK				         0x00001F00U
-#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT								 8U
-#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH								 5U
-#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91
-#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN
-
-#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK				0x001F0000U
-#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT				       16U
-#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH				        5U
-#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91
-#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK
-
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT				           24U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH				            1U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR				            0U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET				            0U
-#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91
-#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN
-
-#define LPDDR4__DENALI_PI_92_READ_MASK				               0x03030301U
-#define LPDDR4__DENALI_PI_92_WRITE_MASK				              0x03030301U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK              0x00000001U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT				      0U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH				      1U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR				      0U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET				      0U
-#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN
-
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK          0x00000300U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT				  8U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH				  2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0
-
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK          0x00030000U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT				 16U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH				  2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1
-
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK          0x03000000U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT				 24U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH				  2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2
-
-#define LPDDR4__DENALI_PI_93_READ_MASK				               0x03FF0103U
-#define LPDDR4__DENALI_PI_93_WRITE_MASK				              0x03FF0103U
-#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK          0x00000003U
-#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT				  0U
-#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH				  2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3
-
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK        0x00000100U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT				8U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH				1U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR				0U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET				0U
-#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93
-#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN
-
-#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK               0x00FF0000U
-#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT				      16U
-#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH				       8U
-#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93
-#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN
-
-#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK            0x03000000U
-#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT				   24U
-#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH				    2U
-#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93
-#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_94_READ_MASK				               0x013F0301U
-#define LPDDR4__DENALI_PI_94_WRITE_MASK				              0x013F0301U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK				        0x00000001U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT								0U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH								1U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR								0U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET								0U
-#define LPDDR4__PI_BIST_GO__REG DENALI_PI_94
-#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO
-
-#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK				    0x00000300U
-#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT				            8U
-#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH				            2U
-#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94
-#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT
-
-#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK				     0x003F0000U
-#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT				            16U
-#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH				             6U
-#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94
-#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE
-
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK				0x01000000U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT				       24U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH				        1U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR				        0U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET				        0U
-#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94
-#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK
-
-#define LPDDR4__DENALI_PI_95_READ_MASK				               0x00000001U
-#define LPDDR4__DENALI_PI_95_WRITE_MASK				              0x00000001U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK				0x00000001U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT				        0U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH				        1U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR				        0U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET				        0U
-#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95
-#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK
-
-#define LPDDR4__DENALI_PI_96_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_96_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT				   0U
-#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH				  32U
-#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96
-#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0
-
-#define LPDDR4__DENALI_PI_97_READ_MASK				               0x0000FF07U
-#define LPDDR4__DENALI_PI_97_WRITE_MASK				              0x0000FF07U
-#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK           0x00000007U
-#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT				   0U
-#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH				   3U
-#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97
-#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1
-
-#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK             0x0000FF00U
-#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT				     8U
-#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH				     8U
-#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97
-#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN
-
-#define LPDDR4__DENALI_PI_98_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_98_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT				       0U
-#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH				      32U
-#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98
-#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0
-
-#define LPDDR4__DENALI_PI_99_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_99_WRITE_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH				      32U
-#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99
-#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1
-
-#define LPDDR4__DENALI_PI_100_READ_MASK				              0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_100_WRITE_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK				0x00000FFFU
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT				        0U
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH				       12U
-#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100
-#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT
-
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK				 0x0FFF0000U
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT				        16U
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH				        12U
-#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100
-#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP
-
-#define LPDDR4__DENALI_PI_101_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_101_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101
-#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0
-
-#define LPDDR4__DENALI_PI_102_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_102_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102
-#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1
-
-#define LPDDR4__DENALI_PI_103_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_103_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103
-#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0
-
-#define LPDDR4__DENALI_PI_104_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_104_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104
-#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1
-
-#define LPDDR4__DENALI_PI_105_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_105_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105
-#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0
-
-#define LPDDR4__DENALI_PI_106_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_106_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106
-#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1
-
-#define LPDDR4__DENALI_PI_107_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_107_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107
-#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0
-
-#define LPDDR4__DENALI_PI_108_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_108_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108
-#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1
-
-#define LPDDR4__DENALI_PI_109_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_109_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109
-#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0
-
-#define LPDDR4__DENALI_PI_110_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_110_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110
-#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1
-
-#define LPDDR4__DENALI_PI_111_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_111_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111
-#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0
-
-#define LPDDR4__DENALI_PI_112_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_112_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112
-#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1
-
-#define LPDDR4__DENALI_PI_113_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_113_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113
-#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0
-
-#define LPDDR4__DENALI_PI_114_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_114_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114
-#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1
-
-#define LPDDR4__DENALI_PI_115_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_115_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115
-#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0
-
-#define LPDDR4__DENALI_PI_116_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_116_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116
-#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1
-
-#define LPDDR4__DENALI_PI_117_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_117_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117
-#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0
-
-#define LPDDR4__DENALI_PI_118_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_118_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118
-#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1
-
-#define LPDDR4__DENALI_PI_119_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_119_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH				   32U
-#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119
-#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0
-
-#define LPDDR4__DENALI_PI_120_READ_MASK				              0x0303070FU
-#define LPDDR4__DENALI_PI_120_WRITE_MASK				             0x0303070FU
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH				    4U
-#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1
-
-#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK				     0x00000700U
-#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT				             8U
-#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH				             3U
-#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE
-
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK				0x00030000U
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT				       16U
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH				        2U
-#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE
-
-#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK				 0x03000000U
-#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT				        24U
-#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH				         2U
-#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE
-
-#define LPDDR4__DENALI_PI_121_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_121_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT				       0U
-#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH				      32U
-#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121
-#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0
-
-#define LPDDR4__DENALI_PI_122_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_122_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH				      32U
-#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122
-#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1
-
-#define LPDDR4__DENALI_PI_123_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_123_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT				       0U
-#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH				      32U
-#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123
-#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2
-
-#define LPDDR4__DENALI_PI_124_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_124_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK               0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT				       0U
-#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH				      32U
-#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124
-#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3
-
-#define LPDDR4__DENALI_PI_125_READ_MASK				              0x0000000FU
-#define LPDDR4__DENALI_PI_125_WRITE_MASK				             0x0000000FU
-#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK				  0x0000000FU
-#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT				          0U
-#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH				          4U
-#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125
-#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM
-
-#define LPDDR4__DENALI_PI_126_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_126_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT				          0U
-#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126
-#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0
-
-#define LPDDR4__DENALI_PI_127_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_127_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT				          0U
-#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127
-#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1
-
-#define LPDDR4__DENALI_PI_128_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_128_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT				          0U
-#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128
-#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2
-
-#define LPDDR4__DENALI_PI_129_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_129_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT				          0U
-#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129
-#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3
-
-#define LPDDR4__DENALI_PI_130_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_130_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT				          0U
-#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130
-#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4
-
-#define LPDDR4__DENALI_PI_131_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_131_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT				          0U
-#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131
-#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5
-
-#define LPDDR4__DENALI_PI_132_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_132_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT				          0U
-#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132
-#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6
-
-#define LPDDR4__DENALI_PI_133_READ_MASK				              0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_133_WRITE_MASK				             0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK				  0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT				          0U
-#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH				         30U
-#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133
-#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7
-
-#define LPDDR4__DENALI_PI_134_READ_MASK				              0x0101010FU
-#define LPDDR4__DENALI_PI_134_WRITE_MASK				             0x0101010FU
-#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK				      0x0000000FU
-#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT				              0U
-#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH				              4U
-#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134
-#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF
-
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK               0x00000100U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT				       8U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH				       1U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR				       0U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET				       0U
-#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134
-#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN
-
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK           0x00010000U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT				  16U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH				   1U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR				   0U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET				   0U
-#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
-#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT
-
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK      0x01000000U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT             24U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH              1U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR              0U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET              0U
-#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134
-#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH
-
-#define LPDDR4__DENALI_PI_135_READ_MASK				              0x01010100U
-#define LPDDR4__DENALI_PI_135_WRITE_MASK				             0x01010100U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK				0x00000001U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT				        0U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH				        1U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR				        0U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET				        0U
-#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135
-#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ
-
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK				0x00000100U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT				        8U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH				        1U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR				        0U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET				        0U
-#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135
-#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT
-
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK				   0x00010000U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT				          16U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH				           1U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR				           0U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET				           0U
-#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135
-#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT
-
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK         0x01000000U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT				24U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH				 1U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR				 0U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET				 0U
-#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135
-#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT
-
-#define LPDDR4__DENALI_PI_136_READ_MASK				              0x00000001U
-#define LPDDR4__DENALI_PI_136_WRITE_MASK				             0x00000001U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK              0x00000001U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT				      0U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH				      1U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR				      0U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET				      0U
-#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136
-#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT
-
-#define LPDDR4__DENALI_PI_137_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_137_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT				            0U
-#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH				           32U
-#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137
-#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON
-
-#define LPDDR4__DENALI_PI_138_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_138_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK				  0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT				          0U
-#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH				         32U
-#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138
-#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE
-
-#define LPDDR4__DENALI_PI_139_READ_MASK				              0xFFFF0101U
-#define LPDDR4__DENALI_PI_139_WRITE_MASK				             0xFFFF0101U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK				       0x00000001U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT				               0U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH				               1U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR				               0U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET				               0U
-#define LPDDR4__PI_DLL_RST__REG DENALI_PI_139
-#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST
-
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK				  0x00000100U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT				          8U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH				          1U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR				          0U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET				          0U
-#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139
-#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN
-
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK				 0xFFFF0000U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT				        16U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH				        16U
-#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139
-#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY
-
-#define LPDDR4__DENALI_PI_140_READ_MASK				              0x000000FFU
-#define LPDDR4__DENALI_PI_140_WRITE_MASK				             0x000000FFU
-#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK               0x000000FFU
-#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT				       0U
-#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH				       8U
-#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140
-#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY
-
-#define LPDDR4__DENALI_PI_141_READ_MASK				              0x03FFFFFFU
-#define LPDDR4__DENALI_PI_141_WRITE_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK				 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT				         0U
-#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH				        26U
-#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141
-#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG
-
-#define LPDDR4__DENALI_PI_142_READ_MASK				              0x01FFFFFFU
-#define LPDDR4__DENALI_PI_142_WRITE_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK				    0x000000FFU
-#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT				            0U
-#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH				            8U
-#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142
-#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS
-
-#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK				  0x01FFFF00U
-#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT				          8U
-#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH				         17U
-#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142
-#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG
-
-#define LPDDR4__DENALI_PI_143_READ_MASK				              0x01FFFFFFU
-#define LPDDR4__DENALI_PI_143_WRITE_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK         0x00FFFFFFU
-#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT				 0U
-#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH				24U
-#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143
-#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0
-
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT				           24U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH				            1U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR				            0U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET				            0U
-#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143
-#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT
-
-#define LPDDR4__DENALI_PI_144_READ_MASK				              0x0101000FU
-#define LPDDR4__DENALI_PI_144_WRITE_MASK				             0x0101000FU
-#define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK				    0x0000000FU
-#define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT				            0U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH				            4U
-#define LPDDR4__PI_RESERVED25__REG DENALI_PI_144
-#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25
-
-#define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK				    0x00000F00U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT				            8U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH				            4U
-#define LPDDR4__PI_RESERVED26__REG DENALI_PI_144
-#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26
-
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK				0x00010000U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT				       16U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH				        1U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR				        0U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET				        0U
-#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144
-#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING
-
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT				           24U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH				            1U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR				            0U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET				            0U
-#define LPDDR4__PI_RESERVED27__REG DENALI_PI_144
-#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27
-
-#define LPDDR4__DENALI_PI_145_READ_MASK				              0xFF010F07U
-#define LPDDR4__DENALI_PI_145_WRITE_MASK				             0xFF010F07U
-#define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK				    0x00000007U
-#define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT				            0U
-#define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH				            3U
-#define LPDDR4__PI_RESERVED28__REG DENALI_PI_145
-#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28
-
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK             0x00000F00U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT				     8U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145
-#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0
-
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK             0x00010000U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT				    16U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH				     1U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR				     0U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145
-#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0
-
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK				     0xFF000000U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT				            24U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145
-#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0
-
-#define LPDDR4__DENALI_PI_146_READ_MASK				              0x0FFF010FU
-#define LPDDR4__DENALI_PI_146_WRITE_MASK				             0x0FFF010FU
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK             0x0000000FU
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT				     0U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1
-
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK             0x00000100U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT				     8U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH				     1U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR				     0U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1
-
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT				            16U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1
-
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK             0x0F000000U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT				    24U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2
-
-#define LPDDR4__DENALI_PI_147_READ_MASK				              0x010FFF01U
-#define LPDDR4__DENALI_PI_147_WRITE_MASK				             0x010FFF01U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK             0x00000001U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT				     0U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH				     1U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR				     0U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2
-
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK				     0x0000FF00U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT				             8U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2
-
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK             0x000F0000U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT				    16U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3
-
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK             0x01000000U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT				    24U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH				     1U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR				     0U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3
-
-#define LPDDR4__DENALI_PI_148_READ_MASK				              0xFF010FFFU
-#define LPDDR4__DENALI_PI_148_WRITE_MASK				             0xFF010FFFU
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK				     0x000000FFU
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT				             0U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3
-
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK             0x00000F00U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT				     8U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4
-
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK             0x00010000U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT				    16U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH				     1U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR				     0U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4
-
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK				     0xFF000000U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT				            24U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4
-
-#define LPDDR4__DENALI_PI_149_READ_MASK				              0x0FFF010FU
-#define LPDDR4__DENALI_PI_149_WRITE_MASK				             0x0FFF010FU
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK             0x0000000FU
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT				     0U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5
-
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK             0x00000100U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT				     8U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH				     1U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR				     0U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5
-
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT				            16U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5
-
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK             0x0F000000U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT				    24U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6
-
-#define LPDDR4__DENALI_PI_150_READ_MASK				              0x010FFF01U
-#define LPDDR4__DENALI_PI_150_WRITE_MASK				             0x010FFF01U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK             0x00000001U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT				     0U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH				     1U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR				     0U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6
-
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK				     0x0000FF00U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT				             8U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6
-
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK             0x000F0000U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT				    16U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH				     4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7
-
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK             0x01000000U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT				    24U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH				     1U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR				     0U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET				     0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7
-
-#define LPDDR4__DENALI_PI_151_READ_MASK				              0x000000FFU
-#define LPDDR4__DENALI_PI_151_WRITE_MASK				             0x000000FFU
-#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK				     0x000000FFU
-#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT				             0U
-#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH				             8U
-#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151
-#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7
-
-#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT				        0U
-#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH				        8U
-#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152
-#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE
-
-#define LPDDR4__DENALI_PI_153_READ_MASK				              0x011F1F01U
-#define LPDDR4__DENALI_PI_153_WRITE_MASK				             0x011F1F01U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK				      0x00000001U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT				              0U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH				              1U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR				              0U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET				              0U
-#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153
-#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK
-
-#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK            0x00001F00U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT				    8U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH				    5U
-#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153
-#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS
-
-#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK            0x001F0000U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT				   16U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH				    5U
-#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153
-#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM
-
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT				           24U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH				            1U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR				            0U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET				            0U
-#define LPDDR4__PI_RESERVED29__REG DENALI_PI_153
-#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29
-
-#define LPDDR4__DENALI_PI_154_READ_MASK				              0x01010103U
-#define LPDDR4__DENALI_PI_154_WRITE_MASK				             0x01010103U
-#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK				  0x00000003U
-#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT				          0U
-#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH				          2U
-#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154
-#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE
-
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK				    0x00000100U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT				            8U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH				            1U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR				            0U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET				            0U
-#define LPDDR4__PI_RESERVED30__REG DENALI_PI_154
-#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30
-
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK				0x00010000U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT				       16U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH				        1U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR				        0U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET				        0U
-#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154
-#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN
-
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT				           24U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH				            1U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR				            0U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET				            0U
-#define LPDDR4__PI_RESERVED31__REG DENALI_PI_154
-#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31
-
-#define LPDDR4__DENALI_PI_155_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_PI_155_WRITE_MASK				             0x01010101U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK				    0x00000001U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT				            0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH				            1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR				            0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET				            0U
-#define LPDDR4__PI_RESERVED32__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32
-
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK				    0x00000100U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT				            8U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH				            1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR				            0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET				            0U
-#define LPDDR4__PI_RESERVED33__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33
-
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK				    0x00010000U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT				           16U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH				            1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR				            0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET				            0U
-#define LPDDR4__PI_RESERVED34__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34
-
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT				           24U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH				            1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR				            0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET				            0U
-#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35
-
-#define LPDDR4__DENALI_PI_156_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_PI_156_WRITE_MASK				             0x01010101U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK				    0x00000001U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT				            0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH				            1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR				            0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET				            0U
-#define LPDDR4__PI_RESERVED36__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36
-
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK				    0x00000100U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT				            8U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH				            1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR				            0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET				            0U
-#define LPDDR4__PI_RESERVED37__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37
-
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK				    0x00010000U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT				           16U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH				            1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR				            0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET				            0U
-#define LPDDR4__PI_RESERVED38__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38
-
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT				           24U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH				            1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR				            0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET				            0U
-#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39
-
-#define LPDDR4__DENALI_PI_157_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_PI_157_WRITE_MASK				             0x01010101U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK				    0x00000001U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT				            0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH				            1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR				            0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET				            0U
-#define LPDDR4__PI_RESERVED40__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40
-
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK				    0x00000100U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT				            8U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH				            1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR				            0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET				            0U
-#define LPDDR4__PI_RESERVED41__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41
-
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK				    0x00010000U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT				           16U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH				            1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR				            0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET				            0U
-#define LPDDR4__PI_RESERVED42__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42
-
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT				           24U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH				            1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR				            0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET				            0U
-#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43
-
-#define LPDDR4__DENALI_PI_158_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_PI_158_WRITE_MASK				             0x01010101U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK				    0x00000001U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT				            0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH				            1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR				            0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET				            0U
-#define LPDDR4__PI_RESERVED44__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44
-
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK				    0x00000100U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT				            8U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH				            1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR				            0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET				            0U
-#define LPDDR4__PI_RESERVED45__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45
-
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK				    0x00010000U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT				           16U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH				            1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR				            0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET				            0U
-#define LPDDR4__PI_RESERVED46__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46
-
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK				    0x01000000U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT				           24U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH				            1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR				            0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET				            0U
-#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47
-
-#define LPDDR4__DENALI_PI_159_READ_MASK				              0x0001FFFFU
-#define LPDDR4__DENALI_PI_159_WRITE_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK         0x000000FFU
-#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT				 0U
-#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH				 8U
-#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159
-#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND
-
-#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK				    0x0001FF00U
-#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT				            8U
-#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH				            9U
-#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159
-#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR
-
-#define LPDDR4__DENALI_PI_160_READ_MASK				              0x0000001FU
-#define LPDDR4__DENALI_PI_160_WRITE_MASK				             0x0000001FU
-#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK          0x0000001FU
-#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT				  0U
-#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH				  5U
-#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160
-#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY
-
-#define LPDDR4__DENALI_PI_161_READ_MASK				              0x0F011F01U
-#define LPDDR4__DENALI_PI_161_WRITE_MASK				             0x0F011F01U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK           0x00000001U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT				   0U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH				   1U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR				   0U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET				   0U
-#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161
-#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF
-
-#define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK				    0x00001F00U
-#define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT				            8U
-#define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH				            5U
-#define LPDDR4__PI_RESERVED48__REG DENALI_PI_161
-#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48
-
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK             0x00010000U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT				    16U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH				     1U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR				     0U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET				     0U
-#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161
-#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN
-
-#define LPDDR4__DENALI_PI_161__PI_CATR_MASK				          0x0F000000U
-#define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT								 24U
-#define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH								  4U
-#define LPDDR4__PI_CATR__REG DENALI_PI_161
-#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR
-
-#define LPDDR4__DENALI_PI_162_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_PI_162_WRITE_MASK				             0x01010101U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK				  0x00000001U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT				          0U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH				          1U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR				          0U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET				          0U
-#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162
-#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ
-
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK            0x00000100U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT				    8U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH				    1U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR				    0U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET				    0U
-#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162
-#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE
-
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK				 0x00010000U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT				        16U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH				         1U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR				         0U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET				         0U
-#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162
-#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC
-
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK         0x01000000U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT				24U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH				 1U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR				 0U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET				 0U
-#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162
-#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START
-
-#define LPDDR4__DENALI_PI_163_READ_MASK				              0xFFFFFF01U
-#define LPDDR4__DENALI_PI_163_WRITE_MASK				             0xFFFFFF01U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK				 0x00000001U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT				         0U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH				         1U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR				         0U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET				         0U
-#define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163
-#define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13
-
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK				       0x0000FF00U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT				               8U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH				               8U
-#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163
-#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0
-
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK				       0x00FF0000U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT				              16U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH				               8U
-#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163
-#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1
-
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK				       0xFF000000U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT				              24U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH				               8U
-#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163
-#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2
-
-#define LPDDR4__DENALI_PI_164_READ_MASK				              0x000000FFU
-#define LPDDR4__DENALI_PI_164_WRITE_MASK				             0x000000FFU
-#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK     0x000000FFU
-#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT             0U
-#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH             8U
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0
-
-#define LPDDR4__DENALI_PI_165_READ_MASK				              0x000000FFU
-#define LPDDR4__DENALI_PI_165_WRITE_MASK				             0x000000FFU
-#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK     0x000000FFU
-#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT             0U
-#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH             8U
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1
-
-#define LPDDR4__DENALI_PI_166_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_PI_166_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK     0x000000FFU
-#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT             0U
-#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH             8U
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2
-
-#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK				     0x000FFF00U
-#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT				             8U
-#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH				            12U
-#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166
-#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0
-
-#define LPDDR4__DENALI_PI_167_READ_MASK				              0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_167_WRITE_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK				     0x00000FFFU
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH				            12U
-#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167
-#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1
-
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK				     0x0FFF0000U
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT				            16U
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH				            12U
-#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167
-#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2
-
-#define LPDDR4__DENALI_PI_168_READ_MASK				              0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_168_WRITE_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK				      0x0000007FU
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT				              0U
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH				              7U
-#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168
-#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0
-
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK				 0x00007F00U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT				         8U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH				         7U
-#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168
-#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0
-
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK				      0x007F0000U
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT				             16U
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH				              7U
-#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168
-#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1
-
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK				 0x7F000000U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT				        24U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH				         7U
-#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168
-#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1
-
-#define LPDDR4__DENALI_PI_169_READ_MASK				              0x03FF7F7FU
-#define LPDDR4__DENALI_PI_169_WRITE_MASK				             0x03FF7F7FU
-#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK				      0x0000007FU
-#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT				              0U
-#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH				              7U
-#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169
-#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2
-
-#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK				 0x00007F00U
-#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT				         8U
-#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH				         7U
-#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169
-#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2
-
-#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK				       0x03FF0000U
-#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT				              16U
-#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH				              10U
-#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169
-#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0
-
-#define LPDDR4__DENALI_PI_170_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_PI_170_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK				       0x000FFFFFU
-#define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT				               0U
-#define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH				              20U
-#define LPDDR4__PI_TREF_F0__REG DENALI_PI_170
-#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0
-
-#define LPDDR4__DENALI_PI_171_READ_MASK				              0x000003FFU
-#define LPDDR4__DENALI_PI_171_WRITE_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK				       0x000003FFU
-#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT				               0U
-#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH				              10U
-#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171
-#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1
-
-#define LPDDR4__DENALI_PI_172_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_PI_172_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK				       0x000FFFFFU
-#define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT				               0U
-#define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH				              20U
-#define LPDDR4__PI_TREF_F1__REG DENALI_PI_172
-#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1
-
-#define LPDDR4__DENALI_PI_173_READ_MASK				              0x000003FFU
-#define LPDDR4__DENALI_PI_173_WRITE_MASK				             0x000003FFU
-#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK				       0x000003FFU
-#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT				               0U
-#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH				              10U
-#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173
-#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2
-
-#define LPDDR4__DENALI_PI_174_READ_MASK				              0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_174_WRITE_MASK				             0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK				       0x000FFFFFU
-#define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT				               0U
-#define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH				              20U
-#define LPDDR4__PI_TREF_F2__REG DENALI_PI_174
-#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2
-
-#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK            0x0F000000U
-#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT				   24U
-#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH				    4U
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0
-
-#define LPDDR4__DENALI_PI_175_READ_MASK				              0x03030F0FU
-#define LPDDR4__DENALI_PI_175_WRITE_MASK				             0x03030F0FU
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT				    0U
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH				    4U
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1
-
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK            0x00000F00U
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT				    8U
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH				    4U
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2
-
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK				   0x00030000U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT				          16U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH				           2U
-#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175
-#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0
-
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK				   0x03000000U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT				          24U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH				           2U
-#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175
-#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1
-
-#define LPDDR4__DENALI_PI_176_READ_MASK				              0x0003FF03U
-#define LPDDR4__DENALI_PI_176_WRITE_MASK				             0x0003FF03U
-#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK				   0x00000003U
-#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT				           0U
-#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH				           2U
-#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176
-#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2
-
-#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK              0x0003FF00U
-#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT				      8U
-#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH				     10U
-#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176
-#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0
-
-#define LPDDR4__DENALI_PI_177_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_177_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK              0x000003FFU
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT				      0U
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH				     10U
-#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177
-#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1
-
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK              0x03FF0000U
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT				     16U
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH				     10U
-#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177
-#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2
-
-#define LPDDR4__DENALI_PI_178_READ_MASK				              0x01FF01FFU
-#define LPDDR4__DENALI_PI_178_WRITE_MASK				             0x01FF01FFU
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT				         0U
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH				         8U
-#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178
-#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0
-
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK				     0x00000100U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT				             8U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH				             1U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR				             0U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET				             0U
-#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178
-#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0
-
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT				        16U
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH				         8U
-#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178
-#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1
-
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK				     0x01000000U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT				            24U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH				             1U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR				             0U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET				             0U
-#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178
-#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1
-
-#define LPDDR4__DENALI_PI_179_READ_MASK				              0x0F0F01FFU
-#define LPDDR4__DENALI_PI_179_WRITE_MASK				             0x0F0F01FFU
-#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT				         0U
-#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH				         8U
-#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179
-#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2
-
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK				     0x00000100U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT				             8U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH				             1U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR				             0U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET				             0U
-#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179
-#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2
-
-#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK				     0x000F0000U
-#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT				            16U
-#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH				             4U
-#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179
-#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0
-
-#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK				 0x0F000000U
-#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT				        24U
-#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH				         4U
-#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179
-#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0
-
-#define LPDDR4__DENALI_PI_180_READ_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_180_WRITE_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK				     0x0000000FU
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH				             4U
-#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180
-#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1
-
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK				 0x00000F00U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT				         8U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH				         4U
-#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180
-#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1
-
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK				     0x000F0000U
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT				            16U
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH				             4U
-#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180
-#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2
-
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK				 0x0F000000U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT				        24U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH				         4U
-#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180
-#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2
-
-#define LPDDR4__DENALI_PI_181_READ_MASK				              0x03030303U
-#define LPDDR4__DENALI_PI_181_WRITE_MASK				             0x03030303U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK				   0x00000003U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT				           0U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH				           2U
-#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0
-
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK              0x00000300U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT				      8U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH				      2U
-#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0
-
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK				   0x00030000U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT				          16U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH				           2U
-#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1
-
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK              0x03000000U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT				     24U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH				      2U
-#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1
-
-#define LPDDR4__DENALI_PI_182_READ_MASK				              0x03030303U
-#define LPDDR4__DENALI_PI_182_WRITE_MASK				             0x03030303U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK				   0x00000003U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT				           0U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH				           2U
-#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2
-
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK              0x00000300U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT				      8U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH				      2U
-#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2
-
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK              0x00030000U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT				     16U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH				      2U
-#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0
-
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK             0x03000000U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT				    24U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH				     2U
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0
-
-#define LPDDR4__DENALI_PI_183_READ_MASK				              0x03030303U
-#define LPDDR4__DENALI_PI_183_WRITE_MASK				             0x03030303U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK               0x00000003U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT				       0U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH				       2U
-#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0
-
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK             0x00000300U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT				     8U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH				     2U
-#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0
-
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK              0x00030000U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT				     16U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH				      2U
-#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1
-
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK             0x03000000U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT				    24U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH				     2U
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1
-
-#define LPDDR4__DENALI_PI_184_READ_MASK				              0x03030303U
-#define LPDDR4__DENALI_PI_184_WRITE_MASK				             0x03030303U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK               0x00000003U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH				       2U
-#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1
-
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK             0x00000300U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT				     8U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH				     2U
-#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1
-
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK              0x00030000U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT				     16U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH				      2U
-#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2
-
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK             0x03000000U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT				    24U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH				     2U
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2
-
-#define LPDDR4__DENALI_PI_185_READ_MASK				              0x7F7F0303U
-#define LPDDR4__DENALI_PI_185_WRITE_MASK				             0x7F7F0303U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK               0x00000003U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT				       0U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH				       2U
-#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185
-#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2
-
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK             0x00000300U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT				     8U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH				     2U
-#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185
-#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2
-
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK				  0x007F0000U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT				         16U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH				          7U
-#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185
-#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0
-
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK				  0x7F000000U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT				         24U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH				          7U
-#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185
-#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1
-
-#define LPDDR4__DENALI_PI_186_READ_MASK				              0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_186_WRITE_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK				  0x0000007FU
-#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT				          0U
-#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH				          7U
-#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186
-#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2
-
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK				  0x00007F00U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT				          8U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH				          7U
-#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186
-#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0
-
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK				  0x007F0000U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT				         16U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH				          7U
-#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186
-#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1
-
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK				  0x7F000000U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT				         24U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH				          7U
-#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186
-#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2
-
-#define LPDDR4__DENALI_PI_187_READ_MASK				              0x00070707U
-#define LPDDR4__DENALI_PI_187_WRITE_MASK				             0x00070707U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK            0x00000007U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH				    3U
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0
-
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK            0x00000700U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT				    8U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH				    3U
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1
-
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK            0x00070000U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT				   16U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH				    3U
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2
-
-#define LPDDR4__DENALI_PI_188_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_188_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK              0x000003FFU
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT				      0U
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH				     10U
-#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188
-#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0
-
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT				16U
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH				10U
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0
-
-#define LPDDR4__DENALI_PI_189_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_189_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK              0x000003FFU
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT				      0U
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH				     10U
-#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189
-#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1
-
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT				16U
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH				10U
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1
-
-#define LPDDR4__DENALI_PI_190_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_190_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK              0x000003FFU
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT				      0U
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH				     10U
-#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190
-#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2
-
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK         0x03FF0000U
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT				16U
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH				10U
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2
-
-#define LPDDR4__DENALI_PI_191_READ_MASK				              0x1F030303U
-#define LPDDR4__DENALI_PI_191_WRITE_MASK				             0x1F030303U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK				   0x00000003U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT				           0U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH				           2U
-#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191
-#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0
-
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK				   0x00000300U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT				           8U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH				           2U
-#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191
-#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1
-
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK				   0x00030000U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT				          16U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH				           2U
-#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191
-#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2
-
-#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK				       0x1F000000U
-#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT				              24U
-#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH				               5U
-#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191
-#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0
-
-#define LPDDR4__DENALI_PI_192_READ_MASK				              0x001F3FFFU
-#define LPDDR4__DENALI_PI_192_WRITE_MASK				             0x001F3FFFU
-#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK				     0x00003FFFU
-#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT				             0U
-#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH				            14U
-#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192
-#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0
-
-#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK				       0x001F0000U
-#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT				              16U
-#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH				               5U
-#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192
-#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1
-
-#define LPDDR4__DENALI_PI_193_READ_MASK				              0x001F3FFFU
-#define LPDDR4__DENALI_PI_193_WRITE_MASK				             0x001F3FFFU
-#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK				     0x00003FFFU
-#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH				            14U
-#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193
-#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1
-
-#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK				       0x001F0000U
-#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT				              16U
-#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH				               5U
-#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193
-#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2
-
-#define LPDDR4__DENALI_PI_194_READ_MASK				              0x1F1F3FFFU
-#define LPDDR4__DENALI_PI_194_WRITE_MASK				             0x1F1F3FFFU
-#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK				     0x00003FFFU
-#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT				             0U
-#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH				            14U
-#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194
-#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2
-
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK				0x001F0000U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT				       16U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH				        5U
-#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194
-#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0
-
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK				 0x1F000000U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT				        24U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH				         5U
-#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194
-#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0
-
-#define LPDDR4__DENALI_PI_195_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_195_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK				0x000003FFU
-#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT				        0U
-#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH				       10U
-#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195
-#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0
-
-#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK				 0x03FF0000U
-#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT				        16U
-#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH				        10U
-#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195
-#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0
-
-#define LPDDR4__DENALI_PI_196_READ_MASK				              0x03FF1F1FU
-#define LPDDR4__DENALI_PI_196_WRITE_MASK				             0x03FF1F1FU
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK				0x0000001FU
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT				        0U
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH				        5U
-#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196
-#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1
-
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK				 0x00001F00U
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT				         8U
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH				         5U
-#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196
-#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1
-
-#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK				0x03FF0000U
-#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT				       16U
-#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH				       10U
-#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196
-#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1
-
-#define LPDDR4__DENALI_PI_197_READ_MASK				              0x1F1F03FFU
-#define LPDDR4__DENALI_PI_197_WRITE_MASK				             0x1F1F03FFU
-#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK				 0x000003FFU
-#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT				         0U
-#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH				        10U
-#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197
-#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1
-
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK				0x001F0000U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT				       16U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH				        5U
-#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197
-#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2
-
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK				 0x1F000000U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT				        24U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH				         5U
-#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197
-#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2
-
-#define LPDDR4__DENALI_PI_198_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_198_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK				0x000003FFU
-#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT				        0U
-#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH				       10U
-#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198
-#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2
-
-#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK				 0x03FF0000U
-#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT				        16U
-#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH				        10U
-#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198
-#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2
-
-#define LPDDR4__DENALI_PI_199_READ_MASK				              0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_199_WRITE_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT     0U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH     7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0
-
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT      8U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH      7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
-
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT    16U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH     7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1
-
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT     24U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH      7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
-
-#define LPDDR4__DENALI_PI_200_READ_MASK				              0x0F0F7F7FU
-#define LPDDR4__DENALI_PI_200_WRITE_MASK				             0x0F0F7F7FU
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT     0U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH     7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2
-
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT      8U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH      7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
-
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK           0x000F0000U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT				  16U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH				   4U
-#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0
-
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK           0x0F000000U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT				  24U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH				   4U
-#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1
-
-#define LPDDR4__DENALI_PI_201_READ_MASK				              0xFF1F0F0FU
-#define LPDDR4__DENALI_PI_201_WRITE_MASK				             0xFF1F0F0FU
-#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK           0x0000000FU
-#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT				   0U
-#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH				   4U
-#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201
-#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2
-
-#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK          0x00000F00U
-#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT				  8U
-#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH				  4U
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0
-
-#define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK				        0x001F0000U
-#define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT				               16U
-#define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH								5U
-#define LPDDR4__PI_TXP_F0__REG DENALI_PI_201
-#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0
-
-#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT				          24U
-#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH				           8U
-#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201
-#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0
-
-#define LPDDR4__DENALI_PI_202_READ_MASK				              0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_202_WRITE_MASK				             0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK				    0x0000001FU
-#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT				            0U
-#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH				            5U
-#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202
-#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0
-
-#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK          0x00000F00U
-#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT				  8U
-#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH				  4U
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1
-
-#define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK				        0x001F0000U
-#define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT				               16U
-#define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH								5U
-#define LPDDR4__PI_TXP_F1__REG DENALI_PI_202
-#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1
-
-#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT				          24U
-#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH				           8U
-#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202
-#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1
-
-#define LPDDR4__DENALI_PI_203_READ_MASK				              0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_203_WRITE_MASK				             0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK				    0x0000001FU
-#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT				            0U
-#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH				            5U
-#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203
-#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1
-
-#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK          0x00000F00U
-#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT				  8U
-#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH				  4U
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2
-
-#define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK				        0x001F0000U
-#define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT				               16U
-#define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH								5U
-#define LPDDR4__PI_TXP_F2__REG DENALI_PI_203
-#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2
-
-#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT				          24U
-#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH				           8U
-#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203
-#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2
-
-#define LPDDR4__DENALI_PI_204_READ_MASK				              0x0003FF1FU
-#define LPDDR4__DENALI_PI_204_WRITE_MASK				             0x0003FF1FU
-#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK				    0x0000001FU
-#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT				            0U
-#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH				            5U
-#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204
-#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2
-
-#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK            0x0003FF00U
-#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT				    8U
-#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH				   10U
-#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204
-#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0
-
-#define LPDDR4__DENALI_PI_205_READ_MASK				              0x03FFFFFFU
-#define LPDDR4__DENALI_PI_205_WRITE_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT				 0U
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH				16U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0
-
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK            0x03FF0000U
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT				   16U
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH				   10U
-#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205
-#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1
-
-#define LPDDR4__DENALI_PI_206_READ_MASK				              0x03FFFFFFU
-#define LPDDR4__DENALI_PI_206_WRITE_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT				 0U
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH				16U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1
-
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK            0x03FF0000U
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT				   16U
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH				   10U
-#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206
-#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2
-
-#define LPDDR4__DENALI_PI_207_READ_MASK				              0x003FFFFFU
-#define LPDDR4__DENALI_PI_207_WRITE_MASK				             0x003FFFFFU
-#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT				 0U
-#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH				16U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2
-
-#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK				   0x003F0000U
-#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT				          16U
-#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH				           6U
-#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207
-#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0
-
-#define LPDDR4__DENALI_PI_208_READ_MASK				              0x003F03FFU
-#define LPDDR4__DENALI_PI_208_WRITE_MASK				             0x003F03FFU
-#define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK				        0x000003FFU
-#define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT								0U
-#define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH				               10U
-#define LPDDR4__PI_TFC_F0__REG DENALI_PI_208
-#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0
-
-#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK				   0x003F0000U
-#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT				          16U
-#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH				           6U
-#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208
-#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1
-
-#define LPDDR4__DENALI_PI_209_READ_MASK				              0x003F03FFU
-#define LPDDR4__DENALI_PI_209_WRITE_MASK				             0x003F03FFU
-#define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK				        0x000003FFU
-#define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT								0U
-#define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH				               10U
-#define LPDDR4__PI_TFC_F1__REG DENALI_PI_209
-#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1
-
-#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK				   0x003F0000U
-#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT				          16U
-#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH				           6U
-#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209
-#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2
-
-#define LPDDR4__DENALI_PI_210_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_210_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK				        0x000003FFU
-#define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT								0U
-#define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH				               10U
-#define LPDDR4__PI_TFC_F2__REG DENALI_PI_210
-#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2
-
-#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK             0x03FF0000U
-#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT				    16U
-#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH				    10U
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0
-
-#define LPDDR4__DENALI_PI_211_READ_MASK				              0x7F7F03FFU
-#define LPDDR4__DENALI_PI_211_WRITE_MASK				             0x7F7F03FFU
-#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK             0x000003FFU
-#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT				     0U
-#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH				    10U
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0
-
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT   16U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH    7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
-
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT    24U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH     7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
-
-#define LPDDR4__DENALI_PI_212_READ_MASK				              0x0003030FU
-#define LPDDR4__DENALI_PI_212_WRITE_MASK				             0x0003030FU
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK          0x0000000FU
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT				  0U
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH				  4U
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0
-
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK				  0x00000300U
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT				          8U
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH				          2U
-#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212
-#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0
-
-#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK               0x00030000U
-#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT				      16U
-#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH				       2U
-#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212
-#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0
-
-#define LPDDR4__DENALI_PI_213_READ_MASK				              0x03FF03FFU
-#define LPDDR4__DENALI_PI_213_WRITE_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK             0x000003FFU
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT				     0U
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH				    10U
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1
-
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK             0x03FF0000U
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT				    16U
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH				    10U
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1
-
-#define LPDDR4__DENALI_PI_214_READ_MASK				              0x030F7F7FU
-#define LPDDR4__DENALI_PI_214_WRITE_MASK				             0x030F7F7FU
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT    0U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH    7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
-
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT     8U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH     7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
-
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK          0x000F0000U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT				 16U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH				  4U
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1
-
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK				  0x03000000U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT				         24U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH				          2U
-#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1
-
-#define LPDDR4__DENALI_PI_215_READ_MASK				              0x0003FF03U
-#define LPDDR4__DENALI_PI_215_WRITE_MASK				             0x0003FF03U
-#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK               0x00000003U
-#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH				       2U
-#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215
-#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1
-
-#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK             0x0003FF00U
-#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT				     8U
-#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH				    10U
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2
-
-#define LPDDR4__DENALI_PI_216_READ_MASK				              0x7F7F03FFU
-#define LPDDR4__DENALI_PI_216_WRITE_MASK				             0x7F7F03FFU
-#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK             0x000003FFU
-#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT				     0U
-#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH				    10U
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2
-
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT   16U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH    7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
-
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT    24U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH     7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
-
-#define LPDDR4__DENALI_PI_217_READ_MASK				              0xFF03030FU
-#define LPDDR4__DENALI_PI_217_WRITE_MASK				             0xFF03030FU
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK          0x0000000FU
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT				  0U
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH				  4U
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2
-
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK				  0x00000300U
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT				          8U
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH				          2U
-#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217
-#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2
-
-#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK               0x00030000U
-#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT				      16U
-#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH				       2U
-#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217
-#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2
-
-#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK				       0xFF000000U
-#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT				              24U
-#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH				               8U
-#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217
-#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0
-
-#define LPDDR4__DENALI_PI_218_READ_MASK				              0xFF3FFFFFU
-#define LPDDR4__DENALI_PI_218_WRITE_MASK				             0xFF3FFFFFU
-#define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK				        0x000000FFU
-#define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT								0U
-#define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH								8U
-#define LPDDR4__PI_TRP_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0
-
-#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK				       0x0000FF00U
-#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT				               8U
-#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH				               8U
-#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0
-
-#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK				       0x003F0000U
-#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT				              16U
-#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH				               6U
-#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0
-
-#define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK				        0xFF000000U
-#define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT				               24U
-#define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH								8U
-#define LPDDR4__PI_TWR_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0
-
-#define LPDDR4__DENALI_PI_219_READ_MASK				              0xFF01FFFFU
-#define LPDDR4__DENALI_PI_219_WRITE_MASK				             0xFF01FFFFU
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK				   0x0001FFFFU
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT				           0U
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH				          17U
-#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219
-#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0
-
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT				          24U
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH				           8U
-#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219
-#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0
-
-#define LPDDR4__DENALI_PI_220_READ_MASK				              0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_220_WRITE_MASK				             0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK				 0x0000000FU
-#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT				         0U
-#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH				         4U
-#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0
-
-#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK				     0x00003F00U
-#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT				             8U
-#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH				             6U
-#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0
-
-#define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT				               16U
-#define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH								8U
-#define LPDDR4__PI_TSR_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0
-
-#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK				       0xFF000000U
-#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT				              24U
-#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH				               8U
-#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0
-
-#define LPDDR4__DENALI_PI_221_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_221_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK				       0x000000FFU
-#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT				               0U
-#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH				               8U
-#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221
-#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0
-
-#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK				       0x0000FF00U
-#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT				               8U
-#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH				               8U
-#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221
-#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1
-
-#define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT				               16U
-#define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH								8U
-#define LPDDR4__PI_TRP_F1__REG DENALI_PI_221
-#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1
-
-#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK				       0xFF000000U
-#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT				              24U
-#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH				               8U
-#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221
-#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1
-
-#define LPDDR4__DENALI_PI_222_READ_MASK				              0x0000FF3FU
-#define LPDDR4__DENALI_PI_222_WRITE_MASK				             0x0000FF3FU
-#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK				       0x0000003FU
-#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT				               0U
-#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH				               6U
-#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222
-#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1
-
-#define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK				        0x0000FF00U
-#define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT								8U
-#define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH								8U
-#define LPDDR4__PI_TWR_F1__REG DENALI_PI_222
-#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1
-
-#define LPDDR4__DENALI_PI_223_READ_MASK				              0xFF01FFFFU
-#define LPDDR4__DENALI_PI_223_WRITE_MASK				             0xFF01FFFFU
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK				   0x0001FFFFU
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT				           0U
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH				          17U
-#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223
-#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1
-
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT				          24U
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH				           8U
-#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223
-#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1
-
-#define LPDDR4__DENALI_PI_224_READ_MASK				              0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_224_WRITE_MASK				             0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK				 0x0000000FU
-#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT				         0U
-#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH				         4U
-#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1
-
-#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK				     0x00003F00U
-#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT				             8U
-#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH				             6U
-#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1
-
-#define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT				               16U
-#define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH								8U
-#define LPDDR4__PI_TSR_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1
-
-#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK				       0xFF000000U
-#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT				              24U
-#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH				               8U
-#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1
-
-#define LPDDR4__DENALI_PI_225_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_225_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK				       0x000000FFU
-#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT				               0U
-#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH				               8U
-#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225
-#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1
-
-#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK				       0x0000FF00U
-#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT				               8U
-#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH				               8U
-#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225
-#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2
-
-#define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT				               16U
-#define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH								8U
-#define LPDDR4__PI_TRP_F2__REG DENALI_PI_225
-#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2
-
-#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK				       0xFF000000U
-#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT				              24U
-#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH				               8U
-#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225
-#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2
-
-#define LPDDR4__DENALI_PI_226_READ_MASK				              0x0000FF3FU
-#define LPDDR4__DENALI_PI_226_WRITE_MASK				             0x0000FF3FU
-#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK				       0x0000003FU
-#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT				               0U
-#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH				               6U
-#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226
-#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2
-
-#define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK				        0x0000FF00U
-#define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT								8U
-#define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH								8U
-#define LPDDR4__PI_TWR_F2__REG DENALI_PI_226
-#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2
-
-#define LPDDR4__DENALI_PI_227_READ_MASK				              0xFF01FFFFU
-#define LPDDR4__DENALI_PI_227_WRITE_MASK				             0xFF01FFFFU
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK				   0x0001FFFFU
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT				           0U
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH				          17U
-#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227
-#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2
-
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT				          24U
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH				           8U
-#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227
-#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2
-
-#define LPDDR4__DENALI_PI_228_READ_MASK				              0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_228_WRITE_MASK				             0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK				 0x0000000FU
-#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT				         0U
-#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH				         4U
-#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2
-
-#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK				     0x00003F00U
-#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT				             8U
-#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH				             6U
-#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2
-
-#define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT				               16U
-#define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH								8U
-#define LPDDR4__PI_TSR_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2
-
-#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK				       0xFF000000U
-#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT				              24U
-#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH				               8U
-#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2
-
-#define LPDDR4__DENALI_PI_229_READ_MASK				              0x1FFFFFFFU
-#define LPDDR4__DENALI_PI_229_WRITE_MASK				             0x1FFFFFFFU
-#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK				       0x000000FFU
-#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT				               0U
-#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH				               8U
-#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229
-#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2
-
-#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK           0x1FFFFF00U
-#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT				   8U
-#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH				  21U
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0
-
-#define LPDDR4__DENALI_PI_230_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_230_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK      0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT              0U
-#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH             32U
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0
-
-#define LPDDR4__DENALI_PI_231_READ_MASK				              0x001FFFFFU
-#define LPDDR4__DENALI_PI_231_WRITE_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK           0x001FFFFFU
-#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT				   0U
-#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH				  21U
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1
-
-#define LPDDR4__DENALI_PI_232_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_232_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK      0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT              0U
-#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH             32U
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1
-
-#define LPDDR4__DENALI_PI_233_READ_MASK				              0x001FFFFFU
-#define LPDDR4__DENALI_PI_233_WRITE_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK           0x001FFFFFU
-#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT				   0U
-#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH				  21U
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2
-
-#define LPDDR4__DENALI_PI_234_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_234_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK      0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT              0U
-#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH             32U
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2
-
-#define LPDDR4__DENALI_PI_235_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_235_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK				       0x0000FFFFU
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT				               0U
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH				              16U
-#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235
-#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0
-
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK				       0xFFFF0000U
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT				              16U
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH				              16U
-#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235
-#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1
-
-#define LPDDR4__DENALI_PI_236_READ_MASK				              0x3F3FFFFFU
-#define LPDDR4__DENALI_PI_236_WRITE_MASK				             0x3F3FFFFFU
-#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK				       0x0000FFFFU
-#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT				               0U
-#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH				              16U
-#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236
-#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2
-
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK				     0x003F0000U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT				            16U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH				             6U
-#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236
-#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0
-
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK				     0x3F000000U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT				            24U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH				             6U
-#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236
-#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1
-
-#define LPDDR4__DENALI_PI_237_READ_MASK				              0xFFFFFF3FU
-#define LPDDR4__DENALI_PI_237_WRITE_MASK				             0xFFFFFF3FU
-#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK				     0x0000003FU
-#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT				             0U
-#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH				             6U
-#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237
-#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2
-
-#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK				      0xFFFFFF00U
-#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT				              8U
-#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH				             24U
-#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237
-#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0
-
-#define LPDDR4__DENALI_PI_238_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_238_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT				             0U
-#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH				            24U
-#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238
-#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0
-
-#define LPDDR4__DENALI_PI_239_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_239_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT				             0U
-#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH				            24U
-#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239
-#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0
-
-#define LPDDR4__DENALI_PI_240_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_240_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT				             0U
-#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH				            24U
-#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240
-#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0
-
-#define LPDDR4__DENALI_PI_241_READ_MASK				              0x0000FFFFU
-#define LPDDR4__DENALI_PI_241_WRITE_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT				              0U
-#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH				             16U
-#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241
-#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0
-
-#define LPDDR4__DENALI_PI_242_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_242_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK				      0x00FFFFFFU
-#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT				              0U
-#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH				             24U
-#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242
-#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1
-
-#define LPDDR4__DENALI_PI_243_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_243_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH				            24U
-#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243
-#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1
-
-#define LPDDR4__DENALI_PI_244_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_244_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH				            24U
-#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244
-#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1
-
-#define LPDDR4__DENALI_PI_245_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_245_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH				            24U
-#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245
-#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1
-
-#define LPDDR4__DENALI_PI_246_READ_MASK				              0x0000FFFFU
-#define LPDDR4__DENALI_PI_246_WRITE_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT				              0U
-#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH				             16U
-#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246
-#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1
-
-#define LPDDR4__DENALI_PI_247_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_247_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK				      0x00FFFFFFU
-#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT				              0U
-#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH				             24U
-#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247
-#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2
-
-#define LPDDR4__DENALI_PI_248_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_248_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT				             0U
-#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH				            24U
-#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248
-#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2
-
-#define LPDDR4__DENALI_PI_249_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_249_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT				             0U
-#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH				            24U
-#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249
-#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2
-
-#define LPDDR4__DENALI_PI_250_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_PI_250_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK				     0x00FFFFFFU
-#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT				             0U
-#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH				            24U
-#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250
-#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2
-
-#define LPDDR4__DENALI_PI_251_READ_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_251_WRITE_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT				              0U
-#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH				             16U
-#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251
-#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2
-
-#define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK				    0x0FFF0000U
-#define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT				           16U
-#define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH				           12U
-#define LPDDR4__PI_RESERVED49__REG DENALI_PI_251
-#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49
-
-#define LPDDR4__DENALI_PI_252_READ_MASK				              0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_252_WRITE_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK				    0x00000FFFU
-#define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT				            0U
-#define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH				           12U
-#define LPDDR4__PI_RESERVED50__REG DENALI_PI_252
-#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50
-
-#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK				     0x0FFF0000U
-#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT				            16U
-#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH				            12U
-#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252
-#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0
-
-#define LPDDR4__DENALI_PI_253_READ_MASK				              0x000FFF7FU
-#define LPDDR4__DENALI_PI_253_WRITE_MASK				             0x000FFF7FU
-#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK				     0x0000007FU
-#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT				             0U
-#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH				             7U
-#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253
-#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0
-
-#define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK				    0x000FFF00U
-#define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT				            8U
-#define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH				           12U
-#define LPDDR4__PI_RESERVED51__REG DENALI_PI_253
-#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51
-
-#define LPDDR4__DENALI_PI_254_READ_MASK				              0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_254_WRITE_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK				    0x00000FFFU
-#define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT				            0U
-#define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH				           12U
-#define LPDDR4__PI_RESERVED52__REG DENALI_PI_254
-#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52
-
-#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK				     0x0FFF0000U
-#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT				            16U
-#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH				            12U
-#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254
-#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1
-
-#define LPDDR4__DENALI_PI_255_READ_MASK				              0x000FFF7FU
-#define LPDDR4__DENALI_PI_255_WRITE_MASK				             0x000FFF7FU
-#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK				     0x0000007FU
-#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH				             7U
-#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255
-#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1
-
-#define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK				    0x000FFF00U
-#define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT				            8U
-#define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH				           12U
-#define LPDDR4__PI_RESERVED53__REG DENALI_PI_255
-#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53
-
-#define LPDDR4__DENALI_PI_256_READ_MASK				              0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_256_WRITE_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK				    0x00000FFFU
-#define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT				            0U
-#define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH				           12U
-#define LPDDR4__PI_RESERVED54__REG DENALI_PI_256
-#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54
-
-#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK				     0x0FFF0000U
-#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT				            16U
-#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH				            12U
-#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256
-#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2
-
-#define LPDDR4__DENALI_PI_257_READ_MASK				              0x000FFF7FU
-#define LPDDR4__DENALI_PI_257_WRITE_MASK				             0x000FFF7FU
-#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK				     0x0000007FU
-#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT				             0U
-#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH				             7U
-#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257
-#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2
-
-#define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK				    0x000FFF00U
-#define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT				            8U
-#define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH				           12U
-#define LPDDR4__PI_RESERVED55__REG DENALI_PI_257
-#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55
-
-#define LPDDR4__DENALI_PI_258_READ_MASK				              0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_258_WRITE_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK				    0x00000FFFU
-#define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT				            0U
-#define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH				           12U
-#define LPDDR4__PI_RESERVED56__REG DENALI_PI_258
-#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56
-
-#define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK				    0x0FFF0000U
-#define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT				           16U
-#define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH				           12U
-#define LPDDR4__PI_RESERVED57__REG DENALI_PI_258
-#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57
-
-#define LPDDR4__DENALI_PI_259_READ_MASK				              0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_259_WRITE_MASK				             0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK        0x0000000FU
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT				0U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH				4U
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0
-
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK        0x00000F00U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT				8U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH				4U
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1
-
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK        0x000F0000U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT               16U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH				4U
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2
-
-#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT				          24U
-#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH				           8U
-#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259
-#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0
-
-#define LPDDR4__DENALI_PI_260_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_260_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT				           0U
-#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH				           8U
-#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0
-
-#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT				           8U
-#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH				           8U
-#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0
-
-#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT				          16U
-#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH				           8U
-#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0
-
-#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT				          24U
-#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH				           8U
-#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0
-
-#define LPDDR4__DENALI_PI_261_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_261_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT				           0U
-#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH				           8U
-#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261
-#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0
-
-#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT				           8U
-#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH				           8U
-#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261
-#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0
-
-#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT				          16U
-#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH				           8U
-#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261
-#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1
-
-#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT				          24U
-#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH				           8U
-#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261
-#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1
-
-#define LPDDR4__DENALI_PI_262_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_262_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK				   0x000000FFU
-#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT				           0U
-#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH				           8U
-#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1
-
-#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT				           8U
-#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH				           8U
-#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1
-
-#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT				          16U
-#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH				           8U
-#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1
-
-#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT				          24U
-#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH				           8U
-#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1
-
-#define LPDDR4__DENALI_PI_263_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_263_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK				   0x000000FFU
-#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT				           0U
-#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH				           8U
-#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263
-#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1
-
-#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT				           8U
-#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH				           8U
-#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263
-#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2
-
-#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT				          16U
-#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH				           8U
-#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263
-#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2
-
-#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT				          24U
-#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH				           8U
-#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263
-#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2
-
-#define LPDDR4__DENALI_PI_264_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_264_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK				   0x000000FFU
-#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT				           0U
-#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH				           8U
-#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2
-
-#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT				           8U
-#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH				           8U
-#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2
-
-#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT				          16U
-#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH				           8U
-#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2
-
-#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT				          24U
-#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH				           8U
-#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2
-
-#define LPDDR4__DENALI_PI_265_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_265_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK				   0x000000FFU
-#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT				           0U
-#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH				           8U
-#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3
-
-#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT				           8U
-#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH				           8U
-#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3
-
-#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT				          16U
-#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH				           8U
-#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3
-
-#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK				   0xFF000000U
-#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT				          24U
-#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH				           8U
-#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3
-
-#define LPDDR4__DENALI_PI_266_READ_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_266_WRITE_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK				   0x000000FFU
-#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT				           0U
-#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH				           8U
-#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266
-#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3
-
-#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT				           8U
-#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH				           8U
-#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266
-#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3
-
-#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT				          16U
-#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH				           8U
-#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266
-#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3
-
-#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK				     0x0F000000U
-#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT				            24U
-#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH				             4U
-#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266
-#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0
-
-#define LPDDR4__DENALI_PI_267_READ_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_267_WRITE_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK				     0x0000000FU
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT				             0U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH				             4U
-#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267
-#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1
-
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK				     0x00000F00U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT				             8U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH				             4U
-#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267
-#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2
-
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK				     0x000F0000U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT				            16U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH				             4U
-#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267
-#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3
-
-#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK				      0x0F000000U
-#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT				             24U
-#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH				              4U
-#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267
-#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0
-
-#define LPDDR4__DENALI_PI_268_READ_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_268_WRITE_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK				      0x0000000FU
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT				              0U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH				              4U
-#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268
-#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1
-
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK				      0x00000F00U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT				              8U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH				              4U
-#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268
-#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2
-
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK				      0x000F0000U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT				             16U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH				              4U
-#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268
-#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3
-
-#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK				 0x0F000000U
-#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT				        24U
-#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH				         4U
-#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268
-#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0
-
-#define LPDDR4__DENALI_PI_269_READ_MASK				              0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_269_WRITE_MASK				             0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK				 0x0000000FU
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT				         0U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH				         4U
-#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269
-#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1
-
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK				 0x00000F00U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT				         8U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH				         4U
-#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269
-#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2
-
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK				 0x000F0000U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT				        16U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH				         4U
-#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269
-#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3
-
-#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK               0xFF000000U
-#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT				      24U
-#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH				       8U
-#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269
-#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0
-
-#define LPDDR4__DENALI_PI_270_READ_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_270_WRITE_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK               0x000000FFU
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT				       0U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH				       8U
-#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270
-#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1
-
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK               0x0000FF00U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT				       8U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH				       8U
-#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270
-#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2
-
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK               0x00FF0000U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT				      16U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH				       8U
-#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270
-#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3
-
-#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK            0x0F000000U
-#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT				   24U
-#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270
-#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0
-
-#define LPDDR4__DENALI_PI_271_READ_MASK				              0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_271_WRITE_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT				    0U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0
-
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK            0x00000F00U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT				    8U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1
-
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK            0x000F0000U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT				   16U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1
-
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK            0x0F000000U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT				   24U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2
-
-#define LPDDR4__DENALI_PI_272_READ_MASK				              0x000F0F0FU
-#define LPDDR4__DENALI_PI_272_WRITE_MASK				             0x000F0F0FU
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK            0x0000000FU
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT				    0U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2
-
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK            0x00000F00U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT				    8U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272
-#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3
-
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK            0x000F0000U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT				   16U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH				    4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3
-
-#define LPDDR4__DENALI_PI_273_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_273_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT				0U
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH               16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0
-
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK        0xFFFF0000U
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT               16U
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH               16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0
-
-#define LPDDR4__DENALI_PI_274_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_274_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT				0U
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH               16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1
-
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK        0xFFFF0000U
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT               16U
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH               16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1
-
-#define LPDDR4__DENALI_PI_275_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_275_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT				         0U
-#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT				         8U
-#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT				        16U
-#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_276_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT				        0U
-#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT				        8U
-#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT				       16U
-#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_277_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_277_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT				         0U
-#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT				         8U
-#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT				        16U
-#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_278_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT				        0U
-#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT				        8U
-#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT				       16U
-#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_279_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_279_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT				         0U
-#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT				         8U
-#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT				        16U
-#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_280_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT				        0U
-#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT				        8U
-#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT				       16U
-#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT				       24U
-#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_281_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_281_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT				         0U
-#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT				         8U
-#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT				        16U
-#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT				       24U
-#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_282_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT				        0U
-#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT				        8U
-#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT				       16U
-#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT				       24U
-#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_283_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_283_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT				         0U
-#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT				         8U
-#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT				        16U
-#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT				       24U
-#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_284_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT				        0U
-#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT				        8U
-#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT				       16U
-#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT				       24U
-#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_285_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_285_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT				         0U
-#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT				         8U
-#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT				        16U
-#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT				       24U
-#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_286_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT				        0U
-#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT				        8U
-#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT				       16U
-#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT				       24U
-#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_287_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_287_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT				         0U
-#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT				         8U
-#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT				        16U
-#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT				       24U
-#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_288_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT				        0U
-#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT				        8U
-#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT				       16U
-#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT				       24U
-#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_289_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_289_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT				         0U
-#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT				         8U
-#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT				        16U
-#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT				       24U
-#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_290_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT				        0U
-#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT				        8U
-#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT				       16U
-#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT				       24U
-#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_291_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_291_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT				         0U
-#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT				         8U
-#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT				        16U
-#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT				       24U
-#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_292_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT				        0U
-#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT				        8U
-#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT				       16U
-#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT				       24U
-#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_293_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_293_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT				         0U
-#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT				         8U
-#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT				        16U
-#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT				       24U
-#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_294_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT				        0U
-#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT				        8U
-#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT				       16U
-#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT				       24U
-#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_295_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_295_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT				         0U
-#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT				         8U
-#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT				        16U
-#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT				       24U
-#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_296_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT				        0U
-#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT				        8U
-#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT				       16U
-#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT				       24U
-#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_297_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_297_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK				 0x000000FFU
-#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT				         0U
-#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH				         8U
-#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK				 0x0000FF00U
-#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT				         8U
-#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH				         8U
-#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT				        16U
-#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH				         8U
-#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT				       24U
-#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH				        8U
-#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_298_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK				0x000000FFU
-#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT				        0U
-#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH				        8U
-#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK				0x0000FF00U
-#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT				        8U
-#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH				        8U
-#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK				0x00FF0000U
-#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT				       16U
-#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH				        8U
-#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK				0xFF000000U
-#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT				       24U
-#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH				        8U
-#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_299_READ_MASK				              0x000007FFU
-#define LPDDR4__DENALI_PI_299_WRITE_MASK				             0x000007FFU
-#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK            0x000007FFU
-#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT				    0U
-#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH				   11U
-#define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299
-#define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF
-
-#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_sanity.h b/drivers/ram/k3-j721e/lpddr4_sanity.h
deleted file mode 100644
index 0f0fc2767c..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_sanity.h
+++ /dev/null
@@ -1,1165 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- *          api-generator: 12.02.13bb8d5
- *          Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-/**
- * This file contains sanity API functions. The purpose of sanity functions
- * is to check input parameters validity. They take the same parameters as
- * original API functions and return 0 on success or EINVAL on wrong parameter
- * value(s).
- */
-
-#ifndef LPDDR4_SANITY_H
-#define LPDDR4_SANITY_H
-
-#include <errno.h>
-#include <linux/types.h>
-#include "lpddr4_if.h"
-
-#define CDN_EOK             0U      /* no error */
-
-static inline uint32_t lpddr4_configsf(const lpddr4_config *obj);
-static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj);
-static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj);
-
-static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize);
-static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg);
-static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd);
-static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue);
-static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp);
-static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus);
-static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus);
-static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask);
-static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask);
-static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus);
-static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr);
-static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask);
-static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus);
-static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr);
-static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo);
-static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off);
-static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
-static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-#define lpddr4_probesf lpddr4_sanityfunction1
-#define lpddr4_initsf lpddr4_sanityfunction2
-#define lpddr4_startsf lpddr4_sanityfunction3
-#define lpddr4_readregsf lpddr4_sanityfunction4
-#define lpddr4_writeregsf lpddr4_sanityfunction5
-#define lpddr4_getmmrregistersf lpddr4_sanityfunction6
-#define lpddr4_setmmrregistersf lpddr4_sanityfunction7
-#define lpddr4_writectlconfigsf lpddr4_sanityfunction8
-#define lpddr4_writephyconfigsf lpddr4_sanityfunction8
-#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction8
-#define lpddr4_readctlconfigsf lpddr4_sanityfunction11
-#define lpddr4_readphyconfigsf lpddr4_sanityfunction11
-#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction11
-#define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
-#define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
-#define lpddr4_checkctlinterruptsf lpddr4_sanityfunction16
-#define lpddr4_ackctlinterruptsf lpddr4_sanityfunction17
-#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction18
-#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction18
-#define lpddr4_checkphyindepinterrupsf lpddr4_sanityfunction20
-#define lpddr4_ackphyindepinterruptsf lpddr4_sanityfunction21
-#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction22
-#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction23
-#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction23
-#define lpddr4_geteccenablesf lpddr4_sanityfunction25
-#define lpddr4_seteccenablesf lpddr4_sanityfunction26
-#define lpddr4_getreducmodesf lpddr4_sanityfunction27
-#define lpddr4_setreducmodesf lpddr4_sanityfunction28
-#define lpddr4_getdbireadmodesf lpddr4_sanityfunction29
-#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction29
-#define lpddr4_setdbimodesf lpddr4_sanityfunction31
-#define lpddr4_getrefreshratesf lpddr4_sanityfunction32
-#define lpddr4_setrefreshratesf lpddr4_sanityfunction32
-#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
-
-/**
- * Function to validate struct Config
- *
- * @param[in] obj pointer to struct to be verified
- * @returns 0 for valid
- * @returns EINVAL for invalid
- */
-static inline uint32_t lpddr4_configsf(const lpddr4_config *obj)
-{
-	uint32_t ret = 0;
-
-	if (obj == NULL)
-	{
-		ret = EINVAL;
-	}
-
-	return ret;
-}
-
-/**
- * Function to validate struct PrivateData
- *
- * @param[in] obj pointer to struct to be verified
- * @returns 0 for valid
- * @returns EINVAL for invalid
- */
-static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj)
-{
-	uint32_t ret = 0;
-
-	if (obj == NULL)
-	{
-		ret = EINVAL;
-	}
-
-	return ret;
-}
-
-/**
- * Function to validate struct RegInitData
- *
- * @param[in] obj pointer to struct to be verified
- * @returns 0 for valid
- * @returns EINVAL for invalid
- */
-static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj)
-{
-	uint32_t ret = 0;
-
-	if (obj == NULL)
-	{
-		ret = EINVAL;
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] config Driver/hardware configuration required.
- * @param[out] configSize Size of memory allocations required.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (configsize == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_configsf(config) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cfg Specifies driver/hardware configuration.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_configsf(cfg) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[out] regValue Register value read
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (regvalue == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(cpp != LPDDR4_CTL_REGS) &&
-		(cpp != LPDDR4_PHY_REGS) &&
-		(cpp != LPDDR4_PHY_INDEP_REGS)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(cpp != LPDDR4_CTL_REGS) &&
-		(cpp != LPDDR4_PHY_REGS) &&
-		(cpp != LPDDR4_PHY_INDEP_REGS)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
- * @param[out] mmrStatus Status of mode register read(mrr) instruction.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mmrvalue == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (mmrstatus == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mrwStatus Status of mode register write(mrw) instruction.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mrwstatus == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_reginitdatasf(regvalues) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (regvalues == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mask == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mask == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (irqstatus == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(intr != LPDDR4_RESET_DONE) &&
-		(intr != LPDDR4_BUS_ACCESS_ERROR) &&
-		(intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) &&
-		(intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) &&
-		(intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) &&
-		(intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) &&
-		(intr != LPDDR4_ECC_SCRUB_DONE) &&
-		(intr != LPDDR4_ECC_SCRUB_ERROR) &&
-		(intr != LPDDR4_PORT_COMMAND_ERROR) &&
-		(intr != LPDDR4_MC_INIT_DONE) &&
-		(intr != LPDDR4_LP_DONE) &&
-		(intr != LPDDR4_BIST_DONE) &&
-		(intr != LPDDR4_WRAP_ERROR) &&
-		(intr != LPDDR4_INVALID_BURST_ERROR) &&
-		(intr != LPDDR4_RDLVL_ERROR) &&
-		(intr != LPDDR4_RDLVL_GATE_ERROR) &&
-		(intr != LPDDR4_WRLVL_ERROR) &&
-		(intr != LPDDR4_CA_TRAINING_ERROR) &&
-		(intr != LPDDR4_DFI_UPDATE_ERROR) &&
-		(intr != LPDDR4_MRR_ERROR) &&
-		(intr != LPDDR4_PHY_MASTER_ERROR) &&
-		(intr != LPDDR4_WRLVL_REQ) &&
-		(intr != LPDDR4_RDLVL_REQ) &&
-		(intr != LPDDR4_RDLVL_GATE_REQ) &&
-		(intr != LPDDR4_CA_TRAINING_REQ) &&
-		(intr != LPDDR4_LEVELING_DONE) &&
-		(intr != LPDDR4_PHY_ERROR) &&
-		(intr != LPDDR4_MR_READ_DONE) &&
-		(intr != LPDDR4_TEMP_CHANGE) &&
-		(intr != LPDDR4_TEMP_ALERT) &&
-		(intr != LPDDR4_SW_DQS_COMPLETE) &&
-		(intr != LPDDR4_DQS_OSC_BV_UPDATED) &&
-		(intr != LPDDR4_DQS_OSC_OVERFLOW) &&
-		(intr != LPDDR4_DQS_OSC_VAR_OUT) &&
-		(intr != LPDDR4_MR_WRITE_DONE) &&
-		(intr != LPDDR4_INHIBIT_DRAM_DONE) &&
-		(intr != LPDDR4_DFI_INIT_STATE) &&
-		(intr != LPDDR4_DLL_RESYNC_DONE) &&
-		(intr != LPDDR4_TDFI_TO) &&
-		(intr != LPDDR4_DFS_DONE) &&
-		(intr != LPDDR4_DFS_STATUS) &&
-		(intr != LPDDR4_REFRESH_STATUS) &&
-		(intr != LPDDR4_ZQ_STATUS) &&
-		(intr != LPDDR4_SW_REQ_MODE) &&
-		(intr != LPDDR4_LOR_BITS)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(intr != LPDDR4_RESET_DONE) &&
-		(intr != LPDDR4_BUS_ACCESS_ERROR) &&
-		(intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) &&
-		(intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) &&
-		(intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) &&
-		(intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) &&
-		(intr != LPDDR4_ECC_SCRUB_DONE) &&
-		(intr != LPDDR4_ECC_SCRUB_ERROR) &&
-		(intr != LPDDR4_PORT_COMMAND_ERROR) &&
-		(intr != LPDDR4_MC_INIT_DONE) &&
-		(intr != LPDDR4_LP_DONE) &&
-		(intr != LPDDR4_BIST_DONE) &&
-		(intr != LPDDR4_WRAP_ERROR) &&
-		(intr != LPDDR4_INVALID_BURST_ERROR) &&
-		(intr != LPDDR4_RDLVL_ERROR) &&
-		(intr != LPDDR4_RDLVL_GATE_ERROR) &&
-		(intr != LPDDR4_WRLVL_ERROR) &&
-		(intr != LPDDR4_CA_TRAINING_ERROR) &&
-		(intr != LPDDR4_DFI_UPDATE_ERROR) &&
-		(intr != LPDDR4_MRR_ERROR) &&
-		(intr != LPDDR4_PHY_MASTER_ERROR) &&
-		(intr != LPDDR4_WRLVL_REQ) &&
-		(intr != LPDDR4_RDLVL_REQ) &&
-		(intr != LPDDR4_RDLVL_GATE_REQ) &&
-		(intr != LPDDR4_CA_TRAINING_REQ) &&
-		(intr != LPDDR4_LEVELING_DONE) &&
-		(intr != LPDDR4_PHY_ERROR) &&
-		(intr != LPDDR4_MR_READ_DONE) &&
-		(intr != LPDDR4_TEMP_CHANGE) &&
-		(intr != LPDDR4_TEMP_ALERT) &&
-		(intr != LPDDR4_SW_DQS_COMPLETE) &&
-		(intr != LPDDR4_DQS_OSC_BV_UPDATED) &&
-		(intr != LPDDR4_DQS_OSC_OVERFLOW) &&
-		(intr != LPDDR4_DQS_OSC_VAR_OUT) &&
-		(intr != LPDDR4_MR_WRITE_DONE) &&
-		(intr != LPDDR4_INHIBIT_DRAM_DONE) &&
-		(intr != LPDDR4_DFI_INIT_STATE) &&
-		(intr != LPDDR4_DLL_RESYNC_DONE) &&
-		(intr != LPDDR4_TDFI_TO) &&
-		(intr != LPDDR4_DFS_DONE) &&
-		(intr != LPDDR4_DFS_STATUS) &&
-		(intr != LPDDR4_REFRESH_STATUS) &&
-		(intr != LPDDR4_ZQ_STATUS) &&
-		(intr != LPDDR4_SW_REQ_MODE) &&
-		(intr != LPDDR4_LOR_BITS)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mask == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (irqstatus == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
-		(intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] debugInfo status
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (debuginfo == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[out] cycles Timing value(in cycles)
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (lpiwakeupparam == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (fspnum == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (cycles == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
-		(*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
-		(*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
-		(*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) &&
-		(*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
-		(*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
-		(*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
-		)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(*fspnum != LPDDR4_FSP_0) &&
-		(*fspnum != LPDDR4_FSP_1) &&
-		(*fspnum != LPDDR4_FSP_2)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] eccParam ECC parameter setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (eccparam == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] eccParam ECC control parameter setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (eccparam == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(*eccparam != LPDDR4_ECC_DISABLED) &&
-		(*eccparam != LPDDR4_ECC_ENABLED) &&
-		(*eccparam != LPDDR4_ECC_ERR_DETECT) &&
-		(*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mode Half Datapath setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mode == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode Half Datapath setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mode == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(*mode != LPDDR4_REDUC_ON) &&
-		(*mode != LPDDR4_REDUC_OFF)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI read value
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (on_off == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode status
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (mode == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(*mode != LPDDR4_DBI_RD_ON) &&
-		(*mode != LPDDR4_DBI_RD_OFF) &&
-		(*mode != LPDDR4_DBI_WR_ON) &&
-		(*mode != LPDDR4_DBI_WR_OFF)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[out] cycles Refresh rate (in cycles)
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles)
-{
-	/* Declaring return variable */
-	uint32_t ret = 0;
-
-	if (fspnum == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (cycles == NULL)
-	{
-		ret = EINVAL;
-	}
-	else if (lpddr4_privatedatasf(pd) == EINVAL)
-	{
-		ret = EINVAL;
-	}
-	else if (
-		(*fspnum != LPDDR4_FSP_0) &&
-		(*fspnum != LPDDR4_FSP_1) &&
-		(*fspnum != LPDDR4_FSP_2)
-		)
-	{
-		ret = EINVAL;
-	}
-	else
-	{
-		/*
-		 * All 'if ... else if' constructs shall be terminated with an 'else' statement
-		 * (MISRA2012-RULE-15_7-3)
-		 */
-	}
-
-	return ret;
-}
-
-#endif  /* LPDDR4_SANITY_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_structs_if.h b/drivers/ram/k3-j721e/lpddr4_structs_if.h
deleted file mode 100644
index dc6dd3570e..0000000000
--- a/drivers/ram/k3-j721e/lpddr4_structs_if.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- *          api-generator: 12.02.13bb8d5
- *          Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-#ifndef LPDDR4_STRUCTS_IF_H
-#define LPDDR4_STRUCTS_IF_H
-
-#include <linux/types.h>
-#include "lpddr4_if.h"
-
-/** @defgroup DataStructure Dynamic Data Structures
- *  This section defines the data structures used by the driver to provide
- *  hardware information, modification and dynamic operation of the driver.
- *  These data structures are defined in the header file of the core driver
- *  and utilized by the API.
- *  @{
- */
-
-/**********************************************************************
-* Structures and unions
-**********************************************************************/
-/**
- * Configuration of device.
- * Object of this type is used for probe and init functions.
- */
-struct lpddr4_config_s
-{
-	/** Base address of controller registers */
-	struct lpddr4_ctlregs_s* ctlbase;
-	/** Information/warning handler */
-	lpddr4_infocallback infohandler;
-	/** Controller interrupt handler */
-	lpddr4_ctlcallback ctlinterrupthandler;
-	/** PHY Independent Module interrupt handler */
-	lpddr4_phyindepcallback phyindepinterrupthandler;
-};
-
-/**
- * Structure contains private data for Core Driver that should not be used by
- * upper layers. This is not a part of API and manipulating of those data may cause
- * unpredictable behavior of Core Driver.
- */
-struct lpddr4_privatedata_s
-{
-	/** Base address of controller registers */
-	struct lpddr4_ctlregs_s* ctlbase;
-	/** Information/warning handler */
-	lpddr4_infocallback infohandler;
-	/** Controller interrupt handler */
-	lpddr4_ctlcallback ctlinterrupthandler;
-	/** PHY Independent Module interrupt handler */
-	lpddr4_phyindepcallback phyindepinterrupthandler;
-};
-
-/** Structure to contain debug information reported by the driver. */
-struct lpddr4_debuginfo_s
-{
-	/** PLL Lock error. */
-	bool pllerror;
-	/** I/O calibration error. */
-	bool iocaliberror;
-	/** RX offset error. */
-	bool rxoffseterror;
-	/** CA training error. */
-	bool catraingerror;
-	/** Write levelling error. */
-	bool wrlvlerror;
-	/** Gate Level error. */
-	bool gatelvlerror;
-	/** Read Level error. */
-	bool readlvlerror;
-	/** Write DQ training error. */
-	bool dqtrainingerror;
-};
-
-/** Frequency Set Point mode register values */
-struct lpddr4_fspmoderegs_s
-{
-	/** MR1 register data for the FSP. */
-	uint8_t mr1data_fn[LPDDR4_MAX_CS];
-	/** MR2 register data for the FSP. */
-	uint8_t mr2data_fn[LPDDR4_MAX_CS];
-	/** MR3 register data for the FSP. */
-	uint8_t mr3data_fn[LPDDR4_MAX_CS];
-	/** MR11 register data for the FSP. */
-	uint8_t mr11data_fn[LPDDR4_MAX_CS];
-	/** MR12 register data for the FSP. */
-	uint8_t mr12data_fn[LPDDR4_MAX_CS];
-	/** MR13 register data for the FSP. */
-	uint8_t mr13data_fn[LPDDR4_MAX_CS];
-	/** MR14 register data for the FSP. */
-	uint8_t mr14data_fn[LPDDR4_MAX_CS];
-	/** MR22 register data for the selected frequency. */
-	uint8_t mr22data_fn[LPDDR4_MAX_CS];
-};
-
-/** Structure to hold data set to initalise registers. */
-struct lpddr4_reginitdata_s
-{
-	/** Register initialisation data for the Controller. */
-	uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT];
-	/** Should be set to true, if the corresponding denaliCtlReg element has been updated. */
-	bool updatectlreg[LPDDR4_CTL_REG_COUNT];
-	/** Register initialisation data for PHY independent module. */
-	uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
-	/** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */
-	bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
-	/** Register initialisation data for the PHY. */
-	uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT];
-	/** Should be set to true, if the corresponding denaliPhyReg element has been updated. */
-	bool updatephyreg[LPDDR4_PHY_REG_COUNT];
-};
-
-#endif  /* LPDDR4_STRUCTS_IF_H */
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index ecc3278cb4..9abed7d490 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -13,6 +13,7 @@
 #define AM65X			0xbb5a
 #define J721E			0xbb64
 #define J7200			0xbb6d
+#define AM64X			0xbb38
 
 #define REV_SR1_0		0
 #define REV_SR2_0		1
@@ -44,6 +45,9 @@ static const char *get_family_string(u32 idreg)
 	case J7200:
 		family = "J7200";
 		break;
+	case AM64X:
+		family = "AM64X";
+		break;
 	default:
 		family = "Unknown Silicon";
 	};
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index c5099ad084..b5a5c9da98 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -23,6 +23,7 @@
 #include <linux/err.h>
 #include <linux/soc/ti/k3-navss-ringacc.h>
 #include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/soc/ti/cppi5.h>
 
 #define set_bit(bit, bitmap)	__set_bit(bit, bitmap)
 #define clear_bit(bit, bitmap)	__clear_bit(bit, bitmap)
@@ -56,6 +57,7 @@ static	u32 ringacc_readl(void __iomem *reg)
 }
 
 #define KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK		GENMASK(19, 0)
+#define K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK		GENMASK(15, 0)
 
 /**
  * struct k3_nav_ring_rt_regs -  The RA Control/Status Registers region
@@ -71,6 +73,13 @@ struct k3_nav_ring_rt_regs {
 };
 
 #define KNAV_RINGACC_RT_REGS_STEP	0x1000
+#define K3_DMARING_RING_RT_REGS_STEP			0x2000
+#define K3_DMARING_RING_RT_REGS_REVERSE_OFS		0x1000
+#define KNAV_RINGACC_RT_OCC_MASK		GENMASK(20, 0)
+#define K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE		BIT(31)
+#define K3_DMARING_RING_RT_DB_ENTRY_MASK		GENMASK(7, 0)
+#define K3_DMARING_RING_RT_DB_TDOWN_ACK		BIT(31)
+
 
 /**
  * struct k3_nav_ring_fifo_regs -  The Ring Accelerator Queues Registers region
@@ -82,36 +91,6 @@ struct k3_nav_ring_fifo_regs {
 	u32	peek_tail_data[128];	/* Ring Peek Tail Entry Data Regs */
 };
 
-/**
- * struct k3_ringacc_proxy_gcfg_regs - RA Proxy Global Config MMIO Region
- */
-struct k3_ringacc_proxy_gcfg_regs {
-	u32	revision;	/* Revision Register */
-	u32	config;		/* Config Register */
-};
-
-#define K3_RINGACC_PROXY_CFG_THREADS_MASK		GENMASK(15, 0)
-
-/**
- * struct k3_ringacc_proxy_target_regs -  RA Proxy Datapath MMIO Region
- */
-struct k3_ringacc_proxy_target_regs {
-	u32	control;	/* Proxy Control Register */
-	u32	status;		/* Proxy Status Register */
-	u8	resv_512[504];
-	u32	data[128];	/* Proxy Data Register */
-};
-
-#define K3_RINGACC_PROXY_TARGET_STEP	0x1000
-#define K3_RINGACC_PROXY_NOT_USED	(-1)
-
-enum k3_ringacc_proxy_access_mode {
-	PROXY_ACCESS_MODE_HEAD = 0,
-	PROXY_ACCESS_MODE_TAIL = 1,
-	PROXY_ACCESS_MODE_PEEK_HEAD = 2,
-	PROXY_ACCESS_MODE_PEEK_TAIL = 3,
-};
-
 #define KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES  (512U)
 #define KNAV_RINGACC_FIFO_REGS_STEP	0x1000
 #define KNAV_RINGACC_MAX_DB_RING_CNT    (127U)
@@ -147,7 +126,6 @@ struct k3_nav_ring_state {
  *
  * @rt - Ring control/status registers
  * @fifos - Ring queues registers
- * @proxy - Ring Proxy Datapath registers
  * @ring_mem_dma - Ring buffer dma address
  * @ring_mem_virt - Ring buffer virt address
  * @ops - Ring operations
@@ -158,12 +136,10 @@ struct k3_nav_ring_state {
  * @ring_id - Ring Id
  * @parent - Pointer on struct @k3_nav_ringacc
  * @use_count - Use count for shared rings
- * @proxy_id - RA Ring Proxy Id (only if @K3_NAV_RINGACC_RING_USE_PROXY)
  */
 struct k3_nav_ring {
 	struct k3_nav_ring_rt_regs __iomem *rt;
 	struct k3_nav_ring_fifo_regs __iomem *fifos;
-	struct k3_ringacc_proxy_target_regs  __iomem *proxy;
 	dma_addr_t	ring_mem_dma;
 	void		*ring_mem_virt;
 	struct k3_nav_ring_ops *ops;
@@ -173,11 +149,11 @@ struct k3_nav_ring {
 	u32		flags;
 #define KNAV_RING_FLAG_BUSY	BIT(1)
 #define K3_NAV_RING_FLAG_SHARED	BIT(2)
+#define K3_NAV_RING_FLAG_REVERSE BIT(3)
 	struct k3_nav_ring_state state;
 	u32		ring_id;
 	struct k3_nav_ringacc	*parent;
 	u32		use_count;
-	int		proxy_id;
 };
 
 struct k3_nav_ringacc_ops {
@@ -188,8 +164,6 @@ struct k3_nav_ringacc_ops {
  * struct k3_nav_ringacc - Rings accelerator descriptor
  *
  * @dev - pointer on RA device
- * @proxy_gcfg - RA proxy global config registers
- * @proxy_target_base - RA proxy datapath region
  * @num_rings - number of ring in RA
  * @rm_gp_range - general purpose rings range from tisci
  * @dma_ring_reset_quirk - DMA reset w/a enable
@@ -200,17 +174,15 @@ struct k3_nav_ringacc_ops {
  * @tisci_ring_ops - ti-sci rings ops
  * @tisci_dev_id - ti-sci device id
  * @ops: SoC specific ringacc operation
+ * @dual_ring: indicate k3_dmaring dual ring support
  */
 struct k3_nav_ringacc {
 	struct udevice *dev;
-	struct k3_ringacc_proxy_gcfg_regs __iomem *proxy_gcfg;
-	void __iomem *proxy_target_base;
 	u32 num_rings; /* number of rings in Ringacc module */
 	unsigned long *rings_inuse;
 	struct ti_sci_resource *rm_gp_range;
 	bool dma_ring_reset_quirk;
 	u32 num_proxies;
-	unsigned long *proxy_inuse;
 
 	struct k3_nav_ring *rings;
 	struct list_head list;
@@ -220,12 +192,22 @@ struct k3_nav_ringacc {
 	u32  tisci_dev_id;
 
 	const struct k3_nav_ringacc_ops *ops;
+	bool dual_ring;
 };
 
-static long k3_nav_ringacc_ring_get_fifo_pos(struct k3_nav_ring *ring)
+static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
+{
+	return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
+}
+
+static void k3_nav_ringacc_ring_update_occ(struct k3_nav_ring *ring)
 {
-	return KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES -
-	       (4 << ring->elm_size);
+	u32 val;
+
+	val = readl(&ring->rt->occ);
+
+	ring->state.occ = val & KNAV_RINGACC_RT_OCC_MASK;
+	ring->state.tdown_complete = !!(val & K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE);
 }
 
 static void *k3_nav_ringacc_get_elm_addr(struct k3_nav_ring *ring, u32 idx)
@@ -235,38 +217,21 @@ static void *k3_nav_ringacc_get_elm_addr(struct k3_nav_ring *ring, u32 idx)
 
 static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem);
 static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem);
 
 static struct k3_nav_ring_ops k3_nav_mode_ring_ops = {
 		.push_tail = k3_nav_ringacc_ring_push_mem,
 		.pop_head = k3_nav_ringacc_ring_pop_mem,
 };
 
-static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
-					    void *elem);
-static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring,
-					   void *elem);
-
-static struct k3_nav_ring_ops k3_nav_mode_msg_ops = {
-		.push_tail = k3_nav_ringacc_ring_push_io,
-		.push_head = k3_nav_ringacc_ring_push_head_io,
-		.pop_tail = k3_nav_ringacc_ring_pop_tail_io,
-		.pop_head = k3_nav_ringacc_ring_pop_io,
+static struct k3_nav_ring_ops k3_dmaring_fwd_ring_ops = {
+		.push_tail = k3_nav_ringacc_ring_push_mem,
+		.pop_head = k3_dmaring_ring_fwd_pop_mem,
 };
 
-static int k3_ringacc_ring_push_head_proxy(struct k3_nav_ring *ring,
-					   void *elem);
-static int k3_ringacc_ring_push_tail_proxy(struct k3_nav_ring *ring,
-					   void *elem);
-static int k3_ringacc_ring_pop_head_proxy(struct k3_nav_ring *ring, void *elem);
-static int k3_ringacc_ring_pop_tail_proxy(struct k3_nav_ring *ring, void *elem);
-
-static struct k3_nav_ring_ops k3_nav_mode_proxy_ops = {
-		.push_tail = k3_ringacc_ring_push_tail_proxy,
-		.push_head = k3_ringacc_ring_push_head_proxy,
-		.pop_tail = k3_ringacc_ring_pop_tail_proxy,
-		.pop_head = k3_ringacc_ring_pop_head_proxy,
+static struct k3_nav_ring_ops k3_dmaring_reverse_ring_ops = {
+		.pop_head = k3_dmaring_ring_reverse_pop_mem,
 };
 
 struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc)
@@ -275,10 +240,8 @@ struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc)
 }
 
 struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
-						int id, u32 flags)
+						int id)
 {
-	int proxy_id = K3_RINGACC_PROXY_NOT_USED;
-
 	if (id == K3_NAV_RINGACC_RING_ID_ANY) {
 		/* Request for any general purpose ring */
 		struct ti_sci_resource_desc *gp_rings =
@@ -300,24 +263,10 @@ struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
 	else if (ringacc->rings[id].flags & K3_NAV_RING_FLAG_SHARED)
 		goto out;
 
-	if (flags & K3_NAV_RINGACC_RING_USE_PROXY) {
-		proxy_id = find_next_zero_bit(ringacc->proxy_inuse,
-					      ringacc->num_proxies, 0);
-		if (proxy_id == ringacc->num_proxies)
-			goto error;
-	}
-
 	if (!try_module_get(ringacc->dev->driver->owner))
 		goto error;
 
-	if (proxy_id != K3_RINGACC_PROXY_NOT_USED) {
-		set_bit(proxy_id, ringacc->proxy_inuse);
-		ringacc->rings[id].proxy_id = proxy_id;
-		pr_debug("Giving ring#%d proxy#%d\n",
-			 id, proxy_id);
-	} else {
-		pr_debug("Giving ring#%d\n", id);
-	}
+	pr_debug("Giving ring#%d\n", id);
 
 	set_bit(id, ringacc->rings_inuse);
 out:
@@ -328,6 +277,27 @@ error:
 	return NULL;
 }
 
+static int k3_dmaring_ring_request_rings_pair(struct k3_nav_ringacc *ringacc,
+					      int fwd_id, int compl_id,
+					      struct k3_nav_ring **fwd_ring,
+					      struct k3_nav_ring **compl_ring)
+{
+	/* k3_dmaring: fwd_id == compl_id, so we ignore compl_id */
+	if (fwd_id < 0)
+		return -EINVAL;
+
+	if (test_bit(fwd_id, ringacc->rings_inuse))
+		return -EBUSY;
+
+	*fwd_ring = &ringacc->rings[fwd_id];
+	*compl_ring = &ringacc->rings[fwd_id + ringacc->num_rings];
+	set_bit(fwd_id, ringacc->rings_inuse);
+	ringacc->rings[fwd_id].use_count++;
+	dev_dbg(ringacc->dev, "Giving ring#%d\n", fwd_id);
+
+	return 0;
+}
+
 int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
 				      int fwd_id, int compl_id,
 				      struct k3_nav_ring **fwd_ring,
@@ -338,11 +308,15 @@ int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
 	if (!fwd_ring || !compl_ring)
 		return -EINVAL;
 
-	*fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id, 0);
+	if (ringacc->dual_ring)
+		return k3_dmaring_ring_request_rings_pair(ringacc, fwd_id, compl_id,
+						    fwd_ring, compl_ring);
+
+	*fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id);
 	if (!(*fwd_ring))
 		return -ENODEV;
 
-	*compl_ring = k3_nav_ringacc_request_ring(ringacc, compl_id, 0);
+	*compl_ring = k3_nav_ringacc_request_ring(ringacc, compl_id);
 	if (!(*compl_ring)) {
 		k3_nav_ringacc_ring_free(*fwd_ring);
 		ret = -ENODEV;
@@ -493,6 +467,13 @@ int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring)
 
 	ringacc = ring->parent;
 
+	/*
+	 * k3_dmaring: rings shared memory and configuration, only forward ring is
+	 * configured and reverse ring considered as slave.
+	 */
+	if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
+		return 0;
+
 	pr_debug("%s flags: 0x%08x\n", __func__, ring->flags);
 
 	if (!test_bit(ring->ring_id, ringacc->rings_inuse))
@@ -511,11 +492,6 @@ int k3_nav_ringacc_ring_free(struct k3_nav_ring *ring)
 			  ring->ring_mem_virt, ring->ring_mem_dma);
 	ring->flags &= ~KNAV_RING_FLAG_BUSY;
 	ring->ops = NULL;
-	if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED) {
-		clear_bit(ring->proxy_id, ringacc->proxy_inuse);
-		ring->proxy = NULL;
-		ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
-	}
 
 no_init:
 	clear_bit(ring->ring_id, ringacc->rings_inuse);
@@ -562,6 +538,75 @@ static int k3_nav_ringacc_ring_cfg_sci(struct k3_nav_ring *ring)
 	return ret;
 }
 
+static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg)
+{
+	struct k3_nav_ringacc *ringacc;
+	struct k3_nav_ring *reverse_ring;
+	int ret = 0;
+
+	if (cfg->elm_size != K3_NAV_RINGACC_RING_ELSIZE_8 ||
+	    cfg->mode != K3_NAV_RINGACC_RING_MODE_RING ||
+	    cfg->size & ~K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK)
+		return -EINVAL;
+
+	ringacc = ring->parent;
+
+	/*
+	 * k3_dmaring: rings shared memory and configuration, only forward ring is
+	 * configured and reverse ring considered as slave.
+	 */
+	if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
+		return 0;
+
+	if (!test_bit(ring->ring_id, ringacc->rings_inuse))
+		return -EINVAL;
+
+	ring->size = cfg->size;
+	ring->elm_size = cfg->elm_size;
+	ring->mode = cfg->mode;
+	memset(&ring->state, 0, sizeof(ring->state));
+
+	ring->ops = &k3_dmaring_fwd_ring_ops;
+
+	ring->ring_mem_virt =
+		dma_alloc_coherent(ring->size * (4 << ring->elm_size),
+				   (unsigned long *)&ring->ring_mem_dma);
+	if (!ring->ring_mem_virt) {
+		dev_err(ringacc->dev, "Failed to alloc ring mem\n");
+		ret = -ENOMEM;
+		goto err_free_ops;
+	}
+
+	ret = k3_nav_ringacc_ring_cfg_sci(ring);
+	if (ret)
+		goto err_free_mem;
+
+	ring->flags |= KNAV_RING_FLAG_BUSY;
+
+	/* k3_dmaring: configure reverse ring */
+	reverse_ring = &ringacc->rings[ring->ring_id + ringacc->num_rings];
+	reverse_ring->size = cfg->size;
+	reverse_ring->elm_size = cfg->elm_size;
+	reverse_ring->mode = cfg->mode;
+	memset(&reverse_ring->state, 0, sizeof(reverse_ring->state));
+	reverse_ring->ops = &k3_dmaring_reverse_ring_ops;
+
+	reverse_ring->ring_mem_virt = ring->ring_mem_virt;
+	reverse_ring->ring_mem_dma = ring->ring_mem_dma;
+	reverse_ring->flags |= KNAV_RING_FLAG_BUSY;
+
+	return 0;
+
+err_free_mem:
+	dma_free_coherent(ringacc->dev,
+			  ring->size * (4 << ring->elm_size),
+			  ring->ring_mem_virt,
+			  ring->ring_mem_dma);
+err_free_ops:
+	ring->ops = NULL;
+	return ret;
+}
+
 int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
 			    struct k3_nav_ring_cfg *cfg)
 {
@@ -570,6 +615,10 @@ int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
 
 	if (!ring || !cfg)
 		return -EINVAL;
+
+	if (ringacc->dual_ring)
+		return k3_dmaring_ring_cfg(ring, cfg);
+
 	if (cfg->elm_size > K3_NAV_RINGACC_RING_ELSIZE_256 ||
 	    cfg->mode > K3_NAV_RINGACC_RING_MODE_QM ||
 	    cfg->size & ~KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK ||
@@ -584,32 +633,14 @@ int k3_nav_ringacc_ring_cfg(struct k3_nav_ring *ring,
 	ring->mode = cfg->mode;
 	memset(&ring->state, 0, sizeof(ring->state));
 
-	if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED)
-		ring->proxy = ringacc->proxy_target_base +
-			      ring->proxy_id * K3_RINGACC_PROXY_TARGET_STEP;
-
 	switch (ring->mode) {
 	case K3_NAV_RINGACC_RING_MODE_RING:
 		ring->ops = &k3_nav_mode_ring_ops;
 		break;
-	case K3_NAV_RINGACC_RING_MODE_QM:
-		/*
-		 * In Queue mode elm_size can be 8 only and each operation
-		 * uses 2 element slots
-		 */
-		if (cfg->elm_size != K3_NAV_RINGACC_RING_ELSIZE_8 ||
-		    cfg->size % 2)
-			goto err_free_proxy;
-	case K3_NAV_RINGACC_RING_MODE_MESSAGE:
-		if (ring->proxy)
-			ring->ops = &k3_nav_mode_proxy_ops;
-		else
-			ring->ops = &k3_nav_mode_msg_ops;
-		break;
 	default:
 		ring->ops = NULL;
 		ret = -EINVAL;
-		goto err_free_proxy;
+		goto err_free_ops;
 	};
 
 	ring->ring_mem_virt =
@@ -640,8 +671,6 @@ err_free_mem:
 			  ring->ring_mem_dma);
 err_free_ops:
 	ring->ops = NULL;
-err_free_proxy:
-	ring->proxy = NULL;
 	return ret;
 }
 
@@ -686,159 +715,63 @@ enum k3_ringacc_access_mode {
 	K3_RINGACC_ACCESS_MODE_PEEK_TAIL,
 };
 
-static int k3_ringacc_ring_cfg_proxy(struct k3_nav_ring *ring,
-				     enum k3_ringacc_proxy_access_mode mode)
+static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem)
 {
-	u32 val;
-
-	val = ring->ring_id;
-	val |= mode << 16;
-	val |= ring->elm_size << 24;
-	ringacc_writel(val, &ring->proxy->control);
-	return 0;
-}
-
-static int k3_nav_ringacc_ring_access_proxy(
-			struct k3_nav_ring *ring, void *elem,
-			enum k3_ringacc_access_mode access_mode)
-{
-	void __iomem *ptr;
-
-	ptr = (void __iomem *)&ring->proxy->data;
-
-	switch (access_mode) {
-	case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
-	case K3_RINGACC_ACCESS_MODE_POP_HEAD:
-		k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_HEAD);
-		break;
-	case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
-	case K3_RINGACC_ACCESS_MODE_POP_TAIL:
-		k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_TAIL);
-		break;
-	default:
-		return -EINVAL;
-	}
+	void *elem_ptr;
+	u32 elem_idx;
+
+	/*
+	 * k3_dmaring: forward ring is always tied DMA channel and HW does not
+	 * maintain any state data required for POP operation and its unknown
+	 * how much elements were consumed by HW. So, to actually
+	 * do POP, the read pointer has to be recalculated every time.
+	 */
+	ring->state.occ = k3_nav_ringacc_ring_read_occ(ring);
+	if (ring->state.windex >= ring->state.occ)
+		elem_idx = ring->state.windex - ring->state.occ;
+	else
+		elem_idx = ring->size - (ring->state.occ - ring->state.windex);
+
+	elem_ptr = k3_nav_ringacc_get_elm_addr(ring, elem_idx);
+	invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
+				ALIGN((unsigned long)ring->ring_mem_virt +
+				      ring->size * (4 << ring->elm_size),
+				      ARCH_DMA_MINALIGN));
 
-	ptr += k3_nav_ringacc_ring_get_fifo_pos(ring);
+	memcpy(elem, elem_ptr, (4 << ring->elm_size));
 
-	switch (access_mode) {
-	case K3_RINGACC_ACCESS_MODE_POP_HEAD:
-	case K3_RINGACC_ACCESS_MODE_POP_TAIL:
-		pr_debug("proxy:memcpy_fromio(x): --> ptr(%p), mode:%d\n",
-			 ptr, access_mode);
-		memcpy_fromio(elem, ptr, (4 << ring->elm_size));
-		ring->state.occ--;
-		break;
-	case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
-	case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
-		pr_debug("proxy:memcpy_toio(x): --> ptr(%p), mode:%d\n",
-			 ptr, access_mode);
-		memcpy_toio(ptr, elem, (4 << ring->elm_size));
-		ring->state.free--;
-		break;
-	default:
-		return -EINVAL;
-	}
+	ring->state.occ--;
+	writel(-1, &ring->rt->db);
 
-	pr_debug("proxy: free%d occ%d\n",
-		 ring->state.free, ring->state.occ);
+	dev_dbg(ring->parent->dev, "%s: occ%d Windex%d Rindex%d pos_ptr%px\n",
+		__func__, ring->state.occ, ring->state.windex, elem_idx,
+		elem_ptr);
 	return 0;
 }
 
-static int k3_ringacc_ring_push_head_proxy(struct k3_nav_ring *ring, void *elem)
+static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem)
 {
-	return k3_nav_ringacc_ring_access_proxy(
-			ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
-}
-
-static int k3_ringacc_ring_push_tail_proxy(struct k3_nav_ring *ring, void *elem)
-{
-	return k3_nav_ringacc_ring_access_proxy(
-			ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
-}
-
-static int k3_ringacc_ring_pop_head_proxy(struct k3_nav_ring *ring, void *elem)
-{
-	return k3_nav_ringacc_ring_access_proxy(
-			ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_ringacc_ring_pop_tail_proxy(struct k3_nav_ring *ring, void *elem)
-{
-	return k3_nav_ringacc_ring_access_proxy(
-			ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_nav_ringacc_ring_access_io(
-		struct k3_nav_ring *ring, void *elem,
-		enum k3_ringacc_access_mode access_mode)
-{
-	void __iomem *ptr;
+	void *elem_ptr;
 
-	switch (access_mode) {
-	case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
-	case K3_RINGACC_ACCESS_MODE_POP_HEAD:
-		ptr = (void __iomem *)&ring->fifos->head_data;
-		break;
-	case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
-	case K3_RINGACC_ACCESS_MODE_POP_TAIL:
-		ptr = (void __iomem *)&ring->fifos->tail_data;
-		break;
-	default:
-		return -EINVAL;
-	}
+	elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->state.rindex);
 
-	ptr += k3_nav_ringacc_ring_get_fifo_pos(ring);
+	if (ring->state.occ) {
+		invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
+					ALIGN((unsigned long)ring->ring_mem_virt +
+					ring->size * (4 << ring->elm_size),
+					ARCH_DMA_MINALIGN));
 
-	switch (access_mode) {
-	case K3_RINGACC_ACCESS_MODE_POP_HEAD:
-	case K3_RINGACC_ACCESS_MODE_POP_TAIL:
-		pr_debug("memcpy_fromio(x): --> ptr(%p), mode:%d\n",
-			 ptr, access_mode);
-		memcpy_fromio(elem, ptr, (4 << ring->elm_size));
+		memcpy(elem, elem_ptr, (4 << ring->elm_size));
+		ring->state.rindex = (ring->state.rindex + 1) % ring->size;
 		ring->state.occ--;
-		break;
-	case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
-	case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
-		pr_debug("memcpy_toio(x): --> ptr(%p), mode:%d\n",
-			 ptr, access_mode);
-		memcpy_toio(ptr, elem, (4 << ring->elm_size));
-		ring->state.free--;
-		break;
-	default:
-		return -EINVAL;
+		writel(-1 & K3_DMARING_RING_RT_DB_ENTRY_MASK, &ring->rt->db);
 	}
 
-	pr_debug("free%d index%d occ%d index%d\n",
-		 ring->state.free, ring->state.windex, ring->state.occ, ring->state.rindex);
+	dev_dbg(ring->parent->dev, "%s: occ%d index%d pos_ptr%px\n",
+		__func__, ring->state.occ, ring->state.rindex, elem_ptr);
 	return 0;
 }
 
-static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
-					    void *elem)
-{
-	return k3_nav_ringacc_ring_access_io(
-			ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
-}
-
-static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem)
-{
-	return k3_nav_ringacc_ring_access_io(
-			ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
-}
-
-static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem)
-{
-	return k3_nav_ringacc_ring_access_io(
-			ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring, void *elem)
-{
-	return k3_nav_ringacc_ring_access_io(
-			ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
 static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem)
 {
 	void *elem_ptr;
@@ -930,7 +863,7 @@ int k3_nav_ringacc_ring_pop(struct k3_nav_ring *ring, void *elem)
 		return -EINVAL;
 
 	if (!ring->state.occ)
-		ring->state.occ = k3_nav_ringacc_ring_get_occ(ring);
+		k3_nav_ringacc_ring_update_occ(ring);
 
 	pr_debug("ring_pop%d: occ%d index%d\n",
 		 ring->ring_id, ring->state.occ, ring->state.rindex);
@@ -952,7 +885,7 @@ int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem)
 		return -EINVAL;
 
 	if (!ring->state.occ)
-		ring->state.occ = k3_nav_ringacc_ring_get_occ(ring);
+		k3_nav_ringacc_ring_update_occ(ring);
 
 	pr_debug("ring_pop_tail: occ%d index%d\n",
 		 ring->state.occ, ring->state.rindex);
@@ -969,6 +902,7 @@ int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem)
 static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
 {
 	struct udevice *dev = ringacc->dev;
+	struct udevice *devp = dev;
 	struct udevice *tisci_dev = NULL;
 	int ret;
 
@@ -981,7 +915,7 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
 	ringacc->dma_ring_reset_quirk =
 			dev_read_bool(dev, "ti,dma-ring-reset-quirk");
 
-	ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
+	ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, devp,
 					   "ti,sci", &tisci_dev);
 	if (ret) {
 		pr_debug("TISCI RA RM get failed (%d)\n", ret);
@@ -991,14 +925,14 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
 	ringacc->tisci = (struct ti_sci_handle *)
 			 (ti_sci_get_handle_from_sysfw(tisci_dev));
 
-	ret = dev_read_u32_default(dev, "ti,sci", 0);
+	ret = dev_read_u32_default(devp, "ti,sci", 0);
 	if (!ret) {
 		dev_err(dev, "TISCI RA RM disabled\n");
 		ringacc->tisci = NULL;
 		return ret;
 	}
 
-	ret = dev_read_u32(dev, "ti,sci-dev-id", &ringacc->tisci_dev_id);
+	ret = dev_read_u32(devp, "ti,sci-dev-id", &ringacc->tisci_dev_id);
 	if (ret) {
 		dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
 		ringacc->tisci = NULL;
@@ -1017,7 +951,7 @@ static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
 
 static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc)
 {
-	void __iomem *base_fifo, *base_rt;
+	void __iomem *base_rt;
 	int ret, i;
 
 	ret = k3_nav_ringacc_probe_dt(ringacc);
@@ -1029,24 +963,6 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
 	if (IS_ERR(base_rt))
 		return PTR_ERR(base_rt);
 
-	base_fifo = (uint32_t *)devfdt_get_addr_name(dev, "fifos");
-	pr_debug("fifos %p\n", base_fifo);
-	if (IS_ERR(base_fifo))
-		return PTR_ERR(base_fifo);
-
-	ringacc->proxy_gcfg = (struct k3_ringacc_proxy_gcfg_regs __iomem *)
-		devfdt_get_addr_name(dev, "proxy_gcfg");
-	if (IS_ERR(ringacc->proxy_gcfg))
-		return PTR_ERR(ringacc->proxy_gcfg);
-	ringacc->proxy_target_base =
-		(struct k3_ringacc_proxy_gcfg_regs __iomem *)
-		devfdt_get_addr_name(dev, "proxy_target");
-	if (IS_ERR(ringacc->proxy_target_base))
-		return PTR_ERR(ringacc->proxy_target_base);
-
-	ringacc->num_proxies = ringacc_readl(&ringacc->proxy_gcfg->config) &
-					 K3_RINGACC_PROXY_CFG_THREADS_MASK;
-
 	ringacc->rings = devm_kzalloc(dev,
 				      sizeof(*ringacc->rings) *
 				      ringacc->num_rings,
@@ -1054,21 +970,15 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
 	ringacc->rings_inuse = devm_kcalloc(dev,
 					    BITS_TO_LONGS(ringacc->num_rings),
 					    sizeof(unsigned long), GFP_KERNEL);
-	ringacc->proxy_inuse = devm_kcalloc(dev,
-					    BITS_TO_LONGS(ringacc->num_proxies),
-					    sizeof(unsigned long), GFP_KERNEL);
 
-	if (!ringacc->rings || !ringacc->rings_inuse || !ringacc->proxy_inuse)
+	if (!ringacc->rings || !ringacc->rings_inuse)
 		return -ENOMEM;
 
 	for (i = 0; i < ringacc->num_rings; i++) {
 		ringacc->rings[i].rt = base_rt +
 				       KNAV_RINGACC_RT_REGS_STEP * i;
-		ringacc->rings[i].fifos = base_fifo +
-					  KNAV_RINGACC_FIFO_REGS_STEP * i;
 		ringacc->rings[i].parent = ringacc;
 		ringacc->rings[i].ring_id = i;
-		ringacc->rings[i].proxy_id = K3_RINGACC_PROXY_NOT_USED;
 	}
 	dev_set_drvdata(dev, ringacc);
 
@@ -1083,12 +993,68 @@ static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringa
 		 ringacc->tisci_dev_id);
 	dev_info(dev, "dma-ring-reset-quirk: %s\n",
 		 ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
-	dev_info(dev, "RA Proxy rev. %08x, num_proxies:%u\n",
-		 ringacc_readl(&ringacc->proxy_gcfg->revision),
-		 ringacc->num_proxies);
 	return 0;
 }
 
+struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
+						struct k3_ringacc_init_data *data)
+{
+	struct k3_nav_ringacc *ringacc;
+	void __iomem *base_rt;
+	int i;
+
+	ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
+	if (!ringacc)
+		return ERR_PTR(-ENOMEM);
+
+	ringacc->dual_ring = true;
+
+	ringacc->dev = dev;
+	ringacc->num_rings = data->num_rings;
+	ringacc->tisci = data->tisci;
+	ringacc->tisci_dev_id = data->tisci_dev_id;
+
+	base_rt = (uint32_t *)devfdt_get_addr_name(dev, "ringrt");
+	if (IS_ERR(base_rt))
+		return base_rt;
+
+	ringacc->rings = devm_kzalloc(dev,
+				      sizeof(*ringacc->rings) *
+				      ringacc->num_rings * 2,
+				      GFP_KERNEL);
+	ringacc->rings_inuse = devm_kcalloc(dev,
+					    BITS_TO_LONGS(ringacc->num_rings),
+					    sizeof(unsigned long), GFP_KERNEL);
+
+	if (!ringacc->rings || !ringacc->rings_inuse)
+		return ERR_PTR(-ENOMEM);
+
+	for (i = 0; i < ringacc->num_rings; i++) {
+		struct k3_nav_ring *ring = &ringacc->rings[i];
+
+		ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i;
+		ring->parent = ringacc;
+		ring->ring_id = i;
+
+		ring = &ringacc->rings[ringacc->num_rings + i];
+		ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i +
+			   K3_DMARING_RING_RT_REGS_REVERSE_OFS;
+		ring->parent = ringacc;
+		ring->ring_id = i;
+		ring->flags = K3_NAV_RING_FLAG_REVERSE;
+	}
+
+	ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops;
+
+	dev_info(dev, "k3_dmaring Ring probed rings:%u, sci-dev-id:%u\n",
+		 ringacc->num_rings,
+		 ringacc->tisci_dev_id);
+	dev_info(dev, "dma-ring-reset-quirk: %s\n",
+		 ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
+
+	return ringacc;
+}
+
 struct ringacc_match_data {
 	struct k3_nav_ringacc_ops ops;
 };
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index e1a5f4b1d1..47921d27b1 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -184,12 +184,6 @@ struct global_data {
 
 #ifdef CONFIG_DM
 	/**
-	 * @dm_flags: additional flags for Driver Model
-	 *
-	 * See &enum gd_dm_flags
-	 */
-	unsigned long dm_flags;
-	/**
 	 * @dm_root: root instance for Driver Model
 	 */
 	struct udevice *dm_root;
@@ -519,12 +513,6 @@ struct global_data {
 #define gd_acpi_ctx()		NULL
 #endif
 
-#if CONFIG_IS_ENABLED(DM)
-#define gd_size_cells_0()	(gd->dm_flags & GD_DM_FLG_SIZE_CELLS_0)
-#else
-#define gd_size_cells_0()	(0)
-#endif
-
 /**
  * enum gd_flags - global data flags
  *
@@ -609,18 +597,6 @@ enum gd_flags {
 	GD_FLG_SMP_READY = 0x40000,
 };
 
-/**
- * enum gd_dm_flags - global data flags for Driver Model
- *
- * See field dm_flags of &struct global_data.
- */
-enum gd_dm_flags {
-	/**
-	 * @GD_DM_FLG_SIZE_CELLS_0: Enable #size-cells=<0> translation
-	 */
-	GD_DM_FLG_SIZE_CELLS_0 = 0x00001,
-};
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
new file mode 100644
index 0000000000..7c30e50c5f
--- /dev/null
+++ b/include/configs/am64x_evm.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 AM642 SoC family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *	Keerthy <j-keerthy@ti.com>
+ */
+
+#ifndef __CONFIG_AM642_EVM_H
+#define __CONFIG_AM642_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1		0x880000000
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"tispl.bin"
+#endif
+
+#ifndef CONFIG_CPU_V7R
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+#if defined(CONFIG_TARGET_AM642_A53_EVM)
+#define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\
+					CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4)
+#else
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x1000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\
+					 CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR         CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START    0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     SZ_16M
+#endif
+
+#define PARTS_DEFAULT \
+	/* Linux partitions */ \
+	"name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS					\
+	"findfdt="							\
+		"if test $board_name = am64x_gpevm; then " \
+			"setenv fdtfile k3-am642-evm.dtb; fi; " \
+		"if test $board_name = am64x_skevm; then " \
+			"setenv fdtfile k3-am642-sk.dtb; fi;" \
+		"if test $fdtfile = undefined; then " \
+			"echo WARNING: Could not determine device tree to use; fi; \0" \
+	"name_kern=Image\0"						\
+	"console=ttyS2,115200n8\0"					\
+	"args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 "	\
+		"${mtdparts}\0"						\
+	"run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC				\
+	"boot=mmc\0"							\
+	"mmcdev=1\0"							\
+	"bootpart=1:2\0"						\
+	"bootdir=/boot\0"						\
+	"rd_spec=-\0"							\
+	"init_mmc=run args_all args_mmc\0"				\
+	"get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+	"get_overlay_mmc="						\
+		"fdt address ${fdtaddr};"				\
+		"fdt resize 0x100000;"					\
+		"for overlay in $name_overlays;"			\
+		"do;"							\
+		"load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && "	\
+		"fdt apply ${dtboaddr};"				\
+		"done;\0"						\
+	"get_kern_mmc=load mmc ${bootpart} ${loadaddr} "		\
+		"${bootdir}/${name_kern}\0"				\
+	"get_fit_mmc=load mmc ${bootpart} ${addr_fit} "			\
+		"${bootdir}/${name_fit}\0"				\
+	"partitions=" PARTS_DEFAULT
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	DEFAULT_LINUX_BOOT_ENV						\
+	DEFAULT_MMC_TI_ARGS						\
+	EXTRA_ENV_AM642_BOARD_SETTINGS					\
+	EXTRA_ENV_AM642_BOARD_SETTINGS_MMC
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+/* MMC ENV related defines */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_SYS_MMC_ENV_PART	1
+#endif
+
+#endif /* __CONFIG_AM642_EVM_H */
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index ce0cd38f56..e6cb1d0540 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -2,7 +2,7 @@
 /*
  * This header provides constants for TI K3-AM65 pinctrl bindings.
  *
- * Copyright (C) 2018 Texas Instruments
+ * Copyright (C) 2018-2021 Texas Instruments
  */
 #ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
 #define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
@@ -38,4 +38,7 @@
 #define J721E_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
 #define J721E_WKUP_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
 
+#define AM64X_IOPAD(pa, val, muxmode)		(((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_MCU_IOPAD(pa, val, muxmode)	(((pa) & 0x1fff)) ((val) | (muxmode))
+
 #endif
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
index 9176277ff0..0ad8f203da 100644
--- a/include/linux/soc/ti/k3-navss-ringacc.h
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -83,22 +83,17 @@ struct k3_nav_ring_cfg {
 };
 
 #define K3_NAV_RINGACC_RING_ID_ANY (-1)
-#define K3_NAV_RINGACC_RING_USE_PROXY BIT(1)
 
 /**
  * k3_nav_ringacc_request_ring - request ring from ringacc
  * @ringacc: pointer on ringacc
  * @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring
- * @flags:
- *	@K3_NAV_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
- *		used to access ring memory. Sopported only for rings in
- *		Message/Credentials/Queue mode.
  *
  * Returns pointer on the Ring - struct k3_nav_ring
  * or NULL in case of failure.
  */
 struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
-						int id, u32 flags);
+						int id);
 
 int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
 				      int fwd_id, int compl_id,
@@ -238,4 +233,19 @@ int k3_nav_ringacc_ring_push_head(struct k3_nav_ring *ring, void *elem);
  */
 int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem);
 
+/* DMA ring support */
+struct ti_sci_handle;
+
+/**
+ * struct struct k3_ringacc_init_data - Initialization data for DMA rings
+ */
+struct k3_ringacc_init_data {
+	const struct ti_sci_handle *tisci;
+	u32 tisci_dev_id;
+	u32 num_rings;
+};
+
+struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
+						struct k3_ringacc_init_data *data);
+
 #endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index eb916ba101..794737923c 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -379,6 +379,13 @@ struct ti_sci_rm_psil_ops {
 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST		0
 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO		2
 
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES	1
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES	2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES	3
+
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN		0
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN		1
+
 /* UDMAP TX/RX channel valid_params common declarations */
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID		BIT(0)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID                BIT(1)
@@ -389,6 +396,7 @@ struct ti_sci_rm_psil_ops {
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID                  BIT(6)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID             BIT(7)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID       BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID		BIT(14)
 
 /**
  * Configures a Navigator Subsystem UDMAP transmit channel
@@ -403,6 +411,8 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID        BIT(11)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)
 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID            BIT(15)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID	BIT(16)
 	u16 nav_id;
 	u16 index;
 	u8 tx_pause_on_err;
@@ -419,6 +429,9 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
 	u8 tx_orderid;
 	u16 fdepth;
 	u8 tx_sched_priority;
+	u8 tx_burst_size;
+	u8 tx_tdtype;
+	u8 extended_ch_type;
 };
 
 /**
@@ -448,6 +461,7 @@ struct ti_sci_msg_rm_udmap_rx_ch_cfg {
 	u8 rx_chan_type;
 	u8 rx_ignore_short;
 	u8 rx_ignore_long;
+	u8 rx_burst_size;
 };
 
 /**
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 6552d09ba3..9b771fdf19 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -5,7 +5,6 @@
 
 #include <common.h>
 #include <dm.h>
-#include <dm/device_compat.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <log.h>
@@ -551,64 +550,6 @@ U_BOOT_DRIVER(fdt_dummy_drv) = {
 	.id	= UCLASS_TEST_DUMMY,
 };
 
-static int zero_size_cells_bus_bind(struct udevice *dev)
-{
-	ofnode child;
-	int err;
-
-	ofnode_for_each_subnode(child, dev_ofnode(dev)) {
-		if (ofnode_get_property(child, "compatible", NULL))
-			continue;
-
-		err = device_bind_driver_to_node(dev,
-						 "zero_size_cells_bus_child_drv",
-						 "zero_size_cells_bus_child",
-						 child, NULL);
-		if (err) {
-			dev_err(dev, "%s: failed to bind %s\n", __func__,
-				ofnode_get_name(child));
-			return err;
-		}
-	}
-
-	return 0;
-}
-
-static const struct udevice_id zero_size_cells_bus_ids[] = {
-	{ .compatible = "sandbox,zero-size-cells-bus" },
-	{ }
-};
-
-U_BOOT_DRIVER(zero_size_cells_bus) = {
-	.name = "zero_size_cells_bus_drv",
-	.id = UCLASS_TEST_DUMMY,
-	.of_match = zero_size_cells_bus_ids,
-	.bind = zero_size_cells_bus_bind,
-};
-
-static int zero_size_cells_bus_child_bind(struct udevice *dev)
-{
-	ofnode child;
-	int err;
-
-	ofnode_for_each_subnode(child, dev_ofnode(dev)) {
-		err = lists_bind_fdt(dev, child, NULL, false);
-		if (err) {
-			dev_err(dev, "%s: lists_bind_fdt, err=%d\n",
-				__func__, err);
-			return err;
-		}
-	}
-
-	return 0;
-}
-
-U_BOOT_DRIVER(zero_size_cells_bus_child_drv) = {
-	.name = "zero_size_cells_bus_child_drv",
-	.id = UCLASS_TEST_DUMMY,
-	.bind = zero_size_cells_bus_child_bind,
-};
-
 static int dm_test_fdt_translation(struct unit_test_state *uts)
 {
 	struct udevice *dev;
@@ -630,17 +571,8 @@ static int dm_test_fdt_translation(struct unit_test_state *uts)
 	/* No translation for busses with #size-cells == 0 */
 	ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 3, &dev));
 	ut_asserteq_str("dev@42", dev->name);
-	/* No translation for busses with #size-cells == 0 */
 	ut_asserteq(0x42, dev_read_addr(dev));
 
-	/* Translation for busses with #size-cells == 0 */
-	gd->dm_flags |= GD_DM_FLG_SIZE_CELLS_0;
-	ut_asserteq(0x8042, dev_read_addr(dev));
-	ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 4, &dev));
-	ut_asserteq_str("dev@19", dev->name);
-	ut_asserteq(0xc019, dev_read_addr(dev));
-	gd->dm_flags &= ~GD_DM_FLG_SIZE_CELLS_0;
-
 	/* dma address translation */
 	ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, &dev));
 	dma_addr[0] = cpu_to_be32(0);