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From patchwork Mon Dec 16 11:01:08 2019
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From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: andrew.murray@arm.com, maz@kernel.org, linux-kernel@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Subject: [PATCH v5 2/6] ARM: dts: bcm2711: Enable PCIe controller
Date: Mon, 16 Dec 2019 12:01:08 +0100
Message-Id: <20191216110113.30436-3-nsaenzjulienne@suse.de>
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Cc: devicetree@vger.kernel.org, f.fainelli@gmail.com,
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This enables bcm2711's PCIe bus, which is hardwired to a VIA
Technologies XHCI USB 3.0 controller.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
Changes since v4:
- Rebase commit taking into account genet support series
Changes since v3:
- Remove unwarranted comment
Changes since v2:
- Remove unused interrupt-map
- correct dma-ranges to it's full size, non power of 2 bus DMA
constraints now supported in linux-next[1]
- add device_type
- rename alias from pcie_0 to pcie0
Changes since v1:
- remove linux,pci-domain
[1] https://lkml.org/lkml/2019/11/21/235
arch/arm/boot/dts/bcm2711.dtsi | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index e2f6ffb00aa9..b56388ce1216 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -331,7 +331,36 @@ scb {
#address-cells = <2>;
#size-cells = <1>;
- ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
+ <0x6 0x00000000 0x6 0x00000000 0x40000000>;
+
+ pcie0: pcie@7d500000 {
+ compatible = "brcm,bcm2711-pcie";
+ reg = <0x0 0x7d500000 0x9310>;
+ device_type = "pci";
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pcie", "msi";
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
+ IRQ_TYPE_LEVEL_HIGH>;
+ msi-controller;
+ msi-parent = <&pcie0>;
+
+ ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
+ 0x0 0x04000000>;
+ /*
+ * The wrapper around the PCIe block has a bug
+ * preventing it from accessing beyond the first 3GB of
+ * memory.
+ */
+ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
+ 0x0 0xc0000000>;
+ brcm,enable-ssc;
+ };
genet: ethernet@7d580000 {
compatible = "brcm,bcm2711-genet-v5";
From patchwork Mon Dec 16 11:01:12 2019
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From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: andrew.murray@arm.com,
maz@kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v5 6/6] arm64: defconfig: Enable Broadcom's STB PCIe
controller
Date: Mon, 16 Dec 2019 12:01:12 +0100
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Cc: linux-arm-kernel@lists.infradead.org, f.fainelli@gmail.com,
linux-pci@vger.kernel.org, phil@raspberrypi.org, jeremy.linton@arm.com,
mbrugger@suse.com, wahrenst@gmx.net, james.quinlan@broadcom.com,
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For now mainly used in the Raspberry Pi 4.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2646fc76b8db..2b80980ef576 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -192,6 +192,7 @@ CONFIG_PCIE_ALTERA_MSI=y
CONFIG_PCI_HOST_THUNDER_PEM=y
CONFIG_PCI_HOST_THUNDER_ECAM=y
CONFIG_PCIE_ROCKCHIP_HOST=m
+CONFIG_PCIE_BRCMSTB=m
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
CONFIG_PCIE_QCOM=y
|
