From fab133265b39b443e3bdb7d9fe0955f7271594ad Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 13 Feb 2020 11:21:16 +0000 Subject: Minor Arm updates --- ...-imx8mq-phanbell-Add-support-for-ethernet.patch | 200 +++++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch (limited to 'arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch') diff --git a/arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch b/arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch new file mode 100644 index 000000000..efa8393c3 --- /dev/null +++ b/arm64-dts-imx8mq-phanbell-Add-support-for-ethernet.patch @@ -0,0 +1,200 @@ +From patchwork Tue Feb 11 13:48:28 2020 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Alifer Moraes +X-Patchwork-Id: 11375533 +Return-Path: + +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E7DAC92A + for ; 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+ }; + ++&fec1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_fec1>; ++ phy-mode = "rgmii-id"; ++ phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; ++ phy-reset-duration = <10>; ++ phy-reset-post-delay = <30>; ++ phy-handle = <ðphy0>; ++ fsl,magic-packet; ++ status = "okay"; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ethphy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0>; ++ }; ++ }; ++}; ++ + &uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +@@ -254,6 +275,26 @@ + }; + + &iomuxc { ++ pinctrl_fec1: fec1grp { ++ fsl,pins = < ++ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 ++ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 ++ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f ++ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f ++ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f ++ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f ++ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 ++ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 ++ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 ++ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 ++ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f ++ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 ++ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 ++ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f ++ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 ++ >; ++ }; ++ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f -- cgit