From 8d05bdd3b68cdde4eb7f710f4cad9b5deb290d7c Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Wed, 5 Aug 2020 23:38:07 +0100 Subject: Upstream 5.9 tegra DT patch, tegra ACPI quirks patch --- ...MCFG-quirks-for-Tegra194-host-controllers.patch | 236 +++++++++++++++++++++ ...-Re-order-PCIe-aperture-mappings-to-suppo.patch | 101 +++++++++ .../generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST | 2 +- .../generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U | 2 +- kernel-aarch64-debug-fedora.config | 4 +- kernel-aarch64-fedora.config | 4 +- kernel.spec | 2 + 7 files changed, 345 insertions(+), 6 deletions(-) create mode 100644 0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch create mode 100644 0002-arm64-tegra-Re-order-PCIe-aperture-mappings-to-suppo.patch diff --git a/0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch b/0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch new file mode 100644 index 000000000..6f785a0fe --- /dev/null +++ b/0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch @@ -0,0 +1,236 @@ +From a74b75072e094e40a8d1c5fb0370b6c9fc4f7f26 Mon Sep 17 00:00:00 2001 +From: Vidya Sagar +Date: Sat, 11 Jan 2020 00:45:00 +0530 +Subject: [PATCH 1/2] PCI: Add MCFG quirks for Tegra194 host controllers + +The PCIe controller in Tegra194 SoC is not completely ECAM-compliant. +With the current hardware design limitations in place, ECAM can be enabled +only for one controller (C5 controller to be precise) with bus numbers +starting from 160 instead of 0. A different approach is taken to avoid this +abnormal way of enabling ECAM for just one controller but to enable +configuration space access for all the other controllers. In this approach, +ops are added through MCFG quirk mechanism which access the configuration +spaces by dynamically programming iATU (internal AddressTranslation Unit) +to generate respective configuration accesses just like the way it is +done in DesignWare core sub-system. + +Signed-off-by: Vidya Sagar +Reported-by: kbuild test robot +Acked-by: Thierry Reding +[ Updated by jonathanh@nvidia.com only permit building the Tegra194 + PCIe driver into the kernel and not as a module ] +Signed-off-by: Jon Hunter +--- + drivers/acpi/pci_mcfg.c | 7 ++ + drivers/pci/controller/dwc/Kconfig | 9 +- + drivers/pci/controller/dwc/Makefile | 2 +- + drivers/pci/controller/dwc/pcie-tegra194.c | 102 +++++++++++++++++++++ + include/linux/pci-ecam.h | 1 + + 5 files changed, 116 insertions(+), 5 deletions(-) + +diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c +index 54b36b7ad47d9..6573d495d9c1f 100644 +--- a/drivers/acpi/pci_mcfg.c ++++ b/drivers/acpi/pci_mcfg.c +@@ -116,6 +116,13 @@ static struct mcfg_fixup mcfg_quirks[] = { + THUNDER_ECAM_QUIRK(2, 12), + THUNDER_ECAM_QUIRK(2, 13), + ++ { "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops}, ++ { "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops}, ++ { "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops}, ++ { "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops}, ++ { "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops}, ++ { "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops}, ++ + #define XGENE_V1_ECAM_MCFG(rev, seg) \ + {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ + &xgene_v1_pcie_ecam_ops } +diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig +index 044a3761c44f2..7745d26420a72 100644 +--- a/drivers/pci/controller/dwc/Kconfig ++++ b/drivers/pci/controller/dwc/Kconfig +@@ -247,10 +247,10 @@ config PCI_MESON + implement the driver. + + config PCIE_TEGRA194 +- tristate ++ bool + + config PCIE_TEGRA194_HOST +- tristate "NVIDIA Tegra194 (and later) PCIe controller - Host Mode" ++ bool "NVIDIA Tegra194 (and later) PCIe controller - Host Mode" + depends on ARCH_TEGRA_194_SOC || COMPILE_TEST + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST +@@ -262,10 +262,11 @@ config PCIE_TEGRA194_HOST + Tegra194. This controller can work either as EP or RC. In order to + enable host-specific features PCIE_TEGRA194_HOST must be selected and + in order to enable device-specific features PCIE_TEGRA194_EP must be +- selected. This uses the DesignWare core. ++ selected. This uses the DesignWare core. ACPI platforms with Tegra194 ++ don't need to enable this. + + config PCIE_TEGRA194_EP +- tristate "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode" ++ bool "NVIDIA Tegra194 (and later) PCIe controller - Endpoint Mode" + depends on ARCH_TEGRA_194_SOC || COMPILE_TEST + depends on PCI_ENDPOINT + select PCIE_DW_EP +diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile +index a751553fa0dbd..dbb9818765566 100644 +--- a/drivers/pci/controller/dwc/Makefile ++++ b/drivers/pci/controller/dwc/Makefile +@@ -17,7 +17,6 @@ obj-$(CONFIG_PCIE_INTEL_GW) += pcie-intel-gw.o + obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o + obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o + obj-$(CONFIG_PCI_MESON) += pci-meson.o +-obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o + obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o + obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o + +@@ -34,4 +33,5 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o + ifdef CONFIG_PCI + obj-$(CONFIG_ARM64) += pcie-al.o + obj-$(CONFIG_ARM64) += pcie-hisi.o ++obj-$(CONFIG_ARM64) += pcie-tegra194.o + endif +diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c +index 92b77f7d83546..cc18814c5bece 100644 +--- a/drivers/pci/controller/dwc/pcie-tegra194.c ++++ b/drivers/pci/controller/dwc/pcie-tegra194.c +@@ -22,6 +22,8 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include +@@ -324,6 +326,103 @@ struct tegra_pcie_dw_of_data { + enum dw_pcie_device_mode mode; + }; + ++#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) ++struct tegra194_pcie_acpi { ++ void __iomem *config_base; ++ void __iomem *iatu_base; ++ void __iomem *dbi_base; ++}; ++ ++static int tegra194_acpi_init(struct pci_config_window *cfg) ++{ ++ struct device *dev = cfg->parent; ++ struct tegra194_pcie_acpi *pcie; ++ ++ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); ++ if (!pcie) ++ return -ENOMEM; ++ ++ pcie->config_base = cfg->win; ++ pcie->iatu_base = cfg->win + SZ_256K; ++ pcie->dbi_base = cfg->win + SZ_512K; ++ cfg->priv = pcie; ++ ++ return 0; ++} ++ ++static inline void atu_reg_write(struct tegra194_pcie_acpi *pcie, int index, ++ u32 val, u32 reg) ++{ ++ u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); ++ ++ writel(val, pcie->iatu_base + offset + reg); ++} ++ ++static void program_outbound_atu(struct tegra194_pcie_acpi *pcie, int index, ++ int type, u64 cpu_addr, u64 pci_addr, u64 size) ++{ ++ atu_reg_write(pcie, index, lower_32_bits(cpu_addr), ++ PCIE_ATU_LOWER_BASE); ++ atu_reg_write(pcie, index, upper_32_bits(cpu_addr), ++ PCIE_ATU_UPPER_BASE); ++ atu_reg_write(pcie, index, lower_32_bits(pci_addr), ++ PCIE_ATU_LOWER_TARGET); ++ atu_reg_write(pcie, index, lower_32_bits(cpu_addr + size - 1), ++ PCIE_ATU_LIMIT); ++ atu_reg_write(pcie, index, upper_32_bits(pci_addr), ++ PCIE_ATU_UPPER_TARGET); ++ atu_reg_write(pcie, index, type, PCIE_ATU_CR1); ++ atu_reg_write(pcie, index, PCIE_ATU_ENABLE, PCIE_ATU_CR2); ++} ++ ++static void __iomem *tegra194_map_bus(struct pci_bus *bus, ++ unsigned int devfn, int where) ++{ ++ struct pci_config_window *cfg = bus->sysdata; ++ struct tegra194_pcie_acpi *pcie = cfg->priv; ++ u32 busdev; ++ int type; ++ ++ if (bus->number < cfg->busr.start || bus->number > cfg->busr.end) ++ return NULL; ++ ++ if (bus->number == cfg->busr.start) { ++ if (PCI_SLOT(devfn) == 0) ++ return pcie->dbi_base + where; ++ else ++ return NULL; ++ } ++ ++ busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | ++ PCIE_ATU_FUNC(PCI_FUNC(devfn)); ++ ++ if (bus->parent->number == cfg->busr.start) { ++ if (PCI_SLOT(devfn) == 0) ++ type = PCIE_ATU_TYPE_CFG0; ++ else ++ return NULL; ++ } else { ++ type = PCIE_ATU_TYPE_CFG1; ++ } ++ ++ program_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0, type, ++ cfg->res.start, busdev, SZ_256K); ++ return (void __iomem *)(pcie->config_base + where); ++} ++ ++struct pci_ecam_ops tegra194_pcie_ops = { ++ .bus_shift = 20, ++ .init = tegra194_acpi_init, ++ .pci_ops = { ++ .map_bus = tegra194_map_bus, ++ .read = pci_generic_config_read, ++ .write = pci_generic_config_write, ++ } ++}; ++#endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */ ++ ++#ifdef CONFIG_PCIE_TEGRA194 ++ + static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci) + { + return container_of(pci, struct tegra_pcie_dw, pci); +@@ -2405,3 +2504,6 @@ MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match); + MODULE_AUTHOR("Vidya Sagar "); + MODULE_DESCRIPTION("NVIDIA PCIe host controller driver"); + MODULE_LICENSE("GPL v2"); ++ ++#endif /* CONFIG_PCIE_TEGRA194 */ ++ +diff --git a/include/linux/pci-ecam.h b/include/linux/pci-ecam.h +index 1af5cb02ef7f9..3fb16ada505a0 100644 +--- a/include/linux/pci-ecam.h ++++ b/include/linux/pci-ecam.h +@@ -57,6 +57,7 @@ extern const struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */ + extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */ + extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */ + extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */ ++extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */ + #endif + + #if IS_ENABLED(CONFIG_PCI_HOST_COMMON) +-- +2.26.2 + diff --git a/0002-arm64-tegra-Re-order-PCIe-aperture-mappings-to-suppo.patch b/0002-arm64-tegra-Re-order-PCIe-aperture-mappings-to-suppo.patch new file mode 100644 index 000000000..d184228ea --- /dev/null +++ b/0002-arm64-tegra-Re-order-PCIe-aperture-mappings-to-suppo.patch @@ -0,0 +1,101 @@ +From 6acf1ba7596a051d6ff4092d22bf9c4ce210d9f5 Mon Sep 17 00:00:00 2001 +From: Vidya Sagar +Date: Sat, 11 Jan 2020 00:44:59 +0530 +Subject: [PATCH 2/2] arm64: tegra: Re-order PCIe aperture mappings to support + ACPI boot + +Re-order Tegra194's PCIe aperture mappings to have IO window moved to +64-bit aperture and have the entire 32-bit aperture used for accessing +the configuration space. This makes it to use the entire 32MB of the 32-bit +aperture for ECAM purpose while booting through ACPI. + +Signed-off-by: Vidya Sagar +--- + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 36 ++++++++++++------------ + 1 file changed, 18 insertions(+), 18 deletions(-) + +diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi +index 4bc187a4eacdb..2b378fa06d19e 100644 +--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi ++++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi +@@ -1404,9 +1404,9 @@ pcie@14100000 { + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */ +- 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ +- 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ ++ ranges = <0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */ ++ 0x82000000 0x00 0x40000000 0x12 0x30000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */ ++ 0x81000000 0x00 0x00000000 0x12 0x3fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */ + }; + + pcie@14120000 { +@@ -1449,9 +1449,9 @@ pcie@14120000 { + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */ +- 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ +- 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ ++ ranges = <0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */ ++ 0x82000000 0x00 0x40000000 0x12 0x70000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */ ++ 0x81000000 0x00 0x00000000 0x12 0x7fff0000 0x0 0x00010000>; /* downstream I/O (64KB) */ + }; + + pcie@14140000 { +@@ -1494,9 +1494,9 @@ pcie@14140000 { + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */ +- 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ +- 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */ ++ ranges = <0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */ ++ 0x82000000 0x00 0x40000000 0x12 0xb0000000 0x0 0x0fff0000 /* non-prefetchable memory (256MB - 64KB) */ ++ 0x81000000 0x00 0x00000000 0x12 0xbfff0000 0x0 0x00010000>; /* downstream I/O (64KB) */ + }; + + pcie@14160000 { +@@ -1539,9 +1539,9 @@ pcie@14160000 { + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */ +- 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ +- 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ ++ ranges = <0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ ++ 0x82000000 0x00 0x40000000 0x17 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */ ++ 0x81000000 0x00 0x00000000 0x17 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */ + }; + + pcie@14180000 { +@@ -1584,9 +1584,9 @@ pcie@14180000 { + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ +- 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ +- 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ ++ ranges = <0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ ++ 0x82000000 0x00 0x40000000 0x1b 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */ ++ 0x81000000 0x00 0x00000000 0x1b 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */ + }; + + pcie@141a0000 { +@@ -1633,9 +1633,9 @@ pcie@141a0000 { + nvidia,aspm-l0s-entrance-latency-us = <3>; + + bus-range = <0x0 0xff>; +- ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ +- 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ +- 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */ ++ ranges = <0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ ++ 0x82000000 0x00 0x40000000 0x1f 0x40000000 0x0 0xbfff0000 /* non-prefetchable memory (3GB - 64KB) */ ++ 0x81000000 0x00 0x00000000 0x1f 0xffff0000 0x0 0x00010000>; /* downstream I/O (64KB) */ + }; + + pcie_ep@14160000 { +-- +2.26.2 + diff --git a/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST b/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST index d79eeb7a7..005ca5c32 100644 --- a/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST +++ b/configs/fedora/generic/arm/aarch64/CONFIG_PCIE_TEGRA194_HOST @@ -1 +1 @@ -CONFIG_PCIE_TEGRA194_HOST=m +CONFIG_PCIE_TEGRA194_HOST=y diff --git a/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U b/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U index 23e44783c..96d1b8819 100644 --- a/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U +++ b/configs/fedora/generic/arm/aarch64/CONFIG_PHY_TEGRA194_P2U @@ -1 +1 @@ -CONFIG_PHY_TEGRA194_P2U=m +CONFIG_PHY_TEGRA194_P2U=y diff --git a/kernel-aarch64-debug-fedora.config b/kernel-aarch64-debug-fedora.config index 675de7410..eb41b870c 100644 --- a/kernel-aarch64-debug-fedora.config +++ b/kernel-aarch64-debug-fedora.config @@ -4709,7 +4709,7 @@ CONFIG_PCIEPORTBUS=y CONFIG_PCIE_PTM=y CONFIG_PCIE_QCOM=y # CONFIG_PCIE_ROCKCHIP_HOST is not set -CONFIG_PCIE_TEGRA194_HOST=m +CONFIG_PCIE_TEGRA194_HOST=y CONFIG_PCIE_XILINX_NWL=y CONFIG_PCIE_XILINX=y # CONFIG_PCI_FTPCI100 is not set @@ -4823,7 +4823,7 @@ CONFIG_PHY_SUN4I_USB=m CONFIG_PHY_SUN50I_USB3=m CONFIG_PHY_SUN6I_MIPI_DPHY=m # CONFIG_PHY_SUN9I_USB is not set -CONFIG_PHY_TEGRA194_P2U=m +CONFIG_PHY_TEGRA194_P2U=y CONFIG_PHY_TEGRA_XUSB=m # CONFIG_PHY_TUSB1210 is not set CONFIG_PHY_XGENE=y diff --git a/kernel-aarch64-fedora.config b/kernel-aarch64-fedora.config index 496acce03..8f4e2c3e7 100644 --- a/kernel-aarch64-fedora.config +++ b/kernel-aarch64-fedora.config @@ -4690,7 +4690,7 @@ CONFIG_PCIEPORTBUS=y CONFIG_PCIE_PTM=y CONFIG_PCIE_QCOM=y # CONFIG_PCIE_ROCKCHIP_HOST is not set -CONFIG_PCIE_TEGRA194_HOST=m +CONFIG_PCIE_TEGRA194_HOST=y CONFIG_PCIE_XILINX_NWL=y CONFIG_PCIE_XILINX=y # CONFIG_PCI_FTPCI100 is not set @@ -4804,7 +4804,7 @@ CONFIG_PHY_SUN4I_USB=m CONFIG_PHY_SUN50I_USB3=m CONFIG_PHY_SUN6I_MIPI_DPHY=m # CONFIG_PHY_SUN9I_USB is not set -CONFIG_PHY_TEGRA194_P2U=m +CONFIG_PHY_TEGRA194_P2U=y CONFIG_PHY_TEGRA_XUSB=m # CONFIG_PHY_TUSB1210 is not set CONFIG_PHY_XGENE=y diff --git a/kernel.spec b/kernel.spec index 1182acada..b353e7840 100644 --- a/kernel.spec +++ b/kernel.spec @@ -857,6 +857,8 @@ Patch98: 0001-arm64-dts-sun50i-a64-pinephone-Enable-LCD-support-on.patch Patch99: 0001-arm64-dts-sun50i-a64-pinephone-Add-touchscreen-suppo.patch Patch100: 0001-Work-around-for-gcc-bug-https-gcc.gnu.org-bugzilla-s.patch +Patch101: 0001-PCI-Add-MCFG-quirks-for-Tegra194-host-controllers.patch +Patch102: 0002-arm64-tegra-Re-order-PCIe-aperture-mappings-to-suppo.patch # END OF PATCH DEFINITIONS %endif -- cgit