diff options
Diffstat (limited to 'patch-5.19-redhat.patch')
| -rw-r--r-- | patch-5.19-redhat.patch | 1848 |
1 files changed, 1839 insertions, 9 deletions
diff --git a/patch-5.19-redhat.patch b/patch-5.19-redhat.patch index 414913c08..db6a113ac 100644 --- a/patch-5.19-redhat.patch +++ b/patch-5.19-redhat.patch @@ -1,15 +1,24 @@ Documentation/admin-guide/kernel-parameters.txt | 9 + + .../devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 1 + + .../bindings/soc/bcm/brcm,bcm2835-pm.txt | 46 - + .../bindings/soc/bcm/brcm,bcm2835-pm.yaml | 86 ++ Kconfig | 2 + Kconfig.redhat | 17 + Makefile | 12 +- arch/arm/Kconfig | 4 +- + arch/arm/boot/dts/bcm2711-rpi.dtsi | 4 + + arch/arm/boot/dts/bcm2711.dtsi | 14 +- + arch/arm/boot/dts/bcm2835-common.dtsi | 1 + + arch/arm/configs/bcm2835_defconfig | 1 + + arch/arm/configs/multi_v7_defconfig | 1 + arch/arm64/Kconfig | 3 +- + arch/arm64/configs/defconfig | 1 + arch/arm64/kernel/acpi.c | 4 + arch/s390/include/asm/ipl.h | 1 + arch/s390/kernel/ipl.c | 5 + arch/s390/kernel/setup.c | 4 + arch/x86/kernel/cpu/common.c | 1 + - arch/x86/kernel/setup.c | 68 ++- + arch/x86/kernel/setup.c | 68 +- drivers/acpi/apei/hest.c | 8 + drivers/acpi/irq.c | 17 +- drivers/acpi/scan.c | 9 + @@ -17,19 +26,30 @@ drivers/char/ipmi/ipmi_dmi.c | 15 + drivers/char/ipmi/ipmi_msghandler.c | 16 +- drivers/firmware/efi/Makefile | 1 + - drivers/firmware/efi/efi.c | 124 +++-- - drivers/firmware/efi/secureboot.c | 38 ++ - drivers/hid/hid-rmi.c | 64 --- + drivers/firmware/efi/efi.c | 124 ++- + drivers/firmware/efi/secureboot.c | 38 + + drivers/gpu/drm/drm_ioctl.c | 8 +- + drivers/gpu/drm/v3d/Kconfig | 5 +- + drivers/gpu/drm/v3d/v3d_debugfs.c | 18 +- + drivers/gpu/drm/v3d/v3d_drv.c | 12 +- + drivers/gpu/drm/v3d/v3d_gem.c | 12 +- + drivers/hid/hid-rmi.c | 64 -- drivers/hwtracing/coresight/coresight-etm4x-core.c | 19 + - drivers/input/rmi4/rmi_driver.c | 124 +++-- + drivers/input/rmi4/rmi_driver.c | 124 +-- drivers/iommu/iommu.c | 22 + drivers/message/fusion/mptsas.c | 10 + drivers/message/fusion/mptspi.c | 11 + + drivers/mfd/bcm2835-pm.c | 74 +- + drivers/net/phy/Kconfig | 5 + + drivers/net/phy/Makefile | 1 + + drivers/net/phy/bcm-phy-lib.h | 19 + + drivers/net/phy/bcm-phy-ptp.c | 944 +++++++++++++++++++++ + drivers/net/phy/broadcom.c | 33 +- drivers/net/wireguard/main.c | 6 + drivers/nvme/host/core.c | 22 +- drivers/nvme/host/multipath.c | 19 +- drivers/nvme/host/nvme.h | 4 + - drivers/pci/pci-driver.c | 78 ++++ + drivers/pci/pci-driver.c | 78 ++ drivers/pci/quirks.c | 24 + drivers/scsi/aacraid/linit.c | 2 + drivers/scsi/be2iscsi/be_main.c | 2 + @@ -39,16 +59,18 @@ drivers/scsi/mpt3sas/mpt3sas_scsih.c | 4 + drivers/scsi/qla2xxx/qla_os.c | 6 + drivers/scsi/qla4xxx/ql4_os.c | 2 + + drivers/soc/bcm/bcm2835-power.c | 72 +- drivers/usb/core/hub.c | 7 + fs/afs/main.c | 3 + include/linux/efi.h | 22 +- include/linux/kernel.h | 21 + include/linux/lsm_hook_defs.h | 2 + include/linux/lsm_hooks.h | 6 + + include/linux/mfd/bcm2835-pm.h | 1 + include/linux/module.h | 1 + include/linux/panic.h | 19 +- include/linux/pci.h | 16 + - include/linux/rh_kabi.h | 515 +++++++++++++++++++++ + include/linux/rh_kabi.h | 515 +++++++++++ include/linux/rmi.h | 1 + include/linux/security.h | 5 + init/Kconfig | 2 +- @@ -57,14 +79,14 @@ kernel/module/main.c | 2 + kernel/module/signing.c | 9 +- kernel/panic.c | 14 + - kernel/rh_messages.c | 209 +++++++++ + kernel/rh_messages.c | 209 +++++ scripts/mod/modpost.c | 8 + scripts/tags.sh | 2 + security/integrity/platform_certs/load_uefi.c | 6 +- security/lockdown/Kconfig | 13 + security/lockdown/lockdown.c | 1 + security/security.c | 6 + - 66 files changed, 1544 insertions(+), 187 deletions(-) + 88 files changed, 2766 insertions(+), 324 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index f2d26cb7e853..c8c658e66f69 100644 @@ -86,6 +108,162 @@ index f2d26cb7e853..c8c658e66f69 100644 usbcore.authorized_default= [USB] Default USB device authorization: (default -1 = authorized except for wireless USB, +diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +index e6485f7b046f..217c42874f41 100644 +--- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml ++++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +@@ -16,6 +16,7 @@ properties: + + compatible: + enum: ++ - brcm,2711-v3d + - brcm,7268-v3d + - brcm,7278-v3d + +diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt +deleted file mode 100644 +index 72ff033565e5..000000000000 +--- a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.txt ++++ /dev/null +@@ -1,46 +0,0 @@ +-BCM2835 PM (Power domains, watchdog) +- +-The PM block controls power domains and some reset lines, and includes +-a watchdog timer. This binding supersedes the brcm,bcm2835-pm-wdt +-binding which covered some of PM's register range and functionality. +- +-Required properties: +- +-- compatible: Should be "brcm,bcm2835-pm" +-- reg: Specifies base physical address and size of the two +- register ranges ("PM" and "ASYNC_BRIDGE" in that +- order) +-- clocks: a) v3d: The V3D clock from CPRMAN +- b) peri_image: The PERI_IMAGE clock from CPRMAN +- c) h264: The H264 clock from CPRMAN +- d) isp: The ISP clock from CPRMAN +-- #reset-cells: Should be 1. This property follows the reset controller +- bindings[1]. +-- #power-domain-cells: Should be 1. This property follows the power domain +- bindings[2]. +- +-Optional properties: +- +-- timeout-sec: Contains the watchdog timeout in seconds +-- system-power-controller: Whether the watchdog is controlling the +- system power. This node follows the power controller bindings[3]. +- +-[1] Documentation/devicetree/bindings/reset/reset.txt +-[2] Documentation/devicetree/bindings/power/power-domain.yaml +-[3] Documentation/devicetree/bindings/power/power-controller.txt +- +-Example: +- +-pm { +- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; +- #power-domain-cells = <1>; +- #reset-cells = <1>; +- reg = <0x7e100000 0x114>, +- <0x7e00a000 0x24>; +- clocks = <&clocks BCM2835_CLOCK_V3D>, +- <&clocks BCM2835_CLOCK_PERI_IMAGE>, +- <&clocks BCM2835_CLOCK_H264>, +- <&clocks BCM2835_CLOCK_ISP>; +- clock-names = "v3d", "peri_image", "h264", "isp"; +- system-power-controller; +-}; +diff --git a/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml +new file mode 100644 +index 000000000000..894786640938 +--- /dev/null ++++ b/Documentation/devicetree/bindings/soc/bcm/brcm,bcm2835-pm.yaml +@@ -0,0 +1,86 @@ ++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause ++%YAML 1.2 ++--- ++$id: "http://devicetree.org/schemas/soc/bcm/brcm,bcm2835-pm.yaml#" ++$schema: "http://devicetree.org/meta-schemas/core.yaml#" ++ ++title: BCM2835 PM (Power domains, watchdog) ++ ++description: | ++ The PM block controls power domains and some reset lines, and includes a ++ watchdog timer. ++ ++maintainers: ++ - Nicolas Saenz Julienne <nsaenz@kernel.org> ++ ++allOf: ++ - $ref: ../../watchdog/watchdog.yaml# ++ ++properties: ++ compatible: ++ items: ++ - enum: ++ - brcm,bcm2835-pm ++ - brcm,bcm2711-pm ++ - const: brcm,bcm2835-pm-wdt ++ ++ reg: ++ minItems: 2 ++ maxItems: 3 ++ ++ reg-names: ++ minItems: 2 ++ items: ++ - const: pm ++ - const: asb ++ - const: rpivid_asb ++ ++ "#power-domain-cells": ++ const: 1 ++ ++ "#reset-cells": ++ const: 1 ++ ++ clocks: ++ minItems: 4 ++ maxItems: 4 ++ ++ clock-names: ++ items: ++ - const: v3d ++ - const: peri_image ++ - const: h264 ++ - const: isp ++ ++ system-power-controller: ++ type: boolean ++ ++ timeout-sec: true ++ ++required: ++ - compatible ++ - reg ++ - "#power-domain-cells" ++ - "#reset-cells" ++ - clocks ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include <dt-bindings/clock/bcm2835.h> ++ ++ watchdog@7e100000 { ++ compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ reg = <0x7e100000 0x114>, ++ <0x7e00a000 0x24>; ++ reg-names = "pm", "asb"; ++ clocks = <&clocks BCM2835_CLOCK_V3D>, ++ <&clocks BCM2835_CLOCK_PERI_IMAGE>, ++ <&clocks BCM2835_CLOCK_H264>, ++ <&clocks BCM2835_CLOCK_ISP>; ++ clock-names = "v3d", "peri_image", "h264", "isp"; ++ system-power-controller; ++ }; diff --git a/Kconfig b/Kconfig index 745bc773f567..f57ff40109d7 100644 --- a/Kconfig @@ -165,6 +343,94 @@ index 7630ba9cb6cc..c2e2991edd11 100644 help The VM uses one page of physical memory for each page table. For systems with a lot of processes, this can use a lot of +diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi +index ca266c5d9f9b..98817a6675b9 100644 +--- a/arch/arm/boot/dts/bcm2711-rpi.dtsi ++++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi +@@ -69,6 +69,10 @@ blconfig: nvram@0 { + }; + }; + ++&v3d { ++ clocks = <&firmware_clocks 5>; ++}; ++ + &vchiq { + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + }; +diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi +index 89af57482bc8..941c4d16791b 100644 +--- a/arch/arm/boot/dts/bcm2711.dtsi ++++ b/arch/arm/boot/dts/bcm2711.dtsi +@@ -107,12 +107,13 @@ dma: dma@7e007000 { + }; + + pm: watchdog@7e100000 { +- compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt"; ++ compatible = "brcm,bcm2711-pm", "brcm,bcm2835-pm-wdt"; + #power-domain-cells = <1>; + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>, + <0x7ec11000 0x20>; ++ reg-names = "pm", "asb", "rpivid_asb"; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, +@@ -601,6 +602,17 @@ genet_mdio: mdio@e14 { + #size-cells = <0x0>; + }; + }; ++ ++ v3d: gpu@7ec00000 { ++ compatible = "brcm,2711-v3d"; ++ reg = <0x0 0x7ec00000 0x4000>, ++ <0x0 0x7ec04000 0x4000>; ++ reg-names = "hub", "core0"; ++ ++ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; ++ resets = <&pm BCM2835_RESET_V3D>; ++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ++ }; + }; + }; + +diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi +index c25e797b9060..a037d2bc5b11 100644 +--- a/arch/arm/boot/dts/bcm2835-common.dtsi ++++ b/arch/arm/boot/dts/bcm2835-common.dtsi +@@ -62,6 +62,7 @@ pm: watchdog@7e100000 { + #reset-cells = <1>; + reg = <0x7e100000 0x114>, + <0x7e00a000 0x24>; ++ reg-names = "pm", "asb"; + clocks = <&clocks BCM2835_CLOCK_V3D>, + <&clocks BCM2835_CLOCK_PERI_IMAGE>, + <&clocks BCM2835_CLOCK_H264>, +diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig +index a9ed79b7f871..9270512c14ea 100644 +--- a/arch/arm/configs/bcm2835_defconfig ++++ b/arch/arm/configs/bcm2835_defconfig +@@ -106,6 +106,7 @@ CONFIG_REGULATOR_GPIO=y + CONFIG_MEDIA_SUPPORT=y + CONFIG_MEDIA_CAMERA_SUPPORT=y + CONFIG_DRM=y ++CONFIG_DRM_V3D=y + CONFIG_DRM_VC4=y + CONFIG_FB_SIMPLE=y + CONFIG_FRAMEBUFFER_CONSOLE=y +diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig +index ce9826bce29b..948d18e59cf5 100644 +--- a/arch/arm/configs/multi_v7_defconfig ++++ b/arch/arm/configs/multi_v7_defconfig +@@ -747,6 +747,7 @@ CONFIG_DRM_IMX_PARALLEL_DISPLAY=m + CONFIG_DRM_IMX_TVE=m + CONFIG_DRM_IMX_LDB=m + CONFIG_DRM_IMX_HDMI=m ++CONFIG_DRM_V3D=m + CONFIG_DRM_VC4=m + CONFIG_DRM_ETNAVIV=m + CONFIG_DRM_MXSFB=m diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1652a9800ebe..834d178f6c70 100644 --- a/arch/arm64/Kconfig @@ -186,6 +452,18 @@ index 1652a9800ebe..834d178f6c70 100644 default "12" if ARM64_16K_PAGES default "11" help +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index 7d1105343bc2..36aace2b5b28 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -754,6 +754,7 @@ CONFIG_DRM_CDNS_MHDP8546=m + CONFIG_DRM_DW_HDMI_AHB_AUDIO=m + CONFIG_DRM_DW_HDMI_CEC=m + CONFIG_DRM_IMX_DCSS=m ++CONFIG_DRM_V3D=m + CONFIG_DRM_VC4=m + CONFIG_DRM_ETNAVIV=m + CONFIG_DRM_HISI_HIBMC=m diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index e4dea8db6924..3f17c7b5bd78 100644 --- a/arch/arm64/kernel/acpi.c @@ -748,6 +1026,206 @@ index 000000000000..de0a3714a5d4 + } + } +} +diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c +index 51fcf1298023..7f1097947731 100644 +--- a/drivers/gpu/drm/drm_ioctl.c ++++ b/drivers/gpu/drm/drm_ioctl.c +@@ -472,7 +472,13 @@ EXPORT_SYMBOL(drm_invalid_op); + */ + static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value) + { +- int len; ++ size_t len; ++ ++ /* don't attempt to copy a NULL pointer */ ++ if (WARN_ONCE(!value, "BUG: the value to copy was not set!")) { ++ *buf_len = 0; ++ return 0; ++ } + + /* don't overflow userbuf */ + len = strlen(value); +diff --git a/drivers/gpu/drm/v3d/Kconfig b/drivers/gpu/drm/v3d/Kconfig +index e973ec487484..ce62c5908e1d 100644 +--- a/drivers/gpu/drm/v3d/Kconfig ++++ b/drivers/gpu/drm/v3d/Kconfig +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0-only + config DRM_V3D + tristate "Broadcom V3D 3.x and newer" +- depends on ARCH_BCM || ARCH_BRCMSTB || COMPILE_TEST ++ depends on ARCH_BCM || ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST + depends on DRM + depends on COMMON_CLK + depends on MMU +@@ -9,4 +9,5 @@ config DRM_V3D + select DRM_GEM_SHMEM_HELPER + help + Choose this option if you have a system that has a Broadcom +- V3D 3.x or newer GPU, such as BCM7268. ++ V3D 3.x or newer GPUs. SoCs supported include the BCM2711, ++ BCM7268 and BCM7278. +diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c +index 29fd13109e43..efbde124c296 100644 +--- a/drivers/gpu/drm/v3d/v3d_debugfs.c ++++ b/drivers/gpu/drm/v3d/v3d_debugfs.c +@@ -4,7 +4,6 @@ + #include <linux/circ_buf.h> + #include <linux/ctype.h> + #include <linux/debugfs.h> +-#include <linux/pm_runtime.h> + #include <linux/seq_file.h> + #include <linux/string_helpers.h> + +@@ -131,11 +130,7 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused) + struct drm_device *dev = node->minor->dev; + struct v3d_dev *v3d = to_v3d_dev(dev); + u32 ident0, ident1, ident2, ident3, cores; +- int ret, core; +- +- ret = pm_runtime_get_sync(v3d->drm.dev); +- if (ret < 0) +- return ret; ++ int core; + + ident0 = V3D_READ(V3D_HUB_IDENT0); + ident1 = V3D_READ(V3D_HUB_IDENT1); +@@ -188,9 +183,6 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused) + (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0); + } + +- pm_runtime_mark_last_busy(v3d->drm.dev); +- pm_runtime_put_autosuspend(v3d->drm.dev); +- + return 0; + } + +@@ -218,11 +210,6 @@ static int v3d_measure_clock(struct seq_file *m, void *unused) + uint32_t cycles; + int core = 0; + int measure_ms = 1000; +- int ret; +- +- ret = pm_runtime_get_sync(v3d->drm.dev); +- if (ret < 0) +- return ret; + + if (v3d->ver >= 40) { + V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3, +@@ -246,9 +233,6 @@ static int v3d_measure_clock(struct seq_file *m, void *unused) + cycles / (measure_ms * 1000), + (cycles / (measure_ms * 100)) % 10); + +- pm_runtime_mark_last_busy(v3d->drm.dev); +- pm_runtime_put_autosuspend(v3d->drm.dev); +- + return 0; + } + +diff --git a/drivers/gpu/drm/v3d/v3d_drv.c b/drivers/gpu/drm/v3d/v3d_drv.c +index 1afcd54fbbd5..8c7f910daa28 100644 +--- a/drivers/gpu/drm/v3d/v3d_drv.c ++++ b/drivers/gpu/drm/v3d/v3d_drv.c +@@ -19,7 +19,6 @@ + #include <linux/module.h> + #include <linux/of_platform.h> + #include <linux/platform_device.h> +-#include <linux/pm_runtime.h> + #include <linux/reset.h> + + #include <drm/drm_drv.h> +@@ -43,7 +42,6 @@ static int v3d_get_param_ioctl(struct drm_device *dev, void *data, + { + struct v3d_dev *v3d = to_v3d_dev(dev); + struct drm_v3d_get_param *args = data; +- int ret; + static const u32 reg_map[] = { + [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG, + [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1, +@@ -69,17 +67,12 @@ static int v3d_get_param_ioctl(struct drm_device *dev, void *data, + if (args->value != 0) + return -EINVAL; + +- ret = pm_runtime_get_sync(v3d->drm.dev); +- if (ret < 0) +- return ret; + if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 && + args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) { + args->value = V3D_CORE_READ(0, offset); + } else { + args->value = V3D_READ(offset); + } +- pm_runtime_mark_last_busy(v3d->drm.dev); +- pm_runtime_put_autosuspend(v3d->drm.dev); + return 0; + } + +@@ -198,6 +191,7 @@ static const struct drm_driver v3d_drm_driver = { + }; + + static const struct of_device_id v3d_of_match[] = { ++ { .compatible = "brcm,2711-v3d" }, + { .compatible = "brcm,7268-v3d" }, + { .compatible = "brcm,7278-v3d" }, + {}, +@@ -280,10 +274,6 @@ static int v3d_platform_drm_probe(struct platform_device *pdev) + return -ENOMEM; + } + +- pm_runtime_use_autosuspend(dev); +- pm_runtime_set_autosuspend_delay(dev, 50); +- pm_runtime_enable(dev); +- + ret = v3d_gem_init(drm); + if (ret) + goto dma_free; +diff --git a/drivers/gpu/drm/v3d/v3d_gem.c b/drivers/gpu/drm/v3d/v3d_gem.c +index 2352e9640922..725a252e837b 100644 +--- a/drivers/gpu/drm/v3d/v3d_gem.c ++++ b/drivers/gpu/drm/v3d/v3d_gem.c +@@ -6,7 +6,6 @@ + #include <linux/io.h> + #include <linux/module.h> + #include <linux/platform_device.h> +-#include <linux/pm_runtime.h> + #include <linux/reset.h> + #include <linux/sched/signal.h> + #include <linux/uaccess.h> +@@ -372,9 +371,6 @@ v3d_job_free(struct kref *ref) + dma_fence_put(job->irq_fence); + dma_fence_put(job->done_fence); + +- pm_runtime_mark_last_busy(job->v3d->drm.dev); +- pm_runtime_put_autosuspend(job->v3d->drm.dev); +- + if (job->perfmon) + v3d_perfmon_put(job->perfmon); + +@@ -476,14 +472,10 @@ v3d_job_init(struct v3d_dev *v3d, struct drm_file *file_priv, + job->v3d = v3d; + job->free = free; + +- ret = pm_runtime_get_sync(v3d->drm.dev); +- if (ret < 0) +- goto fail; +- + ret = drm_sched_job_init(&job->base, &v3d_priv->sched_entity[queue], + v3d_priv); + if (ret) +- goto fail_job; ++ goto fail; + + if (has_multisync) { + if (se->in_sync_count && se->wait_stage == queue) { +@@ -514,8 +506,6 @@ v3d_job_init(struct v3d_dev *v3d, struct drm_file *file_priv, + + fail_deps: + drm_sched_job_cleanup(&job->base); +-fail_job: +- pm_runtime_put_autosuspend(v3d->drm.dev); + fail: + kfree(*container); + *container = NULL; diff --git a/drivers/hid/hid-rmi.c b/drivers/hid/hid-rmi.c index 311eee599ce9..2460c6bd46f8 100644 --- a/drivers/hid/hid-rmi.c @@ -1201,6 +1679,1208 @@ index 388675cc1765..8c7d0740efb6 100644 return 0; out_mptspi_probe: +diff --git a/drivers/mfd/bcm2835-pm.c b/drivers/mfd/bcm2835-pm.c +index 42fe67f1538e..49cd1f03884a 100644 +--- a/drivers/mfd/bcm2835-pm.c ++++ b/drivers/mfd/bcm2835-pm.c +@@ -25,9 +25,52 @@ static const struct mfd_cell bcm2835_power_devs[] = { + { .name = "bcm2835-power" }, + }; + ++static int bcm2835_pm_get_pdata(struct platform_device *pdev, ++ struct bcm2835_pm *pm) ++{ ++ if (of_find_property(pm->dev->of_node, "reg-names", NULL)) { ++ struct resource *res; ++ ++ pm->base = devm_platform_ioremap_resource_byname(pdev, "pm"); ++ if (IS_ERR(pm->base)) ++ return PTR_ERR(pm->base); ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "asb"); ++ if (res) { ++ pm->asb = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(pm->asb)) ++ pm->asb = NULL; ++ } ++ ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, ++ "rpivid_asb"); ++ if (res) { ++ pm->rpivid_asb = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(pm->rpivid_asb)) ++ pm->rpivid_asb = NULL; ++ } ++ ++ return 0; ++ } ++ ++ /* If no 'reg-names' property is found we can assume we're using old DTB. */ ++ pm->base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(pm->base)) ++ return PTR_ERR(pm->base); ++ ++ pm->asb = devm_platform_ioremap_resource(pdev, 1); ++ if (IS_ERR(pm->asb)) ++ pm->asb = NULL; ++ ++ pm->rpivid_asb = devm_platform_ioremap_resource(pdev, 2); ++ if (IS_ERR(pm->rpivid_asb)) ++ pm->rpivid_asb = NULL; ++ ++ return 0; ++} ++ + static int bcm2835_pm_probe(struct platform_device *pdev) + { +- struct resource *res; + struct device *dev = &pdev->dev; + struct bcm2835_pm *pm; + int ret; +@@ -39,10 +82,9 @@ static int bcm2835_pm_probe(struct platform_device *pdev) + + pm->dev = dev; + +- res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +- pm->base = devm_ioremap_resource(dev, res); +- if (IS_ERR(pm->base)) +- return PTR_ERR(pm->base); ++ ret = bcm2835_pm_get_pdata(pdev, pm); ++ if (ret) ++ return ret; + + ret = devm_mfd_add_devices(dev, -1, + bcm2835_pm_devs, ARRAY_SIZE(bcm2835_pm_devs), +@@ -50,30 +92,22 @@ static int bcm2835_pm_probe(struct platform_device *pdev) + if (ret) + return ret; + +- /* We'll use the presence of the AXI ASB regs in the ++ /* ++ * We'll use the presence of the AXI ASB regs in the + * bcm2835-pm binding as the key for whether we can reference + * the full PM register range and support power domains. + */ +- res = platform_get_resource(pdev, IORESOURCE_MEM, 1); +- if (res) { +- pm->asb = devm_ioremap_resource(dev, res); +- if (IS_ERR(pm->asb)) +- return PTR_ERR(pm->asb); +- +- ret = devm_mfd_add_devices(dev, -1, +- bcm2835_power_devs, +- ARRAY_SIZE(bcm2835_power_devs), +- NULL, 0, NULL); +- if (ret) +- return ret; +- } +- ++ if (pm->asb) ++ return devm_mfd_add_devices(dev, -1, bcm2835_power_devs, ++ ARRAY_SIZE(bcm2835_power_devs), ++ NULL, 0, NULL); + return 0; + } + + static const struct of_device_id bcm2835_pm_of_match[] = { + { .compatible = "brcm,bcm2835-pm-wdt", }, + { .compatible = "brcm,bcm2835-pm", }, ++ { .compatible = "brcm,bcm2711-pm", }, + {}, + }; + MODULE_DEVICE_TABLE(of, bcm2835_pm_of_match); +diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig +index 9fee639ee5c8..4bb231013009 100644 +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -104,6 +104,8 @@ config AX88796B_PHY + config BROADCOM_PHY + tristate "Broadcom 54XX PHYs" + select BCM_NET_PHYLIB ++ select BCM_NET_PHYPTP if NETWORK_PHY_TIMESTAMPING ++ depends on PTP_1588_CLOCK_OPTIONAL + help + Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464, + BCM5481, BCM54810 and BCM5482 PHYs. +@@ -160,6 +162,9 @@ config BCM_CYGNUS_PHY + config BCM_NET_PHYLIB + tristate + ++config BCM_NET_PHYPTP ++ tristate ++ + config CICADA_PHY + tristate "Cicada PHYs" + help +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index b12b1d86fc99..f7138d3c896b 100644 +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -47,6 +47,7 @@ obj-$(CONFIG_BCM84881_PHY) += bcm84881.o + obj-$(CONFIG_BCM87XX_PHY) += bcm87xx.o + obj-$(CONFIG_BCM_CYGNUS_PHY) += bcm-cygnus.o + obj-$(CONFIG_BCM_NET_PHYLIB) += bcm-phy-lib.o ++obj-$(CONFIG_BCM_NET_PHYPTP) += bcm-phy-ptp.o + obj-$(CONFIG_BROADCOM_PHY) += broadcom.o + obj-$(CONFIG_CICADA_PHY) += cicada.o + obj-$(CONFIG_CORTINA_PHY) += cortina.o +diff --git a/drivers/net/phy/bcm-phy-lib.h b/drivers/net/phy/bcm-phy-lib.h +index c3842f87c33b..9902fb182099 100644 +--- a/drivers/net/phy/bcm-phy-lib.h ++++ b/drivers/net/phy/bcm-phy-lib.h +@@ -87,4 +87,23 @@ int bcm_phy_cable_test_start_rdb(struct phy_device *phydev); + int bcm_phy_cable_test_start(struct phy_device *phydev); + int bcm_phy_cable_test_get_status(struct phy_device *phydev, bool *finished); + ++#if IS_ENABLED(CONFIG_BCM_NET_PHYPTP) ++struct bcm_ptp_private *bcm_ptp_probe(struct phy_device *phydev); ++void bcm_ptp_config_init(struct phy_device *phydev); ++void bcm_ptp_stop(struct bcm_ptp_private *priv); ++#else ++static inline struct bcm_ptp_private *bcm_ptp_probe(struct phy_device *phydev) ++{ ++ return NULL; ++} ++ ++static inline void bcm_ptp_config_init(struct phy_device *phydev) ++{ ++} ++ ++static inline void bcm_ptp_stop(struct bcm_ptp_private *priv) ++{ ++} ++#endif ++ + #endif /* _LINUX_BCM_PHY_LIB_H */ +diff --git a/drivers/net/phy/bcm-phy-ptp.c b/drivers/net/phy/bcm-phy-ptp.c +new file mode 100644 +index 000000000000..ef00d6163061 +--- /dev/null ++++ b/drivers/net/phy/bcm-phy-ptp.c +@@ -0,0 +1,944 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2022 Meta Platforms Inc. ++ * Copyright (C) 2022 Jonathan Lemon <jonathan.lemon@gmail.com> ++ */ ++ ++#include <asm/unaligned.h> ++#include <linux/mii.h> ++#include <linux/phy.h> ++#include <linux/ptp_classify.h> ++#include <linux/ptp_clock_kernel.h> ++#include <linux/net_tstamp.h> ++#include <linux/netdevice.h> ++#include <linux/workqueue.h> ++ ++#include "bcm-phy-lib.h" ++ ++/* IEEE 1588 Expansion registers */ ++#define SLICE_CTRL 0x0810 ++#define SLICE_TX_EN BIT(0) ++#define SLICE_RX_EN BIT(8) ++#define TX_EVENT_MODE 0x0811 ++#define MODE_TX_UPDATE_CF BIT(0) ++#define MODE_TX_REPLACE_TS_CF BIT(1) ++#define MODE_TX_REPLACE_TS GENMASK(1, 0) ++#define RX_EVENT_MODE 0x0819 ++#define MODE_RX_UPDATE_CF BIT(0) ++#define MODE_RX_INSERT_TS_48 BIT(1) ++#define MODE_RX_INSERT_TS_64 GENMASK(1, 0) ++ ++#define MODE_EVT_SHIFT_SYNC 0 ++#define MODE_EVT_SHIFT_DELAY_REQ 2 ++#define MODE_EVT_SHIFT_PDELAY_REQ 4 ++#define MODE_EVT_SHIFT_PDELAY_RESP 6 ++ ++#define MODE_SEL_SHIFT_PORT 0 ++#define MODE_SEL_SHIFT_CPU 8 ++ ++#define RX_MODE_SEL(sel, evt, act) \ ++ (((MODE_RX_##act) << (MODE_EVT_SHIFT_##evt)) << (MODE_SEL_SHIFT_##sel)) ++ ++#define TX_MODE_SEL(sel, evt, act) \ ++ (((MODE_TX_##act) << (MODE_EVT_SHIFT_##evt)) << (MODE_SEL_SHIFT_##sel)) ++ ++/* needs global TS capture first */ ++#define TX_TS_CAPTURE 0x0821 ++#define TX_TS_CAP_EN BIT(0) ++#define RX_TS_CAPTURE 0x0822 ++#define RX_TS_CAP_EN BIT(0) ++ ++#define TIME_CODE_0 0x0854 ++#define TIME_CODE_1 0x0855 ++#define TIME_CODE_2 0x0856 ++#define TIME_CODE_3 0x0857 ++#define TIME_CODE_4 0x0858 ++ ++#define DPLL_SELECT 0x085b ++#define DPLL_HB_MODE2 BIT(6) ++ ++#define SHADOW_CTRL 0x085c ++#define SHADOW_LOAD 0x085d ++#define TIME_CODE_LOAD BIT(10) ++#define SYNC_OUT_LOAD BIT(9) ++#define NCO_TIME_LOAD BIT(7) ++#define FREQ_LOAD BIT(6) ++#define INTR_MASK 0x085e ++#define INTR_STATUS 0x085f ++#define INTC_FSYNC BIT(0) ++#define INTC_SOP BIT(1) ++ ++#define NCO_FREQ_LSB 0x0873 ++#define NCO_FREQ_MSB 0x0874 ++ ++#define NCO_TIME_0 0x0875 ++#define NCO_TIME_1 0x0876 ++#define NCO_TIME_2_CTRL 0x0877 ++#define FREQ_MDIO_SEL BIT(14) ++ ++#define SYNC_OUT_0 0x0878 ++#define SYNC_OUT_1 0x0879 ++#define SYNC_OUT_2 0x087a ++ ++#define SYNC_IN_DIVIDER 0x087b ++ ++#define SYNOUT_TS_0 0x087c ++#define SYNOUT_TS_1 0x087d ++#define SYNOUT_TS_2 0x087e ++ ++#define NSE_CTRL 0x087f ++#define NSE_GMODE_EN GENMASK(15, 14) ++#define NSE_CAPTURE_EN BIT(13) ++#define NSE_INIT BIT(12) ++#define NSE_CPU_FRAMESYNC BIT(5) ++#define NSE_SYNC1_FRAMESYNC BIT(3) ++#define NSE_FRAMESYNC_MASK GENMASK(5, 2) ++#define NSE_PEROUT_EN BIT(1) ++#define NSE_ONESHOT_EN BIT(0) ++#define NSE_SYNC_OUT_MASK GENMASK(1, 0) ++ ++#define TS_READ_CTRL 0x0885 ++#define TS_READ_START BIT(0) ++#define TS_READ_END BIT(1) ++ ++#define HB_REG_0 0x0886 ++#define HB_REG_1 0x0887 ++#define HB_REG_2 0x0888 ++#define HB_REG_3 0x08ec ++#define HB_REG_4 0x08ed ++#define HB_STAT_CTRL 0x088e ++#define HB_READ_START BIT(10) ++#define HB_READ_END BIT(11) ++#define HB_READ_MASK GENMASK(11, 10) ++ ++#define TS_REG_0 0x0889 ++#define TS_REG_1 0x088a ++#define TS_REG_2 0x088b ++#define TS_REG_3 0x08c4 ++ ++#define TS_INFO_0 0x088c ++#define TS_INFO_1 0x088d ++ ++#define TIMECODE_CTRL 0x08c3 ++#define TX_TIMECODE_SEL GENMASK(7, 0) ++#define RX_TIMECODE_SEL GENMASK(15, 8) ++ ++#define TIME_SYNC 0x0ff5 ++#define TIME_SYNC_EN BIT(0) ++ ++struct bcm_ptp_private { ++ struct phy_device *phydev; ++ struct mii_timestamper mii_ts; ++ struct ptp_clock *ptp_clock; ++ struct ptp_clock_info ptp_info; ++ struct ptp_pin_desc pin; ++ struct mutex mutex; ++ struct sk_buff_head tx_queue; ++ int tx_type; ++ bool hwts_rx; ++ u16 nse_ctrl; ++ bool pin_active; ++ struct delayed_work pin_work; ++}; ++ ++struct bcm_ptp_skb_cb { ++ unsigned long timeout; ++ u16 seq_id; ++ u8 msgtype; ++ bool discard; ++}; ++ ++struct bcm_ptp_capture { ++ ktime_t hwtstamp; ++ u16 seq_id; ++ u8 msgtype; ++ bool tx_dir; ++}; ++ ++#define BCM_SKB_CB(skb) ((struct bcm_ptp_skb_cb *)(skb)->cb) ++#define SKB_TS_TIMEOUT 10 /* jiffies */ ++ ++#define BCM_MAX_PULSE_8NS ((1U << 9) - 1) ++#define BCM_MAX_PERIOD_8NS ((1U << 30) - 1) ++ ++#define BRCM_PHY_MODEL(phydev) \ ++ ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask) ++ ++static struct bcm_ptp_private *mii2priv(struct mii_timestamper *mii_ts) ++{ ++ return container_of(mii_ts, struct bcm_ptp_private, mii_ts); ++} ++ ++static struct bcm_ptp_private *ptp2priv(struct ptp_clock_info *info) ++{ ++ return container_of(info, struct bcm_ptp_private, ptp_info); ++} ++ ++static void bcm_ptp_get_framesync_ts(struct phy_device *phydev, ++ struct timespec64 *ts) ++{ ++ u16 hb[4]; ++ ++ bcm_phy_write_exp(phydev, HB_STAT_CTRL, HB_READ_START); ++ ++ hb[0] = bcm_phy_read_exp(phydev, HB_REG_0); ++ hb[1] = bcm_phy_read_exp(phydev, HB_REG_1); ++ hb[2] = bcm_phy_read_exp(phydev, HB_REG_2); ++ hb[3] = bcm_phy_read_exp(phydev, HB_REG_3); ++ ++ bcm_phy_write_exp(phydev, HB_STAT_CTRL, HB_READ_END); ++ bcm_phy_write_exp(phydev, HB_STAT_CTRL, 0); ++ ++ ts->tv_sec = (hb[3] << 16) | hb[2]; ++ ts->tv_nsec = (hb[1] << 16) | hb[0]; ++} ++ ++static u16 bcm_ptp_framesync_disable(struct phy_device *phydev, u16 orig_ctrl) ++{ ++ u16 ctrl = orig_ctrl & ~(NSE_FRAMESYNC_MASK | NSE_CAPTURE_EN); ++ ++ bcm_phy_write_exp(phydev, NSE_CTRL, ctrl); ++ ++ return ctrl; ++} ++ ++static void bcm_ptp_framesync_restore(struct phy_device *phydev, u16 orig_ctrl) ++{ ++ if (orig_ctrl & NSE_FRAMESYNC_MASK) ++ bcm_phy_write_exp(phydev, NSE_CTRL, orig_ctrl); ++} ++ ++static void bcm_ptp_framesync(struct phy_device *phydev, u16 ctrl) ++{ ++ /* trigger framesync - must have 0->1 transition. */ ++ bcm_phy_write_exp(phydev, NSE_CTRL, ctrl | NSE_CPU_FRAMESYNC); ++} ++ ++static int bcm_ptp_framesync_ts(struct phy_device *phydev, ++ struct ptp_system_timestamp *sts, ++ struct timespec64 *ts, ++ u16 orig_ctrl) ++{ ++ u16 ctrl, reg; ++ int i; ++ ++ ctrl = bcm_ptp_framesync_disable(phydev, orig_ctrl); ++ ++ ptp_read_system_prets(sts); ++ ++ /* trigger framesync + capture */ ++ bcm_ptp_framesync(phydev, ctrl | NSE_CAPTURE_EN); ++ ++ ptp_read_system_postts(sts); ++ ++ /* poll for FSYNC interrupt from TS capture */ ++ for (i = 0; i < 10; i++) { ++ reg = bcm_phy_read_exp(phydev, INTR_STATUS); ++ if (reg & INTC_FSYNC) { ++ bcm_ptp_get_framesync_ts(phydev, ts); ++ break; ++ } ++ } ++ ++ bcm_ptp_framesync_restore(phydev, orig_ctrl); ++ ++ return reg & INTC_FSYNC ? 0 : -ETIMEDOUT; ++} ++ ++static int bcm_ptp_gettimex(struct ptp_clock_info *info, ++ struct timespec64 *ts, ++ struct ptp_system_timestamp *sts) ++{ ++ struct bcm_ptp_private *priv = ptp2priv(info); ++ int err; ++ ++ mutex_lock(&priv->mutex); ++ err = bcm_ptp_framesync_ts(priv->phydev, sts, ts, priv->nse_ctrl); ++ mutex_unlock(&priv->mutex); ++ ++ return err; ++} ++ ++static int bcm_ptp_settime_locked(struct bcm_ptp_private *priv, ++ const struct timespec64 *ts) ++{ ++ struct phy_device *phydev = priv->phydev; ++ u16 ctrl; ++ u64 ns; ++ ++ ctrl = bcm_ptp_framesync_disable(phydev, priv->nse_ctrl); ++ ++ /* set up time code */ ++ bcm_phy_write_exp(phydev, TIME_CODE_0, ts->tv_nsec); ++ bcm_phy_write_exp(phydev, TIME_CODE_1, ts->tv_nsec >> 16); ++ bcm_phy_write_exp(phydev, TIME_CODE_2, ts->tv_sec); ++ bcm_phy_write_exp(phydev, TIME_CODE_3, ts->tv_sec >> 16); ++ bcm_phy_write_exp(phydev, TIME_CODE_4, ts->tv_sec >> 32); ++ ++ /* set NCO counter to match */ ++ ns = timespec64_to_ns(ts); ++ bcm_phy_write_exp(phydev, NCO_TIME_0, ns >> 4); ++ bcm_phy_write_exp(phydev, NCO_TIME_1, ns >> 20); ++ bcm_phy_write_exp(phydev, NCO_TIME_2_CTRL, (ns >> 36) & 0xfff); ++ ++ /* set up load on next frame sync (auto-clears due to NSE_INIT) */ ++ bcm_phy_write_exp(phydev, SHADOW_LOAD, TIME_CODE_LOAD | NCO_TIME_LOAD); ++ ++ /* must have NSE_INIT in order to write time code */ ++ bcm_ptp_framesync(phydev, ctrl | NSE_INIT); ++ ++ bcm_ptp_framesync_restore(phydev, priv->nse_ctrl); ++ ++ return 0; ++} ++ ++static int bcm_ptp_settime(struct ptp_clock_info *info, ++ const struct timespec64 *ts) ++{ ++ struct bcm_ptp_private *priv = ptp2priv(info); ++ int err; ++ ++ mutex_lock(&priv->mutex); ++ err = bcm_ptp_settime_locked(priv, ts); ++ mutex_unlock(&priv->mutex); ++ ++ return err; ++} ++ ++static int bcm_ptp_adjtime_locked(struct bcm_ptp_private *priv, ++ s64 delta_ns) ++{ ++ struct timespec64 ts; ++ int err; ++ s64 ns; ++ ++ err = bcm_ptp_framesync_ts(priv->phydev, NULL, &ts, priv->nse_ctrl); ++ if (!err) { ++ ns = timespec64_to_ns(&ts) + delta_ns; ++ ts = ns_to_timespec64(ns); ++ err = bcm_ptp_settime_locked(priv, &ts); ++ } ++ return err; ++} ++ ++static int bcm_ptp_adjtime(struct ptp_clock_info *info, s64 delta_ns) ++{ ++ struct bcm_ptp_private *priv = ptp2priv(info); ++ int err; ++ ++ mutex_lock(&priv->mutex); ++ err = bcm_ptp_adjtime_locked(priv, delta_ns); ++ mutex_unlock(&priv->mutex); ++ ++ return err; ++} ++ ++/* A 125Mhz clock should adjust 8ns per pulse. ++ * The frequency adjustment base is 0x8000 0000, or 8*2^28. ++ * ++ * Frequency adjustment is ++ * adj = scaled_ppm * 8*2^28 / (10^6 * 2^16) ++ * which simplifies to: ++ * adj = scaled_ppm * 2^9 / 5^6 ++ */ ++static int bcm_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm) ++{ ++ struct bcm_ptp_private *priv = ptp2priv(info); ++ int neg_adj = 0; ++ u32 diff, freq; ++ u16 ctrl; ++ u64 adj; ++ ++ if (scaled_ppm < 0) { ++ neg_adj = 1; ++ scaled_ppm = -scaled_ppm; ++ } ++ ++ adj = scaled_ppm << 9; ++ diff = div_u64(adj, 15625); ++ freq = (8 << 28) + (neg_adj ? -diff : diff); ++ ++ mutex_lock(&priv->mutex); ++ ++ ctrl = bcm_ptp_framesync_disable(priv->phydev, priv->nse_ctrl); ++ ++ bcm_phy_write_exp(priv->phydev, NCO_FREQ_LSB, freq); ++ bcm_phy_write_exp(priv->phydev, NCO_FREQ_MSB, freq >> 16); ++ ++ bcm_phy_write_exp(priv->phydev, NCO_TIME_2_CTRL, FREQ_MDIO_SEL); ++ ++ /* load on next framesync */ ++ bcm_phy_write_exp(priv->phydev, SHADOW_LOAD, FREQ_LOAD); ++ ++ bcm_ptp_framesync(priv->phydev, ctrl); ++ ++ /* clear load */ ++ bcm_phy_write_exp(priv->phydev, SHADOW_LOAD, 0); ++ ++ bcm_ptp_framesync_restore(priv->phydev, priv->nse_ctrl); ++ ++ mutex_unlock(&priv->mutex); ++ ++ return 0; ++} ++ ++static bool bcm_ptp_rxtstamp(struct mii_timestamper *mii_ts, ++ struct sk_buff *skb, int type) ++{ ++ struct bcm_ptp_private *priv = mii2priv(mii_ts); ++ struct skb_shared_hwtstamps *hwts; ++ struct ptp_header *header; ++ u32 sec, nsec; ++ u8 *data; ++ int off; ++ ++ if (!priv->hwts_rx) ++ return false; ++ ++ header = ptp_parse_header(skb, type); ++ if (!header) ++ return false; ++ ++ data = (u8 *)(header + 1); ++ sec = get_unaligned_be32(data); ++ nsec = get_unaligned_be32(data + 4); ++ ++ hwts = skb_hwtstamps(skb); ++ hwts->hwtstamp = ktime_set(sec, nsec); ++ ++ off = data - skb->data + 8; ++ if (off < skb->len) { ++ memmove(data, data + 8, skb->len - off); ++ __pskb_trim(skb, skb->len - 8); ++ } ++ ++ return false; ++} ++ ++static bool bcm_ptp_get_tstamp(struct bcm_ptp_private *priv, ++ struct bcm_ptp_capture *capts) ++{ ++ struct phy_device *phydev = priv->phydev; ++ u16 ts[4], reg; ++ u32 sec, nsec; ++ ++ mutex_lock(&priv->mutex); ++ ++ reg = bcm_phy_read_exp(phydev, INTR_STATUS); ++ if ((reg & INTC_SOP) == 0) { ++ mutex_unlock(&priv->mutex); ++ return false; ++ } ++ ++ bcm_phy_write_exp(phydev, TS_READ_CTRL, TS_READ_START); ++ ++ ts[0] = bcm_phy_read_exp(phydev, TS_REG_0); ++ ts[1] = bcm_phy_read_exp(phydev, TS_REG_1); ++ ts[2] = bcm_phy_read_exp(phydev, TS_REG_2); ++ ts[3] = bcm_phy_read_exp(phydev, TS_REG_3); ++ ++ /* not in be32 format for some reason */ ++ capts->seq_id = bcm_phy_read_exp(priv->phydev, TS_INFO_0); ++ ++ reg = bcm_phy_read_exp(phydev, TS_INFO_1); ++ capts->msgtype = reg >> 12; ++ capts->tx_dir = !!(reg & BIT(11)); ++ ++ bcm_phy_write_exp(phydev, TS_READ_CTRL, TS_READ_END); ++ bcm_phy_write_exp(phydev, TS_READ_CTRL, 0); ++ ++ mutex_unlock(&priv->mutex); ++ ++ sec = (ts[3] << 16) | ts[2]; ++ nsec = (ts[1] << 16) | ts[0]; ++ capts->hwtstamp = ktime_set(sec, nsec); ++ ++ return true; ++} ++ ++static void bcm_ptp_match_tstamp(struct bcm_ptp_private *priv, ++ struct bcm_ptp_capture *capts) ++{ ++ struct skb_shared_hwtstamps hwts; ++ struct sk_buff *skb, *ts_skb; ++ unsigned long flags; ++ bool first = false; ++ ++ ts_skb = NULL; ++ spin_lock_irqsave(&priv->tx_queue.lock, flags); ++ skb_queue_walk(&priv->tx_queue, skb) { ++ if (BCM_SKB_CB(skb)->seq_id == capts->seq_id && ++ BCM_SKB_CB(skb)->msgtype == capts->msgtype) { ++ first = skb_queue_is_first(&priv->tx_queue, skb); ++ __skb_unlink(skb, &priv->tx_queue); ++ ts_skb = skb; ++ break; ++ } ++ } ++ spin_unlock_irqrestore(&priv->tx_queue.lock, flags); ++ ++ /* TX captures one-step packets, discard them if needed. */ ++ if (ts_skb) { ++ if (BCM_SKB_CB(ts_skb)->discard) { ++ kfree_skb(ts_skb); ++ } else { ++ memset(&hwts, 0, sizeof(hwts)); ++ hwts.hwtstamp = capts->hwtstamp; ++ skb_complete_tx_timestamp(ts_skb, &hwts); ++ } ++ } ++ ++ /* not first match, try and expire entries */ ++ if (!first) { ++ while ((skb = skb_dequeue(&priv->tx_queue))) { ++ if (!time_after(jiffies, BCM_SKB_CB(skb)->timeout)) { ++ skb_queue_head(&priv->tx_queue, skb); ++ break; ++ } ++ kfree_skb(skb); ++ } ++ } ++} ++ ++static long bcm_ptp_do_aux_work(struct ptp_clock_info *info) ++{ ++ struct bcm_ptp_private *priv = ptp2priv(info); ++ struct bcm_ptp_capture capts; ++ bool reschedule = false; ++ ++ while (!skb_queue_empty_lockless(&priv->tx_queue)) { ++ if (!bcm_ptp_get_tstamp(priv, &capts)) { ++ reschedule = true; ++ break; ++ } ++ bcm_ptp_match_tstamp(priv, &capts); ++ } ++ ++ return reschedule ? 1 : -1; ++} ++ ++static int bcm_ptp_cancel_func(struct bcm_ptp_private *priv) ++{ ++ if (!priv->pin_active) ++ return 0; ++ ++ priv->pin_active = false; ++ ++ priv->nse_ctrl &= ~(NSE_SYNC_OUT_MASK | NSE_SYNC1_FRAMESYNC | ++ NSE_CAPTURE_EN); ++ bcm_phy_write_exp(priv->phydev, NSE_CTRL, priv->nse_ctrl); ++ ++ cancel_delayed_work_sync(&priv->pin_work); ++ ++ return 0; ++} ++ ++static void bcm_ptp_perout_work(struct work_struct *pin_work) ++{ ++ struct bcm_ptp_private *priv = ++ container_of(pin_work, struct bcm_ptp_private, pin_work.work); ++ struct phy_device *phydev = priv->phydev; ++ struct timespec64 ts; ++ u64 ns, next; ++ u16 ctrl; ++ ++ mutex_lock(&priv->mutex); ++ ++ /* no longer running */ ++ if (!priv->pin_active) { ++ mutex_unlock(&priv->mutex); ++ return; ++ } ++ ++ bcm_ptp_framesync_ts(phydev, NULL, &ts, priv->nse_ctrl); ++ ++ /* this is 1PPS only */ ++ next = NSEC_PER_SEC - ts.tv_nsec; ++ ts.tv_sec += next < NSEC_PER_MSEC ? 2 : 1; ++ ts.tv_nsec = 0; ++ ++ ns = timespec64_to_ns(&ts); ++ ++ /* force 0->1 transition for ONESHOT */ ++ ctrl = bcm_ptp_framesync_disable(phydev, ++ priv->nse_ctrl & ~NSE_ONESHOT_EN); ++ ++ bcm_phy_write_exp(phydev, SYNOUT_TS_0, ns & 0xfff0); ++ bcm_phy_write_exp(phydev, SYNOUT_TS_1, ns >> 16); ++ bcm_phy_write_exp(phydev, SYNOUT_TS_2, ns >> 32); ++ ++ /* load values on next framesync */ ++ bcm_phy_write_exp(phydev, SHADOW_LOAD, SYNC_OUT_LOAD); ++ ++ bcm_ptp_framesync(phydev, ctrl | NSE_ONESHOT_EN | NSE_INIT); ++ ++ priv->nse_ctrl |= NSE_ONESHOT_EN; ++ bcm_ptp_framesync_restore(phydev, priv->nse_ctrl); ++ ++ mutex_unlock(&priv->mutex); ++ ++ next = next + NSEC_PER_MSEC; ++ schedule_delayed_work(&priv->pin_work, nsecs_to_jiffies(next)); ++} ++ ++static int bcm_ptp_perout_locked(struct bcm_ptp_private *priv, ++ struct ptp_perout_request *req, int on) ++{ ++ struct phy_device *phydev = priv->phydev; ++ u64 period, pulse; ++ u16 val; ++ ++ if (!on) ++ return bcm_ptp_cancel_func(priv); ++ ++ /* 1PPS */ ++ if (req->period.sec != 1 || req->period.nsec != 0) ++ return -EINVAL; ++ ++ period = BCM_MAX_PERIOD_8NS; /* write nonzero value */ ++ ++ if (req->flags & PTP_PEROUT_PHASE) ++ return -EOPNOTSUPP; ++ ++ if (req->flags & PTP_PEROUT_DUTY_CYCLE) ++ pulse = ktime_to_ns(ktime_set(req->on.sec, req->on.nsec)); ++ else ++ pulse = (u64)BCM_MAX_PULSE_8NS << 3; ++ ++ /* convert to 8ns units */ ++ pulse >>= 3; ++ ++ if (!pulse || pulse > period || pulse > BCM_MAX_PULSE_8NS) ++ return -EINVAL; ++ ++ bcm_phy_write_exp(phydev, SYNC_OUT_0, period); ++ ++ val = ((pulse & 0x3) << 14) | ((period >> 16) & 0x3fff); ++ bcm_phy_write_exp(phydev, SYNC_OUT_1, val); ++ ++ val = ((pulse >> 2) & 0x7f) | (pulse << 7); ++ bcm_phy_write_exp(phydev, SYNC_OUT_2, val); ++ ++ if (priv->pin_active) ++ cancel_delayed_work_sync(&priv->pin_work); ++ ++ priv->pin_active = true; ++ INIT_DELAYED_WORK(&priv->pin_work, bcm_ptp_perout_work); ++ schedule_delayed_work(&priv->pin_work, 0); ++ ++ return 0; ++} ++ ++static void bcm_ptp_extts_work(struct work_struct *pin_work) ++{ ++ struct bcm_ptp_private *priv = ++ container_of(pin_work, struct bcm_ptp_private, pin_work.work); ++ struct phy_device *phydev = priv->phydev; ++ struct ptp_clock_event event; ++ struct timespec64 ts; ++ u16 reg; ++ ++ mutex_lock(&priv->mutex); ++ ++ /* no longer running */ ++ if (!priv->pin_active) { ++ mutex_unlock(&priv->mutex); ++ return; ++ } ++ ++ reg = bcm_phy_read_exp(phydev, INTR_STATUS); ++ if ((reg & INTC_FSYNC) == 0) ++ goto out; ++ ++ bcm_ptp_get_framesync_ts(phydev, &ts); ++ ++ event.index = 0; ++ event.type = PTP_CLOCK_EXTTS; ++ event.timestamp = timespec64_to_ns(&ts); ++ ptp_clock_event(priv->ptp_clock, &event); ++ ++out: ++ mutex_unlock(&priv->mutex); ++ schedule_delayed_work(&priv->pin_work, HZ / 4); ++} ++ ++static int bcm_ptp_extts_locked(struct bcm_ptp_private *priv, int on) ++{ ++ struct phy_device *phydev = priv->phydev; ++ ++ if (!on) ++ return bcm_ptp_cancel_func(priv); ++ ++ if (priv->pin_active) ++ cancel_delayed_work_sync(&priv->pin_work); ++ ++ bcm_ptp_framesync_disable(phydev, priv->nse_ctrl); ++ ++ priv->nse_ctrl |= NSE_SYNC1_FRAMESYNC | NSE_CAPTURE_EN; ++ ++ bcm_ptp_framesync_restore(phydev, priv->nse_ctrl); ++ ++ priv->pin_active = true; ++ INIT_DELAYED_WORK(&priv->pin_work, bcm_ptp_extts_work); ++ schedule_delayed_work(&priv->pin_work, 0); ++ ++ return 0; ++} ++ ++static int bcm_ptp_enable(struct ptp_clock_info *info, ++ struct ptp_clock_request *rq, int on) ++{ ++ struct bcm_ptp_private *priv = ptp2priv(info); ++ int err = -EBUSY; ++ ++ mutex_lock(&priv->mutex); ++ ++ switch (rq->type) { ++ case PTP_CLK_REQ_PEROUT: ++ if (priv->pin.func == PTP_PF_PEROUT) ++ err = bcm_ptp_perout_locked(priv, &rq->perout, on); ++ break; ++ case PTP_CLK_REQ_EXTTS: ++ if (priv->pin.func == PTP_PF_EXTTS) ++ err = bcm_ptp_extts_locked(priv, on); ++ break; ++ default: ++ err = -EOPNOTSUPP; ++ break; ++ } ++ ++ mutex_unlock(&priv->mutex); ++ ++ return err; ++} ++ ++static int bcm_ptp_verify(struct ptp_clock_info *info, unsigned int pin, ++ enum ptp_pin_function func, unsigned int chan) ++{ ++ switch (func) { ++ case PTP_PF_NONE: ++ case PTP_PF_EXTTS: ++ case PTP_PF_PEROUT: ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ return 0; ++} ++ ++static const struct ptp_clock_info bcm_ptp_clock_info = { ++ .owner = THIS_MODULE, ++ .name = KBUILD_MODNAME, ++ .max_adj = 100000000, ++ .gettimex64 = bcm_ptp_gettimex, ++ .settime64 = bcm_ptp_settime, ++ .adjtime = bcm_ptp_adjtime, ++ .adjfine = bcm_ptp_adjfine, ++ .enable = bcm_ptp_enable, ++ .verify = bcm_ptp_verify, ++ .do_aux_work = bcm_ptp_do_aux_work, ++ .n_pins = 1, ++ .n_per_out = 1, ++ .n_ext_ts = 1, ++}; ++ ++static void bcm_ptp_txtstamp(struct mii_timestamper *mii_ts, ++ struct sk_buff *skb, int type) ++{ ++ struct bcm_ptp_private *priv = mii2priv(mii_ts); ++ struct ptp_header *hdr; ++ bool discard = false; ++ int msgtype; ++ ++ hdr = ptp_parse_header(skb, type); ++ if (!hdr) ++ goto out; ++ msgtype = ptp_get_msgtype(hdr, type); ++ ++ switch (priv->tx_type) { ++ case HWTSTAMP_TX_ONESTEP_P2P: ++ if (msgtype == PTP_MSGTYPE_PDELAY_RESP) ++ discard = true; ++ fallthrough; ++ case HWTSTAMP_TX_ONESTEP_SYNC: ++ if (msgtype == PTP_MSGTYPE_SYNC) ++ discard = true; ++ fallthrough; ++ case HWTSTAMP_TX_ON: ++ BCM_SKB_CB(skb)->timeout = jiffies + SKB_TS_TIMEOUT; ++ BCM_SKB_CB(skb)->seq_id = be16_to_cpu(hdr->sequence_id); ++ BCM_SKB_CB(skb)->msgtype = msgtype; ++ BCM_SKB_CB(skb)->discard = discard; ++ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; ++ skb_queue_tail(&priv->tx_queue, skb); ++ ptp_schedule_worker(priv->ptp_clock, 0); ++ return; ++ default: ++ break; ++ } ++ ++out: ++ kfree_skb(skb); ++} ++ ++static int bcm_ptp_hwtstamp(struct mii_timestamper *mii_ts, ++ struct ifreq *ifr) ++{ ++ struct bcm_ptp_private *priv = mii2priv(mii_ts); ++ struct hwtstamp_config cfg; ++ u16 mode, ctrl; ++ ++ if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) ++ return -EFAULT; ++ ++ switch (cfg.rx_filter) { ++ case HWTSTAMP_FILTER_NONE: ++ priv->hwts_rx = false; ++ break; ++ case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: ++ case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: ++ case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: ++ case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: ++ case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: ++ case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: ++ case HWTSTAMP_FILTER_PTP_V2_EVENT: ++ case HWTSTAMP_FILTER_PTP_V2_SYNC: ++ case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: ++ cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; ++ priv->hwts_rx = true; ++ break; ++ default: ++ return -ERANGE; ++ } ++ ++ priv->tx_type = cfg.tx_type; ++ ++ ctrl = priv->hwts_rx ? SLICE_RX_EN : 0; ++ ctrl |= priv->tx_type != HWTSTAMP_TX_OFF ? SLICE_TX_EN : 0; ++ ++ mode = TX_MODE_SEL(PORT, SYNC, REPLACE_TS) | ++ TX_MODE_SEL(PORT, DELAY_REQ, REPLACE_TS) | ++ TX_MODE_SEL(PORT, PDELAY_REQ, REPLACE_TS) | ++ TX_MODE_SEL(PORT, PDELAY_RESP, REPLACE_TS); ++ ++ bcm_phy_write_exp(priv->phydev, TX_EVENT_MODE, mode); ++ ++ mode = RX_MODE_SEL(PORT, SYNC, INSERT_TS_64) | ++ RX_MODE_SEL(PORT, DELAY_REQ, INSERT_TS_64) | ++ RX_MODE_SEL(PORT, PDELAY_REQ, INSERT_TS_64) | ++ RX_MODE_SEL(PORT, PDELAY_RESP, INSERT_TS_64); ++ ++ bcm_phy_write_exp(priv->phydev, RX_EVENT_MODE, mode); ++ ++ bcm_phy_write_exp(priv->phydev, SLICE_CTRL, ctrl); ++ ++ if (ctrl & SLICE_TX_EN) ++ bcm_phy_write_exp(priv->phydev, TX_TS_CAPTURE, TX_TS_CAP_EN); ++ else ++ ptp_cancel_worker_sync(priv->ptp_clock); ++ ++ /* purge existing data */ ++ skb_queue_purge(&priv->tx_queue); ++ ++ return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; ++} ++ ++static int bcm_ptp_ts_info(struct mii_timestamper *mii_ts, ++ struct ethtool_ts_info *ts_info) ++{ ++ struct bcm_ptp_private *priv = mii2priv(mii_ts); ++ ++ ts_info->phc_index = ptp_clock_index(priv->ptp_clock); ++ ts_info->so_timestamping = ++ SOF_TIMESTAMPING_TX_HARDWARE | ++ SOF_TIMESTAMPING_RX_HARDWARE | ++ SOF_TIMESTAMPING_RAW_HARDWARE; ++ ts_info->tx_types = ++ BIT(HWTSTAMP_TX_ON) | ++ BIT(HWTSTAMP_TX_OFF) | ++ BIT(HWTSTAMP_TX_ONESTEP_SYNC) | ++ BIT(HWTSTAMP_TX_ONESTEP_P2P); ++ ts_info->rx_filters = ++ BIT(HWTSTAMP_FILTER_NONE) | ++ BIT(HWTSTAMP_FILTER_PTP_V2_EVENT); ++ ++ return 0; ++} ++ ++void bcm_ptp_stop(struct bcm_ptp_private *priv) ++{ ++ ptp_cancel_worker_sync(priv->ptp_clock); ++ bcm_ptp_cancel_func(priv); ++} ++EXPORT_SYMBOL_GPL(bcm_ptp_stop); ++ ++void bcm_ptp_config_init(struct phy_device *phydev) ++{ ++ /* init network sync engine */ ++ bcm_phy_write_exp(phydev, NSE_CTRL, NSE_GMODE_EN | NSE_INIT); ++ ++ /* enable time sync (TX/RX SOP capture) */ ++ bcm_phy_write_exp(phydev, TIME_SYNC, TIME_SYNC_EN); ++ ++ /* use sec.nsec heartbeat capture */ ++ bcm_phy_write_exp(phydev, DPLL_SELECT, DPLL_HB_MODE2); ++ ++ /* use 64 bit timecode for TX */ ++ bcm_phy_write_exp(phydev, TIMECODE_CTRL, TX_TIMECODE_SEL); ++ ++ /* always allow FREQ_LOAD on framesync */ ++ bcm_phy_write_exp(phydev, SHADOW_CTRL, FREQ_LOAD); ++ ++ bcm_phy_write_exp(phydev, SYNC_IN_DIVIDER, 1); ++} ++EXPORT_SYMBOL_GPL(bcm_ptp_config_init); ++ ++static void bcm_ptp_init(struct bcm_ptp_private *priv) ++{ ++ priv->nse_ctrl = NSE_GMODE_EN; ++ ++ mutex_init(&priv->mutex); ++ skb_queue_head_init(&priv->tx_queue); ++ ++ priv->mii_ts.rxtstamp = bcm_ptp_rxtstamp; ++ priv->mii_ts.txtstamp = bcm_ptp_txtstamp; ++ priv->mii_ts.hwtstamp = bcm_ptp_hwtstamp; ++ priv->mii_ts.ts_info = bcm_ptp_ts_info; ++ ++ priv->phydev->mii_ts = &priv->mii_ts; ++} ++ ++struct bcm_ptp_private *bcm_ptp_probe(struct phy_device *phydev) ++{ ++ struct bcm_ptp_private *priv; ++ struct ptp_clock *clock; ++ ++ switch (BRCM_PHY_MODEL(phydev)) { ++ case PHY_ID_BCM54210E: ++ break; ++ default: ++ return NULL; ++ } ++ ++ priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return ERR_PTR(-ENOMEM); ++ ++ priv->ptp_info = bcm_ptp_clock_info; ++ ++ snprintf(priv->pin.name, sizeof(priv->pin.name), "SYNC_OUT"); ++ priv->ptp_info.pin_config = &priv->pin; ++ ++ clock = ptp_clock_register(&priv->ptp_info, &phydev->mdio.dev); ++ if (IS_ERR(clock)) ++ return ERR_CAST(clock); ++ priv->ptp_clock = clock; ++ ++ priv->phydev = phydev; ++ bcm_ptp_init(priv); ++ ++ return priv; ++} ++EXPORT_SYMBOL_GPL(bcm_ptp_probe); ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c +index e36809aa6d30..876bc45ede60 100644 +--- a/drivers/net/phy/broadcom.c ++++ b/drivers/net/phy/broadcom.c +@@ -27,6 +27,11 @@ MODULE_DESCRIPTION("Broadcom PHY driver"); + MODULE_AUTHOR("Maciej W. Rozycki"); + MODULE_LICENSE("GPL"); + ++struct bcm54xx_phy_priv { ++ u64 *stats; ++ struct bcm_ptp_private *ptp; ++}; ++ + static int bcm54xx_config_clock_delay(struct phy_device *phydev) + { + int rc, val; +@@ -313,6 +318,22 @@ static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev) + bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val); + } + ++static void bcm54xx_ptp_stop(struct phy_device *phydev) ++{ ++ struct bcm54xx_phy_priv *priv = phydev->priv; ++ ++ if (priv->ptp) ++ bcm_ptp_stop(priv->ptp); ++} ++ ++static void bcm54xx_ptp_config_init(struct phy_device *phydev) ++{ ++ struct bcm54xx_phy_priv *priv = phydev->priv; ++ ++ if (priv->ptp) ++ bcm_ptp_config_init(phydev); ++} ++ + static int bcm54xx_config_init(struct phy_device *phydev) + { + int reg, err, val; +@@ -390,6 +411,8 @@ static int bcm54xx_config_init(struct phy_device *phydev) + bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val); + } + ++ bcm54xx_ptp_config_init(phydev); ++ + return 0; + } + +@@ -418,6 +441,8 @@ static int bcm54xx_suspend(struct phy_device *phydev) + { + int ret; + ++ bcm54xx_ptp_stop(phydev); ++ + /* We cannot use a read/modify/write here otherwise the PHY gets into + * a bad state where its LEDs keep flashing, thus defeating the purpose + * of low power mode. +@@ -741,10 +766,6 @@ static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev) + return IRQ_HANDLED; + } + +-struct bcm54xx_phy_priv { +- u64 *stats; +-}; +- + static int bcm54xx_phy_probe(struct phy_device *phydev) + { + struct bcm54xx_phy_priv *priv; +@@ -761,6 +782,10 @@ static int bcm54xx_phy_probe(struct phy_device *phydev) + if (!priv->stats) + return -ENOMEM; + ++ priv->ptp = bcm_ptp_probe(phydev); ++ if (IS_ERR(priv->ptp)) ++ return PTR_ERR(priv->ptp); ++ + return 0; + } + diff --git a/drivers/net/wireguard/main.c b/drivers/net/wireguard/main.c index ee4da9ab8013..d395d11eadc4 100644 --- a/drivers/net/wireguard/main.c @@ -1752,6 +3432,144 @@ index 9e849f6b0d0f..00f9a1303b93 100644 {0, 0}, }; MODULE_DEVICE_TABLE(pci, qla4xxx_pci_tbl); +diff --git a/drivers/soc/bcm/bcm2835-power.c b/drivers/soc/bcm/bcm2835-power.c +index 1e0041ec8132..5bcd047768b6 100644 +--- a/drivers/soc/bcm/bcm2835-power.c ++++ b/drivers/soc/bcm/bcm2835-power.c +@@ -126,8 +126,7 @@ + + #define ASB_AXI_BRDG_ID 0x20 + +-#define ASB_READ(reg) readl(power->asb + (reg)) +-#define ASB_WRITE(reg, val) writel(PM_PASSWORD | (val), power->asb + (reg)) ++#define BCM2835_BRDG_ID 0x62726467 + + struct bcm2835_power_domain { + struct generic_pm_domain base; +@@ -142,24 +141,41 @@ struct bcm2835_power { + void __iomem *base; + /* AXI Async bridge registers. */ + void __iomem *asb; ++ /* RPiVid bridge registers. */ ++ void __iomem *rpivid_asb; + + struct genpd_onecell_data pd_xlate; + struct bcm2835_power_domain domains[BCM2835_POWER_DOMAIN_COUNT]; + struct reset_controller_dev reset; + }; + +-static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg) ++static int bcm2835_asb_control(struct bcm2835_power *power, u32 reg, bool enable) + { ++ void __iomem *base = power->asb; + u64 start; ++ u32 val; + +- if (!reg) ++ switch (reg) { ++ case 0: + return 0; ++ case ASB_V3D_S_CTRL: ++ case ASB_V3D_M_CTRL: ++ if (power->rpivid_asb) ++ base = power->rpivid_asb; ++ break; ++ } + + start = ktime_get_ns(); + + /* Enable the module's async AXI bridges. */ +- ASB_WRITE(reg, ASB_READ(reg) & ~ASB_REQ_STOP); +- while (ASB_READ(reg) & ASB_ACK) { ++ if (enable) { ++ val = readl(base + reg) & ~ASB_REQ_STOP; ++ } else { ++ val = readl(base + reg) | ASB_REQ_STOP; ++ } ++ writel(PM_PASSWORD | val, base + reg); ++ ++ while (readl(base + reg) & ASB_ACK) { + cpu_relax(); + if (ktime_get_ns() - start >= 1000) + return -ETIMEDOUT; +@@ -168,30 +184,24 @@ static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg) + return 0; + } + +-static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg) ++static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg) + { +- u64 start; +- +- if (!reg) +- return 0; +- +- start = ktime_get_ns(); +- +- /* Enable the module's async AXI bridges. */ +- ASB_WRITE(reg, ASB_READ(reg) | ASB_REQ_STOP); +- while (!(ASB_READ(reg) & ASB_ACK)) { +- cpu_relax(); +- if (ktime_get_ns() - start >= 1000) +- return -ETIMEDOUT; +- } ++ return bcm2835_asb_control(power, reg, true); ++} + +- return 0; ++static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg) ++{ ++ return bcm2835_asb_control(power, reg, false); + } + + static int bcm2835_power_power_off(struct bcm2835_power_domain *pd, u32 pm_reg) + { + struct bcm2835_power *power = pd->power; + ++ /* We don't run this on BCM2711 */ ++ if (power->rpivid_asb) ++ return 0; ++ + /* Enable functional isolation */ + PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISFUNC); + +@@ -213,6 +223,10 @@ static int bcm2835_power_power_on(struct bcm2835_power_domain *pd, u32 pm_reg) + int inrush; + bool powok; + ++ /* We don't run this on BCM2711 */ ++ if (power->rpivid_asb) ++ return 0; ++ + /* If it was already powered on by the fw, leave it that way. */ + if (PM_READ(pm_reg) & PM_POWUP) + return 0; +@@ -626,13 +640,23 @@ static int bcm2835_power_probe(struct platform_device *pdev) + power->dev = dev; + power->base = pm->base; + power->asb = pm->asb; ++ power->rpivid_asb = pm->rpivid_asb; + +- id = ASB_READ(ASB_AXI_BRDG_ID); +- if (id != 0x62726467 /* "BRDG" */) { ++ id = readl(power->asb + ASB_AXI_BRDG_ID); ++ if (id != BCM2835_BRDG_ID /* "BRDG" */) { + dev_err(dev, "ASB register ID returned 0x%08x\n", id); + return -ENODEV; + } + ++ if (power->rpivid_asb) { ++ id = readl(power->rpivid_asb + ASB_AXI_BRDG_ID); ++ if (id != BCM2835_BRDG_ID /* "BRDG" */) { ++ dev_err(dev, "RPiVid ASB register ID returned 0x%08x\n", ++ id); ++ return -ENODEV; ++ } ++ } ++ + power->pd_xlate.domains = devm_kcalloc(dev, + ARRAY_SIZE(power_domain_names), + sizeof(*power->pd_xlate.domains), diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 68e9121c1878..ccd7566adb4b 100644 --- a/drivers/usb/core/hub.c @@ -1912,6 +3730,18 @@ index 91c8146649f5..42a73934404e 100644 * Security hooks for perf events * * @perf_event_open: +diff --git a/include/linux/mfd/bcm2835-pm.h b/include/linux/mfd/bcm2835-pm.h +index ed37dc40e82a..f70a810c55f7 100644 +--- a/include/linux/mfd/bcm2835-pm.h ++++ b/include/linux/mfd/bcm2835-pm.h +@@ -9,6 +9,7 @@ struct bcm2835_pm { + struct device *dev; + void __iomem *base; + void __iomem *asb; ++ void __iomem *rpivid_asb; + }; + + #endif /* BCM2835_MFD_PM_H */ diff --git a/include/linux/module.h b/include/linux/module.h index abd9fa916b7d..f32ae6380ffd 100644 --- a/include/linux/module.h |