diff options
Diffstat (limited to 'arm64-socionext-96b-enablement.patch')
| -rw-r--r-- | arm64-socionext-96b-enablement.patch | 201 |
1 files changed, 201 insertions, 0 deletions
diff --git a/arm64-socionext-96b-enablement.patch b/arm64-socionext-96b-enablement.patch index 8eb99ea42..0a7df3a19 100644 --- a/arm64-socionext-96b-enablement.patch +++ b/arm64-socionext-96b-enablement.patch @@ -108,6 +108,158 @@ index fd4b7f6..14e2419 100644 -- cgit v1.1 +From 33d983b5bb2929ae242606925e708092b1dfdd8f Mon Sep 17 00:00:00 2001 +From: Ard Biesheuvel <ard.biesheuvel@linaro.org> +Date: Sat, 2 Sep 2017 11:01:22 +0100 +Subject: drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS + +In their infinite wisdom, the Socionext engineers have decided +that ITS device IDs should not be hardwired, but it should be +left up to the software to assign them, by allowing it to +redirect MSI doorbell writes via a separate hardware block +that issues the doorbell write with a device ID that is +derived from the memory address. This completely breaks any +kind of isolation, or virtualization in general, for that +matter, but add support for it nonetheless. + +Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> +--- + arch/arm64/Kconfig | 8 +++++++ + drivers/irqchip/irq-gic-v3-its.c | 48 +++++++++++++++++++++++++++++++++++----- + 2 files changed, 51 insertions(+), 5 deletions(-) + +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 0df64a6..c4361df 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065 + + If unsure, say Y. + ++config SOCIONEXT_SYNQUACER_PREITS ++ bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" ++ default y ++ help ++ Socionext Synquacer SoCs implement a separate h/w block to generate ++ MSI doorbell writes with non-zero values for the device ID. ++ ++ If unsure, say Y. + endmenu + + +diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c +index e8d8934..0d372f1 100644 +--- a/drivers/irqchip/irq-gic-v3-its.c ++++ b/drivers/irqchip/irq-gic-v3-its.c +@@ -46,6 +46,7 @@ + #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) + #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) + #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) ++#define ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS (1ULL << 3) + + #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) + +@@ -99,6 +100,10 @@ struct its_node { + struct its_collection *collections; + struct list_head its_device_list; + u64 flags; ++#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS ++ u64 pre_its_base; ++ u64 pre_its_size; ++#endif + u32 ite_size; + u32 device_ids; + int numa_node; +@@ -1102,13 +1107,29 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) + u64 addr; + + its = its_dev->its; +- addr = its->phys_base + GITS_TRANSLATER; ++ ++#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS ++ if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS) ++ ++ /* ++ * The Socionext Synquacer SoC has a so-called 'pre-ITS', ++ * which maps 32-bit writes into a separate window of size ++ * '4 << device_id_bits' onto writes to GITS_TRANSLATER with ++ * device ID taken from bits [device_id_bits + 1:2] of the ++ * window offset. ++ */ ++ addr = its->pre_its_base + (its_dev->device_id << 2); ++ else ++#endif ++ addr = its->phys_base + GITS_TRANSLATER; + + msg->address_lo = lower_32_bits(addr); + msg->address_hi = upper_32_bits(addr); + msg->data = its_get_event_id(d); + +- iommu_dma_map_msi_msg(d->irq, msg); ++ if (!IS_ENABLED(CONFIG_SOCIONEXT_SYNQUACER_PREITS) || ++ !(its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS)) ++ iommu_dma_map_msi_msg(d->irq, msg); + } + + static int its_irq_set_irqchip_state(struct irq_data *d, +@@ -1666,6 +1687,11 @@ static int its_alloc_tables(struct its_node *its) + ids = 0x14; /* 20 bits, 8MB */ + } + ++#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS ++ if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS) ++ ids = ilog2(its->pre_its_size) - 2; ++#endif ++ + its->device_ids = ids; + + for (i = 0; i < GITS_BASER_NR_REGS; i++) { +@@ -2788,11 +2814,21 @@ static const struct gic_quirk its_quirks[] = { + } + }; + +-static void its_enable_quirks(struct its_node *its) ++static void its_enable_quirks(struct its_node *its, ++ struct fwnode_handle *handle) + { + u32 iidr = readl_relaxed(its->base + GITS_IIDR); + + gic_enable_quirks(iidr, its_quirks, its); ++ ++#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS ++ if (!fwnode_property_read_u64_array(handle, ++ "socionext,synquacer-pre-its", ++ &its->pre_its_base, 2)) { ++ its->flags |= ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS; ++ pr_info("ITS: enabling workaround for Socionext Synquacer pre-ITS\n"); ++ } ++#endif + } + + static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) +@@ -2812,7 +2848,9 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) + + inner_domain->parent = its_parent; + irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); +- inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; ++ ++ if (!(its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS)) ++ inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; + info->ops = &its_msi_domain_ops; + info->data = its; + inner_domain->host_data = info; +@@ -2966,7 +3004,7 @@ static int __init its_probe_one(struct resource *res, + } + its->cmd_write = its->cmd_base; + +- its_enable_quirks(its); ++ its_enable_quirks(its, handle); + + err = its_alloc_tables(its); + if (err) +-- +cgit v1.1 + From 26e7bb47b0fb03a01be1e391a08c7375b45335a2 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel <ard.biesheuvel@linaro.org> Date: Mon, 21 Aug 2017 20:29:05 +0100 @@ -173,6 +325,7 @@ index c61be97..7d5a23e 100644 --- a/drivers/pci/dwc/Makefile +++ b/drivers/pci/dwc/Makefile @@ -1,5 +1,6 @@ + # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_DW) += pcie-designware.o obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o +obj-$(CONFIG_PCIE_DW_HOST_ECAM) += pcie-designware-ecam.o @@ -2896,3 +3049,51 @@ index 0000000..4695969 -- cgit v1.1 +From d2fc584f8237746a84e6ec8690d8884f148fc449 Mon Sep 17 00:00:00 2001 +From: Peter Robinson <pbrobinson@gmail.com> +Date: Tue, 10 Oct 2017 11:35:51 +0100 +Subject: [PATCH] add interrupt.h, sort alphabetically + +Signed-off-by: Peter Robinson <pbrobinson@gmail.com> +--- + drivers/net/ethernet/socionext/netsec/netsec_platform.c | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/ethernet/socionext/netsec/netsec_platform.c b/drivers/net/ethernet/socionext/netsec/netsec_platform.c +index 624f6a7093f6..79072bae917d 100644 +--- a/drivers/net/ethernet/socionext/netsec/netsec_platform.c ++++ b/drivers/net/ethernet/socionext/netsec/netsec_platform.c +@@ -14,21 +14,22 @@ + */ + + #include <linux/acpi.h> +-#include <linux/device.h> +-#include <linux/ctype.h> +-#include <linux/netdevice.h> +-#include <linux/types.h> + #include <linux/bitops.h> ++#include <linux/clk.h> ++#include <linux/ctype.h> ++#include <linux/device.h> + #include <linux/dma-mapping.h> ++#include <linux/io.h> ++#include <linux/interrupt.h> + #include <linux/module.h> +-#include <linux/sizes.h> +-#include <linux/platform_device.h> +-#include <linux/clk.h> ++#include <linux/netdevice.h> + #include <linux/of.h> + #include <linux/of_device.h> + #include <linux/of_net.h> +-#include <linux/io.h> ++#include <linux/platform_device.h> + #include <linux/pm_runtime.h> ++#include <linux/sizes.h> ++#include <linux/types.h> + + #include "netsec.h" + +-- +2.14.2 + |