diff options
Diffstat (limited to 'arm64-dts-qcom-Add-Lenovo-Yoga-C630.patch')
| -rw-r--r-- | arm64-dts-qcom-Add-Lenovo-Yoga-C630.patch | 623 |
1 files changed, 623 insertions, 0 deletions
diff --git a/arm64-dts-qcom-Add-Lenovo-Yoga-C630.patch b/arm64-dts-qcom-Add-Lenovo-Yoga-C630.patch new file mode 100644 index 000000000..f823a810b --- /dev/null +++ b/arm64-dts-qcom-Add-Lenovo-Yoga-C630.patch @@ -0,0 +1,623 @@ +From patchwork Thu Sep 5 14:51:12 2019 +Content-Type: text/plain; charset="utf-8" +MIME-Version: 1.0 +Content-Transfer-Encoding: 7bit +X-Patchwork-Submitter: Lee Jones <lee.jones@linaro.org> +X-Patchwork-Id: 11133293 +Return-Path: + <SRS0=FLD0=XA=lists.infradead.org=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@kernel.org> +Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org + [172.30.200.123]) + by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EF29913BD + for <patchwork-linux-arm@patchwork.kernel.org>; + Thu, 5 Sep 2019 14:51:26 +0000 (UTC) +Received: from bombadil.infradead.org (bombadil.infradead.org + [198.137.202.133]) + (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) + (No client certificate requested) + by mail.kernel.org (Postfix) with ESMTPS id 1997020820 + for <patchwork-linux-arm@patchwork.kernel.org>; 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+ Thu, 05 Sep 2019 07:51:15 -0700 (PDT) +Received: from localhost.localdomain ([95.147.198.36]) + by smtp.gmail.com with ESMTPSA id g201sm4376858wmg.34.2019.09.05.07.51.14 + (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); + Thu, 05 Sep 2019 07:51:14 -0700 (PDT) +From: Lee Jones <lee.jones@linaro.org> +To: agross@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, + bjorn.andersson@linaro.org, arnd@arndb.de +Subject: [PATCH v4 1/1] arm64: dts: qcom: Add Lenovo Yoga C630 +Date: Thu, 5 Sep 2019 15:51:12 +0100 +Message-Id: <20190905145112.7366-1-lee.jones@linaro.org> +X-Mailer: git-send-email 2.17.1 +X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 +X-CRM114-CacheID: sfid-20190905_075117_040430_5C619449 +X-CRM114-Status: GOOD ( 14.05 ) +X-Spam-Score: -0.2 (/) +X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: + Content analysis details: (-0.2 points) + pts rule name description + ---- ---------------------- + -------------------------------------------------- + -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, + no trust [2a00:1450:4864:20:0:0:0:343 listed in] + [list.dnswl.org] + -0.0 SPF_PASS SPF: sender matches SPF record + 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record + -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from + envelope-from domain + -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from + author's domain + 0.1 DKIM_SIGNED Message has a DKIM or DK signature, + not necessarily + valid + -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature +X-BeenThere: linux-arm-kernel@lists.infradead.org +X-Mailman-Version: 2.1.29 +Precedence: list +List-Id: <linux-arm-kernel.lists.infradead.org> +List-Unsubscribe: + <http://lists.infradead.org/mailman/options/linux-arm-kernel>, + <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> +List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> +List-Post: <mailto:linux-arm-kernel@lists.infradead.org> +List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> +List-Subscribe: + <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, + <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> +Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, + linux-kernel@vger.kernel.org, soc@kernel.org, + Lee Jones <lee.jones@linaro.org>, + linux-arm-kernel@lists.infradead.org +MIME-Version: 1.0 +Content-Type: text/plain; charset="us-ascii" +Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> +Errors-To: + linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org + +From: Bjorn Andersson <bjorn.andersson@linaro.org> + +The Lenovo Yoga C630 is built on the SDM850 from Qualcomm, but this seem +to be similar enough to the SDM845 that we can reuse the sdm845.dtsi. + +Supported by this patch is: keyboard, battery monitoring, UFS storage, +USB host and Bluetooth. + +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Reviewed-by: Vinod Koul <vkoul@kernel.org> +Acked-by: Sudeep Holla <sudeep.holla@arm.com> +[Lee] Reorder, change licence, remove non-upstream device node +Signed-off-by: Lee Jones <lee.jones@linaro.org> +--- + +Changelog: + * Reorder nodes alphabetically + * Remove superfluous node for driver not yet upstream + * Add (then remove) 'no-dma' property + * Change licence to BSD + +arch/arm64/boot/dts/qcom/Makefile | 1 + + .../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 446 ++++++++++++++++++ + 2 files changed, 447 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts + +diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile +index 0a7e5dfce6f7..670c6c65f9e9 100644 +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -12,5 +12,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb + dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb + dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb + dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb ++dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb + dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb +diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +new file mode 100644 +index 000000000000..ded120d3aef5 +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +@@ -0,0 +1,446 @@ ++// SPDX-License-Identifier: BSD-3-Clause ++/* ++ * Lenovo Yoga C630 ++ * ++ * Copyright (c) 2019, Linaro Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include <dt-bindings/regulator/qcom,rpmh-regulator.h> ++#include "sdm845.dtsi" ++#include "pm8998.dtsi" ++ ++/ { ++ model = "Lenovo Yoga C630"; ++ compatible = "lenovo,yoga-c630", "qcom,sdm845"; ++ ++ aliases { ++ hsuart0 = &uart6; ++ }; ++}; ++ ++&apps_rsc { ++ pm8998-rpmh-regulators { ++ compatible = "qcom,pm8998-rpmh-regulators"; ++ qcom,pmic-id = "a"; ++ ++ vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>; ++ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>; ++ ++ vreg_s2a_1p125: smps2 { ++ }; ++ ++ vreg_s3a_1p35: smps3 { ++ regulator-min-microvolt = <1352000>; ++ regulator-max-microvolt = <1352000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_s4a_1p8: smps4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_s5a_2p04: smps5 { ++ regulator-min-microvolt = <2040000>; ++ regulator-max-microvolt = <2040000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_s7a_1p025: smps7 { ++ }; ++ ++ vdd_qusb_hs0: ++ vdda_hp_pcie_core: ++ vdda_mipi_csi0_0p9: ++ vdda_mipi_csi1_0p9: ++ vdda_mipi_csi2_0p9: ++ vdda_mipi_dsi0_pll: ++ vdda_mipi_dsi1_pll: ++ vdda_qlink_lv: ++ vdda_qlink_lv_ck: ++ vdda_qrefs_0p875: ++ vdda_pcie_core: ++ vdda_pll_cc_ebi01: ++ vdda_pll_cc_ebi23: ++ vdda_sp_sensor: ++ vdda_ufs1_core: ++ vdda_ufs2_core: ++ vdda_usb1_ss_core: ++ vdda_usb2_ss_core: ++ vreg_l1a_0p875: ldo1 { ++ regulator-min-microvolt = <880000>; ++ regulator-max-microvolt = <880000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vddpx_10: ++ vreg_l2a_1p2: ldo2 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ regulator-always-on; ++ }; ++ ++ vreg_l3a_1p0: ldo3 { ++ }; ++ ++ vdd_wcss_cx: ++ vdd_wcss_mx: ++ vdda_wcss_pll: ++ vreg_l5a_0p8: ldo5 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <800000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vddpx_13: ++ vreg_l6a_1p8: ldo6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l7a_1p8: ldo7 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l8a_1p2: ldo8 { ++ }; ++ ++ vreg_l9a_1p8: ldo9 { ++ }; ++ ++ vreg_l10a_1p8: ldo10 { ++ }; ++ ++ vreg_l11a_1p0: ldo11 { ++ }; ++ ++ vdd_qfprom: ++ vdd_qfprom_sp: ++ vdda_apc1_cs_1p8: ++ vdda_gfx_cs_1p8: ++ vdda_qrefs_1p8: ++ vdda_qusb_hs0_1p8: ++ vddpx_11: ++ vreg_l12a_1p8: ldo12 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vddpx_2: ++ vreg_l13a_2p95: ldo13 { ++ }; ++ ++ vreg_l14a_1p88: ldo14 { ++ regulator-min-microvolt = <1880000>; ++ regulator-max-microvolt = <1880000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ regulator-always-on; ++ }; ++ ++ vreg_l15a_1p8: ldo15 { ++ }; ++ ++ vreg_l16a_2p7: ldo16 { ++ }; ++ ++ vreg_l17a_1p3: ldo17 { ++ regulator-min-microvolt = <1304000>; ++ regulator-max-microvolt = <1304000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l18a_2p7: ldo18 { ++ }; ++ ++ vreg_l19a_3p0: ldo19 { ++ regulator-min-microvolt = <3100000>; ++ regulator-max-microvolt = <3108000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l20a_2p95: ldo20 { ++ regulator-min-microvolt = <2960000>; ++ regulator-max-microvolt = <2960000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l21a_2p95: ldo21 { ++ }; ++ ++ vreg_l22a_2p85: ldo22 { ++ }; ++ ++ vreg_l23a_3p3: ldo23 { ++ }; ++ ++ vdda_qusb_hs0_3p1: ++ vreg_l24a_3p075: ldo24 { ++ regulator-min-microvolt = <3075000>; ++ regulator-max-microvolt = <3083000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l25a_3p3: ldo25 { ++ regulator-min-microvolt = <3104000>; ++ regulator-max-microvolt = <3112000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vdda_hp_pcie_1p2: ++ vdda_hv_ebi0: ++ vdda_hv_ebi1: ++ vdda_hv_ebi2: ++ vdda_hv_ebi3: ++ vdda_mipi_csi_1p25: ++ vdda_mipi_dsi0_1p2: ++ vdda_mipi_dsi1_1p2: ++ vdda_pcie_1p2: ++ vdda_ufs1_1p2: ++ vdda_ufs2_1p2: ++ vdda_usb1_ss_1p2: ++ vdda_usb2_ss_1p2: ++ vreg_l26a_1p2: ldo26 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1208000>; ++ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; ++ }; ++ ++ vreg_l28a_3p0: ldo28 { ++ }; ++ ++ vreg_lvs1a_1p8: lvs1 { ++ }; ++ ++ vreg_lvs2a_1p8: lvs2 { ++ }; ++ }; ++}; ++ ++&apps_smmu { ++ /* TODO: Figure out how to survive booting with this enabled */ ++ status = "disabled"; ++}; ++ ++&gcc { ++ protected-clocks = <GCC_QSPI_CORE_CLK>, ++ <GCC_QSPI_CORE_CLK_SRC>, ++ <GCC_QSPI_CNOC_PERIPH_AHB_CLK>; ++}; ++ ++&i2c1 { ++ status = "okay"; ++ clock-frequency = <400000>; ++}; ++ ++&i2c3 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ hid@15 { ++ compatible = "hid-over-i2c"; ++ reg = <0x15>; ++ hid-descr-addr = <0x1>; ++ ++ interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; ++ }; ++ ++ hid@2c { ++ compatible = "hid-over-i2c"; ++ reg = <0x2c>; ++ hid-descr-addr = <0x20>; ++ ++ interrupts-extended = <&tlmm 37 IRQ_TYPE_EDGE_RISING>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_hid_active>; ++ }; ++}; ++ ++&i2c5 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ hid@10 { ++ compatible = "hid-over-i2c"; ++ reg = <0x10>; ++ hid-descr-addr = <0x1>; ++ ++ interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c6_hid_active>; ++ }; ++}; ++ ++&i2c11 { ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ hid@5c { ++ compatible = "hid-over-i2c"; ++ reg = <0x5c>; ++ hid-descr-addr = <0x1>; ++ ++ interrupts-extended = <&tlmm 92 IRQ_TYPE_LEVEL_LOW>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c12_hid_active>; ++ }; ++}; ++ ++&qup_i2c12_default { ++ drive-strength = <2>; ++ bias-disable; ++}; ++ ++&qup_uart6_default { ++ pinmux { ++ pins = "gpio45", "gpio46", "gpio47", "gpio48"; ++ function = "qup6"; ++ }; ++ ++ cts { ++ pins = "gpio45"; ++ bias-pull-down; ++ }; ++ ++ rts-tx { ++ pins = "gpio46", "gpio47"; ++ drive-strength = <2>; ++ bias-disable; ++ }; ++ ++ rx { ++ pins = "gpio48"; ++ bias-pull-up; ++ }; ++}; ++ ++&qupv3_id_0 { ++ status = "okay"; ++}; ++ ++&qupv3_id_1 { ++ status = "okay"; ++}; ++ ++&tlmm { ++ gpio-reserved-ranges = <0 4>, <81 4>; ++ ++ i2c2_hid_active: i2c2-hid-active { ++ pins = <37>; ++ function = "gpio"; ++ ++ input-enable; ++ bias-pull-up; ++ drive-strength = <2>; ++ }; ++ ++ i2c6_hid_active: i2c6-hid-active { ++ pins = <125>; ++ function = "gpio"; ++ ++ input-enable; ++ bias-pull-up; ++ drive-strength = <2>; ++ }; ++ ++ i2c12_hid_active: i2c12-hid-active { ++ pins = <92>; ++ function = "gpio"; ++ ++ input-enable; ++ bias-pull-up; ++ drive-strength = <2>; ++ }; ++}; ++ ++&uart6 { ++ status = "okay"; ++ ++ bluetooth { ++ compatible = "qcom,wcn3990-bt"; ++ ++ vddio-supply = <&vreg_s4a_1p8>; ++ vddxo-supply = <&vreg_l7a_1p8>; ++ vddrf-supply = <&vreg_l17a_1p3>; ++ vddch0-supply = <&vreg_l25a_3p3>; ++ max-speed = <3200000>; ++ }; ++}; ++ ++&ufs_mem_hc { ++ status = "okay"; ++ ++ vcc-supply = <&vreg_l20a_2p95>; ++ vcc-max-microamp = <600000>; ++}; ++ ++&ufs_mem_phy { ++ status = "okay"; ++ ++ vdda-phy-supply = <&vdda_ufs1_core>; ++ vdda-pll-supply = <&vdda_ufs1_1p2>; ++}; ++ ++&usb_1 { ++ status = "okay"; ++}; ++ ++&usb_1_dwc3 { ++ dr_mode = "host"; ++}; ++ ++&usb_1_hsphy { ++ status = "okay"; ++ ++ vdd-supply = <&vdda_usb1_ss_core>; ++ vdda-pll-supply = <&vdda_qusb_hs0_1p8>; ++ vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; ++ ++ qcom,imp-res-offset-value = <8>; ++ qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>; ++ qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>; ++ qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>; ++}; ++ ++&usb_1_qmpphy { ++ status = "okay"; ++ ++ vdda-phy-supply = <&vdda_usb1_ss_1p2>; ++ vdda-pll-supply = <&vdda_usb1_ss_core>; ++}; ++ ++&usb_2 { ++ status = "okay"; ++}; ++ ++&usb_2_dwc3 { ++ dr_mode = "host"; ++}; ++ ++&usb_2_hsphy { ++ status = "okay"; ++ ++ vdd-supply = <&vdda_usb2_ss_core>; ++ vdda-pll-supply = <&vdda_qusb_hs0_1p8>; ++ vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>; ++ ++ qcom,imp-res-offset-value = <8>; ++ qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>; ++}; ++ ++&usb_2_qmpphy { ++ status = "okay"; ++ ++ vdda-phy-supply = <&vdda_usb2_ss_1p2>; ++ vdda-pll-supply = <&vdda_usb2_ss_core>; ++}; |