diff options
Diffstat (limited to 'arm64-allwinner-fixes.patch')
| -rw-r--r-- | arm64-allwinner-fixes.patch | 1548 |
1 files changed, 1548 insertions, 0 deletions
diff --git a/arm64-allwinner-fixes.patch b/arm64-allwinner-fixes.patch new file mode 100644 index 000000000..b37e34881 --- /dev/null +++ b/arm64-allwinner-fixes.patch @@ -0,0 +1,1548 @@ +From 5828729bebbb69d0743488e742bed8a9727b0b71 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Wed, 11 Apr 2018 22:16:40 +0800 +Subject: soc: sunxi: export a regmap for EMAC clock reg on A64 + +The A64 SRAM controller memory zone has a EMAC clock register, which is +needed by the Ethernet MAC driver (dwmac-sun8i). + +Export a regmap for this register on A64. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +[wens@csie.org: export whole address range with only EMAC register + accessible and drop regmap name] +Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + drivers/soc/sunxi/sunxi_sram.c | 57 ++++++++++++++++++++++++++++++++++++++++-- + 1 file changed, 55 insertions(+), 2 deletions(-) + +diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c +index 882be5ed7e84..eec7fc6e9f66 100644 +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -17,6 +17,7 @@ + #include <linux/of_address.h> + #include <linux/of_device.h> + #include <linux/platform_device.h> ++#include <linux/regmap.h> + + #include <linux/soc/sunxi/sunxi_sram.h> + +@@ -281,13 +282,51 @@ int sunxi_sram_release(struct device *dev) + } + EXPORT_SYMBOL(sunxi_sram_release); + ++struct sunxi_sramc_variant { ++ bool has_emac_clock; ++}; ++ ++static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { ++ /* Nothing special */ ++}; ++ ++static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = { ++ .has_emac_clock = true, ++}; ++ ++#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30 ++static bool sunxi_sram_regmap_accessible_reg(struct device *dev, ++ unsigned int reg) ++{ ++ if (reg == SUNXI_SRAM_EMAC_CLOCK_REG) ++ return true; ++ return false; ++} ++ ++static struct regmap_config sunxi_sram_emac_clock_regmap = { ++ .reg_bits = 32, ++ .val_bits = 32, ++ .reg_stride = 4, ++ /* last defined register */ ++ .max_register = SUNXI_SRAM_EMAC_CLOCK_REG, ++ /* other devices have no business accessing other registers */ ++ .readable_reg = sunxi_sram_regmap_accessible_reg, ++ .writeable_reg = sunxi_sram_regmap_accessible_reg, ++}; ++ + static int sunxi_sram_probe(struct platform_device *pdev) + { + struct resource *res; + struct dentry *d; ++ struct regmap *emac_clock; ++ const struct sunxi_sramc_variant *variant; + + sram_dev = &pdev->dev; + ++ variant = of_device_get_match_data(&pdev->dev); ++ if (!variant) ++ return -EINVAL; ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) +@@ -300,12 +339,26 @@ static int sunxi_sram_probe(struct platform_device *pdev) + if (!d) + return -ENOMEM; + ++ if (variant->has_emac_clock) { ++ emac_clock = devm_regmap_init_mmio(&pdev->dev, base, ++ &sunxi_sram_emac_clock_regmap); ++ ++ if (IS_ERR(emac_clock)) ++ return PTR_ERR(emac_clock); ++ } ++ + return 0; + } + + static const struct of_device_id sunxi_sram_dt_match[] = { +- { .compatible = "allwinner,sun4i-a10-sram-controller" }, +- { .compatible = "allwinner,sun50i-a64-sram-controller" }, ++ { ++ .compatible = "allwinner,sun4i-a10-sram-controller", ++ .data = &sun4i_a10_sramc_variant, ++ }, ++ { ++ .compatible = "allwinner,sun50i-a64-sram-controller", ++ .data = &sun50i_a64_sramc_variant, ++ }, + { }, + }; + MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); +-- +cgit 1.2-0.3.lf.el7 +From ede18ae31202256824b47cfbebc8c0dc219354ef Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai <wens@csie.org> +Date: Tue, 22 May 2018 01:02:41 +0800 +Subject: soc: sunxi: sram: Add updated compatible string for A64 system + control + +The SRAM mapping controls on Allwinner SoCs is located in a block called +"System Controls". This block also has registers for identifying the SoC, +reading the state of an external boot-related pin, and on some newer SoCs, +glue layer controls for the EMAC Ethernet controller. + +The A64 variant compatible is renamed to "allwinner,a64-system-control" +to reflect this. The old A64 compatible is deprecated. So far we haven't +seen any actual use of it. + +Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + drivers/soc/sunxi/sunxi_sram.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c +index eec7fc6e9f66..7fec1b160dbb 100644 +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -359,6 +359,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = { + .compatible = "allwinner,sun50i-a64-sram-controller", + .data = &sun50i_a64_sramc_variant, + }, ++ { ++ .compatible = "allwinner,sun50i-a64-system-control", ++ .data = &sun50i_a64_sramc_variant, ++ }, + { }, + }; + MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match); +-- +cgit 1.2-0.3.lf.el7 +From acc26f59f835142a48f495caf80b86592c4af1f5 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <paul.kocialkowski@bootlin.com> +Date: Tue, 10 Jul 2018 10:00:58 +0200 +Subject: soc: sunxi: sram: Add dt match for the A10 system-control compatible + +This binds the new A10 system-control compatible to the associated +driver, with the same driver data as the previous compatible. + +Reviewed-by: Chen-Yu Tsai <wens@csie.org> +Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + drivers/soc/sunxi/sunxi_sram.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c +index 7fec1b160dbb..236f34307c0f 100644 +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -355,6 +355,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = { + .compatible = "allwinner,sun4i-a10-sram-controller", + .data = &sun4i_a10_sramc_variant, + }, ++ { ++ .compatible = "allwinner,sun4i-a10-system-control", ++ .data = &sun4i_a10_sramc_variant, ++ }, + { + .compatible = "allwinner,sun50i-a64-sram-controller", + .data = &sun50i_a64_sramc_variant, +-- +cgit 1.2-0.3.lf.el7 +From 5fdec16b69da273d5654c2c3be01246a59e1bcba Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@bootlin.com> +Date: Tue, 10 Jul 2018 10:00:59 +0200 +Subject: drivers: soc: sunxi: Add support for the C1 SRAM region + +This introduces support for the SRAM C1 section, that is controlled by +the system controller. This SRAM area can be muxed either to the CPU +or the Video Engine, that needs this area to store various tables (e.g. +the Huffman VLD decoding tables). + +This only supports devices with the same layout as the A10 (which also +includes the A13, A20, A33 and other SoCs). + +Reviewed-by: Chen-Yu Tsai <wens@csie.org> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + drivers/soc/sunxi/sunxi_sram.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c +index 236f34307c0f..b19fa2cc67c2 100644 +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -64,6 +64,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_a3_a4 = { + SUNXI_SRAM_MAP(1, 1, "emac")), + }; + ++static struct sunxi_sram_desc sun4i_a10_sram_c1 = { ++ .data = SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31, ++ SUNXI_SRAM_MAP(0, 0, "cpu"), ++ SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")), ++}; ++ + static struct sunxi_sram_desc sun4i_a10_sram_d = { + .data = SUNXI_SRAM_DATA("D", 0x4, 0x0, 1, + SUNXI_SRAM_MAP(0, 0, "cpu"), +@@ -81,6 +87,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = { + .compatible = "allwinner,sun4i-a10-sram-a3-a4", + .data = &sun4i_a10_sram_a3_a4.data, + }, ++ { ++ .compatible = "allwinner,sun4i-a10-sram-c1", ++ .data = &sun4i_a10_sram_c1.data, ++ }, + { + .compatible = "allwinner,sun4i-a10-sram-d", + .data = &sun4i_a10_sram_d.data, +-- +cgit 1.2-0.3.lf.el7 +From 7377330a1ed2e9bb5a97758bdadcdb37e2201b2a Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@bootlin.com> +Date: Wed, 11 Jul 2018 11:25:07 +0200 +Subject: soc: sunxi: Add the A13, A23 and H3 system control compatibles + +The A13, A23 and H3 have variations of the system controls, in part due to +the SRAM that are available (and can be mapped) in the SoC. + +In order to make it future proof, let's add compatibles for these SoCs in +the driver. + +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + drivers/soc/sunxi/sunxi_sram.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c +index b19fa2cc67c2..b4b0f3480bd3 100644 +--- a/drivers/soc/sunxi/sunxi_sram.c ++++ b/drivers/soc/sunxi/sunxi_sram.c +@@ -369,6 +369,18 @@ static const struct of_device_id sunxi_sram_dt_match[] = { + .compatible = "allwinner,sun4i-a10-system-control", + .data = &sun4i_a10_sramc_variant, + }, ++ { ++ .compatible = "allwinner,sun5i-a13-system-control", ++ .data = &sun4i_a10_sramc_variant, ++ }, ++ { ++ .compatible = "allwinner,sun8i-a23-system-control", ++ .data = &sun4i_a10_sramc_variant, ++ }, ++ { ++ .compatible = "allwinner,sun8i-h3-system-control", ++ .data = &sun4i_a10_sramc_variant, ++ }, + { + .compatible = "allwinner,sun50i-a64-sram-controller", + .data = &sun50i_a64_sramc_variant, +-- +cgit 1.2-0.3.lf.el7 +From 0195156340d365540c7dfa239232065826904f59 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Fri, 22 Jun 2018 20:45:37 +0800 +Subject: clk: sunxi-ng: add A64 compatible string + +As claiming Allwinner A64 SRAM C is a prerequisite for all sub-blocks of +the A64 DE2, not only the CCU sub-block, a bus driver is then written for +enabling the access to the whole DE2 part by claiming the SRAM. + +In this situation, the A64 compatible string will be just added with no +other requirments, as they're processed by the parent bus driver. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +index 468d1abaf0ee..bae5ee67a797 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c ++++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +@@ -288,17 +288,14 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { + .compatible = "allwinner,sun8i-v3s-de2-clk", + .data = &sun8i_v3s_de2_clk_desc, + }, ++ { ++ .compatible = "allwinner,sun50i-a64-de2-clk", ++ .data = &sun50i_a64_de2_clk_desc, ++ }, + { + .compatible = "allwinner,sun50i-h5-de2-clk", + .data = &sun50i_a64_de2_clk_desc, + }, +- /* +- * The Allwinner A64 SoC needs some bit to be poke in syscon to make +- * DE2 really working. +- * So there's currently no A64 compatible here. +- * H5 shares the same reset line with A64, so here H5 is using the +- * clock description of A64. +- */ + { } + }; + +-- +cgit 1.2-0.3.lf.el7 +From 2c740e6ab4b66e5bb1cd3c75f00f4ca7e5765037 Mon Sep 17 00:00:00 2001 +From: Emmanuel Vadot <manu@freebsd.org> +Date: Mon, 21 May 2018 13:54:13 +0200 +Subject: [PATCH 01/16] arm64: dts: allwinner: sun50i: a64: Add spi flash node + for sopine + +The Sopine and Pine64-LTS have a winbond w25q128 spi flash on spi0. +Add a node for it. + +Signed-off-by: Emmanuel Vadot <manu@freebsd.org> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +index 43418bd881d8..b94f93c04acb 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +@@ -66,6 +66,18 @@ + }; + }; + ++&spi0 { ++ status = "okay"; ++ ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <40000000>; ++ }; ++}; ++ + #include "axp803.dtsi" + + ®_aldo2 { +-- +2.19.0 + +From dd9caf2662a84eb48ab351679226c3b41a7dc2b3 Mon Sep 17 00:00:00 2001 +From: Jagan Teki <jagan@amarulasolutions.com> +Date: Fri, 1 Jun 2018 23:05:26 +0530 +Subject: [PATCH 02/16] arm64: allwinner: a64: Add RTC clock to phandle 32kHz + external oscillator + +Outside of SOC few chips need external clock source +through RTC example Wifi chip. So RTC clock nodes to +phandle 32kHz external oscillator. + +prefix rtc- with clock-output-names defined in +dt-binding to avoid confusion with existing osc32k name. + +Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 1b2ef28c42bd..82516aec4153 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -634,6 +634,9 @@ + reg = <0x01f00000 0x54>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; ++ clock-output-names = "rtc-osc32k", "rtc-osc32k-out"; ++ clocks = <&osc32k>; ++ #clock-cells = <1>; + }; + + r_intc: interrupt-controller@1f00c00 { +-- +2.19.0 + +From 16b76e6755f70be678dc62ff6b0d9aaa0825bdd5 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Tue, 5 Jun 2018 22:17:00 -0700 +Subject: [PATCH 03/16] arm64: dts: allwinner: a64: add R_I2C controller + +Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has +two groups of pinmuxes on PL bank, so it's called R_I2C. + +Add support for this I2C controller and the pinmux which doesn't conflict +with RSB. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 82516aec4153..1b31a3aaed5a 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -46,6 +46,7 @@ + #include <dt-bindings/clock/sun8i-r-ccu.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/sun50i-a64-ccu.h> ++#include <dt-bindings/reset/sun8i-r-ccu.h> + + / { + interrupt-parent = <&gic>; +@@ -658,6 +659,18 @@ + #reset-cells = <1>; + }; + ++ r_i2c: i2c@1f02400 { ++ compatible = "allwinner,sun50i-a64-i2c", ++ "allwinner,sun6i-a31-i2c"; ++ reg = <0x01f02400 0x400>; ++ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&r_ccu CLK_APB0_I2C>; ++ resets = <&r_ccu RST_APB0_I2C>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun50i-a64-r-pinctrl"; + reg = <0x01f02c00 0x400>; +@@ -669,6 +682,11 @@ + interrupt-controller; + #interrupt-cells = <3>; + ++ r_i2c_pins_a: i2c-a { ++ pins = "PL8", "PL9"; ++ function = "s_i2c"; ++ }; ++ + r_rsb_pins: rsb { + pins = "PL0", "PL1"; + function = "s_rsb"; +-- +2.19.0 + +From 6e634550a1b82f2a1f0e46470388fdf617dd0cfc Mon Sep 17 00:00:00 2001 +From: Andre Przywara <andre.przywara@arm.com> +Date: Tue, 5 Jun 2018 22:17:01 -0700 +Subject: [PATCH 04/16] arm64: dts: allwinner: a64: Add PWM controllers + +The Allwinner A64 SoC features two PWM controllers, which are fully +compatible to the one used in the A13 and H3 chips. + +Add the nodes for the devices (one for the "normal" PWM, the other for +the one in the CPUS domain) and the pins their outputs are connected to. + +On the A64 the "normal" PWM is muxed together with one of the MDIO pins +used to communicate with the Ethernet PHY, so it won't be usable on many +boards. But the Pinebook laptop uses this pin for controlling the LCD +backlight. + +On Pine64 the CPUS PWM pin however is routed to the "RPi2" header, +at the same location as the PWM pin on the RaspberryPi. + +Tested on Pinebook and Teres-I + +[vasily: fixed comment message as requested by Stefan Bruens, added default + muxing options to pwm and r_pwm nodes] + +Signed-off-by: Andre Przywara <andre.przywara@arm.com> +Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> +Tested-by: Harald Geyer <harald@ccbib.org> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 32 +++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 1b31a3aaed5a..2777b2d02d77 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -365,6 +365,11 @@ + bias-pull-up; + }; + ++ pwm_pin: pwm_pin { ++ pins = "PD22"; ++ function = "pwm"; ++ }; ++ + rmii_pins: rmii_pins { + pins = "PD10", "PD11", "PD13", "PD14", "PD17", + "PD18", "PD19", "PD20", "PD22", "PD23"; +@@ -630,6 +635,17 @@ + #interrupt-cells = <3>; + }; + ++ pwm: pwm@1c21400 { ++ compatible = "allwinner,sun50i-a64-pwm", ++ "allwinner,sun5i-a13-pwm"; ++ reg = <0x01c21400 0x400>; ++ clocks = <&osc24M>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + rtc: rtc@1f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; +@@ -671,6 +687,17 @@ + #size-cells = <0>; + }; + ++ r_pwm: pwm@1f03800 { ++ compatible = "allwinner,sun50i-a64-pwm", ++ "allwinner,sun5i-a13-pwm"; ++ reg = <0x01f03800 0x400>; ++ clocks = <&osc24M>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_pwm_pin>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ + r_pio: pinctrl@1f02c00 { + compatible = "allwinner,sun50i-a64-r-pinctrl"; + reg = <0x01f02c00 0x400>; +@@ -687,6 +714,11 @@ + function = "s_i2c"; + }; + ++ r_pwm_pin: pwm { ++ pins = "PL10"; ++ function = "s_pwm"; ++ }; ++ + r_rsb_pins: rsb { + pins = "PL0", "PL1"; + function = "s_rsb"; +-- +2.19.0 + +From 1c566803ecf17d3a68a9375fdc66ea65291b3320 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Tue, 5 Jun 2018 22:17:02 -0700 +Subject: [PATCH 05/16] arm64: dts: allwinner: add support for Pinebook + +Pinebook is a A64-based laptop produced by Pine64, with the following +peripherals: + +USB: +- Two external USB ports (one is directly connected to A64's OTG +controller, the other is under a internal hub connected to the host-only +controller.) +- USB HID keyboard and touchpad connected to the internal hub. +- USB UVC camera connected to the internal hub. + +Power-related: +- A DC IN jack connected to AXP803's DCIN pin. +- A Li-Polymer battery connected to AXP803's battery pins. + +Storage: +- An eMMC by Foresee on the main board (in the product revision of the +main board it's designed to be switchable). +- An external MicroSD card slot. + +Display: +- An eDP LCD panel (1366x768) connected via an ANX6345 RGB-eDP bridge. +- A mini HDMI port. + +Misc: +- A Hall sensor designed to detect the status of lid, connected to GPIO PL12. +- A headphone jack connected to the SoC's internal codec. +- A debug UART port muxed with headphone jack. + +This commit adds basical support for it. + +[vasily: squashed several commits into one, added simplefb node, added usbphy + to ehci0 and ohci0 nodes and other cosmetic changes to dts] + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../dts/allwinner/sun50i-a64-pinebook.dts | 280 ++++++++++++++++++ + 2 files changed, 281 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index c31f90a49481..8664b7aaba82 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +new file mode 100644 +index 000000000000..58253d6f9be1 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +@@ -0,0 +1,280 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz> ++ * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com> ++ * ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-a64.dtsi" ++ ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/input.h> ++#include <dt-bindings/pwm/pwm.h> ++ ++/ { ++ model = "Pinebook"; ++ compatible = "pine64,pinebook", "allwinner,sun50i-a64"; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = &rtl8723cs; ++ }; ++ ++ backlight: backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm 0 50000 0>; ++ brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>; ++ default-brightness-level = <2>; ++ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */ ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ ++ framebuffer-lcd { ++ panel-supply = <®_dc1sw>; ++ dvdd25-supply = <®_dldo2>; ++ dvdd12-supply = <®_fldo1>; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ ++ lid_switch { ++ label = "Lid Switch"; ++ gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */ ++ linux,input-type = <EV_SW>; ++ linux,code = <SW_LID>; ++ linux,can-disable; ++ }; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ wifi_pwrseq: wifi_pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ ++ }; ++}; ++ ++&ehci0 { ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "okay"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_dcdc1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ ++&mmc1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins>; ++ vmmc-supply = <®_dldo4>; ++ vqmmc-supply = <®_eldo1>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ bus-width = <4>; ++ non-removable; ++ status = "okay"; ++ ++ rtl8723cs: wifi@1 { ++ reg = <1>; ++ }; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc2_pins>; ++ vmmc-supply = <®_dcdc1>; ++ vqmmc-supply = <®_eldo1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&ohci0 { ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ status = "okay"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&pwm { ++ status = "okay"; ++}; ++ ++&r_rsb { ++ status = "okay"; ++ ++ axp803: pmic@3a3 { ++ compatible = "x-powers,axp803"; ++ reg = <0x3a3>; ++ interrupt-parent = <&r_intc>; ++ interrupts = <0 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++/* The ANX6345 eDP-bridge is on r_i2c */ ++&r_i2c { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&r_i2c_pins_a>; ++ status = "okay"; ++}; ++ ++#include "axp803.dtsi" ++ ++®_aldo1 { ++ regulator-min-microvolt = <2800000>; ++ regulator-max-microvolt = <2800000>; ++ regulator-name = "vcc-csi"; ++}; ++ ++®_aldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pl"; ++}; ++ ++®_aldo3 { ++ regulator-always-on; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-pll-avcc"; ++}; ++ ++®_dc1sw { ++ regulator-name = "vcc-lcd"; ++}; ++ ++®_dcdc1 { ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-3v3"; ++}; ++ ++®_dcdc2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1300000>; ++ regulator-name = "vdd-cpux"; ++}; ++ ++/* DCDC3 is polyphased with DCDC2 */ ++ ++®_dcdc5 { ++ regulator-always-on; ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-dram"; ++}; ++ ++®_dcdc6 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-sys"; ++}; ++ ++®_dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-hdmi"; ++}; ++ ++®_dldo2 { ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-name = "vcc-edp"; ++}; ++ ++®_dldo3 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "avdd-csi"; ++}; ++ ++®_dldo4 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-wifi"; ++}; ++ ++®_eldo1 { ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "cpvdd"; ++}; ++ ++®_eldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-name = "vdd-1v8-csi"; ++}; ++ ++®_fldo1 { ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-name = "vcc-1v2-hsic"; ++}; ++ ++®_fldo2 { ++ regulator-always-on; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-name = "vdd-cpus"; ++}; ++ ++®_ldo_io0 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-name = "vcc-usb"; ++ status = "okay"; ++}; ++ ++®_rtc_ldo { ++ regulator-name = "vcc-rtc"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; ++ ++&usb_otg { ++ dr_mode = "host"; ++}; ++ ++&usbphy { ++ usb0_vbus-supply = <®_ldo_io0>; ++ usb1_vbus-supply = <®_ldo_io0>; ++ status = "okay"; ++}; +-- +2.19.0 + +From 45c95b7c14c54e1cb9e4ec8c9bfea5132df9ab4e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Wed, 11 Apr 2018 22:16:41 +0800 +Subject: [PATCH 06/16] arm64: dts: allwinner: a64: add SRAM controller device + tree node + +Allwinner A64 has a SRAM controller, and in the device tree currently +we have a syscon node to enable EMAC driver to access the EMAC clock +register. As SRAM controller driver can now export regmap for this +register, replace the syscon node to the SRAM controller device node, +and let EMAC driver to acquire its EMAC clock regmap. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +[wens@csie.org: Updated compatible string] +Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 2777b2d02d77..ff2ddde1e117 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -170,9 +170,24 @@ + ranges; + + syscon: syscon@1c00000 { +- compatible = "allwinner,sun50i-a64-system-controller", +- "syscon"; ++ compatible = "allwinner,sun50i-a64-system-control"; + reg = <0x01c00000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ sram_c: sram@18000 { ++ compatible = "mmio-sram"; ++ reg = <0x00018000 0x28000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x00018000 0x28000>; ++ ++ de2_sram: sram-section@0 { ++ compatible = "allwinner,sun50i-a64-sram-c"; ++ reg = <0x0000 0x28000>; ++ }; ++ }; + }; + + dma: dma-controller@1c02000 { +-- +2.19.0 + +From b1fd604429a17cfd0f47354a2092a1ab99965d13 Mon Sep 17 00:00:00 2001 +From: Emmanuel Vadot <manu@freebsd.org> +Date: Wed, 20 Jun 2018 11:30:55 +0200 +Subject: [PATCH 07/16] arm64: allwinner: a64-sopine: Add cd-gpios to mmc0 node + +The card detect GPIO for Sopine and Pine64-LTS is PF6. +Add this to the dts. + +Signed-off-by: Emmanuel Vadot <manu@freebsd.org> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +index b94f93c04acb..6723b8695e0b 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi +@@ -45,6 +45,8 @@ + + #include "sun50i-a64.dtsi" + ++#include <dt-bindings/gpio/gpio.h> ++ + &mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; +@@ -52,6 +54,7 @@ + non-removable; + disable-wp; + bus-width = <4>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + status = "okay"; + }; + +-- +2.19.0 + +From 66ced6d845a3eb41a564070b594f48220cf7a98a Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Sat, 23 Jun 2018 00:06:30 +0800 +Subject: [PATCH 08/16] arm64: allwinner: a64: change TERES-I DLDO3's name to + start with "vdd" + +Originally the name of the DLDO3 regulator on TERES-I is "eDP12", which +is not consistent with other regulator names. + +Change it to "vdd-edp", in order to make it more consistent. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +index d9baab3dc96b..02fecc42440c 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +@@ -210,7 +210,7 @@ + ®_dldo3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; +- regulator-name = "eDP12"; ++ regulator-name = "vdd-edp"; + }; + + ®_dldo4 { +-- +2.19.0 + +From 7702b17c5cc2f00610875df615c1d01f503081fd Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Sat, 23 Jun 2018 00:06:31 +0800 +Subject: [PATCH 09/16] arm64: allwinner: a64: allow laptops to wake up from + lid + +Currently all ARM kernels will have s2idle enabled if CONFIG_SUSPEND is +present. In this case if the lid is closed, systemd-logind will enter +s2idle mode by default; however there's no possible wakeup source +defined, so the system will enter a forever idle. + +Add the lid itself as a wakeup source, thus the system can wakeup when +the lid is opened. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 1 + + arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +index 58253d6f9be1..e6e5bf11b759 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +@@ -49,6 +49,7 @@ + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; ++ wakeup-source; + }; + }; + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +index 02fecc42440c..33f78e745815 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +@@ -38,6 +38,7 @@ + gpios = <&r_pio 0 8 GPIO_ACTIVE_LOW>; /* PL8 */ + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; ++ wakeup-source; + }; + }; + +-- +2.19.0 + +From bf05dd6ac935e56ed91effa089ca9960abcd93e8 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Fri, 22 Jun 2018 20:45:38 +0800 +Subject: [PATCH 10/16] arm64: dts: allwinner: a64: add necessary device tree + nodes for DE2 CCU + +As we have all necessary parts to enable the DE2 CCU on the Allwinner +A64 SoC, add the needed device tree nodes, including the DE2 CCU itself +and the DE2 bus. + +The "mixer0-lcd0" simplefb device node is updated to use the DE2 CCU. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 30 +++++++++++++++---- + 1 file changed, 24 insertions(+), 6 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index ff2ddde1e117..318c4ba8ae9f 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -43,9 +43,11 @@ + */ + + #include <dt-bindings/clock/sun50i-a64-ccu.h> ++#include <dt-bindings/clock/sun8i-de2.h> + #include <dt-bindings/clock/sun8i-r-ccu.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/sun50i-a64-ccu.h> ++#include <dt-bindings/reset/sun8i-de2.h> + #include <dt-bindings/reset/sun8i-r-ccu.h> + + / { +@@ -58,17 +60,12 @@ + #size-cells = <1>; + ranges; + +-/* +- * The pipeline mixer0-lcd0 depends on clock CLK_MIXER0 from DE2 CCU. +- * However there is no support for this clock on A64 yet, so we depend +- * on the upstream clocks here to keep them (and thus CLK_MIXER0) up. +- */ + simplefb_lcd: framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", + "simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <&ccu CLK_TCON0>, +- <&ccu CLK_DE>, <&ccu CLK_BUS_DE>; ++ <&display_clocks CLK_MIXER0>; + status = "disabled"; + }; + }; +@@ -169,6 +166,27 @@ + #size-cells = <1>; + ranges; + ++ de2@1000000 { ++ compatible = "allwinner,sun50i-a64-de2"; ++ reg = <0x1000000 0x400000>; ++ allwinner,sram = <&de2_sram 1>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x1000000 0x400000>; ++ ++ display_clocks: clock@0 { ++ compatible = "allwinner,sun50i-a64-de2-clk"; ++ reg = <0x0 0x100000>; ++ clocks = <&ccu CLK_DE>, ++ <&ccu CLK_BUS_DE>; ++ clock-names = "mod", ++ "bus"; ++ resets = <&ccu RST_BUS_DE>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ }; ++ + syscon: syscon@1c00000 { + compatible = "allwinner,sun50i-a64-system-control"; + reg = <0x01c00000 0x1000>; +-- +2.19.0 + +From 712cc22f9f494768e2b7536a92155bce435c591b Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Fri, 22 Jun 2018 20:45:39 +0800 +Subject: [PATCH 11/16] arm64: dts: allwinner: a64: add device tree node for + HDMI simplefb + +As the U-Boot bootloader now is also capable of initialize the HDMI on +A64 boards, add a simplefb device tree node for accessing the HDMI +framebuffer initialized by the bootloader. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 318c4ba8ae9f..840753432ea5 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -68,6 +68,15 @@ + <&display_clocks CLK_MIXER0>; + status = "disabled"; + }; ++ ++ simplefb_hdmi: framebuffer-hdmi { ++ compatible = "allwinner,simple-framebuffer", ++ "simple-framebuffer"; ++ allwinner,pipeline = "mixer1-lcd1-hdmi"; ++ clocks = <&display_clocks CLK_MIXER1>, ++ <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; ++ status = "disabled"; ++ }; + }; + + cpus { +-- +2.19.0 + +From c1d41f802698222cffc9240d1a969876c88f84eb Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Fri, 22 Jun 2018 21:05:24 +0800 +Subject: [PATCH 12/16] arm64: dts: allwinner: a64: add HDMI regulator to all + DTs' simplefb_hdmi + +On usual A64 board design the power of HDMI controller is connected to +DLDO1 of the AXP803 PMIC. If this regulator is shut down, the HDMI +output will be blank. Therefore the simplefb driver should keep this +regulator on. + +Add the regulator to all currently available A64 boards' simplefb_hdmi +device node, if the board is capable of outputing HDMI. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 4 ++++ + arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 4 ++++ + 8 files changed, 32 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +index 0716b1441187..094cfed13df9 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts +@@ -296,6 +296,10 @@ + regulator-name = "vcc-rtc"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +index e2dce48fa29a..98dbff19f5cc 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts +@@ -195,6 +195,10 @@ + regulator-name = "vcc-rtc"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +index 3b3081b10ecb..3f531393eaee 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +@@ -214,6 +214,10 @@ + regulator-name = "vcc-rtc"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +index bf42690a3361..1221764f5719 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts +@@ -191,6 +191,10 @@ + regulator-name = "vcc-rtc"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +index a75825798a71..1b9b92e541d2 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -229,6 +229,10 @@ + regulator-name = "vcc-rtc"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + /* On Euler connector */ + &spdif { + status = "disabled"; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +index e6e5bf11b759..897e60cbe38d 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts +@@ -264,6 +264,10 @@ + regulator-name = "vcc-rtc"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +index abe179de35d7..c21f2331add6 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts +@@ -134,6 +134,10 @@ + regulator-name = "vcc-wifi"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +index 33f78e745815..81f8e0098699 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +@@ -254,6 +254,10 @@ + regulator-name = "vcc-rtc"; + }; + ++&simplefb_hdmi { ++ vcc-hdmi-supply = <®_dldo1>; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; +-- +2.19.0 + +From bf81d87b75ea84824628c5f9cc04e56df2864210 Mon Sep 17 00:00:00 2001 +From: Corentin Labbe <clabbe@baylibre.com> +Date: Wed, 18 Jul 2018 11:40:41 +0000 +Subject: [PATCH 13/16] arm64: dts: allwinner: a64: Remove unused + address-cells/size-cells of dwmac-sun8i + +address-cells/size-cells is unnecessary for dwmac-sun8i node. +It was in early days, but since a mdio node is used, it could be +removed. + +This patch fix the following DT warning: +Warning (avoid_unnecessary_addr_size): /soc/ethernet@1c50000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property + +Signed-off-by: Corentin Labbe <clabbe@baylibre.com> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 -- + 1 file changed, 2 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 840753432ea5..d3daf90a8715 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -656,8 +656,6 @@ + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + status = "disabled"; +- #address-cells = <1>; +- #size-cells = <0>; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; +-- +2.19.0 + +From 7ddff282050da462d6dad6458b853b675789d34c Mon Sep 17 00:00:00 2001 +From: Emmanuel Vadot <manu@freebsd.org> +Date: Fri, 27 Jul 2018 13:52:02 +0200 +Subject: [PATCH 14/16] arm64: dts: allwinner: a64: Add SID node + +The A64 have a SID controller which consist of EFUSE (starting at 0x200) +and three registers to read/write some of the protected efuses. + +Signed-off-by: Emmanuel Vadot <manu@freebsd.org> +Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index d3daf90a8715..925bf38fb536 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -270,6 +270,11 @@ + #size-cells = <0>; + }; + ++ sid: eeprom@1c14000 { ++ compatible = "allwinner,sun50i-a64-sid"; ++ reg = <0x1c14000 0x400>; ++ }; ++ + usb_otg: usb@1c19000 { + compatible = "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; +-- +2.19.0 + +From 2ddf078f930a3e7aa8cba8066da0f4985b011691 Mon Sep 17 00:00:00 2001 +From: Andre Przywara <andre.przywara@arm.com> +Date: Mon, 30 Jul 2018 13:31:19 +0100 +Subject: [PATCH 15/16] arm64: dts: allwinner: a64: Add L2 cache nodes + +Current kernels complain when booting on an A64 Soc: +.... +[ 1.904297] cacheinfo: Unable to detect cache hierarchy for CPU 0 +.... +Not a real biggie on this flat topology, but also easy enough to fix. + +Add the L2 cache node and let each CPU point to it. + +Signed-off-by: Andre Przywara <andre.przywara@arm.com> +Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index 925bf38fb536..b73f9287c3f0 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -88,6 +88,7 @@ + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; ++ next-level-cache = <&L2>; + }; + + cpu1: cpu@1 { +@@ -95,6 +96,7 @@ + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; ++ next-level-cache = <&L2>; + }; + + cpu2: cpu@2 { +@@ -102,6 +104,7 @@ + device_type = "cpu"; + reg = <2>; + enable-method = "psci"; ++ next-level-cache = <&L2>; + }; + + cpu3: cpu@3 { +@@ -109,6 +112,12 @@ + device_type = "cpu"; + reg = <3>; + enable-method = "psci"; ++ next-level-cache = <&L2>; ++ }; ++ ++ L2: l2-cache { ++ compatible = "cache"; ++ cache-level = <2>; + }; + }; + +-- +2.19.0 + +From 77c5a2e6107485ac93a306a64c55d39dcfd79054 Mon Sep 17 00:00:00 2001 +From: Andre Przywara <andre.przywara@arm.com> +Date: Mon, 30 Jul 2018 13:31:20 +0100 +Subject: [PATCH 16/16] arm64: dts: allwinner: a64: Add Pine64-LTS device tree + file + +The Pine64-LTS is a variant of the Pine64 board, from the software +visible side resembling a SoPine module on a baseboard, though the +board has the SoC and DRAM integrated on one PCB. +Due to this it basically shares the DT with the SoPine baseboard, which +we mimic in our DT by inclucing the boardboard .dts into the new file, +just overwriting the model name. +Having a separate .dts for this seems useful, since we don't know yet if +there are subtle differences between the two. Also the SoC on the LTS +board is technically an "R18" instead of the original "A64", although as +far as we know this is just a relabelled version of the original SoC. + +Signed-off-by: Andre Przywara <andre.przywara@arm.com> +Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../boot/dts/allwinner/sun50i-a64-pine64-lts.dts | 13 +++++++++++++ + 2 files changed, 14 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 8664b7aaba82..ed411325123a 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-bananapi-m64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts +new file mode 100644 +index 000000000000..72d6961dc312 +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-lts.dts +@@ -0,0 +1,13 @@ ++/* ++ * SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ * ++ * Copyright (c) 2018 ARM Ltd. ++ */ ++ ++#include "sun50i-a64-sopine-baseboard.dts" ++ ++/ { ++ model = "Pine64 LTS"; ++ compatible = "pine64,pine64-lts", "allwinner,sun50i-r18", ++ "allwinner,sun50i-a64"; ++}; +-- +2.19.0 + |